Battery charging device, battery charging circuit, and semiconductor integrated circuit device

Abstract

Even if the battery voltage applied to the output drive circuit temporarily increases, the control signals input to the gates of the complementary P-type FET and N-type FET in the output circuit are level-shifted to ensure that the gate-source voltage remains below the gate breakdown voltage, enabling stable synchronous rectification control. [Solution] The level shift circuit section 50 converts the input control signal E10 into a high-side control signal E21 and a low-side control signal E11. The control signal E21 is level-shifted to a control signal E24 that changes within a voltage range between the power supply voltage and a voltage Vp that is a predetermined voltage lower than the power supply voltage and less than the gate breakdown voltage of the P-type FET 60, and input to the gate of the P-type FET 60. The control signal E11 is level-shifted to a control signal E13 that changes within a voltage range between the ground voltage and a voltage Vn that is a predetermined voltage higher than the ground voltage and less than the gate breakdown voltage of the N-type FET 62, and input to the gate of the N-type FET 62.

Description

Technical Field

[0001] The present invention relates to battery charging technology, and particularly to a battery charging device for a two-wheeled vehicle, a battery charging circuit, and a semiconductor integrated circuit device for battery charging control.

Background Art

[0002] Conventionally, various battery charging devices for two-wheeled vehicles have been proposed. For example, in the battery charging device of Patent Document 1, in order to prevent the battery charging voltage from being controlled by synchronous rectification and the phase voltage from becoming unbalanced due to the transition between the charging state and the non-charging state occurring in a short time, resulting in a decrease in battery charging efficiency, a method of holding the charging state and the non-charging state for an arbitrary period is disclosed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the battery charging device of Patent Document 1, in a battery charging device that inputs the output of a permanent magnet type three-phase AC generator and charges a battery with a DC voltage rectified by a three-phase full-wave rectification circuit, charging control is performed by a control circuit composed of a group of diodes (rectifying element group) connected to the plus side and a group of FETs (switching element group) connected to the minus side of the three-phase full-wave rectification circuit.

[0005] The control circuit's charge control detects the zero-crossing at the rising edge when the AC input voltage rises from negative to positive as the timing for synchronous rectification, and turns off each FET by setting its gate signal to L level to charge the battery. It also detects the zero-crossing at the falling edge when the AC input voltage falls from positive to negative, and turns on each FET by setting its gate signal to H level to return the battery to the generator and stop charging, performing three-phase full-wave rectification charge control, also known as three-phase one-cycle synchronous rectification control.

[0006] In this case, the output stage of the control circuit that outputs control signals to the gate terminals of each FET in the three-phase full-wave rectifier circuit is provided with the output circuit shown in Figure 12.

[0007] In this context, the semiconductor integrated circuit (INCR) devices that make up the control circuit of a battery charging device can be bipolar or CMOS. The bipolar configuration has the advantage of a small offset and simple circuit, but the disadvantage is that the larger circuit area makes the wafer process more expensive. In contrast, the CMOS configuration has the disadvantage of a larger offset, but the advantage is that the smaller circuit area makes the wafer process cheaper. For these reasons, CMOS control circuits are used.

[0008] Figure 12 shows an output circuit provided in the output stage of a control circuit with a CMOS configuration. It is a grounded power supply (non-floating power supply) in which the negative terminal of the battery is connected to ground without floating the ground.

[0009] The output circuit includes a complementary driver circuit in which a P-type FET 100 and an N-type FET 102 are complementaryally connected between the power line connected to the positive terminal of the battery and the ground line connected to the negative terminal of the battery. When the control signals for the gates of the P-type FET 100 and the N-type FET 102 are set to a low level, the P-type FET turns on as the gate-source voltage VGS increases, and the N-type FET turns off as no gate-source voltage VGS is generated. A high-level control signal, which is the power supply voltage level, is output from the output terminal OUT to the corresponding FETs of the three-phase full-wave rectifier circuit to turn them on.

[0010] Furthermore, when the control signals for the gates of the P-type FET 100 and N-type FET 102 are set to a high level, the P-type FET turns off because no gate-source voltage VGS is generated, and the N-type FET turns on as the gate-source voltage VGS increases. A low-level control signal, which is at ground level, is output from the output terminal OUT to the corresponding FET of the three-phase full-wave rectifier circuit to turn it off.

[0011] Furthermore, a level shift circuit 106 is provided on the input side of the complementary driver circuit. The control signal (logic signal) from input IN, which changes within a voltage range of the internal power supply voltage lower than the power supply voltage propagated through the control circuit, is amplified by amplifier 104 and input to the level shift circuit 106. There, it is level-shifted to a control signal that changes within the voltage range of the power supply voltage VCC, and then input to the gates of the P-type FET 100 and N-type FET 102 via inverter 108.

[0012] Here, the power supply voltage VCC associated with battery charging is arbitrary, but for example, it is 14 volts under normal conditions, and the gate-source voltage VGS applied when the P-type FET 100 or N-type FET 102 is turned on will also be 14 volts. Therefore, the P-type FET 100 and N-type FET 102 are selected and used to have a gate withstand voltage greater than the gate-source voltage VGS, for example, a gate withstand voltage of 20 volts.

[0013] However, if the AC output of a three-phase AC generator increases due to high engine speed, the battery charging voltage due to charge control will temporarily increase, and consequently the power supply voltage VCC will increase, potentially resulting in a power supply voltage of, for example, 30 volts, exceeding the gate withstand voltage of 20 volts, being applied to the output circuit.

[0014] When a power supply voltage exceeding the gate withstand voltage is applied to the output circuit in this manner, the gate-source voltage VGS of the P-type FET 100 or N-type FET 102 increases from the normal 14 volts to 30 volts when a control signal to turn them on is input, which may exceed the gate withstand voltage of 20 volts. This can lead to degradation or destruction of the P-type FET 100 and N-type FET 102, potentially causing instability in battery charging control.

[0015] The present invention aims to provide a battery charging device, a battery charging circuit, and a semiconductor integrated circuit device that enable stable synchronous rectification control by level-shifting the control signals input to the gates of complementary P-type FETs and N-type FETs in an output circuit so that the gate-source voltage remains below the gate breakdown voltage even if the battery voltage applied to the output drive circuit temporarily increases. [Means for solving the problem]

[0016] (Battery charging device) The present invention is a battery charging device that takes the output of an AC power source as input and charges a battery with a DC voltage rectified by a rectifier circuit equipped with a group of switching elements, It comprises a control circuit equipped with an output circuit that controls the gates of a group of switch elements, the positive terminal of the battery is connected to the power line, and the negative terminal of the battery is connected to the ground line. The output circuit consists of a driver circuit in which a high-side P-type FET and a low-side N-type FET are complementaryly connected between the power line and the ground line, A level shift circuit controls the driver circuit to protect the P-type and N-type FETs by maintaining their gate-source voltages below their respective gate breakdown voltages when the power supply voltage of the power line increases from a predetermined steady-state power supply voltage to a power supply voltage exceeding the gate breakdown voltage. It is characterized by having the following features.

[0017] (Level shift circuit) The output circuit is, The system includes a level shift circuit that converts the input control signal into a high-side control signal and a low-side control signal. The high-side control signal is level-shifted to a control signal that changes within a voltage range between the power supply voltage of the power line and a predetermined voltage lower than the power supply voltage by less than the gate breakdown voltage of the P-type FET, and input to the gate of the P-type FET. The low-side control signal is level-shifted to a control signal that changes within a voltage range between the ground voltage of the ground line and a predetermined voltage higher than the ground voltage by less than the gate breakdown voltage of the N-type FET, and input to the gate of the N-type FET.

[0018] (Level shift circuit configuration) The level shift circuit is, A signal conversion circuit that converts the input control signal into a high-side control signal and a low-side control signal, A low-side clamp generation circuit generates a low-side clamp voltage (Vn) that is higher by a predetermined voltage than the ground voltage of the ground line and less than the gate breakdown voltage of the N-type FET, A high-side clamp generation circuit generates a high-side clamp voltage (Vp) that is lower by a predetermined voltage, which is less than the gate breakdown voltage of the P-type FET and lower than the power supply voltage of the power line. A low-side level shift circuit that levels-shifts the low-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the ground voltage and the low-side clamp voltage, and inputs it to the gate of an N-type FET, A high-side level shift circuit that levels-shifts the high-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the power supply voltage and the high-side clamp voltage, and inputs it to the gate of a P-type FET, It is equipped with.

[0019] (High-side two-stage level shift circuit) The high-side level shift circuit is A first level shift circuit that level shifts the high-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the ground voltage and the low-side clamp voltage, A second level shift circuit that level-shifts a control signal from a first level shift circuit to a control signal that varies within a voltage range between a power supply voltage and a high-side clamp voltage, is provided.

[0020] (Low voltage protection circuit) Further, when the control circuit is transitioning to a low voltage detection state that goes from a predetermined power supply voltage to a predetermined low power supply voltage, the control circuit includes a low voltage protection circuit that maintains a P-type FET in an off state against a decrease in the power supply voltage and operates normally.

[0021] (Battery charging circuit) Further, the present invention is a battery charging circuit that charges a battery with a DC voltage rectified by a rectifying circuit including a switch element group, with an output of an AC power supply as an input, and includes a control circuit having an output circuit that controls gates of the switch element group, connects a plus terminal of the battery to a power supply line, and connects a minus terminal of the battery to a ground line, where the output circuit includes a driver circuit in which a P-type FET on the high side and an N-type FET on the low side are complementarily connected between the power supply line and the ground line, and a level shift circuit that controls the driver circuit so as to maintain the gate-source voltage of the P-type FET and the N-type FET below their respective gate breakdown voltages and protect them when the power supply voltage of the power supply line increases from a predetermined steady power supply voltage to a power supply voltage exceeding the gate breakdown voltage. In this case, the level shift circuit, the high-side level shift circuit, and the low voltage protection circuit of the battery charging circuit are the same as those in the case of the battery charging device described above.

[0022] (Semiconductor integrated circuit device) Further, the present invention is a semiconductor integrated circuit device including a control circuit that controls a switch element group so as to charge a battery with a DC voltage rectified by a rectifying circuit including a switch element group, with an output of an AC power supply as an input, where the control circuit includes an output circuit that controls gates of the switch element group and connects a plus terminal of the battery to a power supply line, The output circuit is, A driver circuit is provided between the power line and the ground line, with a P-type FET on the high side and an N-type FET on the low side connected in a complementary manner. The device includes a level shift circuit that controls the driver circuit to maintain the gate-source voltages of the P-type FETs and N-type FETs below their respective gate breakdown voltages when the power supply voltage of the power line increases from a predetermined steady-state power supply voltage to a power supply voltage exceeding the gate breakdown voltage. In this case as well, the level shift circuit, high-side level shift circuit, and undervoltage protection circuit of the semiconductor integrated circuit device are the same as those in the battery charging device described above. [Effects of the Invention]

[0023] (Effects of battery charging device) The present invention is a battery charging device that takes the output of an AC power source as input and charges a battery with a DC voltage rectified by a rectifier circuit equipped with a group of switch elements, and comprises a control circuit equipped with an output circuit that controls the gates of the group of switch elements, the positive terminal of the battery is connected to the power line and the negative terminal of the battery is connected to the ground line, and the output circuit comprises a driver circuit in which a high-side P-type FET and a low-side N-type FET are complementaryly connected between the power line and the ground line, and a level shift circuit that controls the driver circuit to maintain the gate-source voltage of the P-type FET and N-type FET below their respective gate withstand voltages when the power supply voltage of the power line increases from a predetermined steady-state power supply voltage to a power supply voltage exceeding the gate withstand voltage, thereby protecting them, three When the AC output of a phase AC generator increases due to high engine speed, the battery charging voltage due to charge control temporarily increases, and consequently the power supply voltage VCC also increases. In some cases, a power supply voltage exceeding the gate withstand voltage may be applied to the output drive circuit. However, even if the power supply voltage increases to a voltage exceeding the gate withstand voltage, the gate-source voltage VGS applied when turning on the high-side P-type FET is always maintained at a predetermined voltage lower than the gate withstand voltage, and never exceeds the gate withstand voltage. Similarly, the gate-source voltage VGS applied when turning on the low-side N-type FET is always maintained at a predetermined voltage higher than the ground level, and never exceeds the gate withstand voltage, thus reliably preventing degradation and destruction of the P-type FET and N-type FET.

[0024] (Effect of the level shift circuit) Furthermore, the output circuit comprises a level shift circuit that converts the input control signal into a high-side control signal and a low-side control signal, the high-side control signal is level-shifted to a control signal that changes within a voltage range between the power supply voltage of the power line and a voltage lower than the power supply voltage by a predetermined voltage less than the gate breakdown voltage of the P-type FET, and input to the gate of the P-type FET, and the low-side control signal is level-shifted to a control signal that changes within a voltage range between the ground voltage of the ground line and a voltage higher than the ground voltage by a predetermined voltage less than the gate breakdown voltage of the N-type FET, and input to the gate of the N-type FET. The level shift circuit comprises a signal conversion circuit that converts the input control signal into a high-side control signal and a low-side control signal, a low-side clamp generation circuit that generates a low-side clamp voltage (Vn) that is higher than the ground voltage of the ground line by a predetermined voltage less than the gate breakdown voltage of the N-type FET, and a level shift circuit that generates a low-side clamp voltage (Vn) that is lower than the power supply voltage of the power line by a predetermined voltage less than the gate breakdown voltage of the P-type FET. The system includes a high-side clamp generation circuit that generates a high-side clamp voltage (Vp), a low-side level shift circuit that levels-shifts the low-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the ground voltage and the low-side clamp voltage and inputs it to the gate of an N-type FET, and a high-side level shift circuit that levels-shifts the high-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the power supply voltage and the high-side clamp voltage and inputs it to the gate of a P-type FET. As an internal power supply, the high-side clamp circuit generates a predetermined high-side clamp voltage (Vp), the low-side clamp circuit generates a predetermined low-side clamp voltage (Vn), and the high-side level shift circuit and low-side level shift circuit operate individually. This ensures that even if the power supply voltage increases beyond the gate breakdown voltage, the gate-source voltage VGS of the high-side P-type FET and the low-side N-type FET will not exceed the gate breakdown voltage.

[0025] (Effect of the high-side two-stage level shift circuit) Furthermore, the high-side level shift circuit includes a first level shift circuit that level shifts the high-side control signal converted by the signal conversion circuit to a control signal that changes within the voltage range between the ground voltage and the low-side clamp voltage, and a second level shift circuit that level shifts the control signal from the first level shift circuit to a control signal that changes within the voltage range between the power supply voltage and the high-side clamp voltage. As the input control signal changes within the voltage range of the internal power supply which is lower than the power supply voltage, a level shift is performed in two stages to gradually increase the high-potential control signal that changes between the power supply voltage and a predetermined voltage lower than it, thereby enabling stable level shifting.

[0026] (Effect of low-voltage protection circuit) Furthermore, the control circuit is equipped with a low-voltage protection circuit that keeps the P-type FET in the off state in response to a drop in power supply voltage when transitioning from a predetermined power supply voltage to a predetermined low power supply voltage, thus enabling normal operation. However, in the low-voltage detection state, the level-shifted high-side control signal becomes undefined and reaches an L level, turning on the P-type FET, while the level-shifted low-side control signal remains normal, turning on the N-type FET. This can cause a malfunction where both the P-type and N-type FETs turn on simultaneously, resulting in a shoot-through current. The low-voltage protection circuit applies a protection voltage to the P-type FET to maintain its off state, thus reliably preventing this malfunction. [Brief explanation of the drawing]

[0027] [Figure 1] This is an explanatory diagram showing the configuration of a battery charging device. [Figure 2] This is a time chart showing an example of the voltage waveform when a battery charging device is in the charging state. [Figure 3] This is a time chart diagram showing examples of voltage waveforms in the charged and uncharged states of a battery charging device. [Figure 4] This is an explanatory diagram showing the circuit configuration of the control circuit of a battery charging device. [Figure 5] This is an explanatory diagram showing the setting and operation of the reference voltage of a comparator using a ground-connected power supply. [Figure 6] This is an explanatory diagram showing the circuit configuration of the output circuit. [Figure 7] This is a time chart showing the signal waveform of the output circuit when the power supply voltage is a steady-state voltage of 14 volts. [Figure 8] This is a time chart showing the signal waveform of the output circuit when the power supply voltage is increased to 30 volts, which exceeds the gate voltage withstand voltage. [Figure 9] This is a time chart showing the malfunction of the output circuit in the low voltage detection state in Figure 6. [Figure 10] This is an explanatory diagram showing the circuit configuration of an output circuit equipped with a low-voltage protection circuit. [Figure 11] This is a time chart showing the operation of the output circuit in Figure 10. [Figure 12] This is an explanation of a conventional output circuit. [Modes for carrying out the invention]

[0028] Embodiments of the battery charging device, battery charging circuit, and semiconductor integrated circuit device according to the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to the following embodiments.

[0029] [Basic Concepts of the Embodiment] First, the basic concepts of the embodiment will be explained. The embodiment generally relates to a battery charging device that takes the output of an AC power source as input and charges a battery with a DC voltage rectified by a rectifier circuit equipped with a group of switching elements. More specifically, it relates to a battery charging device that takes the three-phase power output of a permanent magnet type three-phase AC generator as input and charges a battery by rectifying it into a DC voltage using a full-wave rectifier circuit equipped with a group of switching elements.

[0030] Here, a "permanent magnet type three-phase AC generator" is a generator driven by the rotation of a motorcycle engine, consisting of a stator with three-phase winding coils arranged in a stator yoke, and a rotor with an even number of permanent magnets arranged inside the stator so that the north poles repel each other or the south poles repel each other. The rotor rotates at the center of the stator to generate electricity and output three-phase AC power.

[0031] Furthermore, a "full-wave rectifier circuit" is a circuit that takes the three-phase power output of a three-phase AC generator as input, and has a group of rectifier elements connected to the positive side and a group of switch elements connected to the negative side to output a full-wave rectified DC voltage to charge a battery.

[0032] Furthermore, a "rectifier element group" is a collection of rectifier elements connected to each of the three positive phase lines of a full-wave rectifier circuit. Its configuration and type are arbitrary, but it typically uses diodes as power semiconductors, such as Schottky barrier diodes or equivalents.

[0033] Furthermore, a "group of switching elements" refers to a collection of switching elements connected to each of the three negative phase lines of a full-wave rectifier circuit. While its configuration and type are arbitrary, FETs or equivalent power semiconductors are typically used.

[0034] Furthermore, the battery charging device of this embodiment includes a control circuit that has an output circuit for controlling the gates of a group of switch elements, and operates with a ground-connected power supply that connects the positive terminal of the battery to a power line and the negative terminal of the battery to a ground line.

[0035] Here, the "control circuit" detects the zero-crossing at the rising edge (positive edge) when the AC input voltage rises from negative to positive for each phase of the three-phase power output as the timing for synchronous rectification. By setting the gate signal of the FET to L level, it turns it off to charge the battery. Conversely, it detects the zero-crossing at the falling edge (negative edge) when the AC input voltage falls from positive to negative, and by setting the gate signal of the FET to H level, it turns it on, returning the battery to the three-phase AC generator and preventing charging. This is known as three-phase one-cycle synchronous rectification control.

[0036] Furthermore, "H level" refers to one level of a binary logic signal and includes concepts such as high level, high potential, and "1". Similarly, "L level" refers to the other level of a binary logic signal and includes concepts such as low level, low potential, and "0".

[0037] Furthermore, the "output circuit of the control circuit" consists of a driver circuit and a level shift circuit.

[0038] Here, a "driver circuit" is a circuit in which a high-side P-type FET and a low-side N-type FET are complementaryly connected between the power line and the ground line. A "P-type FET" refers to a P-channel MOSFET, which turns on with a low-level gate signal input and turns off with a high-level gate signal input. Similarly, an "N-type FET" refers to an N-channel MOSFET, which turns on with a high-level gate signal input and turns off with a low-level gate signal input.

[0039] Furthermore, "complementary connection of the high-side P-type FET and the low-side N-type FET" means that the P-type FET and N-type FET, which have opposite polarities, are connected complementaryally. Depending on the input gate signal, one becomes ON and the other OFF, resulting in a large amplitude output. In a steady state, the two FETs are not ON at the same time, so the static power consumption is very small, resulting in advantages such as low power consumption and robustness against noise.

[0040] Furthermore, the "level shift circuit" converts (separates) the input control signal into a high-side control signal and a low-side control signal. The high-side control signal is level-shifted to a control signal that changes within a voltage range between the power supply voltage of the power line and a predetermined voltage lower than the power supply voltage by less than the gate breakdown voltage of the P-type FET, and input to the gate of the P-type FET. The low-side control signal is level-shifted to a control signal that changes within a voltage range between the ground voltage of the ground line and a predetermined voltage higher than the ground voltage by less than the gate breakdown voltage of the N-type FET, and input to the gate of the N-type FET.

[0041] Here, assuming a steady-state power supply voltage of 14 volts and a gate breakdown voltage of 20 volts, the high-side control signal is level-shifted to a control signal that changes within a voltage range between the power supply voltage of 14 volts and a predetermined voltage less than the gate breakdown voltage of the P-type FET (20 volts), for example, 6 volts (8 volts lower), and input to the gate of the P-type FET. The low-side control signal is level-shifted to a low-side control signal that changes within a voltage range between the ground voltage of 0 volts and a predetermined voltage less than the gate breakdown voltage of the N-type FET (20 volts), for example, 12 volts higher, and input to the gate of the N-type FET.

[0042] Furthermore, if the power supply voltage increases from a predetermined steady-state voltage to a power supply voltage exceeding the gate breakdown voltage, for example, if the power supply voltage increases from a steady-state power supply voltage of 14 volts to a power supply voltage exceeding the gate breakdown voltage of 20 volts, for example, to a power supply voltage of 30 volts, the gate-source voltage of the P-type FET is maintained at 8 volts, which is below the gate breakdown voltage, for protection, and the gate-source voltage of the N-type FET is maintained at 12 volts, which is below the gate breakdown voltage, for protection.

[0043] Therefore, when the AC output of a three-phase AC generator increases due to high engine speed, the battery charging voltage due to charge control temporarily increases, and consequently the power supply voltage also increases. In some cases, a power supply voltage exceeding the gate withstand voltage may be applied to the output drive circuit. However, even if the power supply voltage increases to a voltage exceeding the gate withstand voltage, the gate-source voltage VGS applied when turning on the high-side P-type FET is always maintained at a predetermined voltage lower than the gate withstand voltage, and never exceeds the gate withstand voltage. Similarly, the gate-source voltage VGS applied when turning on the low-side N-type FET is always maintained at a predetermined voltage higher than the ground level, and never exceeds the gate withstand voltage, thus reliably preventing deterioration and destruction of the P-type FET and N-type FET.

[0044] Furthermore, the "level shift circuit" consists of a signal conversion circuit, a low-side clamp circuit, a high-side clamp circuit, a low-side level shift circuit, and a high-side level shift circuit.

[0045] Here, the "signal conversion circuit" converts (separates) the input control signal into a high-side control signal and a low-side control signal, making it possible to perform level shifts on each individually.

[0046] Furthermore, the "low-side clamp generation circuit" generates a low-side clamp voltage Vn that is lower than the ground voltage of the ground line and lower than the gate breakdown voltage of the N-type FET, for example, less than 20 volts, for example, 12 volts higher.

[0047] Furthermore, the "high-side clamp generation circuit" generates a high-side clamp voltage Vp that is lower by a predetermined voltage, for example, 8 volts, than the power supply voltage of the power line, for example, 14 volts, and less than the gate breakdown voltage of the P-type FET, for example, less than 20 volts.

[0048] Furthermore, the "low-side level shift circuit" level-shifts the low-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the ground voltage and the low-side clamp voltage Vn, and inputs it to the gate of the P-type FET.

[0049] Furthermore, the "high-side level shift circuit" level-shifts the high-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the power supply voltage and the high-side clamp voltage Vp, and inputs it to the gate of the P-type FET.

[0050] Therefore, as an internal power supply, a high-side clamp circuit generates a predetermined high-side clamp voltage Vp, and a low-side clamp circuit generates a predetermined low-side clamp voltage Vn. By operating the high-side level shift circuit and the low-side level shift circuit individually, it becomes possible to individually level shift the low-side gate signal and the high-side gate signal so that even if the power supply voltage increases beyond the gate breakdown voltage, the gate-source voltage VGS of the high-side P-type FET and the low-side N-type FET does not exceed the gate breakdown voltage.

[0051] Furthermore, the "high-side level shift circuit" consists of a first level shift circuit and a second level shift circuit.

[0052] Here, the "first level shift circuit" level shifts the high-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the ground voltage and the low-side clamp voltage. The "second level shift circuit" then level shifts the control signal from the first level shift circuit into a control signal that changes within the voltage range between the power supply voltage and the high-side clamp voltage.

[0053] Therefore, a stable level shift is made possible by performing a level shift in two stages, which increases the input control signal, which changes within the voltage range of the internal power supply lower than the power supply voltage, into a high-side control signal, which is on the high potential side and changes between the power supply voltage and a predetermined voltage lower than that.

[0054] Furthermore, the "control circuit" includes a low-voltage protection circuit. Here, the "low-voltage protection circuit" maintains the P-type FET in the off state in response to a drop in power supply voltage when the power supply voltage transitions to a low-voltage detection state where the power supply voltage reaches a predetermined low power supply voltage, thereby ensuring normal operation.

[0055] Therefore, in the low-voltage detection state, the level-shifted high-side control signal becomes undefined and reaches an L level, turning on the P-type FET, while the level-shifted low-side control signal remains normal, turning on the N-type FET. This results in a malfunction where both the P-type and N-type FETs turn on simultaneously, causing a shoot-through current to flow. However, by applying a protection voltage to the P-type FET from the low-voltage protection circuit to maintain its normal OFF state, this error operation can be reliably prevented.

[0056] Furthermore, the battery charging circuit and semiconductor integrated circuit device of the embodiment have substantially the same characteristics as the battery charging device described above.

[0057] The following describes specific embodiments using a "battery charging device" as an example. The details will be explained in the following sections. a. Overview of the battery charging device b. Charging control c. Circuit configuration d. Output circuit configuration d1. Driver circuit d2. Level shift circuit section d3. Low-side level shift d4. Highside level shift d5.2-level shift e. Operation of the output circuit e1. Operation at steady-state power supply voltage e2. Operation at power supply voltages exceeding the gate breakdown voltage. f. Output circuit with low voltage protection circuit f1. Malfunction under low voltage conditions f2. Low voltage protection circuit g. Semiconductor integrated circuit equipment h. Modified Examples of the Invention

[0058] [a. Overview of Battery Charging Devices] This section will describe the battery charging device. Refer to Figure 1, which shows the configuration of the battery charging device, for further explanation.

[0059] As shown in Figure 1, the battery charging device of this embodiment takes the three-phase AC outputs U, V, and W of a permanent magnet type three-phase AC generator 10 as input, charges the battery 14 via a fuse 18 using the DC voltage rectified by the three-phase full-wave rectifier circuit 12, and supplies DC power to the load 16 to operate it. The device consists of a three-phase full-wave rectifier circuit 12 and a control circuit 20.

[0060] The three-phase full-wave rectifier circuit 12 is a circuit that takes the three-phase output voltage of the three-phase AC generator 10 as input and rectifies it into a DC voltage. The three-phase full-wave rectifier circuit 12 consists of a group of rectifier elements 22 connected to the positive side and a group of switch elements 24 connected to the negative side.

[0061] The rectifier element group 22 has rectifier elements 2210, 2212, and 2214 connected to each phase. The configuration and type of rectifier elements 2210, 2212, and 2214 are arbitrary, but Schottky barrier diodes or equivalents are used as examples of rectifier elements, and since they are for power supply purposes, they are used as power semiconductor diodes.

[0062] Furthermore, the switching element group 24 has FETs 2410, 2412, and 2414, which are examples of switching elements, connected to each phase, and since it is for power supply purposes, these are FETs as power semiconductors.

[0063] The control circuit 20 controls the FETs 2410, 2412, and 2414 of the switching element group 24 when charging the battery 14 with the DC voltage rectified by the three-phase full-wave rectifier circuit 12. The control circuit 20 operates on a grounded power supply, with the positive terminal of the battery 14 connected to the power line 26 and the negative terminal of the battery 14 connected to the ground line 28.

[0064] [b. Charge control] Next, the charging control by the control circuit 20 will be described. In this description, refer to Figure 2, which is a time chart showing an example of the voltage waveform when the battery charging device is in a charging state, and Figure 3, which is a time chart showing examples of the voltage waveform when the battery charging device is in a charging state and when it is not charging.

[0065] In controlling the charging state of the battery charging device shown in Figure 2, for example, taking the U-phase voltage as an example, the zero-crossing at the rising edge of the U-phase voltage when it rises from negative to positive, for example at time t1, is detected as the timing for synchronous rectification. By changing the gate signal E1 of FET2410 from a high level to a low level, FET2410 is turned off, and the rectifier element 2210 rectifies the voltage to charge the battery 14.

[0066] Next, a zero-crossing occurs at the falling edge of the U-phase voltage at time t2, when the voltage falls from positive to negative. This detects the zero-crossing and changes the gate signal E1 of the FET2410 from L level to H level, thereby turning on the FET2410 and returning the battery 14 to the three-phase AC generator 10, thus preventing charging.

[0067] The same applies to the V-phase voltage and W-phase voltage. The control is repeated by detecting the zero-crossing of the rising edge to turn off FETs 2412 and 2414 and charge the battery 14, and then detecting the zero-crossing of the falling edge to turn off FETs 2412 and 2414 and stop charging.

[0068] Figure 3 shows a scenario where the battery is charged for a long period and then decharged for a short period. The power supply voltage (battery voltage) drops below a steady-state voltage of 14 volts before time t11 and after t13, indicating a charging state. The voltage rises above the steady-state voltage between time t11 and t12, indicating a decharge state.

[0069] If the power supply voltage VCC is below the steady-state voltage up to time t11, the control process is repeated to charge the battery 14 by detecting the zero-crossing of the rising edges of the U, V, and W phase voltages, setting the gate signals E1, E2, and E3 to L level, and turning off FETs 2410, 2412, and 2414, similar to the charging control shown in Figure 2.

[0070] If the power supply voltage VCC increases above the steady-state voltage at time t11, even if the zero-crossing of the rising edge of the U, V, and W phase voltages is detected, the gate signals E1, E2, and E3 are kept at the H level without being set to the L level, and FETs 2410, 2412, and 2414 are turned on to prevent charging of the battery 14. As a result, the increasing power supply voltage VCC decreases and falls below the steady-state voltage at time t12.

[0071] However, even if the power supply voltage VCC falls below the steady-state voltage at time t12, the gate signals E1, E2, and E3 are maintained at a high level for a predetermined half-cycle period to maintain a non-charged state, and then the system enters a charged state, causing the power supply voltage VCC to increase from time t13.

[0072] In this manner, when a non-charging state occurs briefly while the battery is charging, maintaining the non-charging state for a specified period prevents the phase voltages of the three-phase AC generator 10 from becoming unbalanced, thus preventing a decrease in battery charging efficiency. Similarly, when a charging state occurs briefly while the battery is non-charging, maintaining the charging state for a specified period prevents the phase voltages of the three-phase AC generator 10 from becoming unbalanced, thus preventing a decrease in battery charging efficiency. This control method, which charges the battery 14 by inputting the U, V, and W phase voltages via the control circuit 20, is called three-phase one-cycle synchronous rectification control. Furthermore, the charging control for each phase is referred to as U-phase one-cycle synchronous rectification control, for example, in the case of the U phase.

[0073] [c. Configuration of the control circuit] Next, the configuration of the control circuit will be described. In this description, refer to Figure 4, which shows the circuit configuration of the control circuit of the battery charging device, and Figure 5, which shows the setting and operation of the comparator's reference voltage using a ground-connected power supply.

[0074] As shown in Figure 4, the charge control circuit system is configured to correspond to the U, V, and W phases, so we will explain using the U phase as an example.

[0075] Between the input terminal 30U and the output terminal 54U, a comparator 32U, an inverter 38U, a positive-edge one-shot 40U, a negative-edge one-shot 42U, an AND circuit 44U, a latch circuit 46U, a NOR circuit 48U, a level shift circuit section 50U, and a driver circuit 52U are provided. "One-shot" is an abbreviation for "one-shot multivibrator."

[0076] Here, the inverter 38U, positive edge one-shot 40U, negative edge one-shot 42U, AND circuit 44U, latch circuit 46U, and NOR circuit 48U form a charge control unit 36 ​​configured as a CMOS semiconductor integrated device, the comparator 32U forms an input circuit section 35, and the level shift circuit section 50U and driver circuit 52U form an output circuit section 37.

[0077] The input terminal 30U receives the U-phase voltage from the permanent magnet type three-phase AC generator 10 shown in Figure 1 as a control signal.

[0078] Comparator 32U detects the timing of zero-crossings of the falling and rising edges of the input control signal. Upon detection of a zero-crossing on the rising edge, it outputs a control signal that changes from a high level to a low level, and upon detection of a zero-crossing on the falling edge, it outputs a control signal that changes from a low level to a high level.

[0079] Therefore, a control signal that becomes the U-phase voltage is input to the positive terminal of comparator 32U, and a reference voltage for detecting the zero-crossing timing is input to the negative terminal. The reference voltage is provided as a reference voltage +Vref for detecting the zero-crossing of the rising edge of the control signal and a reference voltage -Vref for detecting the zero-crossing of the falling edge of the control signal, and can be selectively switched to comparator 32U by the switching circuit 34U.

[0080] Here, since the control circuit 20 is operating with a ground-connected power supply, the reference voltages +Vref and -Vref for the comparator 32U are set as shown in Figure 5.

[0081] As shown in Figure 5, for the comparator 32U, a voltage that is a predetermined voltage higher than the ground voltage of 0 volts, for example 1.0 volts, is set as relative 0 volts. A reference voltage +Vref that is, for example, +10 millivolts higher and a reference voltage -Vref that is 10 millivolts lower than relative 0 volts are set. Therefore, the reference voltage +Vref is set to 1.01 volts (= 1.0 volts + 10 millivolts), and the reference voltage -Vref is set to 0.99 volts (= 1.0 volts - 10 millivolts).

[0082] The operation of comparator 32U is as follows: when the falling edge of the input control signal (input voltage) E1 reaches the reference voltage +Vref, which is the negative edge zero-crossing detection point 90, the comparator output inverts from a high level to a low level, and consequently, the input reference voltage to the negative input terminal of comparator 32U is instantaneously switched from the reference voltage +Vref to the reference voltage -Vref.

[0083] Next, when the rising edge of the input control signal (input voltage) E1 reaches the reference voltage -Vref, which is the positive edge zero-cross detection point 92, the comparator output inverts from L level to H level, and consequently, the input reference voltage to the negative input terminal of comparator 32U is instantaneously switched from reference voltage Vref to reference voltage +Vref.

[0084] Referring again to Figure 4, the output of comparator 32U is input to positive edge one-shot 40U and negative edge one-shot 42U via inverter 38U. Positive edge one-shot 40U operates on the comparator output for zero-crossing detection of the rising edge of the control signal and outputs a one-shot signal that is at a high level for a predetermined period. Negative edge one-shot 42U operates on the comparator output for zero-crossing detection of the falling edge of the control signal and outputs a one-shot signal that is at a low level for a predetermined period.

[0085] The one-shot signal from the negative edge one-shot 42U is input to the latch circuit 46U as a set signal via the AND circuit 44U, and the set operation sets the latch output to a high level. The one-shot signal from the positive edge one-shot 40U is input to the latch circuit 46U as a reset signal, and the reset operation sets the latch output to a low level. The AND circuit 44U is input to a charge enable signal E4, which becomes high level when the power supply voltage VCC is within a predetermined starting voltage range, for example, 0.3 to 30 volts, and puts the AND circuit 44U into an enable state.

[0086] The control signal from the latch circuit 46U is input to the level shift circuit 50U via the NOR circuit 48U, where it undergoes a level shift to increase to a predetermined voltage level and is input to the driver circuit 52U. From the driver circuit 52U, the gate signal E1 is output to the U-phase FET 2410 shown in Figure 1 via the output terminal 54U.

[0087] Since the control circuits for the V-phase and W-phase are the same as those for the U-phase described above, their explanation will be omitted.

[0088] Furthermore, the control circuit is equipped with a low-voltage detection circuit 56. The low-voltage detection circuit 56 receives the power supply voltage VCC as input and outputs a reset signal E5 corresponding to the low-voltage state. Specifically, a rising-point reference voltage and a falling-point reference voltage with hysteresis are set, and if the power supply voltage VCC is less than the reference voltage, the reset signal E5 is set to the H level by low-voltage detection, and if the power supply voltage VCC is equal to or greater than the reference voltage, the reset signal E5 is set to the L level. If the steady-state voltage of the power supply voltage VCC is 14 volts, the rising-point reference voltage and the falling-point reference voltage can be set arbitrarily, but for example, the rising-point reference voltage is set to 8 volts and the falling-point reference voltage to 7.5 volts to provide hysteresis.

[0089] The reset signal E5 from the low voltage detection circuit 56 is input to the latch circuits 46U, 46V, 46W and NOR circuits 48U, 48V, 48W for each phase. The H level output of the reset signal E5 latches the reset signal E5 to the latch circuits 46U, 46V, 46W, and fixes the outputs of the NOR circuits 48U, 48V, 48W to L level. The gate signals E1, E2, E3 for FETs 2410, 2412, 2414 in Figure 1 are also fixed to L level, thereby turning off FETs 2410, 2412, 2414 and stopping the three-phase one-cycle synchronous rectification control. The battery 14 is then charged by the generated voltage of all phases to restore the power supply voltage. When the reset signal E5 from the low voltage detection circuit 56 becomes L level, the battery charging control by three-phase one-cycle synchronous rectification control is performed.

[0090] Furthermore, the control circuit is provided with an overvoltage detection circuit 58. The overvoltage detection circuit 58 receives the power supply voltage VCC as input and outputs an overvoltage detection signal E6 that is at a high level when it detects a predetermined overvoltage, for example, 16 volts. The overvoltage detection signal E6 from the overvoltage detection circuit 58 is input as a reset signal to the latch circuits 46U, 46V, and 46W, fixing the outputs of the latch circuits 46U, 46V, and 46W to a high level. By fixing the gate signals E1, E2, and E3 for FETs 2410, 2412, and 2414 in Figure 1 to a high level, all FETs 2410, 2412, and 2414 are turned on, stopping the three-phase one-cycle synchronous rectification control and putting all phases into a non-charged state, allowing the battery 14 to be returned to the three-phase AC generator 10 and lowering the power supply voltage VCC.

[0091] [d. Output circuit configuration] Next, the output circuit provided in the control circuit will be described. For this description, please refer to Figure 6, which shows the circuit configuration of the output circuit. As shown in Figure 6, the output circuit consists of a level shift circuit section 50 and a driver circuit 52, and will be explained using the U phase as an example. The output circuits for the V phase and W phase are similar.

[0092] (d1. Driver circuit) The driver circuit 52 has complementary connections between the power line 26 and the ground line 28, with a high-side P-type FET 60 and a low-side N-type FET 62. The level shift circuit 52 individually inputs control signals E24 and E13 to the gates. Here, the high-level and low-level voltages are different due to the level shift circuit 52 individually shifting the levels, resulting in different voltages for control signals E24 and E13.

[0093] When control signal E24 is at a low level and control signal E13 is at a low level, the P-type FET 60 turns on and the N-type FET 62 turns off. Current flows from the power line 26 through the on-up P-type FET 60 to the output terminal 54, and the gate signal E1 from the output terminal 54 becomes high.

[0094] Furthermore, when gate signal E24 is at a high level and gate signal E13 is at a high level, the P-type FET 60 turns off and the N-type FET 62 turns on. Current flows from output terminal 54 through the on-up N-type FET 62 to the ground line 28, and the gate signal E1 from output terminal 54 becomes low.

[0095] (d2. Level shift circuit section) The level shift circuit section 50 consists of a signal conversion circuit 68, a low-side clamp circuit 70, a low-side level shift circuit 72, an inverter 74, a high-side clamp circuit 76, a high-side first level shift circuit 78, a high-side second level shift circuit 80, and an inverter 82.

[0096] The signal conversion circuit 68 receives the control signal E10 from the input terminal 64, i.e., the control signal E10 from the NOR circuit 48U in Figure 4, and converts (separates) it into a low-side control signal E11 and a high-side control signal E21. In this embodiment, the steady-state voltage of the power supply voltage VCC is, for example, 14 volts, and the internal power supply voltage of the control circuit is, for example, 5.8 volts. Therefore, the control signal E10 is a signal that changes within a voltage range between the internal power supply voltage of 5.8 volts and the ground voltage of 0 volts.

[0097] The reset terminal 66 receives a set signal E5 from the low-voltage detection circuit 56 shown in Figure 4. During the rising edge of the power supply voltage to start battery charging, the reset signal remains at the H level until the power supply voltage increases to, for example, 8 volts, resetting the U-phase 1-cycle synchronous rectification control. When the power supply voltage reaches 8 volts, the reset signal E5 becomes L level, releasing the reset and starting the U-phase 1-cycle synchronous rectification control. Furthermore, when the steady-state power supply voltage of 14 volts drops to, for example, 7.5 volts, the reset signal E5 changes from L level to H level, resetting the U-phase 1-cycle synchronous rectification control.

[0098] (d3. Level shift on the low side) The low-side clamp circuit 70 outputs a low-side clamp voltage, which is the internal power supply voltage Vn on the low side, by connecting a resistor and a Zener diode in series between the power supply line 26 and the ground line 28. Here, since the steady-state voltage of the power supply voltage VCC is 14 volts, the low-side clamp voltage Vn is set to, for example, 12 volts, corresponding to the threshold voltage (gate-source voltage VGS) that turns on the N-type FET 62 and the gate breakdown voltage.

[0099] The low-side level shift circuit 72 receives a control signal E11 that changes within a voltage range between the internal power supply voltage of 5.8 volts and the ground voltage of 0 volts, level-shifts it to a control signal E12 that changes within a voltage range between the low-side clamp voltage Vn=12 volts and the ground voltage of 0 volts, and inputs the control signal E13 to the gate of the N-type FET 62 via an inverter 74 that functions as a buffer.

[0100] Here, the N-type FET 62 that turns on at a gate-source voltage VGS of 12 volts, which is above the threshold voltage, is selected and used, and has a gate withstand voltage of a sufficiently large value, for example, 20 volts, relative to the steady-state voltage of the power supply voltage VCC of 14 volts.

[0101] Therefore, the control signal E13, which is the gate signal of the N-type FET62, will always be a signal that changes within the voltage range of 12 volts and 0 volts, even if the power supply voltage VCC fluctuates, as long as the power supply voltage does not fall below the low-side clamp voltage Vn of 12 volts, and the gate-source voltage VGS will never exceed the gate withstand voltage of 20 volts.

[0102] (d4. Highside level shift) The high-side clamp circuit 76 outputs a high-side clamp voltage Vp, which is the internal power supply voltage Vp on the high-side, by connecting a Zener diode and a resistor in series between the power supply line 26 and the ground line 28. Here, since the steady-state voltage of the power supply voltage VCC is 14 volts, the high-side clamp voltage Vp is set to a predetermined voltage that is less than the gate breakdown voltage of the 14-volt power supply voltage VCC, for example, 6 volts, which is 8 volts lower, corresponding to the threshold voltage (gate-source voltage VGS) that turns on the P-type FET 60 and the gate breakdown voltage.

[0103] The high-side control signal E21 output from the signal conversion circuit 68 is always level-shifted in response to fluctuations in the power supply voltage VCC to a signal E24 that changes within a voltage range between the power supply voltage VCC and a high-side clamp voltage Vp that is a predetermined voltage lower than the power supply voltage VCC by less than the gate breakdown voltage, and is then input to the gate of the P-type FET 60.

[0104] Here, the P-type FET 60 that turns on at a gate-source voltage VGS of 8 volts, which is above the threshold voltage, is selected and used, and has a gate withstand voltage of a sufficiently large value, for example, 20 volts, relative to the steady-state voltage of the power supply voltage VCC of 14 volts.

[0105] Therefore, the control signal E24, which is the gate signal of the P-type FET 60, will always be a signal that changes within a voltage range of the fluctuating power supply voltage VCC and a voltage 8 volts lower than the power supply voltage VCC, as long as the power supply voltage does not fall below the high-side clamp voltage Vp of 6 volts, even if the power supply voltage VCC fluctuates, and the gate-source voltage VGS will never exceed the gate withstand voltage of 20 volts.

[0106] (d5.2-level shift) In this embodiment, the level shift of the high-side control signal E21 is a two-stage level shift performed by a high-side first level shift circuit 78 and a high-side second level shift circuit 80.

[0107] The high-side first level shift circuit 78 is similar to the low-side level shift circuit 72, and takes a high-side control signal E21 that changes within a voltage range between the internal power supply voltage of 5.8 volts and the ground voltage of 0 volts as input, and levels-shifts it to output a control signal E22 that changes within a voltage range between the low-side clamp voltage Vn = 12 volts and the ground voltage of 0 volts.

[0108] The high-side second level shift circuit 80 receives a high-side control signal E22 from the high-side first level shift circuit 78, which varies in a voltage range between a 12-volt low-side clamp voltage Vn and a ground voltage of 0 volts. It level-shifts this signal to a control signal E23, which varies in a voltage range between the power supply voltage VCC and a high-side clamp voltage Vp that is 8 volts lower, and inputs this control signal E24 to the gate of the P-type FET 60 via an inverter 82 that acts as a buffer.

[0109] In this way, the high-side control signal E21, which changes in a low voltage range between the internal power supply voltage of 5.8 volts and the ground voltage of 0 volts, is level-shifted in two stages by the high-side first level shift circuit 78 and the high-side second level shift circuit 80, thereby suppressing the voltage range caused by a single level shift and enabling stable level shifting.

[0110] [e. Operation of the output circuit] Next, we will explain the operation of the output circuit shown in Figure 6, separately for the case where the power supply voltage VCC is a steady-state voltage of 14 volts and the case where the power supply voltage exceeds the gate breakdown voltage, for example, when it is increased to 30 volts.

[0111] (e1. Operation at steady-state power supply voltage) The operation of the output circuit when the power supply voltage VCC is a steady voltage of 14 volts will be described. In this description, refer to Figure 7, which is a time chart showing the signal waveform of the output circuit when the steady voltage is 14 volts.

[0112] As shown in Figure 7, the input control signal E10 generated based on the U-phase comparator 32U is level-shifted into high-side and low-side signals under a steady-state voltage of 14 volts VCC. The high-side control signal E24 is a signal converted between the power supply voltage VCC (high level) and a high-side clamp voltage Vp (low level) that is 8 volts lower, while the low-side control signal E13 is a signal converted between a low-side clamp voltage Vn (high level) of 12 volts and a ground voltage of 0 volts (low level).

[0113] Then, the high-side control signal E24 is input to the gate of the P-type FET 60, and the low-side control signal E13 is input to the gate of the N-type FET 62. At the moment when the P-type FET 60 turns on and the N-type FET 62 turns off, a gate signal E1 is output that sets the 14-volt power supply voltage VCC to a high level. At this time, as the gate signal E1 rises from a low level to a high level, VCC current flows instantaneously. Also, at the moment when the P-type FET 60 turns off and the N-type FET 62 turns on, a gate signal E1 is output that sets the 0-volt ground voltage to a low level.

[0114] In this case, when the P-type FET 60 is off, the gate-source voltage VGS is 8 volts, which is below the gate withstand voltage of 20 volts. Similarly, when the N-type FET 62 is off, the gate-source voltage VGS is 12 volts, which is below the gate withstand voltage of 20 volts, ensuring stable battery charging control.

[0115] (e2. Operation at power supply voltages exceeding the gate withstand voltage) The operation of the output circuit when the power supply voltage increases beyond the gate withstand voltage will be explained. In this explanation, refer to Figure 8, a time chart showing the signal waveform of the output circuit when the power supply voltage is increased to 30 volts, which exceeds the gate withstand voltage.

[0116] When the AC output of the three-phase AC generator increases due to high engine speed, the battery charging voltage due to charge control temporarily increases, and consequently, the power supply voltage VCC also increases to a power supply voltage exceeding the 20-volt gate withstand voltage, for example, 30 volts, as shown in Figure 8.

[0117] In this case, the input control signal E10 is level-shifted into high-side and low-side signals when the power supply voltage VCC is increased to a power supply withstand voltage of 30 volts. The high-side control signal E24 is a signal that converts between the 30-volt power supply voltage VCC (high level) and the high-side clamp voltage Vp (low level), which is 8 volts lower. The low-side control signal E13 is a signal that converts between the 12-volt low-side clamp voltage Vn (high level) and the 0-volt ground voltage (low level).

[0118] Then, the high-side control signal E24 is input to the gate of the P-type FET 60, and the low-side control signal E13 is input to the gate of the N-type FET 62. When the P-type FET 60 turns on and the N-type FET 62 turns off, a gate signal E1 is output that sets the 30-volt power supply voltage VCC to a high level. Also, when the P-type FET 60 turns off and the N-type FET 62 turns on, a gate signal E1 is output that sets the 0-volt ground voltage to a low level.

[0119] In this case as well, when the P-type FET 60 is off, the gate-source voltage VGS is 8 volts, which is below the gate breakdown voltage of 20 volts. Similarly, when the N-type FET 62 is off, the gate-source voltage VGS is 12 volts, which is below the gate breakdown voltage of 20 volts. Even if the power supply voltage is increased to a power supply breakdown voltage of 30 volts, the gate-source voltage VGS will not exceed the gate breakdown voltage of 20 volts. This ensures stable battery charging control without causing degradation or damage to the P-type FET 60 and N-type FET 62.

[0120] [f. Output circuit with undervoltage protection circuit] Next, the low-voltage protection circuit in the output circuit shown in Figure 6 will be described. In this description, refer to Figure 9, which is a time chart showing the malfunction of the output circuit in Figure 6 at low voltage, Figure 10, which shows the circuit configuration of the output circuit with the low-voltage protection circuit, and Figure 11, which is a time chart showing the operation of the output circuit in Figure 10.

[0121] (f1. Malfunction due to low voltage) Figure 9 is a time chart showing the drive timing of the output circuit, indicating the drive timing from the start to the end of charging of the battery 14. The operation timing can be divided into the rising state at time t21-t22, the U-phase 1-cycle synchronous rectification control at time t22-t23, and the falling state at time t23-t24.

[0122] In the rising state, the U-phase 1-cycle synchronous rectification control is reset by the reset signal E5, which is at the H level, the gate signal E1 is at the L level, the U-phase switching element 2410 of the three-phase full-wave rectifier circuit 12 is turned off, and the U-phase generated voltage is rectified by the U-phase rectifier element 2210 to permanently charge the battery 14.

[0123] When the power supply voltage VCC reaches 8 volts at time t22 in the low voltage detection state, the reset signal E5 becomes L level, releasing the reset, and U-phase 1-cycle synchronous rectification control is performed, charging the power supply voltage VCC to a steady voltage of 14 volts.

[0124] In the falling edge state, if the power supply voltage falls below, for example, 7.5 volts at time t23, the reset signal E5 becomes high, resetting the U-phase 1-cycle synchronous rectification control. However, as the power supply voltage drops, the high-side control signal E24 remains undefined at a low level, causing a malfunction where it stays in the ON state, while the low-side control signal E13 enters normally and turns on at the correct timing. As a result, from time t23, both the P-type FET 60 and the N-type FET 62 turn on, and a through-current flows as VCC current. This causes the gate signal E1 to the U-phase switch element 2410 of the three-phase full-wave rectifier circuit 12 to be in a voltage state that is neither high nor low, leading to a malfunction where the operation of the three-phase full-wave rectifier circuit 12 becomes unstable.

[0125] (f2. Low voltage protection circuit) To prevent malfunction of the P-type FET 60 in the low-voltage detection state shown in Figure 9, a low-voltage protection circuit 84 is provided, as shown in the output circuit of Figure 10, and the output of the low-voltage protection circuit 84 is connected to the gate of the P-type FET 60.

[0126] As shown in the time chart in Figure 11, the low-voltage protection circuit 84 outputs a low-voltage protection signal E25 that increases linearly from the rising state at t21 until the power supply voltage VCC reaches 8 volts at time t22 and the reset is released, initiating three-phase one-cycle charging control.

[0127] Furthermore, the low-voltage protection circuit 84 outputs a linearly decreasing low-voltage protection signal E25 from the moment the power supply voltage VCC drops to 7.5 volts at time t23, resetting the U-phase 1-cycle synchronous rectification control. As a result, the high-side control signal E24 is maintained at an H level by the low-voltage protection signal E25, causing the P-type FET 60 to remain in the normally off state. Consequently, the gate signal E1 to the switching element 2410 of the three-phase full-wave rectifier circuit 12 becomes L level, and the three-phase full-wave rectifier circuit 12 operates stably.

[0128] [g. Semiconductor integrated circuit equipment] In the example configuration of the control circuit 20 shown in Figure 4, all or part of the control circuit 20, for example, the charge control unit 36 ​​in Figure 4, can be integrated into an integrated circuit, thereby reducing the number of components and the mounting area, and thus reducing costs. The circuit of this integrated circuit portion is formed on a CMOS semiconductor chip and commercialized as a semiconductor integrated device. Furthermore, the integrated semiconductor integrated circuit device and the other components mounted on a wiring board constitute the battery charging circuit that makes up the battery charging device.

[0129] [h. Variations of the invention] Modifications of the battery charging device according to the present invention will now be described. In addition to the embodiments described above, the battery charging device of the present invention includes the following modifications.

[0130] (High-side level shift circuit) The above embodiment configures the high-side level shift circuit in two stages, but is not limited to this, and may use one stage or three or more stages.

[0131] (others) Furthermore, the present invention includes appropriate modifications that do not impair its purpose and advantages, and is not limited by the numerical values ​​shown in the above embodiments.

[0132] For example, in the above embodiment, a "three-phase" system such as a three-phase AC generator is used as an example, but the technical concept of the present invention can be applied to other phases such as multi-phase or single-phase systems to achieve the desired effects. Furthermore, although the rectifier circuit is a full-wave rectifier circuit, the same desired effects can be achieved by applying it to a half-wave rectifier circuit. [Explanation of Symbols]

[0133] 10: Three-phase AC generator 12: Three-phase full-wave rectifier circuit 14: Battery 16: Load 18: Fuse 20: Control circuits 22: Rectifier element group 2210, 2212, 2214: Rectifier elements 24: Switching element group 2410, 2412, 2414: Switch elements 26: Power line 28: Grand Line 30U, 30V, 30W: Input terminal 32U, 32V, 32W: Comparator 34U, 34V, 34W: Switching section 35: Input Circuit Section 36: Charging Control Unit 37: Output Circuit Section 38U, 38V, 38W: Inverter 40U, 40V, 40W: Posi-edge one-shot 42U, 42V, 42W: Negative Edge One Shot 44U, 44V, 44W: AND circuit 46U, 46V, 46W: Latch 48U, 48V, 48W: NOR circuit 50, 50U, 50V, 50W: Level shift circuit section 52, 52U, 52V, 52W: Driver circuit 54U, 54V, 54W: Output terminals 56: Low voltage detection circuit 58: Overvoltage detection circuit 60:P type FET 62:N type FET 64: Input terminals 66: Reset terminal 68: Signal conversion circuit 70: Low-side clamp circuit 72: Low-side level shift circuit 74,82: Inverter 76: High-side clamp circuit 78: High-side first level shift circuit 80: High-side second level shift circuit 84: Low voltage protection circuit

Claims

1. A battery charging device that takes the output of an AC power source as input and charges the battery with a DC voltage rectified by a rectifier circuit equipped with a group of switching elements, The control circuit comprises an output circuit that controls the gates of the aforementioned switch element group, the positive terminal of the battery is connected to the power line, and the negative terminal of the battery is connected to the ground line. The output circuit includes a driver circuit in which a high-side P-type FET and a low-side N-type FET are complementaryly connected between the power line and the ground line. When the power supply voltage of the power supply line increases from a predetermined steady-state power supply voltage to a power supply voltage exceeding the gate breakdown voltage, a level shift circuit controls the driver circuit to protect the P-type FET and the N-type FET by maintaining the gate-source voltages of the P-type FET and the N-type FET below their respective gate breakdown voltages. A battery charging device characterized by comprising the following:

2. A battery charging device according to claim 1, The battery charging device is characterized by comprising a level shift circuit that converts an input control signal into a high-side control signal and a low-side control signal, levels shifts the high-side control signal to a control signal that changes within a voltage range between the power supply voltage of the power supply line and a voltage that is lower than the power supply voltage by a predetermined voltage less than the gate breakdown voltage of the P-type FET, and inputs it to the gate of the P-type FET, and levels shifts the low-side control signal to a control signal that changes within a voltage range between the ground voltage of the ground line and a voltage that is higher than the ground voltage by a predetermined voltage less than the gate breakdown voltage of the N-type FET, and inputs it to the gate of the N-type FET.

3. A battery charging device according to claim 2, The level shift circuit described above is A signal conversion circuit that converts the input control signal into a high-side control signal and a low-side control signal, A low-side clamp generation circuit generates a low-side clamp voltage that is higher by a predetermined voltage than the ground voltage of the ground line and less than the gate breakdown voltage of the N-type FET, A high-side clamp generation circuit generates a high-side clamp voltage that is lower by a predetermined voltage, which is less than the gate breakdown voltage of the P-type FET, than the power supply voltage of the power line. A low-side level shift circuit that levels-shifts the low-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the ground voltage and the low-side clamp voltage, and inputs it to the gate of the N-type FET, A high-side level shift circuit that levels-shifts the high-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the power supply voltage and the high-side clamp voltage, and inputs it to the gate of the P-type FET, A battery charging device characterized by having the following features.

4. A battery charging device according to claim 3, The aforementioned high-side level shift circuit is A first level shift circuit that level shifts the high-side control signal converted by the signal conversion circuit to a control signal that changes within the voltage range between the ground voltage and the low-side clamp voltage, A second level shift circuit that level shifts the control signal from the first level shift circuit to a control signal that changes within a voltage range between the power supply voltage and the high-side clamp voltage, A battery charging device characterized by having the following features.

5. A battery charging device according to claim 4, The battery charging device is characterized in that the control circuit includes a low-voltage protection circuit that maintains the P-type FET in the off state and allows it to operate normally when the power supply voltage drops, in response to a decrease in the power supply voltage, when the control circuit is transitioning from a predetermined power supply voltage to a predetermined low power supply voltage.

6. A battery charging circuit that takes the output of an AC power source as input and charges the battery with a DC voltage rectified by a rectifier circuit equipped with a group of switching elements, The control circuit comprises an output circuit that controls the gates of the aforementioned switch element group, and connects the positive terminal of the battery to a power line. The output circuit includes a driver circuit in which a high-side P-type FET and a low-side N-type FET are complementaryly connected between the power line and the ground line. When the power supply voltage of the power supply line increases from a predetermined steady-state power supply voltage to a power supply voltage exceeding the gate breakdown voltage, a level shift circuit controls the driver circuit to protect the P-type FET and the N-type FET by maintaining the gate-source voltages of the P-type FET and the N-type FET below their respective gate breakdown voltages. A battery charging circuit characterized by comprising the following:

7. A battery charging circuit according to claim 6, The battery charging circuit is characterized by comprising a level shift circuit that converts the input control signal into a high-side control signal and a low-side control signal, levels the high-side control signal to be input to the gate of the P-type FET, and levels the low-side control signal to be input to the gate of the N-type FET, and levels the low-side control signal to be input to the gate of the N-type FET, and levels the low-side control signal to be input to the gate of the N-type FET, and levels the output circuit to be input to the gate of the N-type FET.

8. A battery charging circuit according to claim 7, The level shift circuit described above is A signal conversion circuit that converts the input control signal into a high-side control signal and a low-side control signal, A low-side clamp generation circuit generates a low-side clamp voltage that is higher by a predetermined voltage than the ground voltage of the ground line and less than the gate breakdown voltage of the N-type FET, A high-side clamp generation circuit generates a high-side clamp voltage that is lower by a predetermined voltage, which is less than the gate breakdown voltage of the P-type FET, than the power supply voltage of the power line. A low-side level shift circuit that levels-shifts the low-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the ground voltage and the low-side clamp voltage, and inputs it to the gate of the N-type FET, A high-side level shift circuit that levels-shifts the high-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the power supply voltage and the high-side clamp voltage, and inputs it to the gate of the P-type FET, A battery charging circuit characterized by having the following features.

9. A battery charging circuit according to claim 8, The aforementioned high-side level shift circuit is A first level shift circuit that level shifts the high-side control signal converted by the signal conversion circuit to a control signal that changes within the voltage range between the ground voltage and the low-side clamp voltage, A second level shift circuit that level shifts the control signal from the first level shift circuit to a control signal that changes within a voltage range between the power supply voltage and the high-side clamp voltage, A battery charging circuit characterized by having the following features.

10. A battery charging circuit according to claim 9, The battery charging circuit is characterized in that, when the control circuit transitions from a predetermined power supply voltage to a predetermined low power supply voltage detection state, it includes a low voltage protection circuit that keeps the P-type FET in the off state in response to a drop in the power supply voltage, thereby enabling normal operation.

11. A semiconductor integrated circuit device comprising a control circuit that takes the output of an AC power source as input and controls a group of switch elements to charge a battery with a DC voltage rectified by a rectifier circuit equipped with a group of switch elements, The control circuit comprises an output circuit that controls the gate of the switch element group, and connects the positive terminal of the battery to the power line. The output circuit includes a driver circuit in which a high-side P-type FET and a low-side N-type FET are complementaryly connected between the power line and the ground line. When the power supply voltage of the power supply line increases from a predetermined steady-state power supply voltage to a power supply voltage exceeding the gate breakdown voltage, a level shift circuit controls the driver circuit to protect the P-type FET and the N-type FET by maintaining the gate-source voltages of the P-type FET and the N-type FET below their respective gate breakdown voltages. A semiconductor integrated circuit device characterized by comprising the following:

12. A semiconductor integrated circuit apparatus according to claim 11, The semiconductor integrated circuit apparatus is characterized by comprising a level shift circuit that converts an input control signal into a high-side control signal and a low-side control signal, levels shifts the high-side control signal to a control signal that changes within a voltage range between the power supply voltage of the power supply line and a voltage that is lower than the power supply voltage by a predetermined voltage less than the gate breakdown voltage of the P-type FET, and inputs it to the gate of the P-type FET, and levels shifts the low-side control signal to a control signal that changes within a voltage range between the ground voltage of the ground line and a voltage that is higher than the ground voltage by a predetermined voltage less than the gate breakdown voltage of the N-type FET, and inputs it to the gate of the N-type FET.

13. A semiconductor integrated circuit apparatus according to claim 12, The level shift circuit described above is A signal conversion circuit that converts the input control signal into a high-side control signal and a low-side control signal, A low-side clamp generation circuit generates a low-side clamp voltage that is higher by a predetermined voltage than the ground voltage of the ground line and less than the gate breakdown voltage of the N-type FET, A high-side clamp generation circuit generates a high-side clamp voltage that is lower by a predetermined voltage, which is less than the gate breakdown voltage of the P-type FET, than the power supply voltage of the power line. A low-side level shift circuit that levels-shifts the low-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the ground voltage and the low-side clamp voltage, and inputs it to the gate of the N-type FET, A high-side level shift circuit that levels-shifts the high-side control signal converted by the signal conversion circuit into a control signal that changes within the voltage range between the power supply voltage and the high-side clamp voltage, and inputs it to the gate of the P-type FET, A semiconductor integrated circuit device characterized by having the following features.

14. A semiconductor integrated circuit apparatus according to claim 13, The aforementioned high-side level shift circuit is A first level shift circuit that level shifts the high-side control signal converted by the signal conversion circuit to a control signal that changes within the voltage range between the ground voltage and the low-side clamp voltage, A second level shift circuit that level shifts the control signal from the first level shift circuit to a control signal that changes within a voltage range between the power supply voltage and the high-side clamp voltage, A semiconductor integrated circuit device characterized by having the following features.

15. A semiconductor integrated circuit apparatus according to claim 14, The semiconductor integrated circuit apparatus is characterized in that the control circuit includes a low-voltage protection circuit that maintains the P-type FET in the off state and allows it to operate normally when the power supply voltage drops, in response to a decrease in the power supply voltage, when the control circuit is transitioning from a predetermined power supply voltage to a predetermined low power supply voltage.

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