Display panel and display device

Abstract

The application discloses a display panel and a display device, and relates to the technical field of display. The display panel comprises a plurality of first pixel circuits and a plurality of second pixel circuits which are alternately arranged in each pixel circuit group, the design directions of the plurality of first pixel circuits and the plurality of second pixel circuits are opposite, and the plurality of first pixel circuits and the plurality of second pixel circuits are offset arranged in a first direction. Therefore, the distance between the first connection of the first pixel circuit and the second connection of the second pixel circuit in the first direction can be small. Further, the first signal line can be directly connected with the first connection and the second connection, and it is not necessary to design a switching hole between adjacent pixel circuits and to connect through a wiring layer. The scheme of the application can reduce the number of switching holes required to be designed in the layout, so that even if the requirement of PPI of the display panel is high, there is still enough space to design a small number of switching holes to realize the transmission of signals.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] An organic light-emitting diode (OLED) display panel has been widely applied due to its self-emitting, low driving voltage, and fast response speed. The OLED display panel generally includes a plurality of pixel units, each of which includes a light-emitting device and a pixel circuit connected to the light-emitting device.

[0003] In the related art, in order to improve the screen ratio of the display panel, the camera of the display device can be arranged in the display area of the display panel. In order to increase the transmittance of the area where the camera is located (i.e., the camera area), one or more wiring layers can be added, and a plurality of signal connection lines can be designed in the wiring layer to connect the pixel circuits of a row or a column of pixel units in the camera area. Thus, the driving circuit located in the peripheral area of the display panel can provide driving signals for the pixel circuits of the row or column of pixel units to drive the light-emitting device to emit light.

[0004] However, the pixel density (PPI) of the display panel is required to be high, and the space between adjacent pixel circuits is relatively small, so it is difficult to realize the signal connection between the pixel circuits. SUMMARY

[0005] The present application provides a display panel and a display device, which can solve the problem of difficulty in realizing signal connection between pixel circuits in the related art. The technical solution is as follows:

[0006] In one aspect, a display panel is provided, which includes:

[0007] a substrate substrate having a first display area, the first display area being configured to arrange an optical sensor;

[0008] A plurality of pixel circuit groups arranged along a first direction in the first display area, at least one of the pixel circuit groups comprising: a plurality of first pixel circuits arranged along a second direction and a plurality of second pixel circuits arranged along the second direction, and the plurality of first pixel circuits and the plurality of second pixel circuits being arranged alternately, each of the pixel circuits comprising a first boundary extending along the second direction and arranged along the first direction and a second boundary extending along the second direction and arranged along the first direction, the first boundary and the second boundary of the first pixel circuits being arranged in a direction opposite to the first boundary and the second boundary of the second pixel circuits, for each of the pixel circuit groups, a distance between the first boundary of the first pixel circuits and the first boundary of the second pixel circuits along the first direction being greater than a first distance, and a distance between the second boundary of the first pixel circuits and the second boundary of the second pixel circuits along the first direction being less than the first distance, the first distance being a distance between the first boundary and the second boundary of the same pixel circuit along the first direction;

[0009] and a plurality of first signal lines corresponding to the plurality of pixel circuit groups one by one, each of the first signal lines being connected to each of the first pixel circuits in a corresponding one of the pixel circuit groups at a first connection and being connected to each of the second pixel circuits in the corresponding one of the pixel circuit groups at a second connection;

[0010] wherein a distance between the first connection and the first boundary of the first pixel circuit is equal to a distance between the second connection and the first boundary of the second pixel circuit, a distance between the first connection and the second connection along the first direction being less than a second distance, the second distance being a distance between the first boundary of the first pixel circuit and the second boundary of the second pixel circuit along the first direction.

[0011] Optionally, the first signal lines are light-emitting control signal lines.

[0012] Optionally, the plurality of pixel circuit groups comprises at least a first pixel circuit group and a second pixel circuit group arranged along the first direction, a distance between the first boundary of the second pixel circuit in the first pixel circuit group and the first boundary of the first pixel circuit in the second pixel circuit group along the first direction being less than the second distance.

[0013] The display panel further comprises a plurality of second signal lines in the first display area, each of the second signal lines being connected to the second pixel circuit in the first pixel circuit group and being connected to the first pixel circuit in the second pixel circuit group.

[0014] Optionally, the substrate further has a second display area, the second display area at least partially surrounds the first display area; the display panel further comprises: a first connection wire in the second display area, the first connection wire at least partially surrounds the first display area.

[0015] Each of the second signal lines is connected to the first connection wire at least at one end, and each of the second signal lines transmits a signal received from the first connection wire to a pixel circuit connected to the second signal line.

[0016] Optionally, the second signal line is a first reset power line.

[0017] Optionally, the display panel further comprises: a plurality of third signal lines corresponding to the plurality of pixel circuit groups one by one;

[0018] Each of the third signal lines is connected to a first pixel circuit and a second pixel circuit in a corresponding one of the pixel circuit groups.

[0019] The third signal line transmits a signal different from the signal transmitted by the first signal line.

[0020] Optionally, each of the first pixel circuit and the second pixel circuit in each of the pixel circuit groups comprises:

[0021] A first transistor, a gate of the first transistor being connected to a first reset signal line, a first pole of the first transistor being connected to a first reset power line, and a second pole of the first transistor being connected to a second node;

[0022] A second transistor, a gate of the second transistor being connected to a first gate signal line included in the display panel, a first pole of the second transistor being connected to a third node, and a second pole of the second transistor being connected to the second node;

[0023] A third transistor, a gate of the third transistor being connected to the second node, a first pole of the third transistor being connected to a first node, and a second pole of the third transistor being connected to the third node;

[0024] A fourth transistor, a gate of the fourth transistor being connected to a second gate signal line included in the display panel, a first pole of the fourth transistor being connected to a data signal line included in the display panel, and a second pole of the fourth transistor being connected to the first node;

[0025] A fifth transistor, a gate of the fifth transistor being connected to an emission control signal line, a first pole of the fifth transistor being connected to a driving power line included in the display panel, and a second pole of the fifth transistor being connected to the first node.

[0026] a sixth transistor, a gate of the sixth transistor being connected with the light-emitting control signal line, a first pole of the sixth transistor being connected with the third node, and a second pole of the sixth transistor being connected with the light-emitting unit;

[0027] a seventh transistor, a gate of the seventh transistor being connected with a second gate signal line included in the display panel, a first pole of the seventh transistor being connected with a second reset power supply line, and a second pole of the seventh transistor being connected with the light-emitting unit;

[0028] a storage capacitor, one end of the storage capacitor being connected with the driving power supply line, and the other end of the storage capacitor being connected with the second node.

[0029] Optionally, the third signal line is the second gate signal line.

[0030] Optionally, the first transistor and the second transistor are oxide thin film transistors.

[0031] The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are low-temperature polysilicon thin film transistors.

[0032] Optionally, the display panel includes, in a direction away from the substrate substrate, an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a buffer layer, an oxide layer, a third gate insulating layer, a third gate layer, an interlayer dielectric layer, and a first source-drain layer, which are stacked in sequence and constitute the pixel circuit.

[0033] The second transistor is constituted by the second gate layer, the oxide layer, and the third gate layer.

[0034] The first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth thin film transistor are constituted by the active layer, the first gate layer, and the first source-drain layer.

[0035] Optionally, the display panel includes, in a direction away from the substrate substrate, an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a buffer layer, an oxide layer, a third gate insulating layer, a third gate layer, an interlayer dielectric layer, and a first source-drain layer, which are stacked in sequence and constitute the pixel circuit.

[0036] The first signal line is located in the first gate layer, and the second signal line is located in the first source-drain layer.

[0037] The third signal line comprises a first portion, a second portion and a third portion connected in sequence, a projection of the first portion on the substrate substrate at least partially overlaps with a projection of the first pixel circuit on the substrate substrate, a projection of the second portion on the substrate substrate does not overlap with the projection of the first pixel circuit on the substrate substrate and a projection of the second pixel circuit on the substrate substrate, and a projection of the third portion on the substrate substrate at least partially overlaps with the projection of the second pixel circuit on the substrate substrate; the first portion and the third portion are located in the first gate layer, and the second portion is located in the first source-drain layer.

[0038] Optionally, each of the first pixel circuit and the second pixel circuit included in each of the pixel circuit groups further comprises an eighth transistor, a gate of the eighth transistor is connected with the second reset signal line, a first pole of the eighth transistor is connected with a third reset power line included in the display panel, and a second pole of the eighth transistor is connected with the first node.

[0039] The third signal line is the third reset power line.

[0040] Optionally, the second transistor is an oxide thin film transistor.

[0041] The first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth transistor are low-temperature polysilicon thin film transistors.

[0042] Optionally, the display panel comprises, in a direction away from the substrate substrate, an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a buffer layer, an oxide layer, a third gate insulating layer, a third gate layer, an interlayer dielectric layer and a first source-drain layer which are stacked in sequence and constitute the pixel circuit.

[0043] The second transistor is composed of the second gate layer, the oxide layer and the third gate layer.

[0044] The first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor and the eighth thin film transistor are composed of the active layer, the first gate layer and the first source-drain layer.

[0045] Optionally, the display panel comprises, in a direction away from the substrate, an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a third gate insulating layer, an oxide layer, a fourth gate insulating layer, a third gate layer, an interlayer dielectric layer, and a first source-drain layer, which constitute the pixel circuit.

[0046] The first signal line is located in the first gate layer, the second signal line is located in the first source-drain layer, and the third signal line is located in the third gate layer.

[0047] Optionally, the display panel further comprises, in a direction away from the first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, a second source-drain layer, and a third planarization layer, which constitute the pixel circuit.

[0048] Optionally, each target signal line in the display panel comprises a first sub-signal line, a second sub-signal line, and a second connection wiring.

[0049] The first sub-signal line is located in the first display area, and the first sub-signal line is connected to a plurality of first pixel circuits in one pixel circuit group.

[0050] The second sub-signal line is located in the first display area, and the second sub-signal line is connected to a plurality of second pixel circuits in one pixel circuit group. The plurality of second pixel circuits connected by the second sub-signal line of each target signal line and the plurality of first pixel circuits connected by the first sub-signal line of the target signal line belong to the same pixel circuit group.

[0051] The second connection wiring is located in the second display area, one end of the second connection wiring is connected to the first sub-signal line, and the other end of the second connection wiring is connected to the second sub-signal line.

[0052] The target signal line is a signal line other than the first signal line, the second signal line, and the third signal line in the display panel, which provides a signal in the second direction.

[0053] Optionally, the first sub-signal line comprises a fourth part and a fifth part connected to each other. The fourth part is at least partially overlapped with the orthographic projection of the first pixel circuit on the substrate. The fifth part is located between the orthographic projections of two adjacent first pixel circuits on the substrate.

[0054] The second sub-signal line comprises a connected sixth portion and a seventh portion; a projection of the sixth portion on the substrate substrate at least partially overlaps with a projection of a second pixel circuit on the substrate substrate; a projection of the seventh portion on the substrate substrate is located between projections of two adjacent second pixel circuits on the substrate substrate;

[0055] The fourth portion and the sixth portion are located in the same layer, and the fourth portion and the sixth portion are located in a metal layer; the fifth portion and the seventh portion are located in the same layer, and the fifth portion and the seventh portion are located in a wire layer.

[0056] In another aspect, a display panel is provided, comprising:

[0057] A substrate substrate having a first display area for disposing an optical sensor;

[0058] A plurality of pixel circuit groups arranged along a first direction in the first display area, at least one of the pixel circuit groups comprising a plurality of first pixel circuits arranged along a second direction and a plurality of second pixel circuits arranged along the second direction, the plurality of first pixel circuits and the plurality of second pixel circuits being alternately arranged, each pixel circuit comprising a first boundary extending along the second direction and arranged along the first direction and a second boundary extending along the second direction and arranged along the first direction, the first boundary and the second boundary of the first pixel circuit being arranged in a direction opposite to the first boundary and the second boundary of the second pixel circuit, for each of the pixel circuit groups, a distance between the first boundary of the first pixel circuit and the first boundary of the second pixel circuit along the first direction is greater than a first distance, and a distance between the second boundary of the first pixel circuit and the second boundary of the second pixel circuit along the first direction is less than the first distance, the first distance being a distance between the first boundary and the second boundary of a same pixel circuit along the first direction;

[0059] And a plurality of first signal lines corresponding to the plurality of pixel circuit groups one by one, each of the first signal lines being connected to the first pixel circuit and the second pixel circuit in a corresponding one of the pixel circuit groups;

[0060] The first pixel circuit and the second pixel circuit in each of the adjacent two of the plurality of pixel circuit groups enclose a plurality of target areas, a projection of each of the target areas on the substrate substrate does not overlap with a projection of the first pixel circuit on the substrate substrate and a projection of the second pixel circuit on the substrate substrate, and a transmittance of the target area is greater than a transmittance of an area where the first pixel circuit and the second pixel circuit are located.

[0061] In yet another aspect, a display device is provided, which includes the display panel and the optical sensor according to the above aspects, and a projection of the optical sensor on the display panel at least partially overlaps the first display area in the display panel.

[0062] The technical solutions provided in the present application have at least the following beneficial effects:

[0063] The display panel and the display device provided in the present application include a plurality of first pixel circuits and a plurality of second pixel circuits in each pixel circuit group, which are arranged alternately, and the design directions of the plurality of first pixel circuits and the plurality of second pixel circuits are opposite and offset in the first direction. In this way, the distance between the first connection of the first pixel circuit and the second connection of the second pixel circuit in the first direction can be small. Further, the first signal line can be directly connected with the first connection and the second connection, without the need to design a switching hole between adjacent pixel circuits and connect through a wiring layer. The solutions provided in the present application can reduce the number of switching holes required to be designed in the layout, so that even if the requirement for the PPI of the display panel is high, there is still enough space to design a small number of switching holes to realize the transmission of signals. BRIEF DESCRIPTION OF DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0065] Figure 1 is a top view of a display panel provided by an embodiment of the present application;

[0066] Figure 2 is Figure 1 is a partial structure schematic diagram of the display panel in the first display area;

[0067] Figure 3 is a partial structure schematic diagram of a second signal line and a first connection wiring provided by an embodiment of the present application;

[0068] Figure 4 is a partial structure schematic diagram of another display panel provided by an embodiment of the present application;

[0069] Figure 5 is Figure 4 is an equivalent circuit diagram of a pixel circuit in the display panel;

[0070] Figure 6 is a timing diagram of each signal line in a pixel circuit provided by an embodiment of the present application;

[0071] Figure 7 is a cross-sectional view of a display panel provided by an embodiment of the present application;

[0072] Figure 8 is a partial schematic view of an active layer in a display panel provided by an embodiment of the present application;

[0073] Figure 9 is a partial schematic view of a first gate layer in a display panel provided by an embodiment of the present application;

[0074] Figure 10 is a partial superimposed schematic view of an active layer and a first gate layer in a display panel provided by an embodiment of the present application;

[0075] Figure 11 is a partial schematic view of a second gate layer in a display panel provided by an embodiment of the present application;

[0076] Figure 12 is a partial superimposed schematic view of an active layer, a first gate layer and a second gate layer in a display panel provided by an embodiment of the present application;

[0077] Figure 13 is a partial schematic view of an oxide layer in a display panel provided by an embodiment of the present application;

[0078] Figure 14 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer and an oxide layer in a display panel provided by an embodiment of the present application;

[0079] Figure 15 is a partial schematic view of a third gate layer in a display panel provided by an embodiment of the present application;

[0080] Figure 16 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer and a third gate layer in a display panel provided by an embodiment of the present application;

[0081] Figure 17 is a partial schematic view of a first interlayer dielectric layer in a display panel provided by an embodiment of the present application;

[0082] Figure 18 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer and a first interlayer dielectric layer in a display panel provided by an embodiment of the present application;

[0083] Figure 19 is a partial schematic view of a second interlayer dielectric layer in a display panel provided by an embodiment of the present application;

[0084] Figure 20 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, and a second interlayer dielectric layer in a display panel provided by an embodiment of the present application;

[0085] Figure 21 is a partial schematic view of a first source-drain layer in a display panel provided by an embodiment of the present application;

[0086] Figure 22 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, and a first source-drain layer in a display panel provided by an embodiment of the present application;

[0087] Figure 23 is a partial schematic view of a passivation layer in a display panel provided by an embodiment of the present application;

[0088] Figure 24 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, and a passivation layer in a display panel provided by an embodiment of the present application;

[0089] Figure 25 is a partial schematic view of a first wiring layer in a display panel provided by an embodiment of the present application;

[0090] Figure 26 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, and a first wiring layer in a display panel provided by an embodiment of the present application;

[0091] Figure 27 is a partial schematic view of a first planarization layer in a display panel provided by an embodiment of the present application;

[0092] Figure 28 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, and a first planarization layer in a display panel provided by an embodiment of the present application;

[0093] Figure 29 is a partial schematic view of a second wiring layer in a display panel provided by an embodiment of the present application;

[0094] Figure 30is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer interlayer dielectric layer, a second layer interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, and a second wiring layer in a display panel provided by an embodiment of the present application;

[0095] Figure 31 is a partial schematic view of a second planarization layer in a display panel provided by an embodiment of the present application;

[0096] Figure 32 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer interlayer dielectric layer, a second layer interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, and a second planarization layer in a display panel provided by an embodiment of the present application;

[0097] Figure 33 is a partial schematic view of a second source-drain layer in a display panel provided by an embodiment of the present application;

[0098] Figure 34 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer interlayer dielectric layer, a second layer interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, and a second source-drain layer in a display panel provided by an embodiment of the present application;

[0099] Figure 35 is a partial schematic view of a third planarization layer in a display panel provided by an embodiment of the present application;

[0100] Figure 36 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer interlayer dielectric layer, a second layer interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, a first source-drain layer, and a third planarization layer in a display panel provided by an embodiment of the present application;

[0101] Figure 37 is a partial schematic view of an anode layer in a display panel provided by an embodiment of the present application;

[0102] Figure 38 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer interlayer dielectric layer, a second layer interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, a second source-drain layer, a third planarization layer, and an anode layer in a display panel provided by an embodiment of the present application;

[0103] Figure 39 is a schematic diagram of a partial structure of a display panel provided by an embodiment of the present application;

[0104] Figure 40 is a schematic diagram of a partial structure of a display panel provided by an embodiment of the present application;

[0105] Figure 41 is Figure 39 or Figure 40 is an equivalent circuit diagram of a pixel circuit in the display panel shown in FIG. 1;

[0106] Figure 42 is a timing diagram of various signal lines in another pixel circuit provided by an embodiment of the present application;

[0107] Figure 43 is a partial schematic diagram of an active layer in another display panel provided by an embodiment of the present application;

[0108] Figure 44 is a partial schematic diagram of a first gate layer in another display panel provided by an embodiment of the present application;

[0109] Figure 45 is a partial superimposed schematic diagram of an active layer and a first gate layer in another display panel provided by an embodiment of the present application;

[0110] Figure 46 is a partial schematic diagram of a second gate layer in another display panel provided by an embodiment of the present application;

[0111] Figure 47 is a partial superimposed schematic diagram of an active layer, a first gate layer and a second gate layer in another display panel provided by an embodiment of the present application;

[0112] Figure 48 is a partial schematic diagram of an oxide layer in another display panel provided by an embodiment of the present application;

[0113] Figure 49 is a partial superimposed schematic diagram of an active layer, a first gate layer, a second gate layer and an oxide layer in another display panel provided by an embodiment of the present application;

[0114] Figure 50 is a partial schematic diagram of a third gate layer in another display panel provided by an embodiment of the present application;

[0115] Figure 51 is a partial superimposed schematic diagram of an active layer, a first gate layer, a second gate layer, an oxide layer and a third gate layer in another display panel provided by an embodiment of the present application;

[0116] Figure 52 FIG. 3 is a partial schematic view of a first interlayer dielectric layer in another display panel according to embodiments of the present application;

[0117] Figure 53 FIG. 4 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, and a first interlayer dielectric layer in another display panel according to embodiments of the present application;

[0118] Figure 54 FIG. 5 is a partial schematic view of a second interlayer dielectric layer in another display panel according to embodiments of the present application;

[0119] Figure 55 FIG. 6 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, and a second interlayer dielectric layer in another display panel according to embodiments of the present application;

[0120] Figure 56 FIG. 7 is a partial schematic view of a first source-drain layer in another display panel according to embodiments of the present application;

[0121] Figure 57 FIG. 8 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, and a first source-drain layer in another display panel according to embodiments of the present application;

[0122] Figure 58 FIG. 9 is a partial schematic view of a passivation layer in another display panel according to embodiments of the present application;

[0123] Figure 59 FIG. 10 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, and a passivation layer in another display panel according to embodiments of the present application;

[0124] Figure 60 FIG. 11 is a partial schematic view of a first wiring layer in another display panel according to embodiments of the present application;

[0125] Figure 61 FIG. 12 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, and a first wiring layer in another display panel according to embodiments of the present application;

[0126] Figure 62 FIG. 13 is a partial schematic view of a first planarization layer in another display panel according to embodiments of the present application;

[0127] Figure 63 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer of interlayer dielectric, a second layer of interlayer dielectric, a first source-drain layer, a passivation layer, a first wiring layer, and a first planarization layer in another display panel provided by an embodiment of the present application;

[0128] Figure 64 is a partial schematic view of a second wiring layer in another display panel provided by an embodiment of the present application;

[0129] Figure 65 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer of interlayer dielectric, a second layer of interlayer dielectric, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, and a second wiring layer in another display panel provided by an embodiment of the present application;

[0130] Figure 66 is a partial schematic view of a second planarization layer in another display panel provided by an embodiment of the present application;

[0131] Figure 67 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer of interlayer dielectric, a second layer of interlayer dielectric, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, and a second planarization layer in another display panel provided by an embodiment of the present application;

[0132] Figure 68 is a partial schematic view of a second source-drain layer in another display panel provided by an embodiment of the present application;

[0133] Figure 69 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer of interlayer dielectric, a second layer of interlayer dielectric, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, and a second source-drain layer in another display panel provided by an embodiment of the present application;

[0134] Figure 70 is a partial schematic view of a third planarization layer in another display panel provided by an embodiment of the present application;

[0135] Figure 71 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer of interlayer dielectric, a second layer of interlayer dielectric, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, a first source-drain layer, and a third planarization layer in another display panel provided by an embodiment of the present application;

[0136] Figure 72 is a partial schematic view of an anode layer in another display panel provided by embodiments of the present application;

[0137] Figure 73 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, a second source-drain layer, a third planarization layer, and an anode layer in another display panel provided by embodiments of the present application;

[0138] Figure 74 is a partial structural schematic view of still another display panel provided by embodiments of the present application;

[0139] Figure 75 is a partial cross-sectional view of a first sub-signal line provided by embodiments of the present application;

[0140] Figure 76 is a partial schematic view of a first gate layer of yet another display panel provided by embodiments of the present application;

[0141] Figure 77 is a partial superimposed schematic view of an active layer and a first gate layer of yet another display panel provided by embodiments of the present application;

[0142] Figure 78 is a partial schematic view of a second gate layer of yet another display panel provided by embodiments of the present application;

[0143] Figure 79 is a partial superimposed schematic view of an active layer, a first gate layer, and a second gate layer of yet another display panel provided by embodiments of the present application;

[0144] Figure 80 is a partial schematic view of an oxide layer of yet another display panel provided by embodiments of the present application;

[0145] Figure 81 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, and an oxide layer of yet another display panel provided by embodiments of the present application;

[0146] Figure 82 is a partial schematic view of a third gate layer of yet another display panel provided by embodiments of the present application;

[0147] Figure 83 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, and a third gate layer of yet another display panel provided by embodiments of the present application;

[0148] Figure 84 is a partial structural diagram of a first source-drain layer of a display panel provided by an embodiment of the present application;

[0149] Figure 85 is a partial stack diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, and a first source-drain layer of a display panel provided by an embodiment of the present application;

[0150] Figure 86 is a partial structural diagram of a first wiring layer of a display panel provided by an embodiment of the present application;

[0151] Figure 87 is a partial stack diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, and a first wiring layer of a display panel provided by an embodiment of the present application;

[0152] Figure 88 is a partial structural diagram of a second wiring layer provided by an embodiment of the present application;

[0153] Figure 89 is a partial stack diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a first wiring layer, a first planar layer, and a second wiring layer of a display panel provided by an embodiment of the present application;

[0154] Figure 90 is a partial stack diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a first wiring layer, a first planar layer, a second wiring layer, and a second planar layer of a display panel provided by an embodiment of the present application;

[0155] Figure 91 is a partial stack diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a first wiring layer, a first planar layer, a second wiring layer, a second planar layer, and a second source-drain layer of a display panel provided by an embodiment of the present application;

[0156] Figure 92 is a partial stack diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a first wiring layer, a first planar layer, a second wiring layer, a second planar layer, a second source-drain layer, and a third planar layer of a display panel provided by an embodiment of the present application;

[0157] Figure 93 is a partial stack diagram of a local layer of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, a second source-drain layer, a third planarization layer, and an anode layer provided by an embodiment of the present application;

[0158] Figure 94 is a partial structure diagram of a display panel provided by another embodiment of the present application;

[0159] Figure 95 is a structure diagram of a display device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0160] To make the purpose, technical solutions and advantages of the present application clearer, the embodiments of the present application will be further described in detail below with reference to the drawings.

[0161] Figure 1 is a top view of a display panel provided by an embodiment of the present application. Referring to Figure 1 , the substrate 101 of the display panel 10 can have a first display area 10a. The first display area 10a can be used to set an optical sensor. Optionally, the optical sensor can be a front camera, and the first display area 10a can be referred to as a full display with camera (FDC) area.

[0162] Figure 2 is a partial structure diagram of a display panel as shown in Figure 1 . Referring to Figure 2 , the display panel 10 can include a substrate 101, a plurality of pixel circuit groups 102, and a plurality of first signal lines 103 corresponding to the plurality of pixel circuit groups 102 one by one.

[0163] In the embodiments of the present application, the plurality of pixel circuit groups 102 are located in the first display area 10a and arranged along a first direction X. At least one pixel circuit group 102 includes a plurality of first pixel circuits 1021 arranged along a second direction Y and a plurality of second pixel circuits 1022 arranged along the second direction Y. Wherein, the first direction X and the second direction Y are perpendicular, for example, the first direction X is a pixel column direction, and the second direction Y is a pixel row direction.

[0164] The first and second pixel circuit groups 1021 and 1022 are alternately arranged, and each pixel circuit in the first and second pixel circuit groups 1021 and 1022 includes a first boundary and a second boundary extending along the second direction Y and arranged along the first direction X. The arrangement direction of the first and second boundaries 1021a and 1021b of the first pixel circuit 1021 is opposite to the arrangement direction of the first and second boundaries 1022a and 1022b of the second pixel circuit 1022.

[0165] For each pixel circuit group 102, the distance between the first boundary 1021a of the first pixel circuit 1021 and the first boundary 1022a of the second pixel circuit 1022 along the first direction X is greater than the first distance H1, and the distance between the second boundary 1021b of the first pixel circuit 1021 and the second boundary 1022b of the second pixel circuit 1022 along the first direction X is less than the first distance H1. The first distance H1 is the distance between the first and second boundaries of the same pixel circuit along the first direction X, such as the distance between the first and second boundaries of the first pixel circuit 1021 or the second pixel circuit 1022 along the first direction X. The distance between the first and second boundaries 1021a and 1021b of the first pixel circuit 1021 along the first direction X is equal to the distance between the first and second boundaries 1022a and 1022b of the second pixel circuit 1022 along the first direction X.

[0166] The first boundary 1021a of the first pixel circuit 1021 can correspond to the first boundary 1022a of the second pixel circuit 1022, and the second boundary 1021b of the first pixel circuit 1021 can correspond to the second boundary 1022b of the second pixel circuit 1022. The correspondence between the two boundaries can refer to the structure of the pixel circuit at the position of the two boundaries being the same structure. The design direction of the first and second pixel circuit groups 1021 and 1022 is opposite. Assuming that the design direction of the first pixel circuit 1021 is referred to as the positive direction, the design direction of the second pixel circuit 1022 can be referred to as the reverse direction. Alternatively, assuming that the design direction of the first pixel circuit 1021 is referred to as the reverse direction, the design direction of the second pixel circuit 1022 can be referred to as the positive direction.

[0167] In the embodiments of the present application, the first or second boundary of the pixel circuit 1021 is described and represented as the pixel circuit 1021 having a strict boundary division, and the boundary of the pixel circuit 1021 is not Figure 1The illustrated strict rectangle. In the embodiments of the present application, the boundary of the pixel circuit 1021 can refer to the boundary of the smallest region of the plurality of patterns constituting the pixel circuit 1021, which can be the minimum circumscribed figure of the pixel circuit. Thus, the first boundary and the second boundary of the pixel circuit 1021 can be the two boundaries farthest apart from each other in the first direction X.

[0168] Thus, the above arrangement of the first pixel circuit 1021 and the second pixel circuit 1022 can make the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 have a certain offset in the first direction X. After the offset, the second boundary 1021b of the plurality of first pixel circuits 1021 and the second boundary 1022b of the plurality of second pixel circuits 1022 are both located between the extension line of the first boundary 1021a of the first pixel circuit 1021 and the extension line of the first boundary 1022a of the second pixel circuit 1022.

[0169] In the embodiments of the present application, each first signal line 103 can be a one-piece structure, and can be connected to the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 included in the corresponding one pixel circuit group 102, so as to provide signals for all pixel circuits located in the first display area 10a included in the corresponding one pixel circuit group 102. Wherein, the first signal line 103 being a one-piece structure can mean that the portion of the first signal line 103 in the first display area 10a is located in only one film layer of the display panel 10, without the need to change layers.

[0170] Optionally, since the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 are offset arranged in the first direction X and the design directions are opposite, the connection positions of the first signal line 103 with the plurality of first pixel circuits 1021 and the connection positions of the first signal line 103 with the plurality of second pixel circuits 1022 can also have a certain offset in the first direction X. For example, each first signal line 103 is connected with each first pixel circuit 1021 in the corresponding one pixel circuit group 102 at a first connection position (i.e., the connection position of the first pixel circuit 1021 is referred to as the first connection position), and the first signal line 103 is connected with each second pixel circuit 1022 in the corresponding one pixel circuit group 102 at a second connection position (i.e., the connection position of the second pixel circuit 1022 is referred to as the second connection position).

[0171] Wherein, the position of the first connection position of the first pixel circuit 1021 corresponds to the position of the second connection position of the second pixel circuit 1022. That is, the distance w1 between the first connection position and the first boundary of the first pixel circuit 1021 is equal to the distance w1 between the second connection position and the first boundary of the second pixel circuit 1022.

[0172] In the embodiment of the present application, by making the design directions of the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 different, having a certain offset in the first direction X, and being arranged alternately, the distance of the first connection and the second connection in the first direction X can be small, such as being on the same horizontal line or near the same horizontal line in the second direction Y.

[0173] The first connection and the second connection in the first direction X can be smaller than the second distance H2. The second distance H2 is the distance of the first boundary 1021a of the first pixel circuit 1021 and the second boundary 1022b of the second pixel circuit 1022 in the first direction X (i.e. the offset distance of the first pixel circuit 1021 and the second pixel circuit 1022 in the first direction X). In this way, the first signal line 103 can be directly connected with the pixel circuits (the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022) in the pixel circuit group 102, without the need to design a transfer hole between adjacent pixel circuits and connect through a wiring layer. Further, the number of transfer holes required to be designed in the layout can be reduced, and even if the requirement of the PPI of the display panel is high, there is still enough space to design a small number of transfer holes to realize the transmission of signals.

[0174] In summary, the embodiment of the present application provides a display panel, which includes a plurality of first pixel circuits and a plurality of second pixel circuits in each pixel circuit group, the plurality of first pixel circuits and the plurality of second pixel circuits in each pixel circuit group are arranged alternately, the design directions of the plurality of first pixel circuits and the plurality of second pixel circuits in each pixel circuit group are opposite, and the plurality of first pixel circuits and the plurality of second pixel circuits are arranged offset in the first direction. In this way, the distance of the first connection of the first pixel circuit and the second connection of the second pixel circuit in the first direction can be small. Further, the first signal line can be directly connected with the first connection and the second connection, without the need to design a transfer hole between adjacent pixel circuits and connect through a wiring layer. The scheme of the embodiment of the present application can reduce the number of transfer holes required to be designed in the layout, and even if the requirement of the PPI of the display panel is high, there is still enough space to design a small number of transfer holes to realize the transmission of signals.

[0175] Optionally, the first signal line 103 can be a light-emitting control signal line EM.

[0176] Reference Figure 1It can also be seen that the plurality of pixel circuit groups 102 at least include a first pixel circuit group 102a and a second pixel circuit group 102b arranged along the first direction X. Among them, the distance between the first boundary 1022a of the second pixel circuit 1022 in the first pixel circuit group 102a and the first boundary 1021a of the first pixel circuit 1021 in the second pixel circuit group 102b along the first direction X is less than the second distance H2. That is, the distance between the second pixel circuit 1022 in the first pixel circuit group 102a and the first pixel circuit 1021 in the second pixel circuit 1022 along the first direction X is closer.

[0177] Therefore, the display panel 10 further includes a plurality of second signal lines 104 located in the first display area 10a. Each second signal line 104 is connected with the second pixel circuit 1022 in the first pixel circuit group 102a and the first pixel circuit 1021 in the second pixel circuit group 102b. Therefore, the second signal line 104 can simultaneously provide signals for the second pixel circuit 1022 in the first pixel circuit group 102a and the first pixel circuit 1021 in the second pixel circuit group 102b. Optionally, the second signal line 104 can be the first reset power line vinit1.

[0178] Reference Figure 1 The substrate 101 of the display panel 10 further has a second display area 10b which at least partially surrounds the first display area 10a. Figure 3 is another partial structure schematic diagram of a display panel provided by the embodiments of the present application. Reference Figure 3 The display panel 10 further includes a first connection trace 105 located in the second display area 10b. The first connection trace 105 at least partially surrounds the first display area 10a. For example, taking the first display area 10a as a rectangle as an example, the first connection trace 105 is a rectangular ring trace which can surround the first display area 10a. Figure 3 In the above-mentioned embodiments, the second signal line is simply illustrated as a straight line. In fact, the second signal line is not a straight line, and this is hereby stated.

[0179] Among them, at least one end of each second signal line 104 in the plurality of second signal lines 104 is connected with the first connection trace 105, such as Figure 3 In the above-mentioned embodiments, both ends of each second signal line 104 are connected with the first connection trace. Each second signal line 104 transmits the signal received from the first connection trace 105 to the pixel circuit connected with the second signal line 104. Since each second signal line 104 in the plurality of second signal lines 104 is connected with the first connection trace 105, the signals transmitted by the plurality of second signal lines 104 connected with the first connection trace 105 can be the same signal. Among them, the same signal can mean that the signal type and the signal potential are the same.

[0180] Referring to Figure 1 The display panel 10 can further include a plurality of third signal lines 106 corresponding to the plurality of pixel circuit groups 102 one-to-one. Each third signal line 106 can be connected with the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 included in the corresponding one pixel circuit group 102, so as to provide signals for the first pixel circuits 1021 and the second pixel circuits 1022 included in the corresponding one pixel circuit group 102.

[0181] The third signal line 106 can be an integral structure or can not be an integral structure. The third signal line 106 being an integral structure can mean that the third signal line 106 in the first display area 10a is located in only one film layer of the display panel, without layer switching. The third signal line 106 not being an integral structure can mean that the third signal line 106 in the first display area 10a needs to be designed by layer switching, and the film layer where the third signal line 106 is located is a metal layer.

[0182] The third signal line 106 can be an integral structure or can not be an integral structure. The third signal line 106 being an integral structure can mean that the third signal line 106 in the first display area 10a is located in only one film layer of the display panel, without layer switching. The third signal line 106 not being an integral structure can mean that the third signal line 106 in the first display area 10a needs to be designed by layer switching, and the film layer where the third signal line 106 is located is a metal layer.

[0183] As a first optional implementation, each pixel circuit group 102 includes a plurality of first pixel circuits 1021 and a plurality of second pixel circuits 1022, and each pixel circuit in the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 includes eight transistors and one storage capacitor Cst (i.e., 8T1C), for example Figure 4 . Figure 4 In order to clearly show the pixel circuit, only the first source-drain layer is shown, and the film layer on the side of the first source-drain layer away from the substrate 101 is not shown.

[0184] Figure 5 is Figure 4 the equivalent circuit diagram of a pixel circuit in the display panel shown in FIG. 8. Referring to Figure 5 , the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a storage capacitor Cst.

[0185] The gate of the first transistor T1 is connected with a first reset signal line Preset included in the display panel, the first electrode of the first transistor T1 is connected with a first reset power line vinit1, and the second electrode of the first transistor T1 is connected with the third node N3. The first transistor T1 can also be referred to as a reset transistor.

[0186] The gate of the second transistor T2 is connected with a first gate signal line Gate_N included in the display panel, the first electrode of the second transistor T2 is connected with the third node N3, and the second electrode of the second transistor T2 is connected with the second node N2. The second transistor T2 can also be referred to as a compensation transistor.

[0187] The gate of the third transistor T3 is connected with the second node N2, the first electrode of the third transistor T3 is connected with the first node N1, and the second electrode of the third transistor T3 is connected with the third node N3. The third transistor T3 can also be referred to as a driving transistor.

[0188] The gate of the fourth transistor T4 is connected with a second gate signal line Gate_P included in the display panel, the first electrode of the fourth transistor T4 is connected with a data signal line Data included in the display panel, and the second electrode of the fourth transistor T4 is connected with the first node N1. The fourth transistor T4 can be a data writing transistor in a pixel circuit.

[0189] The gate of the fifth transistor T5 is connected with an emission control signal line EM, the first electrode of the fifth transistor T5 is connected with a driving power line VDD, and the second electrode of the fifth transistor T5 is connected with the first node N1. Since the gate of the fifth transistor T5 is connected with the emission control signal line EM, the fifth transistor T5 can also be referred to as an emission control transistor.

[0190] The gate of the sixth transistor T6 is connected with the emission control signal line EM, the first electrode of the sixth transistor T6 is connected with the third node N3, and the second electrode of the sixth transistor T6 is connected with an emission unit. Since the gate of the sixth transistor T6 is connected with the emission control signal line EM, the sixth transistor T6 can also be referred to as an emission control transistor.

[0191] The gate of the seventh transistor T7 is connected with a second reset signal line Preset_H included in the display panel, the first electrode of the seventh transistor T7 is connected with a second reset power line vinit2, and the second electrode of the seventh transistor T7 is connected with the emission unit. The seventh transistor T7 can be a reset transistor in a pixel circuit.

[0192] The gate of the eighth transistor T8 is connected to the second reset signal line Preset_H, the first terminal of the eighth transistor T8 is connected to the third reset power supply line vinit3 included in the display panel, and the second terminal of the eighth transistor T8 is connected to the first node N1. The eighth transistor T8 can be a reset transistor in a pixel circuit.

[0193] One end of the storage capacitor Cst is connected to the drive power line VDD, and the other end of the storage capacitor Cst is connected to the second node N2.

[0194] Optionally, the storage capacitor Cst may include two capacitor plates Cst1 and Cst2. In the embodiments of this application, capacitor plate Cst1 may be referred to as one end, the first end, or the first storage capacitor electrode of the storage capacitor Cst, and capacitor plate Cst2 may be referred to as the other end, the second end, or the second storage capacitor electrode of the storage capacitor Cst.

[0195] In this embodiment, the third signal line 106 can be a third reset power supply line vinit3. That is, when the pixel circuit includes eight transistors and a storage capacitor Cst, the aforementioned third signal line 106 can be a third reset power supply line vinit3. This third reset power supply line vinit3 can provide a third reset power signal to a plurality of first pixel circuits 1021 and a plurality of second pixel circuits 1022 in a pixel circuit group 102.

[0196] Optionally, the second transistor T2 is an N-type transistor. The first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all P-type transistors.

[0197] Optionally, each N-type transistor described in the embodiments of this application can be an oxide thin-film transistor, and each P-type transistor can be an LTPS thin-film transistor. The oxide material can include indium gallium zinc oxide (IGZO), that is, the oxide thin-film transistor can be an IGZO thin-film transistor. The pixel circuit composed of these 8 transistors can also be called an LTPO pixel circuit. A display panel whose pixel circuit is this LTPO pixel circuit can be called an LTPO display panel.

[0198] by Figure 5 Taking the pixel circuit shown as an example, where the first potential is higher than the second potential, the driving principle of the pixel circuit described in the embodiments of this application will be introduced as follows. Figure 6 This is a timing diagram of each signal line in a pixel circuit provided in an embodiment of this application. For example... Figure 6 As shown:

[0199] In the initialization stage t1, the potential of the first reset signal provided by the first reset signal line Preset, the potential of the second gate driving signal provided by the second gate signal line Gate_P, and the potential of the light emitting control signal provided by the light emitting control signal line EM are all the first potential. The potential of the first gate driving signal provided by the first gate signal line Gate_N and the potential of the second reset signal provided by the second reset signal line Preset_H are both the second potential. Correspondingly, the seventh transistor T7 and the eighth transistor T8 are turned on. The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are all turned off. In this way, the second reset power signal of the second potential provided by the second reset power supply line vinit2 can be transmitted to the anode of the light emitting unit through the turned-on seventh transistor T7, and the third reset power signal of the second potential provided by the third reset power supply line vinit3 can be transmitted to the first node N1 through the turned-on eighth transistor T8, so as to reset the anode of the light emitting unit and the first node N1.

[0200] In the compensation stage t2, the potential of the first reset signal provided by the first reset signal line Preset jumps to the second potential, the potential of the first gate driving signal provided by the first gate signal line Gate_N jumps to the first potential, and the potential of the light emitting control signal provided by the light emitting control signal line EM remains the first potential. Correspondingly, the first transistor T1 and the second transistor T2 are both turned on, and the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all turned off. In this way, the data signal of the first potential can be transmitted to the first node N1 through the turned-on fourth transistor T4, and then transmitted to the third node N3 through the turned-on third transistor T3, and the second transistor T2 adjusts the potential of the second node N2 based on the potential of the third node N3. In addition, the reset power signal of the second potential provided by the first reset power supply line vinit1 can be transmitted to the second node N2 through the turned-on first transistor T1 and the second transistor T2, so as to reset the second node N2.

[0201] In the writing stage t3, the potential of the first reset signal provided by the first reset signal line Preset jumps to the second potential, the potential of the second reset signal provided by the second reset signal line Preset_H remains the second potential, the potential of the second gate driving signal provided by the second gate signal line Gate_P jumps to the first potential, the first gate signal line Gate_N remains the second potential, and the potential of the light emitting control signal provided by the light emitting control signal line EM remains the first potential. Under the bootstrap action of the storage capacitor Cst, the potential of the second node N2 remains the second potential. Correspondingly, the second transistor T2, the third transistor T3 and the fourth transistor T4 are turned on, and the first transistor T1, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 are turned off. In this way, the data signal provided by the data signal line Data can be transmitted to the second node N2 through the fourth transistor T4, the third transistor T3 and the second transistor T2 which are turned on in sequence.

[0202] In the light emitting stage t4, the potential of the first reset signal provided by the first reset signal line Preset remains the second potential, the potential of the second reset signal provided by the second reset signal line Preset_H remains the second potential, the potential of the second gate driving signal provided by the second gate signal line Gate_P jumps to the first potential, the first gate signal line Gate_N jumps to the first potential, and the potential of the light emitting control signal provided by the light emitting control signal line EM jumps to the first potential. Under the bootstrap action of the storage capacitor Cst, the potential of the second node N2 remains the second potential of the data signal line Data. Correspondingly, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4, the seventh transistor T7 and the eighth transistor T8 are turned off. In this way, the driving power signal provided by the driving power supply line VDD can be transmitted to the first node N1 through the turned-on fifth transistor T5, and the third transistor T3 can transmit a driving current to the third node N3 based on the potential of the second node N2 and the potential transmitted to the first node N1. Then, the driving current can be transmitted to the anode of the light emitting unit through the turned-on sixth transistor T6, a pressure difference is generated between the anode and the cathode layer of the light emitting unit, and the light emitting unit emits light. The cathode layer is connected with the driving power supply line VSS.

[0203] Figure 7 is a cross-sectional view of a display panel provided by an embodiment of the present application. Referring to Figure 7It can be seen that the display panel 10 can include an active layer a, a first gate insulator layer (GI1), a first gate layer b, a second gate insulator layer GI2, a second gate layer c, a third gate insulator layer GI3, an oxide layer d, a fourth gate insulator layer GI4, a third gate layer e, an inter level dielectric (ILD), and a first source-drain layer f, which constitute a pixel circuit and are sequentially stacked in a direction away from the substrate base plate 101. In addition, the display panel 10 further includes a passivation layer (PVX), a first wiring layer g, a first planarization layer (PLN1), a second wiring layer h, a second planarization layer PLN2, a second source-drain layer i, and a third planarization layer PLN3, which constitute a pixel circuit and are sequentially stacked in a direction away from the first source-drain layer f. Among them, the first signal line 103 can be located in the first gate layer b, and the third signal line 106 can be located in the third gate layer e.

[0204] It should be noted that, Figure 7 This is only to show the stacking relationship of each film layer, and is not used to represent the cross-sectional view of a specific part of the display panel and the connection relationship of the transistors of the pixel circuit in the display panel. Figure 7 An oxide thin film transistor and an LTPS thin film transistor are shown. For example, the oxide thin film transistor is the second transistor T2, and the LTPS thin film transistor is the sixth transistor T6.

[0205] In the embodiments of the present application, the second transistor T2 is an oxide thin film transistor, so that the second transistor T2 can be composed of the second gate layer c, the oxide layer d, and the third gate layer e. The material of the oxide layer d can be IGZO.

[0206] For example, the second transistor T2 can be a double-gate transistor. The second gate layer c can include a gate pattern of a bottom gate of the second transistor T2. The oxide layer d can include an oxide pattern of the second transistor T2. The third gate layer e can include a gate pattern of a top gate of the second transistor T2.

[0207] In addition, the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 are all LTPS thin film transistors, so that the first transistor T1, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can be composed of the active layer a, the first gate layer b, and the first source-drain layer f.

[0208] For example, the active layer a can include an active pattern of the first transistor T1, an active pattern of the third transistor T3, an active pattern of the fourth transistor T4, an active pattern of the fifth transistor T5, an active pattern of the sixth transistor T6, an active pattern of the seventh transistor T7, and an active pattern of the eighth transistor T8.

[0209] The first gate layer b can include a gate pattern of the first transistor T1, a gate pattern of the third transistor T3, a gate pattern of the fourth transistor T4, a gate pattern of the fifth transistor T5, a gate pattern of the sixth transistor T6, a gate pattern of the seventh transistor T7, and a gate pattern of the eighth transistor T8.

[0210] In the embodiment of the present application, in the first display area 10a, the light-emitting control signal line EM can be located in the first gate layer b. The first reset power supply line vinit1 is located in the first source-drain layer f. The third reset power supply line vinit3 is located in the third gate layer e. That is, in this scheme, the third signal line 106 (the third reset power supply line vinit3) is a one-piece structure.

[0211] In addition, for other horizontal signal lines, such as the first gate signal line Gate_N, the second gate signal line Gate_P, the first reset signal line Preset, and the second reset signal line Preset_H, a multi-layer film layer can be designed, that is, layer switching is needed, which will be described in detail later. For vertical signal lines, such as the data signal line Data and the driving power supply line VDD, they can be located in the second source-drain layer i. Among them, the horizontal signal lines mainly provide signals for the pixel circuits arranged in the horizontal direction, and the vertical signal lines mainly provide signals for the pixel circuits arranged in the vertical direction.

[0212] In the embodiment of the present application, in order to clearly show each film layer, the following will introduce each film layer of the pixel circuit including eight transistors in a single layer and step-by-step lamination manner.

[0213] Figure 8 FIG. 1 is a local schematic diagram of an active layer in a display panel provided by an embodiment of the present application. Referring to FIG. 1, Figure 8 The active layer a can have a curved or bent shape, and the active layer a includes an active pattern (channel region) and a doped region pattern (source-drain doped region) of each transistor, and the active pattern and the doped region pattern of each transistor in the same pixel circuit are integrally arranged.

[0214] It should be noted that the active layer a can include a low-temperature polysilicon layer formed integrally, and the source region and the drain region can be conductorized by doping to realize electrical connection of each structure. That is, the semiconductor layer of each transistor of each pixel circuit is an integral pattern formed of p-silicon, and each transistor in the same pixel circuit includes a doping region pattern (i.e., the source region and the drain region) and an active pattern, and the active patterns of different transistors are separated.

[0215] The active layer a can be made of amorphous silicon, polysilicon, oxide semiconductor material, etc. It should be noted that the source region and the drain region described above can be regions doped with n-type impurities or p-type impurities.

[0216] The display panel includes a first gate insulating layer on the side of the active layer a away from the substrate 101, for insulating the active layer a from the first gate layer b formed subsequently.

[0217] Figure 9 is a partial schematic view of a first gate layer in a display panel provided by an embodiment of the present application. Figure 10 is a partial superimposed schematic view of an active layer and a first gate layer in a display panel provided by an embodiment of the present application. Figure 9 and Figure 10 It is shown that the display panel includes a first gate layer b, which is disposed on the first gate insulating layer and thus insulated from the active layer a. The first gate layer b can include a second storage capacitor electrode Cst2, an emission control signal line EM, a gate layer pattern b1 of a first reset signal line Preset for providing a first reset signal to the gate of the first transistor T1, a gate layer pattern b2 of a second gate signal line Gate_P, and a gate layer pattern b3 of a second reset signal line Preset_H for providing a second reset signal to the gate of the eighth transistor T8. Among them, each pattern included in the first gate layer b has a gap. Moreover, the position where the first gate layer b overlaps with the active layer a can constitute the gate of each transistor.

[0218] For example, in combination with Figure 8 to Figure 10 The gate of the first transistor T1 is the part where the gate layer pattern b1 of the first reset signal line Preset overlaps with the active layer a. The gate of the third transistor T3 can be the second storage capacitor electrode Cst2. The gate of the fourth transistor T4 is the part where the gate layer pattern b2 of the second gate signal line Gate_P overlaps with the active layer a. The gates of the fifth transistor T5 and the sixth transistor T6 are respectively the parts where the emission control signal line EM overlaps with different regions in the active layer a. The seventh transistor T7 and the eighth transistor T8 are respectively the parts where the gate layer pattern b3 of the second reset signal line Preset_H overlaps with different regions in the active layer a.

[0219] It should be noted that Figure 10 Each dotted rectangular frame in FIG. 8 shows a portion of the first gate layer b overlapping the active layer a. As a channel region of each transistor, the active layer a on both sides of each channel region is conductive as the first electrode and the second electrode of each transistor by ion doping or the like. The source electrode and the drain electrode of the transistor can be symmetrical in structure, so the source electrode and the drain electrode can be physically indistinguishable. In the embodiments of the present application, in order to distinguish the transistors, one electrode is directly described as the first electrode and the other electrode is directly described as the second electrode in addition to the gate electrode as the control electrode, so the first electrode and the second electrode of all or part of the transistors in the embodiments of the present application can be interchangeable as needed.

[0220] As shown in FIG. 9, Figure 9 and Figure 10 The light-emitting control signal line EM is an integral structure located in the first gate layer b. In addition, the first gate layer b described above can be formed with a second gate insulating layer for insulating the first gate layer b described above from the second gate layer c formed subsequently.

[0221] Figure 11 FIG. 10 is a partial schematic view of a second gate layer in a display panel provided by the embodiments of the present application, Figure 12 FIG. 11 is a partial superimposed schematic view of an active layer, a first gate layer, and a second gate layer in a display panel provided by the embodiments of the present application. As shown in FIG. 11, Figure 11 and Figure 12 The second gate layer c includes the first storage capacitor electrode Cst1 and a bottom gate pattern c1 of the second transistor T2 located in the second gate layer c. The first storage capacitor electrode Cst1 located in the second gate layer c at least partially overlaps the second storage capacitor electrode Cst2 located in the first gate layer b to form a storage capacitor Cst. The bottom gate pattern c1 is also used for a portion of the first gate signal line Gate_N located in the second gate layer c.

[0222] In addition, the second gate layer c described above can be formed with a third gate insulating layer for insulating the second gate layer c described above from the oxide layer d formed subsequently.

[0223] Figure 13 FIG. 12 is a partial schematic view of an oxide layer in a display panel provided by the embodiments of the present application, Figure 14 FIG. 13 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, and an oxide layer in a display panel provided by the embodiments of the present application. As shown in FIG. 13, Figure 13 and Figure 14 The oxide layer d includes an oxide pattern d1 for forming the second transistor T2.

[0224] In addition, a fourth gate insulating layer can be formed on the oxide layer d to insulate the oxide layer d from a third gate layer e to be formed later.

[0225] Figure 15 is a local schematic diagram of a third gate layer in a display panel provided by an embodiment of the present application, Figure 16 is a local superimposed schematic diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, and a third gate layer in a display panel provided by an embodiment of the present application. As shown in Figure 15 and Figure 16 As shown in the third gate layer e includes a top gate pattern e1 in the second transistor T2 located on the third gate layer e, and a third reset power supply line vinit3. The third reset power supply line vinit3 is an integral structure located on the third gate layer e.

[0226] In addition, two interlayer dielectric layers can be formed on the second gate layer c to insulate the third gate layer e from a first source-drain layer f to be formed later. Figure 17 is a local schematic diagram of a first interlayer dielectric layer in a display panel provided by an embodiment of the present application. Figure 18 is a local superimposed schematic diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, and a first interlayer dielectric layer in a display panel provided by an embodiment of the present application. Figure 19 is a local schematic diagram of a second interlayer dielectric layer in a display panel provided by an embodiment of the present application. Figure 20 is a local superimposed schematic diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, and a second interlayer dielectric layer in a display panel provided by an embodiment of the present application.

[0227] In order to show the respective via holes 1 in the first interlayer dielectric layer (ILD1) and the respective via holes 2 in the second interlayer dielectric layer (ILD2) more clearly, Figure 17 to Figure 20 In FIG. 6, a filling pattern is used to represent the via holes. The areas not drawn with the filling pattern are used to represent the areas where the interlayer dielectric layer has a solid material. It should be noted that the respective via holes in the interlayer dielectric layer are used to connect the film layers to be formed later to the film layer close to the substrate 101 on the side of the interlayer dielectric layer. That is, the respective via holes are via holes for film layer connection.

[0228] Figure 21 is a local schematic diagram of a first source-drain layer in a display panel provided by an embodiment of the present application, Figure 22 is a local superimposed schematic diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, and a first source-drain layer in a display panel provided by an embodiment of the present application.

[0229] As shown in Figure 21 and Figure 22 The first source-drain layer f includes:

[0230] The first reset power line vinit1 directly transmits signals through the first source-drain layer f, without the need to design a bonding hole of a wiring layer, thereby facilitating the layout design of other wirings.

[0231] The first source-drain pattern f1 is used to connect the first electrode of the first transistor T1.

[0232] The second source-drain pattern f2 is used to connect the gate layer pattern c1 of the second gate layer c in the first gate signal line Gate_N and the gate layer pattern e1 of the third gate layer e in the first gate signal line Gate_N, and is also used to connect the pattern of the first wiring layer g formed subsequently.

[0233] The third source-drain pattern f3 is used to connect the gate layer pattern of the first gate layer b in the second gate signal line Gate_P and the pattern of the first wiring layer g formed subsequently.

[0234] The fourth source-drain pattern f4 is used to connect the second electrode of the fourth transistor T4 and the second electrode of the eighth transistor T8, and the second electrode of the fourth transistor T4 and the second electrode of the eighth transistor T8 are connected with the second node N2.

[0235] The fifth source-drain pattern f5 is used to connect the first electrode of the fifth transistor T5, and the first electrode of the fifth transistor T5 is connected with the driving power line VDD (the driving power line VDD is located in the second wiring layer h).

[0236] The sixth source-drain pattern f6 is used to connect the gate layer pattern of the first gate layer b of the second reset signal line Preset_H and the pattern of the first wiring layer g formed subsequently.

[0237] The seventh source-drain pattern f7 is used to connect the first electrode of the eighth transistor T8 and the third reset power line vinit3.

[0238] The eighth source-drain pattern f8 is the pattern of the second reset power line vinit2 located in the first source-drain layer f, and the second reset power line vinit is connected with the first electrode of the seventh transistor T7.

[0239] The ninth source-drain pattern f9 is used for connecting the second reset signal line Preset_H to the gate layer pattern of the first gate layer b and the pattern of the first trace layer g formed subsequently.

[0240] The tenth source-drain pattern f10 is used for connecting the second gate signal line Gate_P to the gate layer pattern of the first gate layer b and the pattern of the first trace layer g formed subsequently.

[0241] The eleventh source-drain pattern f11 is used for the first gate signal line Gate_N to the gate layer pattern of the third gate layer e and the pattern of the first trace layer g formed subsequently.

[0242] The twelfth source-drain pattern f12 is used for the second electrode of the first transistor T1 and the first electrode of the second transistor T2, and is also used for connecting the first electrode of the second transistor T2 and the first electrode of the sixth transistor T6, the second electrode of the first transistor T1, the first electrode of the second transistor T2 and the first electrode of the sixth transistor T6 are connected to the third node N3.

[0243] The thirteenth source-drain pattern f13 is used for connecting the first electrode of the fourth transistor T4 and the data signal line in the second trace layer h formed subsequently.

[0244] The fourteenth source-drain pattern f14 is used for connecting the second electrode of the second transistor T2 and the gate of the third transistor T3, and the second electrode of the second transistor T2 and the gate of the third transistor T3 are connected to the second node N2.

[0245] The fifteenth source-drain pattern f15 can be a dummy pattern, which is used for improving the design uniformity of the first source-drain layer f.

[0246] In addition, the first source-drain layer f can be formed with a passivation layer, which is used for insulating the first source-drain layer f and the first trace layer g formed subsequently. Figure 23 A partial schematic view of a passivation layer in a display panel is provided in the embodiments of the present application. Figure 24 A partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer and a passivation layer in a display panel is provided in the embodiments of the present application.

[0247] In order to show the various vias 3 in the passivation layer, Figure 23 to Figure 24The via hole is represented by a fill pattern. The area without the fill pattern is used to represent the area where the passivation layer has a solid material. It should be noted that each via hole in the passivation layer is used for the film layer formed subsequently to connect with the film layer close to the substrate 101 side of the passivation layer. That is, each via hole is a via hole for film layer connection.

[0248] Figure 25 is a local schematic diagram of a first wiring layer in a display panel provided by an embodiment of the present application, Figure 26 is a local superimposed schematic diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, and a first wiring layer in a display panel provided by an embodiment of the present application.

[0249] As shown in Figure 25 and Figure 26 , the first wiring layer g includes:

[0250] a first wiring pattern g1, which is a pattern of a first reset signal line Preset for connecting a plurality of first pixel circuits 1021.

[0251] a second wiring pattern g2, which is a pattern of a first reset signal line Preset for connecting a plurality of second pixel circuits 1022.

[0252] a third wiring pattern g3, which is used to connect the first electrode of the fourth transistor T4 and a data signal line Data of a second wiring layer h formed subsequently.

[0253] a fourth wiring pattern g4 and a fifth wiring pattern g5, which are used to connect a second reset power line vinit2 of the second wiring layer h formed subsequently.

[0254] a sixth wiring pattern g6, which is a wiring layer pattern of a second gate signal line Gate_P.

[0255] a seventh wiring pattern g7, which is a wiring layer pattern of a first gate signal line Gate_N.

[0256] an eighth wiring pattern g8, which is a wiring layer pattern of a second reset signal line Preset_H.

[0257] and a ninth wiring pattern g9, which is used to connect a driving power line VDD in the second wiring layer h formed subsequently.

[0258] In addition, a first planarization layer can be formed on the first wiring layer g to insulate the first wiring layer g from a second wiring layer h to be formed later. Figure 27 FIG. 6 is a partial schematic view of a first planarization layer in a display panel according to an embodiment of the present application. Figure 28 FIG. 7 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, and a second wiring layer in a display panel according to an embodiment of the present application.

[0259] To facilitate the illustration of the various via holes 4 in the first planarization layer, Figure 27 to Figure 28 The via holes are represented by filled patterns in FIG. 6. The areas not drawn with filled patterns represent areas where the first planarization layer has a solid material. It should be noted that the various via holes in the first planarization layer are for connecting the film layers to be formed later to the film layer on the side of the first planarization layer close to the substrate 101. That is, the various via holes are via holes for film layer connection.

[0260] Figure 29 FIG. 8 is a partial schematic view of a second planarization layer in a display panel according to an embodiment of the present application. Figure 30 FIG. 9 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, and a second planarization layer in a display panel according to an embodiment of the present application. As shown in FIG. 9, the second planarization layer i includes a second source-drain layer j. Figure 29 and Figure 30 As shown in FIG. 9, the second wiring layer h includes a driving power supply line VDD, a data signal line Data, and a second reset power supply line vinit2. The driving power supply line VDD, the data signal line Data, and the second reset power supply line vinit2 extend along the pixel column direction Y and are arranged in sequence along the pixel row direction X.

[0261] In addition, a second planarization layer can be formed on the second wiring layer h to insulate the second wiring layer h from a second source-drain layer i to be formed later. Figure 31 FIG. 10 is a partial schematic view of a second planarization layer in a display panel according to an embodiment of the present application. Figure 32 FIG. 11 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, and a second planarization layer in a display panel according to an embodiment of the present application.

[0262] To facilitate the illustration of the various via holes 5 in the first planarization layer, Figure 30 to Figure 31The filled pattern is used to represent the via hole. The area without the filled pattern is used to represent the area where the second planar layer has a material. It should be noted that each via hole in the second planar layer is used for the film layer formed subsequently to connect with the film layer on the side of the second planar layer close to the substrate 101. That is, each via hole is a via hole for film layer connection.

[0263] Figure 33 is a partial schematic view of a second source-drain layer in a display panel provided by an embodiment of the present application, Figure 34 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planar layer, a second wiring layer, a second planar layer, and a second source-drain layer in a display panel provided by an embodiment of the present application. As shown in Figure 33 and Figure 34 As shown in the second source-drain layer i includes a sixteenth source-drain pattern i1. The sixteenth source-drain pattern i1 is used to connect the seventh transistor T7 and the anode layer of the light-emitting unit formed subsequently.

[0264] In addition, a third planar layer can be formed on the second source-drain layer i described above, for insulating the second source-drain layer i described above from the anode layer of the light-emitting unit formed subsequently. Figure 35 is a partial schematic view of a third planar layer in a display panel provided by an embodiment of the present application. Figure 36 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planar layer, a second wiring layer, a second planar layer, a first source-drain layer, and a third planar layer in a display panel provided by an embodiment of the present application.

[0265] In order to facilitate the illustration of each via hole 6 in the third planar layer, Figure 35 to Figure 36 The filled pattern is used to represent the via hole. The area without the filled pattern is used to represent the area where the third planar layer has a material. It should be noted that each via hole in the third planar layer is used for the film layer formed subsequently to connect with the film layer on the side of the third planar layer close to the substrate 101. That is, each via hole is a via hole for film layer connection.

[0266] Figure 37 is a partial schematic view of an anode layer in a display panel provided by an embodiment of the present application, Figure 38This is a partial superimposed schematic diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source / drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, a second source / drain layer, a third planarization layer, and an anode layer in a display panel provided in an embodiment of this application. Figure 37 and Figure 38 As shown, the anode of the light-emitting unit is connected to the fifteenth source-drain pattern i1 of the second source-drain layer i through a via 6 in the third planarization layer. Wherein, Figure 37 and Figure 38 The patterns shown are for illustrative purposes only and do not represent the actual shape of the anode.

[0267] As a second optional implementation, each pixel circuit in each pixel circuit group 102, comprising multiple first pixel circuits 1021 and multiple second pixel circuits 1022, includes seven transistors and a storage capacitor Cst (i.e., 7T1C), for example... Figure 39 and Figure 40 As shown. Figure 40 In order to clearly illustrate the pixel circuit, only the first source and drain layer is shown, and the film layer on the side of the first source and drain layer away from the substrate 101 is not shown.

[0268] Figure 39 and Figure 40 The difference is: Figure 39 The first reset power line, vinit1, needs to be changed through the routing layer. Figure 40 The first reset power line, vinit1, does not require changing layers through the routing layer.

[0269] Figure 41 yes Figure 39 or Figure 40 The diagram shows the equivalent circuit diagram of a pixel circuit in the display panel. (Reference) Figure 41 The pixel circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a storage capacitor Cst.

[0270] The gate of the first transistor T1 is connected to the first reset signal line Preset. The first terminal of the first transistor T1 can be connected to the first reset power supply line vinit1. The second terminal of the first transistor T1 is connected to the second node N2. The first transistor T1 can also be called a reset transistor.

[0271] The gate of the second transistor T2 can be connected with the first gate signal line Gate_N, the first electrode of the second transistor T2 is connected with the third node N3, and the second electrode of the second transistor T2 can be connected with the second node N2. The second thin film transistor T2 can also be referred to as a compensation transistor.

[0272] The gate of the third transistor T3 can be connected with the second node N2, the first electrode of the third transistor T3 can be connected with the first node N1, and the second electrode of the third transistor T3 is connected with the third node N3. The third transistor T3 can also be referred to as a driving transistor.

[0273] The gate of the fourth transistor T4 can be connected with the second gate signal line Gate_P, the first electrode of the fourth transistor T4 is connected with the data signal line Data, and the second electrode of the fourth transistor T4 is connected with the first node N1. The fourth transistor T4 can be a data writing transistor in the pixel circuit.

[0274] The gate of the fifth transistor T5 can be connected with the emission control signal line EM, the first electrode of the fifth transistor T5 can be connected with the driving power supply line VDD, and the second electrode of the fifth transistor T5 can be connected with the first node N1. Since the gate of the fifth transistor T5 is connected with the emission control signal line EM, the fifth transistor T5 can also be referred to as an emission control transistor.

[0275] The gate of the sixth transistor T6 can be connected with the emission control signal line EM, the first electrode of the sixth transistor T6 can be connected with the third node N3, and the second electrode of the sixth transistor T6 can be connected with the anode of the light emitting unit. Since the gate of the sixth transistor T6 is connected with the emission control signal line EM, the sixth transistor T6 can also be referred to as an emission control transistor.

[0276] The gate of the seventh transistor T7 can be connected with the second gate signal line Gate_P, the first electrode of the seventh transistor T7 can be connected with the first reset power supply line vinit1, and the second electrode of the seventh transistor T7 can be connected with the anode of the light emitting unit. The seventh transistor T7 can be a reset transistor in the pixel circuit.

[0277] One end of the storage capacitor Cst can be connected with the driving power supply line VDD, and the other end of the storage capacitor Cst can be connected with the second node N2. Optionally, the storage capacitor Cst can include two capacitor plates Cst1 and Cst2. In the embodiment of the present application, the capacitor plate Cst1 can be referred to as one end, a first end, or a first storage capacitor electrode of the storage capacitor Cst, and the capacitor plate Cst2 can be referred to as the other end, a second end, or a second storage capacitor electrode of the storage capacitor Cst.

[0278] In the embodiment of the present application, the third signal line 106 can be a second gate signal line Gate P. That is, in the case that the pixel circuit includes seven transistors and one storage capacitor Cst, the third signal line 106 can be a second gate signal line Gate P. The second gate signal line Gate P can provide the second gate signal for the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 in the pixel circuit group 102.

[0279] Optionally, the first transistor T1 and the second transistor T2 are N-type transistors. The third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are P-type transistors.

[0280] Optionally, each N-type transistor in the embodiment of the present application can be an oxide thin film transistor, and each P-type transistor can be an LTPS thin film transistor. The oxide material can include IGZO, that is, the oxide thin film transistor can be an IGZO thin film transistor. The pixel circuit composed of the seven transistors can also be referred to as an LTPO pixel circuit. The display panel in which the pixel circuit is the LTPO pixel circuit can be referred to as an LTPO display panel.

[0281] As shown in the pixel circuit shown in FIG. 6, the first potential is high with respect to the second potential, for example, the driving principle of the pixel circuit in the embodiment of the present application is introduced as follows. Figure 41 Figure 42 is a timing diagram of the signal lines in another pixel circuit provided by the embodiment of the present application. As shown in FIG. 7, the first potential is low with respect to the second potential. Figure 42

[0282] In the initialization phase t1, the potential of the reset signal provided by the first reset signal line Preset, the potential of the second gate driving signal provided by the second gate signal line Gate P, and the potential of the emission control signal provided by the emission control signal line EM are all the first potential. The potential of the first gate driving signal provided by the first gate signal line Gate N is the second potential. Correspondingly, the first transistor T1 is turned on. The second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all turned off. In this way, the reset power signal of the second potential provided by the first reset power line vinit1 can be transmitted to the second node N2 through the turned-on first transistor T1, so as to reset the second node N2.

[0283] ​​In the compensation stage t2, the potential of the reset signal provided by the first reset signal line Preset and the potential of the second gate driving signal provided by the second gate signal line Gate_P both jump to the second potential, the potential of the first gate driving signal provided by the first gate signal line Gate_N jumps to the first potential, and the potential of the light emitting control signal provided by the light emitting control signal line EM remains the first potential. Under the bootstrap action of the storage capacitor Cst, the potential of the second node N2 remains the second potential. Correspondingly, the second transistor T2, the third transistor T3, the fourth transistor T4 and the seventh transistor T7 are all turned on, and the first transistor T1, the fifth transistor T5 and the sixth transistor T6 are all turned off. In this way, the data signal of the first potential can be transmitted to the first node N1 through the turned-on fourth transistor T4, and then transmitted to the third node N3 through the turned-on third transistor T3, and the second transistor T2 adjusts the potential of the second node N2 based on the potential of the third node N3. In addition, the reset power signal of the second potential provided by the first reset power line vinit1 can be transmitted to the light emitting unit a2 through the turned-on seventh transistor T7, so as to reset the light emitting unit.

[0284] In the light emitting stage t3, the potential of the reset signal provided by the first reset signal line Preset remains the second potential, the potential of the second gate driving signal provided by the second gate signal line Gate_P jumps to the first potential, and the potential of the first gate driving signal provided by the first gate signal line Gate_N jumps to the second potential. Under the bootstrap action of the storage capacitor Cst, the potential of the second node N2 remains the second potential. Correspondingly, the third transistor T3, the fifth transistor T5 and the sixth transistor T6 are turned on, and the first transistor T1, the second transistor T2, the fourth transistor T4 and the seventh transistor T7 are all turned off. In this way, the driving power signal provided by the driving power line VDD can be transmitted to the first node N1 through the turned-on fifth transistor T5, and the third transistor T3 can transmit the driving current to the third node N3 based on the potential of the second node N2 and the potential transmitted to the first node N1. Then, the driving current can be transmitted to the anode pattern of the light emitting unit through the turned-on sixth transistor T6, a pressure difference is generated between the anode pattern of the light emitting unit and the cathode layer, and the light emitting unit emits light. The cathode layer is connected with the driving power line VSS.

[0285] The layer stacking relationship of the film layer in this implementation manner can also be referred to Figure 7The first signal line 103 is located at the first gate layer b, and the third signal line 106 can include a first portion, a second portion and a third portion connected in sequence. The first portion has a projection on the substrate 101 which at least partially overlaps with a projection of the first pixel circuit 1021 on the substrate 101, the second portion has a projection on the substrate 101 which does not overlap with the projection of the first pixel circuit 1021 on the substrate 101 and a projection of the second pixel circuit 1022 on the substrate 101, and the third portion has a projection on the substrate 101 which at least partially overlaps with the projection of the second pixel circuit 1022 on the substrate 101. The first portion and the third portion are both located at the first gate layer b, and the second portion is located at the first source-drain layer f. That is, in this implementation, the third signal line 106 is arranged in two layers, and both layers are metal layers.

[0286] In the embodiments of the present application, the first transistor T1 and the second transistor T2 are oxide thin film transistors, so that the first transistor T1 and the second transistor T2 can be composed of the second gate layer c, the oxide layer d and the third gate layer e. The material of the oxide layer d can be IGZO.

[0287] For example, the first transistor T1 and the second transistor T2 are double-gate transistors. The second gate layer c can include a gate pattern of a bottom gate of the first transistor T1 and a gate pattern of a bottom gate of the second transistor T2. The oxide layer d can include an oxide pattern of the first transistor T1 and an oxide pattern of the second transistor T2. The third gate layer e can include a gate pattern of the bottom gate of the first transistor T1 and a gate pattern of a top gate of the second transistor T2.

[0288] In addition, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all LTPS thin film transistors, so that the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 can be composed of the active layer a, the first gate layer b and the first source-drain layer f.

[0289] For example, the active layer a can include an active pattern of the third transistor T3, an active pattern of the fourth transistor T4, an active pattern of the fifth transistor T5, an active pattern of the sixth transistor T6 and an active pattern of the seventh transistor T7.

[0290] The first gate layer b can include a gate pattern of the third transistor T3, a gate pattern of the fourth transistor T4, a gate pattern of the fifth transistor T5, a gate pattern of the sixth transistor T6 and a gate pattern of the seventh transistor T7.

[0291] In the embodiment of the present application, in the first display area 10a, the light-emitting control signal line EM can be located in the first gate layer b. The first reset power supply line vinit1 is located in the first source-drain layer f. The second gate signal line Gate_P is located in the first gate layer b and the first source-drain layer f.

[0292] In the embodiment of the present application, in order to clearly show each film layer, the following is a brief introduction to each single layer and the step-by-step lamination of Figure 40 The following is a brief introduction to each film layer when the pixel circuit includes seven transistors.

[0293] Figure 43 FIG. 6 is a partial schematic diagram of an active layer in another display panel provided by the embodiment of the present application. Figure 43 The active layer can have a curved or bent shape, and the active layer a includes an active pattern (channel region) and a doped region pattern (source-drain doped region) of each transistor, and the active pattern and the doped region pattern of each transistor in the same pixel circuit are integrally arranged.

[0294] It should be noted that the active layer a can include an integrally formed low-temperature polysilicon layer, and the source region and the drain region can be conductorized by doping to realize electrical connection of each structure. That is, the semiconductor layer of each transistor of each pixel circuit is an integral pattern formed by p-silicon, and each transistor in the same pixel circuit includes a doped region pattern (i.e., a source region and a drain region) and an active pattern, and the active patterns of different transistors are separated.

[0295] The active layer a can be made of amorphous silicon, polysilicon, oxide semiconductor material, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0296] The display panel includes a first gate insulating layer on the side of the active layer a away from the substrate 101, for insulating the active layer a from the subsequently formed first gate layer b. Figure 44 FIG. 5 is a partial schematic diagram of a first gate layer in another display panel provided by the embodiment of the present application. Figure 45 FIG. 6 is a partial schematic diagram of an active layer and a first gate layer in another display panel provided by the embodiment of the present application. Figure 44 and Figure 45 It is shown that the display panel includes the first gate layer b, which is arranged on the first gate insulating layer, thereby being insulated from the active layer a. The first gate layer b can include a gate layer pattern b1 of the second storage capacitor electrode Cst2, the light-emitting control signal line EM, and the second gate signal line Gate_P. The position where the first gate layer b overlaps the active layer a can constitute the gate of each transistor.

[0297] For example, in combination with Figure 43 to Figure 45The gate of the third transistor T3 can be the second storage capacitor electrode Cst2. The gate of the fourth transistor T4 and the gate of the seventh transistor T7 are respectively the part of the gate layer pattern b2 of the second gate signal line Gate_P and the active layer a which are overlapped. The gate of the fifth transistor T5 and the gate of the sixth transistor T6 are respectively the part of the light emitting control signal line EM and the active layer a which are overlapped.

[0298] It should be noted that, Figure 45 The dashed rectangular frame in each of the above figures shows the part of the first gate layer b and the active layer a which are overlapped. As the channel region of each transistor, the active layer a on both sides of each channel region is conductive by ion doping or other processes as the first pole and the second pole of each transistor. The source and the drain of the transistor can be symmetrical in structure, so the source and the drain can be physically indistinguishable. In the embodiments of the present application, in order to distinguish the transistors, one pole is directly described as the first pole and the other pole is the second pole except the gate as the control pole, so the first pole and the second pole of all or part of the transistors in the embodiments of the present application can be interchangeable as needed.

[0299] As shown in Figure 44 and Figure 45 , the light emitting control signal line EM is an integral structure located in the first gate layer b. In addition, the first gate layer b described above can be formed with a second gate insulating layer for insulating the first gate layer b described above from the second gate layer c formed subsequently.

[0300] Figure 46 is another partial schematic view of the second gate layer in the display panel provided by the embodiments of the present application, Figure 47 is a partial superimposed schematic view of the active layer, the first gate layer and the second gate layer in the display panel provided by the embodiments of the present application.

[0301] As shown in Figure 46 and Figure 47 , the second gate layer c includes:

[0302] The first storage capacitor electrode Cst1 located in the second gate layer c at least partially overlaps the second storage capacitor electrode Cst2 located in the first gate layer b to form a storage capacitor Cst.

[0303] The bottom gate pattern c1 of the first transistor T1 is also used for a part of the first reset signal line Preset located in the second gate layer c.

[0304] The bottom gate pattern c2 of the second transistor T2 is also used for a part of the first gate signal line Gate_N located in the second gate layer c.

[0305] In addition, a third gate insulating layer can be formed on the second gate layer c to insulate the second gate layer c from an oxide layer d formed subsequently.

[0306] Figure 48 is a partial schematic view of an oxide layer in another display panel provided by an embodiment of the present application, Figure 49 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, and an oxide layer in another display panel provided by an embodiment of the present application. Figure 48 and Figure 49 As shown in FIG. 5 and FIG. 6, the oxide layer d includes an oxide pattern d1 for forming the first transistor T1 and the second transistor T2. The oxide pattern d1 of the first transistor T1 and the second transistor T2 are integrated.

[0307] In addition, a fourth gate insulating layer can be formed on the oxide layer d to insulate the oxide layer d from a third gate layer e formed subsequently.

[0308] Figure 50 is a partial schematic view of a third gate layer in another display panel provided by an embodiment of the present application, Figure 51 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, and a third gate layer in another display panel provided by an embodiment of the present application.

[0309] As shown in FIG. 7 and FIG. 8, the third gate layer e includes: Figure 50 and Figure 51

[0310] a top gate pattern e1 of the first transistor T1, the top gate pattern e1 is also used for a part of the third gate layer e in a first reset signal line Preset.

[0311] and a top gate pattern e2 of the second transistor T2, the top gate pattern e2 is also used for a part of the third gate layer e in a first gate signal line Gate_N.

[0312] In addition, two interlayer dielectric layers can be formed on the second gate layer c to insulate the third gate layer e from a first source-drain layer f formed subsequently. Figure 52 is a partial schematic view of a first interlayer dielectric layer in another display panel provided by an embodiment of the present application. Figure 53 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, and a first interlayer dielectric layer in another display panel provided by an embodiment of the present application. Figure 54 is a partial schematic view of a second interlayer dielectric layer in another display panel provided by an embodiment of the present application. Figure 55 ​is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer and a first source-drain layer in another display panel provided by an embodiment of the present application.

[0313] In order to show the respective via hole 1 in the first interlayer dielectric layer (ILD1) and the respective via hole 2 in the second interlayer dielectric layer (ILD2) conveniently, Figure 52 to Figure 55 The via hole is represented by a filling pattern in the figure. The area without the filling pattern is used to represent the area where the interlayer dielectric layer has a solid material. It should be noted that each via hole in the interlayer dielectric layer is used for the film layer formed subsequently to connect with the film layer close to the side of the interlayer dielectric layer close to the substrate 101. That is, each via hole is a via hole for the film layer connection.

[0314] Figure 56 is a partial schematic view of a first source-drain layer in another display panel provided by an embodiment of the present application, Figure 57 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer and a first source-drain layer in another display panel provided by an embodiment of the present application.

[0315] As shown in Figure 56 and Figure 57 , the first source-drain layer f includes:

[0316] The first reset power line vinit1 directly realizes signal transmission through the first source-drain layer f, without the need to design a lap joint hole of a wiring layer, which is convenient for the arrangement of other signal lines. Moreover, since the resistance of the first source-drain layer f is smaller than the resistance of the wiring layer, the resistance of the first reset power line vinit1 in this mode is smaller, thereby being capable of improving the picture uniformity of the display panel.

[0317] The first source-drain pattern f1 is used to connect the bottom gate pattern c1 of the first transistor T1 in the first pixel circuit 1021 located in the second gate layer c and the top gate pattern e1 of the first transistor T1 located in the third gate layer e.

[0318] The second source-drain pattern f2 is used to connect the bottom gate pattern c1 of the first transistor T1 in the second pixel circuit 1022 located in the second gate layer c and the top gate pattern e1 of the first transistor T1 located in the third gate layer e.

[0319] The third source-drain pattern f3 is used to connect the bottom gate pattern c2 of the second transistor T2 located in the second gate layer c and the top gate pattern e2 of the second transistor T2 located in the third gate layer e.

[0320] The fourth source-drain pattern f4 is used to connect the gate layer pattern b1 of the second gate signal line Gate_P in the first pixel circuit 1021 and the gate layer pattern b1 of the second gate signal line Gate_P in the second pixel circuit 1022, i.e., the signal of the second gate signal line Gate_P only needs to be overlapped through the first source-drain layer f, and there is no need to design an overlap hole of the wiring layer. This design can improve the partial transmittance, and most importantly, the second gate signal line Gate_P is entirely used to realize signal transmission through the first gate layer and the first source-drain layer, and there is no need to use a wiring layer with large resistance, which can greatly reduce the resistance of the second gate signal line Gate_P and meet the requirement of high refresh rate. Although the second gate signal line Gate_P and the light-emitting control signal line EM are overlapped in projection, the second gate signal line Gate_P and the light-emitting control signal line EM do not have pulse overlap of signals (the pulse of the light-emitting control signal line EM always covers the pulse of the second gate signal line Gate_P), and thus the interference is small.

[0321] The fifth source-drain pattern f5 is used to connect the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5, both of which are connected with the first node N1, and the fifth source-drain pattern f5 is also used to connect the first electrode of the fifth transistor T5 and the driving power line VDD in the second wiring layer h.

[0322] The sixth source-drain pattern f6 is used to connect the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, both of which are connected with the anode layer of the subsequently formed light-emitting unit.

[0323] The seventh source-drain pattern f7 is used to connect the first electrode of the second transistor T2 and the first electrode of the sixth transistor T6, both of which are connected with the third node N3.

[0324] The eighth source-drain pattern f8 is used to connect the gate layer pattern (the top gate pattern of the second transistor T2) of the third gate layer e in the first gate signal line Gate_N and the pattern of the first wiring layer g which is subsequently formed.

[0325] The ninth source-drain pattern f9 is used to connect the second electrode of the second transistor T2 and the gate of the third transistor T3, both of which are connected with the second node N2.

[0326] and a tenth source-drain pattern f10, the tenth source-drain pattern f10 being used for connecting the first electrode of the fourth transistor T4 and a data signal line Data in a second electrode wiring layer formed subsequently.

[0327] In addition, a passivation layer can be formed on the first source-drain layer f, and used for insulating the first source-drain layer f from a first wiring layer g formed subsequently. Figure 58 Another partial schematic view of a passivation layer in a display panel provided by an embodiment of the present application. Figure 59 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, and a passivation layer in another display panel provided by an embodiment of the present application.

[0328] In order to facilitate the illustration of each via hole 3 in the passivation layer, Figure 58 to Figure 59 In the figure, a filling pattern is used to represent the via hole. Other areas not drawn with the filling pattern are used to represent areas where the passivation layer has a solid material. It should be noted that each via hole in the passivation layer is used for connecting a film layer formed subsequently to a film layer on the side of the passivation layer close to the substrate 101. That is, each via hole is a via hole for film layer connection.

[0329] Figure 60 is a partial schematic view of a first wiring layer in another display panel provided by an embodiment of the present application, Figure 61 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, and a first wiring layer in another display panel provided by an embodiment of the present application.

[0330] As shown in Figure 60 and Figure 61 , the first wiring layer g includes:

[0331] a first wiring pattern g1, the first wiring pattern g1 being a pattern used for connecting a plurality of first reset signal lines Preset of the second pixel circuit 1022.

[0332] a second wiring pattern g2, the second wiring pattern g2 being a pattern used for connecting a plurality of first reset signal lines Preset of the first pixel circuit 1021.

[0333] a third wiring pattern g3, the third wiring pattern g3 being a wiring layer pattern of a first gate signal line Gate_N of the second pixel circuit 1022.

[0334] a fourth wiring pattern g4, the fourth wiring pattern g4 being a wiring layer pattern of a first gate signal line Gate_N of the first pixel circuit 1021.

[0335] The fifth wiring pattern g5 is used to connect the first electrode of the fourth transistor T4 and the data signal line Data in the second wiring layer h formed subsequently.

[0336] The sixth wiring pattern g6 is used to connect the first electrode of the fifth transistor T5 and the part of the driving power supply line VDD located in the second wiring layer h.

[0337] And the seventh wiring pattern g7 is used to connect the sixth transistor T6 and the anode layer of the light emitting unit formed subsequently.

[0338] In addition, the first flat layer can be formed on the first wiring layer g, so as to insulate the first wiring layer g from the second wiring layer h formed subsequently. Figure 62 Figure 2 is a partial schematic view of the first flat layer in another display panel provided by the embodiment of the present application. Figure 63 Figure 3 is a partial superimposed schematic view of the active layer, the first gate layer, the second gate layer, the oxide layer, the third gate layer, the first interlayer dielectric layer, the second interlayer dielectric layer, the first source-drain layer, the passivation layer, the first wiring layer and the first flat layer in another display panel provided by the embodiment of the present application.

[0339] In order to facilitate the illustration of the various via holes 4 in the first flat layer, Figure 62 to Figure 63 In Figure 4, the via holes are represented by filling patterns. The areas not drawn with filling patterns are used to represent the areas where the first flat layer has a solid material. It should be noted that the various via holes in the first flat layer are used to connect the film layers formed subsequently with the film layers on the side of the first flat layer close to the substrate 101. That is, the various via holes are used for the film connection.

[0340] Figure 64 Figure 5 is a partial schematic view of the second wiring layer in another display panel provided by the embodiment of the present application, Figure 65 Figure 6 is a partial superimposed schematic view of the active layer, the first gate layer, the second gate layer, the oxide layer, the third gate layer, the first interlayer dielectric layer, the second interlayer dielectric layer, the first source-drain layer, the passivation layer, the first wiring layer, the first flat layer and the second wiring layer in another display panel provided by the embodiment of the present application. As shown in Figure 64 and Figure 65 As shown in Figure 5, the second wiring layer h includes the data signal line Data, the pattern h1 of the second wiring layer h where the driving power supply line VDD is located, and the pattern h2 used to connect with the anode layer of the light emitting unit.

[0341] In addition, the second flat layer can be formed on the second wiring layer h, so as to insulate the second wiring layer h from the second source-drain layer i formed subsequently. Figure 66This is a partial schematic diagram of the second planarization layer in another display panel provided in an embodiment of this application. Figure 67 This is a partial superimposed schematic diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, and a second planarization layer in another display panel provided in this application embodiment.

[0342] To facilitate the illustration of the various vias 5 in the first planarization layer Figure 66 to Figure 67 The vias are represented by filled patterns. Other areas without filled patterns represent areas where the second planarization layer has solid material. It should be noted that each via in the second planarization layer is used to connect a subsequently formed film layer to the side of the second planarization layer closest to the substrate 101. That is, each via is used for film layer connection.

[0343] Figure 68 This is a partial schematic diagram of the second source / drain layer in another display panel provided in this application embodiment. Figure 69 This is a partial superimposed schematic diagram of the active layer, first gate layer, second gate layer, oxide layer, third gate layer, first interlayer dielectric layer, second interlayer dielectric layer, first source / drain layer, passivation layer, first wiring layer, first planarization layer, second wiring layer, second planarization layer, and second source / drain layer in another display panel provided in this application embodiment. Figure 68 and Figure 69 As shown, the second source-drain layer i includes an eleventh source-drain pattern i1 and a twelfth source-drain pattern i2. The eleventh source-drain pattern i1 is the pattern of the driving power line VDD located in the second source-drain layer i, and it is connected to the pattern h1 of the driving power line VDD located in the second trace layer h through a via in the second planarization layer. The twelfth source-drain pattern i2 is used to connect the anode layer of the light-emitting unit, and it is connected to the pattern h2 located in the second electrode layer through a via in the second planarization layer.

[0344] In addition, a third planarization layer can be formed on the second source-drain layer i to insulate the second source-drain layer i from the anode layer of the subsequently formed light-emitting unit. Figure 70 This is a partial schematic diagram of the third planarization layer in another display panel provided in an embodiment of this application. Figure 71 This is a partial superimposed schematic diagram of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, a first source-drain layer, and a third planarization layer in another display panel provided in this application embodiment.

[0345] For the convenience of showing each via hole 6 in the third planar layer, Figure 70 to Figure 71 The other areas without filling patterns are used to represent the areas where the third planar layer has a solid material. It should be noted that each via hole in the third planar layer is used for the film layer formed later to connect with the film layer close to the side of the substrate 101 of the third planar layer. That is, each via hole is a via hole for film layer connection.

[0346] Figure 72 is a partial schematic view of an anode layer in another display panel provided by an embodiment of the present application, Figure 73 is a partial superimposed schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first interlayer dielectric layer, a second interlayer dielectric layer, a first source-drain layer, a passivation layer, a first wiring layer, a first planar layer, a second wiring layer, a second planar layer, a second source-drain layer, a third planar layer, and an anode layer in another display panel provided by an embodiment of the present application. As shown in Figure 72 and Figure 73 As shown in FIG. 6 and FIG. 7, the anode layer of the light emitting unit is connected with the twelfth source-drain pattern i2 of the second source-drain layer i through the via hole 6 in the third planar layer. Among them, Figure 72 and Figure 73 Each pattern shown in FIG. 6 and FIG. 7 is only used to show the position of the anode layer, and does not represent the actual shape of the anode layer.

[0347] In the above two implementation manners, with reference to Figure 74 Each target signal line m in the display panel 10 includes a first sub-signal line m1, a second sub-signal line m2, and a second connection wiring m3. Among them, the target signal line m is a signal line in the display panel 10 other than the first signal line 103, the second signal line 104, and the third signal line 106, which provides a signal along the second direction Y. For example, in the first implementation manner, the target signal line m includes the first gate signal line Gate_N, the second gate signal line Gate_P, the first reset signal line Preset, and the second reset signal line Preset_H. In the second implementation manner, the target signal line m includes the first reset signal line Preset and the first gate signal line Gate_N.

[0348] The first sub-signal line m1 is located in the first display area 10a, and the first sub-signal line m1 is connected with the plurality of first pixel circuits 1021 in one pixel circuit group 102. The second sub-signal line m2 is located in the first display area 10a, and the second sub-signal line m2 is connected with the plurality of second pixel circuits 1022 in one pixel circuit group 102. The plurality of second pixel circuits 1022 connected with the second sub-signal line m2 of each target signal line m, and the plurality of first pixel circuits 1021 connected with the first sub-signal line m1 of the target signal line m belong to the same pixel circuit group 102. The second connection wire m3 is located in the second display area 10b, one end of the second connection wire m3 is connected with the first sub-signal line m1, and the other end is connected with the second sub-signal line m2. That is, the first sub-signal line m1 and the second sub-signal line m2 are connected through the second connection wire m3, so that the signal provided by the first sub-signal line m1 for the plurality of first pixel circuits 1021 in the pixel circuit group 102 is the same as the signal provided by the second sub-signal line m2 for the plurality of second pixel circuits 1022 in the pixel circuit group 102.

[0349] Optionally, the first sub-signal line m1 can include a connected fourth part m11 and a fifth part m12. The fourth part m11 is at least partially overlapped with the orthographic projection of the first pixel circuit 1021 on the substrate 101, and the fifth part m12 is located between the orthographic projections of the adjacent two first pixel circuits 1021 on the substrate 101. The second sub-signal line m2 can include a connected sixth part m21 and a seventh part m22. The sixth part m21 is at least partially overlapped with the orthographic projection of the second pixel circuit 1022 on the substrate 101, and the seventh part m22 is located between the orthographic projections of the adjacent two second pixel circuits 1022 on the substrate 101.

[0350] Wherein, the fourth part m11 and the sixth part m21 are located in the same layer, and the fourth part m11 and the sixth part m21 are located in the metal layer, such as the gate layer or the source-drain layer. The fifth part m12 and the seventh part m22 are located in the same layer, and the fifth part m12 and the seventh part m22 are located in the wire layer, such as the first wire layer g. Thus, referring to Figure 75 , the fourth part m11 and the fifth part m12 are connected through the via in the insulating layer between them. Similarly, the sixth part m21 and the seventh part m22 are connected through the via in the insulating layer between them.

[0351] For example, if the target signal line m is the first gate signal line Gate_N, the fourth part m11 and the sixth part m21 are located at the second gate layer c and the third gate layer e, and the fifth part m12 and the seventh part m22 are located at the first trace layer g. In this case, the insulating layer between the fourth part m11 and the fifth part m12, and between the sixth part m21 and the seventh part m22 includes the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2, and the passivation layer PVX.

[0352] If the target signal line m is the second gate signal line Gate_P or the second reset signal line Preset_H, the fourth part m11 and the sixth part m21 are located at the first gate layer b, and the fifth part m12 and the seventh part m22 are located at the first trace layer g. In this case, the insulating layer between the fourth part m11 and the fifth part m12, and between the sixth part m21 and the seventh part m22 includes the second gate insulating layer G2, the third gate insulating layer G3, the fourth gate insulating layer G4, the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2, and the passivation layer PVX.

[0353] Alternatively, the first sub-signal line m1 and the second sub-signal line m2 of the target signal line m are located at the trace layer, and do not include the part located at the metal layer. For example, the first sub-signal line m1 and the second sub-signal line m2 are located at the first trace layer g. For example, the first trace pattern g1 and the second trace pattern g2 of the first trace layer g in the first implementation.

[0354] It should be noted that the second connection trace m3 can be located at the metal layer or the trace layer. The embodiments of the present application do not limit this, as long as the first sub-signal line m1 and the second sub-signal line m2 can be connected.

[0355] In order to clearly show the film layers at the position of the second connection trace (the area close to the first display area 10a of the second display area 10b can be referred to as the FDC transition area), the film layers at the position of the second connection trace when the pixel circuit includes eight transistors are briefly introduced in the following in the form of single layers and gradually stacked layers.

[0356] Figure 76 is a partial schematic view of the first gate layer of another display panel provided by the embodiments of the present application. Figure 77 is a partial schematic view of the active layer and the first gate layer of another display panel provided by the embodiments of the present application. Referring to Figure 76 and Figure 77 The first gate layer b includes the first gate insulating layer G1, the second gate insulating layer G2, the third gate insulating layer G3, the fourth gate insulating layer G4, the first interlayer dielectric layer ILD1, the second interlayer dielectric layer ILD2, and the passivation layer PVX. Figure 9 and Figure 10In addition to the patterns introduced in the above, the second connection wire m3a is further included. One end of the second connection wire m3a is connected with the gate layer pattern b1 of the first reset signal line Preset in the first pixel circuit, and the other end is connected with the gate layer pattern b1 of the first reset signal line Preset in the second pixel circuit.

[0357] Figure 78 is a partial schematic view of a second gate layer of a display panel provided by an embodiment of the present application. Figure 79 is a partial schematic view of an active layer, a first gate layer, and a second gate layer of a display panel provided by an embodiment of the present application. Refer to Figure 78 and Figure 79 , the related design of the second gate layer c can be the same as the design shown in Figure 11 and Figure 12 , which will not be described herein again by the embodiment of the present application.

[0358] Figure 80 is a partial schematic view of an oxide layer of a display panel provided by an embodiment of the present application. Figure 81 is a partial schematic view of an active layer, a first gate layer, a second gate layer, and an oxide layer of a display panel provided by an embodiment of the present application. Refer to Figure 78 and Figure 79 , the related design of the second gate layer c can be the same as the design shown in Figure 13 and Figure 14 , which will not be described herein again by the embodiment of the present application.

[0359] Figure 82 is a partial schematic view of a third gate layer of a display panel provided by an embodiment of the present application. Figure 83 is a partial schematic view of an active layer, a first gate layer, a second gate layer, an oxide layer, and a third gate layer of a display panel provided by an embodiment of the present application. Refer to Figure 82 and Figure 83 , the third gate layer e further includes, in addition to the patterns introduced in the above, Figure 15 and Figure 16 , the second connection wire m3b is further included. One end of the second connection wire m3b is connected with the top gate pattern e1 of the second transistor T2 in the first pixel circuit, and the other end is connected with the top gate pattern e1 of the second transistor T2 in the second pixel circuit. The second connection wire m3b can be used as a part of the first gate signal line Gate_N.

[0360] Figure 84 is a partial schematic view of a first source-drain layer of a display panel provided by an embodiment of the present application. Figure 85Figure 1 is a partial schematic diagram of a first wiring layer of a display panel according to an embodiment of the present application. Figure 84 and Figure 85 In addition to the various patterns described in Figure 21 and Figure 22 , the first source-drain layer f also includes a second connection trace m3c. One end of the second connection trace m3c is connected to the gate layer pattern b2 of the second gate signal line Gate_P in the first pixel circuit, and the other end is connected to the gate layer pattern b2 of the second gate signal line Gate_P in the second pixel circuit. Since the gate layer pattern b2 is located in the first gate layer b, and the second connection trace m3c is located in the first source-drain layer f, the second connection trace m3c and the gate layer pattern b2 are connected through a via in the insulating layer therebetween.

[0361] In addition, Figure 84 and Figure 85 The first reset power supply line vinit1' is only a short line because it can be a first reset power supply line of the first display area 10a closest to the second display area 10b, and the first reset power supply line vinit1' can be directly connected to the first connection trace 105.

[0362] Figure 86 Figure 1 is a partial schematic diagram of a first wiring layer of a display panel according to an embodiment of the present application. Figure 87 Figure 1 is a partial schematic diagram of a first wiring layer of a display panel according to an embodiment of the present application. Figure 86 and Figure 87 In addition to the various patterns described in Figure 25 and Figure 26 , the first wiring layer g also includes a second connection trace m3d. One end of the second connection trace m3d is connected to the gate layer pattern b3 of the second reset signal line Preset_H in the first pixel circuit, and the other end is connected to the gate layer pattern b3 of the second reset signal line Preset_H in the second pixel circuit. Since the gate layer pattern b3 is located in the first gate layer b, and the second connection trace m3d is located in the first wiring layer g, the second connection trace m3d and the gate layer pattern b3 are connected through a via in the insulating layer therebetween.

[0363] Figure 88 Figure 1 is a partial schematic diagram of a first wiring layer of a display panel according to an embodiment of the present application. Figure 89Figure 1 is a partial stack diagram of an active layer of a display panel according to an embodiment of the present application, which includes a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer of interlayer dielectric, a second layer of interlayer dielectric, a first source-drain layer, a first wiring layer, a first planarization layer, and a second wiring layer. Figure 88 and Figure 89 The related design of the second wiring layer h can be the same as the design shown in Figure 29 and Figure 30 , which will not be described herein again.

[0364] Figure 90 Figure 2 is a partial stack diagram of an active layer of a display panel according to another embodiment of the present application, which includes a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer of interlayer dielectric, a second layer of interlayer dielectric, a first source-drain layer, a first wiring layer, a first planarization layer, a second wiring layer, and a second planarization layer. Figure 91 Figure 3 is a partial stack diagram of an active layer of a display panel according to another embodiment of the present application, which includes a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer of interlayer dielectric, a second layer of interlayer dielectric, a first source-drain layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, and a second source-drain layer. Figure 92 Figure 4 is a partial stack diagram of an active layer of a display panel according to another embodiment of the present application, which includes a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer of interlayer dielectric, a second layer of interlayer dielectric, a first source-drain layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, a second source-drain layer, and a third planarization layer. Figure 93 Figure 5 is a partial stack diagram of an active layer of a display panel according to another embodiment of the present application, which includes a first gate layer, a second gate layer, an oxide layer, a third gate layer, a first layer of interlayer dielectric, a second layer of interlayer dielectric, a first source-drain layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, a second source-drain layer, a third planarization layer, and an anode layer. Figure 90 to Figure 93 The related design of the second planarization layer PLN2, the second wiring layer i, the third planarization layer PLN3, and the anode layer can be the same as the design described in the first implementation manner above, which will not be described herein again.

[0365] In combination with Figure 76 to Figure 94The first target signal line is a first reset signal line Preset. The first sub-signal line m1 and the second sub-signal line m2 of the first reset signal line Preset do not include a part located in a metal layer, but are located in the first routing layer g. The second connection routing m3a of the first reset signal line Preset can be located in the first gate layer. The second target signal line is a first gate signal line Gate_N. The second connection routing m3b of the first gate signal line Gate_N is located in the third gate layer. The third target signal line is a second gate signal line Gate_P. The second connection routing m3c of the second gate signal line Gate_P is located in the first source-drain layer. The fourth target signal line is a second reset signal line Preset_H. The second connection routing m3d of the second reset signal line Preset_H is located in the first routing layer g.

[0366] It should be noted that the second connection routings m3 of different target signal lines can also be designed in other manners, which are not limited in the embodiments of the present application.

[0367] Reference Figure 7 The display panel 10 can further include an anode layer 1071, a pixel definition layer (PDL) 1072, a light-emitting layer 1073, and a cathode layer 1074, which are sequentially stacked in a direction away from the substrate 101 and constitute a light-emitting unit 107. The anode layer 1071 of each light-emitting unit is connected to at least one pixel circuit. The pixel definition layer includes a plurality of hollow regions, each of which is used to expose the anode layer of a light-emitting unit.

[0368] It should be noted that the display panel 10 further includes a pixel circuit group located in the second display area 10b, and the pixel circuit group located in the second display area 10b can also include a plurality of first pixel circuits and a plurality of second pixel circuits.

[0369] The second display area 10b and the first display area 10a are the same in that the plurality of first pixel circuits and the plurality of second pixel circuits are offset arranged in the first direction X, and the plurality of first pixel circuits and the plurality of second pixel circuits are staggered arranged.

[0370] The second display area 10b and the first display area 10a are different in that the design directions of the plurality of first pixel circuits and the plurality of second pixel circuits of the second display area 10b can be the same. In addition, the second display area 10b does not need to design an optical sensor, and thus the transmittance requirement thereof can be less than that of the first display area 10a. Therefore, the signal lines of the second display area 10b can all achieve signal transmission through a metal layer, without layer switching through a routing layer.

[0371] In the embodiments of the present application, the material of the first wiring layer g and the second wiring layer h can be a conductive transparent material, for example, indium tin oxide (ITO). The first wiring layer g can be referred to as an ITO1 layer, and the second wiring layer can be referred to as an ITO2 layer.

[0372] To sum up, the display panel provided in the embodiments of the present application includes a plurality of first pixel circuits and a plurality of second pixel circuits in each pixel circuit group, the plurality of first pixel circuits and the plurality of second pixel circuits in each pixel circuit group are arranged alternately, the design directions of the plurality of first pixel circuits and the plurality of second pixel circuits in each pixel circuit group are opposite, and the plurality of first pixel circuits and the plurality of second pixel circuits are arranged offset in the first direction. In this way, the distance between the first connection of the first pixel circuit and the second connection of the second pixel circuit in the first direction can be small. Further, the first signal line can be directly connected with the first connection and the second connection, without the need to design a switching hole between adjacent pixel circuits and connect through a wiring layer. The scheme of the embodiments of the present application can reduce the number of switching holes required to be designed in the layout, so that even if the requirement of PPI of the display panel is high, there is still enough space to design a small number of switching holes to realize the transmission of signals.

[0373] In the embodiments of the present application, with reference to Figure 1 The substrate 101 of the display panel 10 can have a first display area 10a. The first display area 10a is used to arrange an optical sensor. Optionally, the optical sensor can be a front camera, and the first display area 10a can be referred to as an FDC area.

[0374] With reference to Figure 2 The display panel 10 can include a substrate 101, a plurality of pixel circuit groups 102, and a plurality of first signal lines 103 corresponding to the plurality of pixel circuit groups 102.

[0375] In the embodiments of the present application, the plurality of pixel circuit groups 102 are arranged along a first direction X in the first display area 10a. At least one pixel circuit group 102 includes a plurality of first pixel circuits 1021 arranged along a second direction Y and a plurality of second pixel circuits 1022 arranged along the second direction Y. The first direction X and the second direction Y are perpendicular, for example, the first direction X is a pixel column direction, and the second direction Y is a pixel row direction.

[0376] The first and second pixel circuit groups 102 and 103 are alternately arranged in the first direction X. Each of the first and second pixel circuit groups 102 and 103 includes a plurality of first pixel circuits 1021 and a plurality of second pixel circuits 1022 arranged in the second direction Y. Each of the first and second pixel circuits 1021 and 1022 includes a first boundary and a second boundary extending in the second direction Y and arranged in the first direction X. The first and second boundaries 1021a and 1021b of the first pixel circuit 1021 are arranged in a direction opposite to the first and second boundaries 1022a and 1022b of the second pixel circuit 1022.

[0377] The distance between the first boundary 1021a of the first pixel circuit 1021 and the first boundary 1022a of the second pixel circuit 1022 in the first direction X is greater than the first distance H1, and the distance between the second boundary 1021b of the first pixel circuit 1021 and the second boundary 1022b of the second pixel circuit 1022 in the first direction X is less than the first distance H1. The first distance H1 is the distance between the first and second boundaries of the same pixel circuit in the first direction X, such as the distance between the first and second boundaries of the first pixel circuit 1021 or the second pixel circuit 1022 in the first direction X. The distance between the first and second boundaries 1021a and 1021b of the first pixel circuit 1021 in the first direction X is equal to the distance between the first and second boundaries 1022a and 1022b of the second pixel circuit 1022 in the first direction X.

[0378] The first boundary 1021a of the first pixel circuit 1021 can correspond to the first boundary 1022a of the second pixel circuit 1022, and the second boundary 1021b of the first pixel circuit 1021 can correspond to the second boundary 1022b of the second pixel circuit 1022. The two boundaries can correspond to the same structure of the pixel circuit at the position of the two boundaries. The design direction of the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 is opposite. Assuming that the design direction of the first pixel circuit 1021 is referred to as a positive direction, the design direction of the second pixel circuit 1022 can be referred to as a reverse direction. Alternatively, assuming that the design direction of the first pixel circuit 1021 is referred to as a reverse direction, the design direction of the second pixel circuit 1022 can be referred to as a positive direction.

[0379] Thus, the above arrangement of the first and second pixel circuits 1021 and 1022 can cause the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 to have a certain offset in the first direction X. After the offset, the second boundaries 1021b of the plurality of first pixel circuits 1021 and the second boundaries 1022b of the plurality of second pixel circuits 1022 are located between the extension lines of the first boundaries 1021a of the first pixel circuits 1021 and the first boundaries 1022a of the second pixel circuits 1022.

[0380] In the embodiment of the present application, each first signal line 103 can be a unitary structure, and can be connected to each of the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 included in the corresponding one pixel circuit group 102, so that each first signal line 103 provides signals for all pixel circuits included in the corresponding one pixel circuit group 102 located in the first display area 10a. Wherein, the first signal line 103 being a unitary structure can mean that the first signal line 103 is located in only one film layer of the display panel 10 in the part of the first display area 10a, without the need to change layers.

[0381] Optionally, since the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 are offset and arranged in the first direction X, and the design directions are opposite, the connection positions of the first signal line 103 and the plurality of first pixel circuits 1021, and the connection positions of the first signal line 103 and the plurality of second pixel circuits 1022 can also have a certain offset in the first direction X. For example, each first signal line 103 is connected to each first pixel circuit 1021 in the corresponding one pixel circuit group 102, and the first signal line 103 is connected to each second pixel circuit 1022 in the corresponding one pixel circuit group 102.

[0382] In the embodiment of the present application, since the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 are offset and arranged in the first direction X, and the design directions are opposite, the first pixel circuits 1021 and the second pixel circuits 1022 in the adjacent two pixel circuit groups of the plurality of pixel circuit groups 102 enclose a plurality of target areas. The orthographic projection of the target area on the substrate 101 does not overlap with the orthographic projection of the first pixel circuit 1021 on the substrate 101 and the orthographic projection of the second pixel circuit 1022 on the substrate 101. Wherein, the transmittance of the target area is greater than the transmittance of the area where the first pixel circuit 1021 and the second pixel circuit 1022 are located. Thus, even if the pixel circuit is built-in in the FDC area, the target area of the FDC area can also have a certain light transmittance, so that the photoelectric sensor arranged in the FDC area can be normally used.

[0383] In addition, by making the design directions of the plurality of first pixel circuits 1021 and the plurality of second pixel circuits 1022 different, having a certain offset in the first direction X, and being arranged alternately, the connection positions of the first signal line 103 and the first pixel circuit 1021, and the connection positions of the first signal line 103 and the second pixel circuit 1022 can have a smaller distance in the first direction X, such as being on the same horizontal line or near the same horizontal line in the second direction Y.

[0384] Therefore, the first signal line 103 can be directly connected with the pixel circuits (the first pixel circuits 1021 and the second pixel circuits 1022) in the pixel circuit group 102, without designing a switching hole between adjacent pixel circuits and connecting through a wiring layer. Further, the number of switching holes required to be designed in a layout can be reduced, and even if the PPI requirement of the display panel is high, there is still enough space to design a smaller number of switching holes to realize signal transmission.

[0385] Optionally, the distance between the connection of the first signal line 103 and the first pixel circuit 1021 and the connection of the first signal line 103 and the second pixel circuit 1022 in the first direction X is less than a distance threshold. The distance threshold can be a pre-designed fixed value. The distance threshold can be small enough to make the two connections almost on the same horizontal line or near the same horizontal line.

[0386] In summary, the display panel provided in the embodiments of the present application includes that the first pixel circuits and the second pixel circuits in each pixel circuit group are alternately arranged, the first pixel circuits and the second pixel circuits in each pixel circuit group are designed in opposite directions, and the first pixel circuits and the second pixel circuits are offset arranged in the first direction. Therefore, the distance between the connection of the first signal line and the first pixel circuit and the connection of the first signal line and the second pixel circuit in the first direction can be small. Further, adjacent pixel circuits can be directly connected through the first signal line, without designing a switching hole between adjacent pixel circuits and connecting through a wiring layer. The scheme of the embodiments of the present application can reduce the number of switching holes required to be designed in a layout, and even if the PPI requirement of the display panel is high, there is still enough space to design a smaller number of switching holes to realize signal transmission.

[0387] For this embodiment, other related features can be the same as those of the above-mentioned embodiments, and further, the detailed description of the above-mentioned embodiments can be referred to, which will not be repeated here.

[0388] Figure 95 is a structural schematic diagram of a display device provided in the embodiments of the present application. Referring to Figure 95The display device can include the display panel 10 and the electrical element such as the sensor 02 provided in the above embodiments, for example, an optical sensor. Taking a mobile phone as an example, the display device includes optical sensors such as a front camera, a proximity light sensor, a 3D sensing module, and the like. These optical components need to receive light from the display side of the display device to realize the corresponding functions. In the display device, the optical sensor is usually installed on the non-display side of the display panel, and the photosensitive surface side of the optical sensor faces the display panel. The optical sensor has a normal projection on the substrate 101, and the normal projection at least partially overlaps the first display area 10a in the substrate 101.

[0389] In the embodiments of the present application, the display device can be an active-matrix organic light-emitting diode (AMOLED) display device, a passive-matrix organic light-emitting diode (PMOLED) display device, a quantum dot light emitting diode (QLED) display device, electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function.

[0390] Since the display device can have substantially the same technical effects as the display panel described in the above embodiments, for the purpose of brevity, the technical effects of the display device are not described again here.

[0391] It will be understood that, although the terms first and second, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed above could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0392] Spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device in the figures is inverted, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or one or more intervening layers can also be present.

[0393] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. In the description, specific details are set forth in order to provide a thorough understanding of certain embodiments or examples. However, various embodiments or examples can be practiced without these specific details. In other instances, well-known methods, procedures, components and / or circuits have not been described in detail so as not to unnecessarily obscure aspects of the embodiments or examples.

[0394] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0395] The above description is merely illustrative of the exemplary embodiments of this application and is not intended to limit the scope of the application. As such, modifications and variations of the embodiments disclosed herein can be made by those skilled in the art without departing from the spirit or the scope of the application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate substrate having a first display area; a plurality of pixel circuit groups arranged along a first direction in the first display area, at least one of the pixel circuit groups comprising a plurality of first pixel circuits arranged along a second direction and a plurality of second pixel circuits arranged along the second direction, and the plurality of first pixel circuits and the plurality of second pixel circuits being arranged alternately, each pixel circuit comprising a first boundary extending along the second direction and arranged along the first direction and a second boundary extending along the second direction and arranged along the first direction, the first boundary and the second boundary of the first pixel circuit being arranged in a direction opposite to the first boundary and the second boundary of the second pixel circuit, for each of the pixel circuit groups, a distance between the first boundary of the first pixel circuit and the first boundary of the second pixel circuit along the first direction being greater than a first distance, and a distance between the second boundary of the first pixel circuit and the second boundary of the second pixel circuit along the first direction being less than the first distance, the first distance being a distance between the first boundary and the second boundary of the same pixel circuit along the first direction; and a plurality of first signal lines corresponding to the plurality of pixel circuit groups one by one, each of the first signal lines being connected to each of the first pixel circuits in the corresponding pixel circuit group at a first connection and being connected to each of the second pixel circuits in the corresponding pixel circuit group at a second connection; wherein a distance between the first connection and the first boundary of the first pixel circuit is equal to a distance between the second connection and the first boundary of the second pixel circuit, a distance between the first connection and the second connection along the first direction is less than a second distance, and the second distance is a distance between the first boundary of the first pixel circuit and the second boundary of the second pixel circuit along the first direction.

2. The display panel of claim 1, wherein, The first signal lines are light-emitting control signal lines.

3. The display panel of claim 1, wherein, The plurality of pixel circuit groups at least comprises a first pixel circuit group and a second pixel circuit group arranged along the first direction, a distance between the first boundary of the second pixel circuit in the first pixel circuit group and the first boundary of the first pixel circuit in the second pixel circuit group along the first direction being less than the second distance. The display panel further comprises a plurality of second signal lines in the first display area, each of the second signal lines being connected to the second pixel circuit in the first pixel circuit group and to the first pixel circuit in the second pixel circuit group.

4. The display panel of claim 3, wherein, The substrate substrate further has a second display area at least partially surrounding the first display area, and the display panel further comprises a first connection trace in the second display area, the first connection trace at least partially surrounding the first display area; wherein at least one end of each of the second signal lines is connected to the first connection trace, and each of the second signal lines transmits a signal received from the first connection trace to the pixel circuit connected to the second signal line.

5. The display panel of claim 3, wherein, The second signal lines are first reset power supply lines.

6. The display panel of any of claims 1 to 5, wherein, The display panel further comprises a plurality of third signal lines corresponding to the plurality of pixel circuit groups one by one; Each third signal line is connected with the first pixel circuit and the second pixel circuit in the corresponding pixel circuit group; The signal transmitted by the third signal line is different from the signal transmitted by the first signal line.

7. The display panel of claim 6, wherein, Each pixel circuit in the first pixel circuit and the second pixel circuit in each pixel circuit group comprises: A first transistor, a gate of the first transistor is connected with a first reset signal line, a first pole of the first transistor is connected with a first reset power supply line, and a second pole of the first transistor is connected with a second node; A second transistor, a gate of the second transistor is connected with a first gate signal line included in the display panel, a first pole of the second transistor is connected with a third node, and a second pole of the second transistor is connected with the second node; A third transistor, a gate of the third transistor is connected with the second node, a first pole of the third transistor is connected with a first node, and a second pole of the third transistor is connected with the third node; A fourth transistor, a gate of the fourth transistor is connected with a second gate signal line included in the display panel, a first pole of the fourth transistor is connected with a data signal line included in the display panel, and a second pole of the fourth transistor is connected with the first node; A fifth transistor, a gate of the fifth transistor is connected with a light-emitting control signal line, a first pole of the fifth transistor is connected with a driving power supply line included in the display panel, and a second pole of the fifth transistor is connected with the first node; A sixth transistor, a gate of the sixth transistor is connected with the light-emitting control signal line, a first pole of the sixth transistor is connected with the third node, and a second pole of the sixth transistor is connected with a light-emitting unit; A seventh transistor, a gate of the seventh transistor is connected with the second gate signal line included in the display panel, a first pole of the seventh transistor is connected with a second reset power supply line, and a second pole of the seventh transistor is connected with the light-emitting unit; A storage capacitor, one end of the storage capacitor is connected with the driving power supply line, and the other end of the storage capacitor is connected with the second node.

8. The display panel of claim 7, wherein, The third signal line is the second gate signal line.

9. The display panel of claim 7, wherein, The first transistor and the second transistor are oxide thin film transistors; The third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are low-temperature polysilicon thin film transistors.

10. The display panel of claim 9, wherein, The display panel comprises, in a direction away from the substrate, an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a buffer layer, an oxide layer, a third gate insulating layer, a third gate layer, an interlayer dielectric layer, and a first source-drain layer which are sequentially stacked and constitute the pixel circuit; The second transistor is composed of the second gate layer, the oxide layer, and the third gate layer; The first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, and the seventh transistor are composed of the active layer, the first gate layer, and the first source-drain layer.

11. The display panel of claim 7, wherein, The display panel comprises an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a buffer layer, an oxide layer, a third gate insulating layer, a third gate layer, an interlayer dielectric layer, and a first source-drain layer which are sequentially stacked in a direction away from the substrate and constitute the pixel circuit; The first signal line is located on the first gate layer, and the second signal line is located on the first source-drain layer. The third signal line comprises a first part, a second part, and a third part which are sequentially connected, the first part has at least partial overlap with the first pixel circuit on the substrate, the second part has no overlap with the first pixel circuit and the second pixel circuit on the substrate, and the third part has at least partial overlap with the second pixel circuit on the substrate; the first part and the third part are located on the first gate layer, and the second part is located on the first source-drain layer.

12. The display panel of claim 7, wherein, Each of the first pixel circuit and the second pixel circuit in each of the pixel circuit groups further comprises an eighth transistor, the gate of the eighth transistor is connected with a second reset signal line of the display panel, the first pole of the eighth transistor is connected with a third reset power line of the display panel, and the second pole of the eighth transistor is connected with the first node. The third signal line is the third reset power line.

13. The display panel of claim 12, wherein, The second transistor is an oxide thin film transistor. The first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are low-temperature polysilicon thin film transistors.

14. The display panel of claim 13, wherein, The display panel comprises an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a buffer layer, an oxide layer, a third gate insulating layer, a third gate layer, an interlayer dielectric layer, and a first source-drain layer which are sequentially stacked in a direction away from the substrate and constitute the pixel circuit; The second transistor is composed of the second gate layer, the oxide layer, and the third gate layer; The first transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are composed of the active layer, the first gate layer, and the first source-drain layer.

15. The display panel of claim 13, wherein, The display panel comprises, in a direction away from the substrate, an active layer, a first gate insulating layer, a first gate layer, a second gate insulating layer, a second gate layer, a third gate insulating layer, an oxide layer, a fourth gate insulating layer, a third gate layer, an interlayer dielectric layer, and a first source-drain layer, which constitute the pixel circuit. The first signal line is located in the first gate layer, the second signal line is located in the first source-drain layer, and the third signal line is located in the third gate layer.

16. The display panel of any one of claims 10-11, and 14-15, wherein, The display panel further comprises, in a direction away from the first source-drain layer, a passivation layer, a first wiring layer, a first planarization layer, a second wiring layer, a second planarization layer, a second source-drain layer, and a third planarization layer, which constitute the pixel circuit.

17. The display panel of claim 6, wherein, Each target signal line in the display panel comprises a first sub-signal line, a second sub-signal line, and a second connection wiring. The first sub-signal line is located in the first display area, and the first sub-signal line is connected to a plurality of first pixel circuits in one pixel circuit group. The second sub-signal line is located in the first display area, and the second sub-signal line is connected to a plurality of second pixel circuits in one pixel circuit group. The plurality of second pixel circuits connected by the second sub-signal line of each target signal line and the plurality of first pixel circuits connected by the first sub-signal line of the target signal line belong to the same pixel circuit group. The second connection wiring is located in the second display area, one end of the second connection wiring is connected to the first sub-signal line, and the other end of the second connection wiring is connected to the second sub-signal line. The target signal line is a signal line other than the first signal line, the second signal line, and the third signal line in the display panel, which provides a signal in the second direction.

18. The display panel of claim 17, wherein, The first sub-signal line comprises a connected fourth part and a fifth part. The orthographic projection of the fourth part on the substrate at least partially overlaps the orthographic projection of the first pixel circuit on the substrate. The orthographic projection of the fifth part on the substrate is located between the orthographic projections of two adjacent first pixel circuits on the substrate. The second sub-signal line comprises a connected sixth part and a seventh part. The orthographic projection of the sixth part on the substrate at least partially overlaps the orthographic projection of the second pixel circuit on the substrate. The orthographic projection of the seventh part on the substrate is located between the orthographic projections of two adjacent second pixel circuits on the substrate. The fourth part and the sixth part are located in the same layer, and the fourth part and the sixth part are located in a metal layer. The fifth part and the seventh part are located in the same layer, and the fifth part and the seventh part are located in a wiring layer.

19. A display panel, characterized by The display panel comprises: a substrate, the substrate having a first display area; A plurality of pixel circuit groups arranged in a first direction in the first display area, at least one of the pixel circuit groups comprising: a plurality of first pixel circuits arranged in a second direction and a plurality of second pixel circuits arranged in the second direction, and the plurality of first pixel circuits and the plurality of second pixel circuits being arranged alternately, each of the pixel circuits comprising a first boundary extending in the second direction and arranged in the first direction and a second boundary extending in the second direction and arranged in the first direction, the first boundary and the second boundary of the first pixel circuits being arranged in a direction opposite to the first boundary and the second boundary of the second pixel circuits, for each of the pixel circuit groups, a distance between the first boundary of the first pixel circuit and the first boundary of the second pixel circuit in the first direction being greater than a first distance, and a distance between the second boundary of the first pixel circuit and the second boundary of the second pixel circuit in the first direction being less than the first distance, the first distance being a distance between the first boundary and the second boundary of the same pixel circuit in the first direction; and a plurality of first signal lines corresponding to the plurality of pixel circuit groups one by one, each of the first signal lines being connected to the first pixel circuit and the second pixel circuit in a corresponding one of the pixel circuit groups; wherein the first pixel circuit and the second pixel circuit in each of two adjacent pixel circuit groups of the plurality of pixel circuit groups enclose a plurality of target areas, a projection of each of the target areas on the substrate is not overlapped with a projection of the first pixel circuit on the substrate and a projection of the second pixel circuit on the substrate, and a transmittance of each of the target areas is greater than a transmittance of an area where the first pixel circuit and the second pixel circuit are located.

20. A display device comprising: The display device comprises the display panel and the optical sensor of any one of claims 1 to 19, and a projection of the optical sensor on the display panel at least partially overlaps with the first display area in the display panel.

Images