Display substrate, display panel and display device

Abstract

A display substrate, a display panel and a display device are provided. The display substrate comprises a first semiconductor layer arranged on a substrate, a first conductive layer arranged on a side of the first semiconductor layer away from the substrate, and a second conductive layer arranged on a side of the first conductive layer away from the substrate. The display substrate further comprises a pixel driving circuit arranged on the substrate, the pixel driving circuit comprising a driving circuit, a storage circuit and a reset circuit. The reset circuit is electrically connected to a first terminal of the driving circuit, and is configured to initialize a potential of the first terminal of the driving circuit in an initialization stage. The driving circuit is configured to control communication between the first terminal of the driving circuit and a second terminal of the driving circuit under control of a potential of a control terminal of the driving circuit. The storage circuit is electrically connected to the control terminal of the driving circuit, and is configured to store electrical energy. The reset circuit comprises a first capacitor, and the storage circuit comprises a second capacitor. An area of an overlapping portion of a first plate of the first capacitor and a second plate of the first capacitor in a projection of the substrate is less than an area of an overlapping portion of a first plate of the second capacitor and a second plate of the second capacitor in the projection of the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a display substrate, a display panel, and a display device. Background Art

[0002] An organic light-emitting diode (OLED) display device is a type of display device that uses light-emitting OLEDs to display images and other information. OLED display devices have characteristics such as low power consumption, high brightness, and high response speed. Low-temperature polysilicon oxide thin-film transistor (LTPO TFT) technology is an emerging thin-film transistor technology in recent years. Theoretically, LTPO TFT can save 5-15% of power compared to traditional low-temperature polysilicon thin-film transistor (LTPS TFT) technology, making the power consumption of the entire display screen lower.

[0003] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art. Summary of the Invention

[0004] In one aspect, a display substrate is provided, wherein the display substrate comprises: a base substrate;

[0005] A first semiconductor layer provided on the base substrate;

[0006] A first conductive layer disposed on a side of the first semiconductor layer away from the base substrate; and

[0007] a second conductive layer disposed on a side of the first conductive layer away from the base substrate;

[0008] The display substrate further includes a pixel driving circuit disposed on the base substrate, the pixel driving circuit including a driving circuit, a storage circuit, and a reset circuit, the reset circuit being electrically connected to the first terminal of the driving circuit or the second terminal of the driving circuit and configured to initialize the potential of the first terminal of the driving circuit or the second terminal of the driving circuit during an initialization phase, the driving circuit being configured to control communication between the first terminal of the driving circuit and the second terminal of the driving circuit under the control of the potential of its control terminal, and the energy storage circuit being electrically connected to the control terminal of the driving circuit and configured to store electrical energy;

[0009] The reset circuit includes a first capacitor, the storage circuit includes a second capacitor, the first capacitor includes a first plate and a second plate arranged opposite to each other, the second capacitor includes a first plate and a second plate arranged opposite to each other, the first plate of the first capacitor and the first plate of the second capacitor are located in the first conductive layer, the second plate of the first capacitor and the second plate of the second capacitor are located in the second conductive layer, the first plate of the first capacitor and the first plate of the second capacitor are arranged at an orthographic projection interval on the substrate, the second plate of the first capacitor and the second plate of the second capacitor are arranged at an orthographic projection interval on the substrate, and the first plate of the first capacitor and the second plate of the first capacitor are arranged at an orthographic projection interval on the substrate. The orthographic projections of the first plate of the second capacitor and the second plate of the second capacitor on the substrate at least partially overlap, the orthographic projections of the first plate of the first capacitor and the second plate of the second capacitor on the substrate at least partially overlap, the area of ​​the overlapping portion of the orthographic projections of the first plate of the first capacitor and the second plate of the first capacitor on the substrate is smaller than the area of ​​the overlapping portion of the orthographic projections of the first plate of the second capacitor and the second plate of the second capacitor on the substrate, and the ratio of the area of ​​the overlapping portion of the orthographic projections of the first plate of the second capacitor and the second plate of the second capacitor on the substrate to the area of ​​the overlapping portion of the orthographic projections of the first plate of the first capacitor and the second plate of the first capacitor on the substrate is in a range of 5 to 20.

[0010] According to some exemplary embodiments, the display substrate also includes a first light-emitting control line arranged on the base substrate, and the first light-emitting control line is used to supply a first light-emitting control signal to the pixel driving circuit; the first light-emitting control line is located in the first conductive layer, and the part where the first light-emitting control line overlaps with the second plate of the first capacitor constitutes the first plate of the first capacitor.

[0011] According to some exemplary embodiments, the pixel driving circuit includes a first light-emitting control circuit and a second light-emitting control circuit, the first light-emitting control circuit includes a fifth transistor, the second light-emitting control circuit includes a sixth transistor, the fifth transistor includes a fifth gate, the sixth transistor includes a sixth gate, and the first light-emitting control line applies a first light-emitting control signal to the fifth gate, the sixth gate and the first plate of the first capacitor.

[0012] According to some exemplary embodiments, a portion of the first light-emitting control line overlapping with the first semiconductor layer constitutes the fifth gate, another portion of the first light-emitting control line overlapping with the first semiconductor layer constitutes the sixth gate, the first light-emitting control line also includes a widening portion, the widening portion is located between the fifth gate and the sixth gate along the first direction, a size of the widening portion along the second direction is larger than a size of each of the fifth gate and the sixth gate along the second direction, wherein the first light-emitting control line extends along the first direction, the second direction intersects with the first direction; and at least a portion of the widening portion constitutes the first plate of the first capacitor.

[0013] According to some exemplary embodiments, the orthographic projection of the second plate of the first capacitor on the substrate covers the orthographic projection of the widened portion on the substrate; and / or

[0014] The orthographic projection area of ​​the first electrode plate of the second capacitor on the substrate is larger than the orthographic projection area of ​​the widened portion on the substrate; and / or,

[0015] An orthographic projection area of ​​the second plate of the second capacitor on the substrate is larger than an orthographic projection area of ​​the second plate of the first capacitor on the substrate.

[0016] According to some exemplary embodiments, a ratio of an area of ​​an overlapping portion of an orthographic projection of the first plate of the second capacitor and the second plate of the second capacitor on the substrate to an area of ​​an overlapping portion of an orthographic projection of the first plate of the first capacitor and the second plate of the first capacitor on the substrate is in a range of 8 to 10.

[0017] According to some exemplary embodiments, the second plate of the second capacitor includes a through hole, the through hole exposing at least a portion of the first plate of the second capacitor, and a ratio of an area of ​​an orthographic projection of the second plate of the first capacitor on the substrate to an area of ​​an orthographic projection of the through hole on the substrate is in a range of 1.1 to 5.

[0018] According to some exemplary embodiments, the display substrate further includes a light-emitting element reset line located in the first conductive layer and a light-emitting element arranged on the base substrate, and the pixel driving circuit includes a second initialization circuit, which is used to initialize the first pole of the light-emitting element under the control of a signal provided by the light-emitting element reset line.

[0019] According to some exemplary embodiments, the display substrate further includes a reset control line in the first conductive layer, the pixel driving circuit includes a first initialization circuit, and the first initialization circuit is used to initialize the driving circuit under the control of a reset control signal provided by the reset control line; and the frequency of the signal provided by the light-emitting element reset line is higher than the frequency of the reset control signal provided by the reset control line.

[0020] According to some exemplary embodiments, the display substrate further includes a light-emitting element reset line located in the first conductive layer and a light-emitting element arranged on the base substrate, the pixel driving circuit includes a second initialization circuit, the second initialization circuit includes a seventh transistor, and the portion of the light-emitting element reset line overlapping with the first semiconductor layer constitutes the seventh gate of the seventh transistor; and the orthographic projection of the first plate of the first capacitor on the base substrate is located in the second direction between the orthographic projection of the first plate of the second capacitor on the base substrate and the orthographic projection of the light-emitting element reset line on the base substrate.

[0021] According to some exemplary embodiments, the pixel driving circuit includes a first transistor, the portion where the reset control line overlaps with the first semiconductor layer constitutes a first gate of the first transistor; and the distance between the first gate and the first plate of the first capacitor in the first direction is smaller than the distance between the seventh gate and the first plate of the first capacitor in the first direction.

[0022] According to some exemplary embodiments, the display substrate further includes a second light-emitting control line located in the second conductive layer, and the second light-emitting control line, the second plate of the second capacitor, and the orthographic projection of the second plate of the first capacitor on the base substrate are spaced apart along the second direction; and the orthographic projection of the second plate of the first capacitor on the base substrate and the orthographic projection of the second light-emitting control line on the base substrate are respectively located on both sides of the orthographic projection of the second plate of the second capacitor on the base substrate in the second direction.

[0023] According to some exemplary embodiments, the display substrate further includes: a second semiconductor layer arranged on a side of the second conductive layer away from the base substrate; and a third conductive layer arranged on a side of the second semiconductor layer away from the base substrate, the second semiconductor layer including an oxide semiconductor material; the display substrate includes another second light-emitting control line located in the third conductive layer, the one second light-emitting control line and the other second light-emitting control line being electrically connected; the pixel driving circuit includes an on-off control circuit, the on-off control circuit includes an eighth transistor, the portion of the one second light-emitting control line overlapping with the second semiconductor layer constitutes a bottom gate of the eighth transistor, and the portion of the other second light-emitting control line overlapping with the second semiconductor layer constitutes a top gate of the eighth transistor.

[0024] According to some exemplary embodiments, the display substrate further includes a fourth conductive layer disposed on a side of the third conductive layer away from the base substrate, the driving circuit includes a third transistor; and the display substrate includes a fifth conductive component located in the fourth conductive layer, one end of the fifth conductive component being electrically connected to the second plate of the first capacitor through a first via, and the other end of the fifth conductive component being electrically connected to the first electrode of the third transistor through a second via.

[0025] According to some exemplary embodiments, the display substrate includes a sixth conductive component located in the fourth conductive layer, the sixth conductive component including a first portion, a second portion and a third portion; and the first portion of the sixth conductive component is electrically connected to the first electrode of the fifth transistor through a third via, and the second portion of the sixth conductive component is electrically connected to the second plate of the second capacitor through a fourth via.

[0026] According to some exemplary embodiments, the display substrate further includes a fifth conductive layer disposed on a side of the fourth conductive layer away from the base substrate, the display substrate further includes a first voltage line disposed in the fifth conductive layer; and the third portion of the sixth conductive component is electrically connected to the first voltage line through a fifth via.

[0027] According to some exemplary embodiments, the display substrate includes a seventh conductive component located in the fourth conductive layer, the seventh conductive component being electrically connected to the first electrode of the sixth transistor; and the orthographic projection of the first plate of the first capacitor on the base substrate is located between the orthographic projection of the sixth conductive component on the base substrate and the orthographic projection of the seventh conductive component on the base substrate in a first direction, and any two of the orthographic projection of the first plate of the first capacitor on the base substrate, the orthographic projection of the sixth conductive component on the base substrate, and the orthographic projection of the seventh conductive component on the base substrate are spaced apart.

[0028] According to some exemplary embodiments, a second plate of the first capacitor overlaps, in a plan view, a portion of a projection of the seventh conductive component on the substrate.

[0029] According to some exemplary embodiments, the display substrate comprises a fourth conductive component in the fourth conductive layer, one end of the fourth conductive component is electrically connected to the first electrode of the eighth transistor through a sixth via, and the other end of the fourth conductive component is electrically connected to the third gate of the third transistor through a seventh via and a via hole.

[0030] According to some exemplary embodiments, a projection of the first voltage line on the substrate covers a projection of the fourth conductive component on the substrate; and / or, a projection of the first voltage line on the substrate covers a projection of the active layer of the eighth transistor on the substrate.

[0031] In another aspect, a display panel is provided, comprising the display substrate as described above.

[0032] In yet another aspect, a display device is provided, comprising the display substrate as described above or the display panel as described above. BRIEF DESCRIPTION OF DRAWINGS

[0033] The features and advantages of the present disclosure will become more apparent from the detailed description of example embodiments thereof in conjunction with the accompanying drawings.

[0034] Figure 1 is a plan view of a display device according to some embodiments of the present disclosure;

[0035] Figure 2 is a plan view of a display substrate comprised by a display device according to some embodiments of the present disclosure;

[0036] Figure 3 is a structural block diagram of a pixel driving circuit according to some embodiments of the present disclosure;

[0037] Figure 4 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure;

[0038] Figure 5 is Figure 4 is a timing diagram of at least one embodiment of the pixel driving circuit shown;

[0039] Figure 6A and Figure 6B are respectively schematic diagrams of signals provided by a reset line of a light emitting element according to some exemplary embodiments of the present disclosure;

[0040] Figure 7is a schematic diagram illustrating a planar structure of a first semiconductor layer of a pixel driving circuit according to an example embodiment of the present disclosure;

[0041] Figure 8 is a schematic diagram illustrating a planar structure of a first conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure;

[0042] Figure 9 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer and a first conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure;

[0043] Figure 10 is a schematic diagram illustrating a planar structure of a second conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure;

[0044] Figure 11 is a schematic diagram illustrating a planar structure of a second semiconductor layer of a pixel driving circuit according to an example embodiment of the present disclosure;

[0045] Figure 12 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, and a second semiconductor layer of a pixel driving circuit according to an example embodiment of the present disclosure;

[0046] Figure 13 is a schematic diagram illustrating a planar structure of a third conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure;

[0047] Figure 14 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure;

[0048] Figure 15 is a schematic diagram illustrating a via hole in an insulating layer formed on the structure of Figure 14 ;

[0049] Figure 16 is a schematic diagram illustrating a via hole in an insulating layer formed on the structure of Figure 15 ;

[0050] Figure 17 is a schematic diagram illustrating a planar structure of a fourth conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure;

[0051] Figure 18 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure;

[0052] Figure 19 is a schematic diagram illustrating a planar structure of a fifth conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0053] Figure 20 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0054] Figure 21 is a plan view schematically illustrating relative areas of a first capacitor and a second capacitor;

[0055] Figure 22 FIG. 1 is a diagram showing a display substrate according to some exemplary embodiments of the present disclosure. Figure 20 A schematic diagram of a cross-sectional structure taken along line AA' in FIG; and

[0056] Figure 23 is used Figure 6B The luminous effect diagram of the light-emitting element when a high-frequency signal is applied is shown. DETAILED DESCRIPTION

[0057] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0058] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0059] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, it can be directly on, directly connected to, or directly coupled to the other element, or intervening elements can be present. In contrast, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. Other terms of relationship between elements are to be interpreted in a like fashion, such as "between" versus "directly between," "adjacent" versus "directly adjacent," or "on" versus "directly on," etc. Furthermore, the term "connected" can refer to physical or electrical connection, communication connection, and / or fluid connection. In addition, the X-axis, Y-axis and Z-axis are not limited to three axes of a rectangular coordinate system, and can be interpreted in a wider sense. For example, the X-axis, Y-axis and Z-axis can be perpendicular to one another, or can represent different directions that are not perpendicular to one another. For the purposes of the present disclosure, "at least one of X, Y and Z" and "at least one selected from the group consisting of X, Y and Z" can be interpreted to include only X, only Y, only Z, or any combination of two or more of X, Y and Z such as XYZ, XYY, YZ and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated items.

[0060] It should be noted that, although the terms "first," "second," etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer and / or section from another element, component, region, layer and / or section. Thus, a first element, component, region, layer and / or section discussed below could be termed a second element, component, region, layer and / or section without departing from the teachings of the present disclosure.

[0061] Spatially relative terms, such as "upper," "lower," "left," "right," and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described is turned over in the figure, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Similarly, if a device is turned over, elements described as "above" other elements or features would then be oriented "below" the other elements or features.

[0062] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0063] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0064] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0065] In this document, the term "transistor" may refer to a triode, a thin-film transistor, a field-effect transistor, or other device with similar characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of a transistor other than the control electrode, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode. In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode may be the drain electrode, and the second electrode may be the source electrode; alternatively, the first electrode may be the source electrode, and the second electrode may be the drain electrode.

[0066] The embodiments of the present disclosure provide at least one display substrate. The display substrate includes: a base substrate; a first semiconductor layer provided on the base substrate; a first conductive layer provided on the side of the first semiconductor layer away from the base substrate; and a second conductive layer provided on the side of the first conductive layer away from the base substrate; wherein the display substrate also includes a pixel driving circuit provided on the base substrate, the pixel driving circuit includes a driving circuit, a storage circuit and a reset circuit, the reset circuit is electrically connected to the first end of the driving circuit or the second end of the driving circuit, and is used to initialize the potential of the first end of the driving circuit or the second end of the driving circuit during the initialization phase, the driving circuit is used to control the connection between the first end of the driving circuit and the second end of the driving circuit under the control of the potential of its control end, the energy storage circuit is electrically connected to the control end of the driving circuit, and is used to store electrical energy; the reset circuit includes a first capacitor, the storage circuit includes a second capacitor, and the first capacitor includes a first plate and a second plate that are relatively arranged. The second capacitor includes a first electrode plate and a second electrode plate arranged opposite to each other, the first electrode plate of the first capacitor and the first electrode plate of the second capacitor are located in the first conductive layer, the second electrode plate of the first capacitor and the second electrode plate of the second capacitor are located in the second conductive layer, the orthographic projections of the first electrode plate of the first capacitor and the first electrode plate of the second capacitor on the substrate are arranged at intervals, the orthographic projections of the second electrode plate of the first capacitor and the second electrode plate of the second capacitor on the substrate are arranged at intervals, the orthographic projections of the first electrode plate of the first capacitor and the second electrode plate of the first capacitor on the substrate at least partially overlap, the orthographic projections of the first electrode plate of the second capacitor and the second electrode plate of the second capacitor on the substrate at least partially overlap, and the area of ​​the overlapping portion of the orthographic projections of the first electrode plate of the first capacitor and the second electrode plate of the first capacitor on the substrate is smaller than the area of ​​the overlapping portion of the orthographic projections of the first electrode plate of the second capacitor and the second electrode plate of the second capacitor on the substrate. In an embodiment of the present disclosure, when the pixel driving circuit is operating, before the data voltage is written into the driving circuit, in the initialization stage, the reset circuit initializes the potential of the first end of the driving circuit or the potential of the second end of the driving circuit, which can improve the hysteresis phenomenon of the driving circuit and solve the afterimage, flicker and other phenomena caused by the hysteresis of the driving transistor in the low-frequency state.

[0067] Figure 1 1 is a schematic plan view of a display device according to some embodiments of the present disclosure. For example, the display device may be an OLED display device. Figure 1The display device 1000 can include a display panel 1100, a gate driver 1200, a data driver 1300, a controller 1400, and a voltage generator 1500. The display panel 1100 can include an array substrate 1000 and a plurality of pixels PX, the array substrate 1000 can include a display area AA and a non-display area NA, and the plurality of pixels PX are arranged in the display area AA in an array form. Signals generated by the gate driver 1200 can be applied to the pixels PX through signal lines such as scan signal lines GL, and signals generated by the data driver 1300 can be applied to the pixels PX through signal lines such as data lines DL. A first voltage such as VDD and a second voltage such as VSS can be applied to the pixels PX. The first voltage such as VDD can be higher than the second voltage such as VSS. Alternatively, the first voltage such as VDD can be applied to an anode of a light emitting element (e.g., an OLED), and the second voltage such as VSS can be applied to a cathode of the light emitting element, so that the light emitting element can emit light.

[0068] For example, each of the pixels PX can include a plurality of sub-pixels, such as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or can include a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0069] Figure 2 A plan view of a display substrate included in a display device according to some embodiments of the present disclosure. For example, the display substrate can be an array substrate for an OLED display panel.

[0070] Referring to Figure 2 The display substrate can include a display area AA and a non-display area NA. For example, the display area AA and the non-display area NA can include a plurality of boundaries, such as AAS1, AAS2, AAS3, and AAS4 as shown in Figure 2 The display substrate can further include a driver located within the non-display area NA. For example, the driver can be located at least one side of the display area AA. In the embodiment shown in Figure 2 the driver is located at the left side and the right side of the display area AA, respectively. It should be noted that the left side and the right side herein can be the left side and the right side of the display substrate (screen) as viewed by a human eye during display. The driver can be used to drive each pixel in the display substrate to display. For example, the driver can include the above-mentioned gate driver 1200 and the data driver 1300. The data driver 1300 is used to sequentially latch the input data according to the timing of the clock signal and convert the latched data into an analog signal and then input to each data line of the display substrate. The gate driver 1200 is usually realized by a shift register, which converts the clock signal into an on / off voltage and outputs to each scan signal line of the display substrate, respectively.

[0071] It should be noted that although Figure 2 , the driver circuit is shown to be located on the left and right sides of the display area AA. However, the embodiments of the present disclosure are not limited thereto, and the driver circuit may be located at any appropriate position in the non-display area NA.

[0072] For example, the driver can adopt GOA technology, i.e., Gate Driver on Array (GDA). In GOA technology, the gate driver circuit is directly arranged on the array substrate to replace the external driver chip. Each GOA unit acts as a shift register, and each shift register is connected to a gate line. The shift registers at each level sequentially output the turn-on voltage to achieve row-by-row scanning of pixels. In some embodiments, each shift register can also be connected to multiple gate lines. In this way, it can adapt to the development trend of high-resolution and narrow-frame display substrates.

[0073] Reference Figure 2 The display substrate includes a left GOA circuit DA1, multiple pixels P located in the display area AA, and a right GOA circuit DA2. The left and right GOA circuits DA1 and DA2 are each electrically connected to a display IC via signal lines. The display IC controls the supply of GOA signals. The display IC is, for example, located on the lower side of the display substrate (the direction of human viewing). The left and right GOA circuits DA1 and DA2 are also electrically connected to each pixel via signal lines (e.g., scan signal lines GL) to supply drive signals to each pixel.

[0074] It should be noted that the figure exemplarily shows that the shape of the orthographic projection of the sub-pixel on the substrate is a rounded rectangle, but the embodiments of the present disclosure are not limited to this. For example, the shape of the orthographic projection of the sub-pixel on the substrate can be other shapes such as rectangle, hexagon, pentagon, square, circle, etc. Moreover, the arrangement of the three sub-pixels in a pixel unit is not limited to Figure 1 and Figure 2 The method shown in .

[0075] Combined with reference Figure 1 and Figure 2 Each pixel unit PX may include a plurality of sub-pixels, for example, a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. For ease of understanding, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be described as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, the embodiments of the present disclosure are not limited thereto.

[0076] The plurality of sub-pixels are arranged in an array on the base substrate 1 along the row direction X and the column direction Y. It should be noted that although the row direction X and the column direction Y are perpendicular to each other in the illustrated embodiment, the embodiments of the present disclosure are not limited thereto.

[0077] It should be understood that in the embodiments of the present disclosure, each sub-pixel includes a pixel driving circuit and a light-emitting element. For example, the light-emitting element may be an OLED light-emitting element, including a stacked anode, a light-emitting layer, and a cathode. The pixel driving circuit may include multiple thin-film transistors and at least one storage capacitor.

[0078] Figure 3 is a structural block diagram of a pixel driving circuit according to some embodiments of the present disclosure, Figure 4 is an equivalent circuit diagram of a pixel driving circuit according to some embodiments of the present disclosure. It should be noted that in the following description, an 8T2C pixel driving circuit is used as an example to describe the structure of the pixel driving circuit in detail. However, the embodiments of the present disclosure are not limited to the 8T2C pixel driving circuit. Other known pixel driving circuit structures can be applied to the embodiments of the present disclosure unless there is a conflict.

[0079] like Figure 3 As shown, a pixel driving circuit according to an embodiment of the present disclosure is used to drive a light-emitting element 100. The pixel driving circuit includes a driving circuit 110 and a reset circuit 220. The reset circuit 220 is electrically connected to a first terminal of the driving circuit 110 and is used to initialize the potential of the first terminal of the driving circuit 110 during an initialization phase. The driving circuit 110 is used to control the communication between the first terminal of the driving circuit 110 and the second terminal of the driving circuit 110 under the control of the potential of its control terminal.

[0080] In the embodiment of the present disclosure, when the pixel driving circuit is operating, before the data voltage is written into the driving circuit, in the initialization stage, the reset circuit initializes the potential of the first end of the driving circuit or the potential of the second end of the driving circuit, so as to improve the hysteresis phenomenon of the driving transistor and solve the afterimage, flicker and other phenomena caused by the hysteresis of the driving transistor in the low-frequency state.

[0081] Continue to refer to Figure 3 The pixel driving circuit further includes a first light emitting control circuit 310 and a second light emitting control circuit 320 .

[0082] The first light emitting control circuit 310 is electrically connected with the first light emitting control line E1, the first end of the driving circuit 11 and the first voltage line V1 respectively, and is configured to control the first end of the driving circuit 11 to be in communication with the first voltage line V1 under the control of a first light emitting control signal provided by the first light emitting control line E1.

[0083] The second light emitting control circuit 320 is electrically connected with the second light emitting control line E2, the second end of the driving circuit 11 and the first pole of the light emitting element 100, and is configured to control the second end of the driving circuit 110 to be in communication with the first pole of the light emitting element 100 under the control of a second light emitting control signal provided by the second light emitting control line E2.

[0084] The second pole of the light emitting element 100 is electrically connected with the second voltage line V2.

[0085] In the embodiment of the present disclosure, when the pixel driving circuit is working, in the light emitting stage, the first light emitting control circuit 310 controls the first end of the driving circuit 110 to be in communication with the first voltage line V1 under the control of the first light emitting control signal, and the second light emitting control circuit 320 controls the second end of the driving circuit 110 to be in communication with the first pole of the light emitting element 100 under the control of the second light emitting control signal.

[0086] Referring to Figure 3 and Figure 4 , the pixel driving circuit further comprises a reset circuit 20, and the reset circuit 20 can comprise a first capacitor C1, and the first capacitor C1 can comprise a first pole plate C1a and a second pole plate C1b.

[0087] The first pole plate of the first capacitor C1 is electrically connected with the first light emitting control line E1, and the second pole plate of the first capacitor C1 is electrically connected with the first end of the driving circuit 11.

[0088] In Figure 4 , the label N1 is a first node electrically connected with the control end of the driving circuit 11, the label N2 is a second node electrically connected with the first end of the driving circuit 11, and the label N3 is a third node electrically connected with the second end of the driving circuit 11.

[0089] In an embodiment of the present disclosure, when the pixel driving circuit is working, in the initialization stage, the potential of the light-emitting control signal provided by E1 changes from a low voltage Vgl to a high voltage Vgh, N2 is in a floating state, and the potential of N2 changes with the change of the potential of the first plate of the first capacitor C1, and the potential of N2 becomes V1+Vgh-Vgl. At this time, the gate-source voltage of the driving transistor in the driving circuit 110 is less than Vth (Vth is the threshold voltage of the driving transistor), and the driving transistor is in a conductive bias state, reducing the hysteresis caused by the floating of N2.

[0090] In an embodiment of the present disclosure, when the pixel driving circuit is operating, before data is written, the driving transistor is in an on-bias state, ensuring that the driving transistor in each pixel driving circuit is charged and compensated from the on-bias state without being affected by the data voltage of the previous frame. This can eliminate the influence of the hysteresis of the driving transistor and improve the afterimage and response time.

[0091] Continue to refer to Figure 3 and Figure 4 The pixel driving circuit may further include a storage circuit 210, a data writing circuit 530, a compensation control circuit 520, an on-off control circuit 510, a first initialization circuit 410, and a second initialization circuit 420. The storage circuit 210 is electrically connected to the control terminal of the driving circuit 11 for storing electrical energy. The data writing circuit 530 is electrically connected to the scan line S1, the data line D1, and the first terminal of the driving circuit 110, respectively, and is configured to control the writing of the data voltage on the data line D1 into the first terminal of the driving circuit 110 under the control of the scan signal provided by the scan line S1. The on-off control circuit 510 is electrically connected to the scan line S1, the control terminal of the driving circuit 110, and the connection node N0, respectively, and is configured to control the communication between the control terminal of the driving circuit 110 and the connection node N0 under the control of the scan signal. The compensation control circuit 520 is electrically connected to the scan line S1, the connection node N0, and the second end of the driver circuit 110, respectively, and is configured to control the connection between the connection node N0 and the second end of the driver circuit 110 under the control of the scan signal provided by the scan line S1. The first initialization circuit 410 is electrically connected to the reset control line R1, the first initial voltage line Vi1, and the connection node N0, respectively, and is configured to write the first initial voltage provided by the first initial voltage line to the connection node N0 under the control of the reset control signal provided by the reset control line R1. The second initialization circuit 420 is electrically connected to the light-emitting element reset line R2, the second initial voltage line Vi2, and the first electrode of the light-emitting element 100, respectively, and is configured to write the second initial voltage provided by the second initial voltage line to the first electrode of the light-emitting element 10 under the control of the reset control signal provided by the light-emitting element reset line R2.

[0092] In an embodiment of the present disclosure, when the pixel driving circuit is in operation, a display period may include an initialization phase, a data writing phase, and a light emitting phase that are arranged in sequence.

[0093] During the initialization phase, the on-off control circuit 510, under the control of a scan signal, controls the connection between the control end of the drive circuit 110 and the connection node N0. The first initialization circuit 410, under the control of a reset control signal, writes a first initial voltage into the connection node N0 to write the first initial voltage into the control end of the drive circuit 110. The second initialization circuit 420, under the control of a reset control signal provided by the light-emitting element reset line R2, writes a second initial voltage provided by the second initial voltage line Vi2 into the first electrode of the light-emitting element 100 to control the light-emitting element 100 not to emit light and clear the residual charge in the first electrode of the light-emitting element 100.

[0094] During the data writing phase, the data writing circuit 530, under the control of a scan signal, controls the writing of the data voltage on the data line D1 into the first terminal of the driving circuit 110. The compensation control circuit 520, under the control of a scan signal, controls the connection between the connection node N0 and the second terminal of the driving circuit 110. At the beginning of the data writing phase, the driving transistor in the driving circuit 110 turns on to charge the energy storage circuit with the data voltage, thereby changing the potential of the control terminal of the driving circuit 110, until the driving transistor turns off.

[0095] In the light-emitting stage, the first light-emitting control circuit 310 controls the first end of the driving circuit 110 to be connected to the first voltage line V1 under the control of the first light-emitting control signal, and the second light-emitting control circuit 320 controls the second end of the driving circuit 110 to be connected to the first pole of the light-emitting element 100 under the control of the second light-emitting control signal, and the driving circuit 110 drives the light-emitting element 100 to emit light.

[0096] For example, in Figure 4 In the illustrated embodiment, the reset circuit 220 includes a first capacitor C1; the first light-emitting control circuit 310 includes a fifth transistor T5, and the second light-emitting control circuit 320 includes a sixth transistor T6; the on-off control circuit 510 includes an eighth transistor T8; the second initialization circuit 420 includes a seventh transistor T7; the first initialization circuit 410 includes a first transistor T1, the compensation control circuit 520 includes a second transistor T2, the data writing circuit 530 includes a fourth transistor T4, the driving circuit 110 includes a driving transistor T3, and the energy storage circuit 210 includes a second capacitor C2; and the light-emitting element is an organic light-emitting diode 100.

[0097] The first plate of the first capacitor C1 is electrically connected to the light emitting control line E1, and the second plate of the first capacitor C1 is electrically connected to the node N2, that is, the second plate of the first capacitor C1 is electrically connected to the second electrode of the fifth transistor T5 and the first electrode of the third transistor T3.

[0098] A first plate of the second capacitor C2 is electrically connected to the node N1 , and a second plate of the second capacitor C2 is electrically connected to the first voltage line.

[0099] The gate of the first transistor T1 is electrically connected to the reset control line R1, the first electrode of the first transistor T1 is electrically connected to the first initial voltage line Vi1, and the second electrode of the first transistor T1 is electrically connected to the node N0. For example, the first initial voltage line Vi1 is used to provide a first initial voltage.

[0100] The gate of the second transistor T2 is electrically connected to the scan line S1, the second electrode of the second transistor T2 is electrically connected to the node N3, and the first electrode of the second transistor T2 is electrically connected to the node N0, that is, the first electrode of the second transistor T2 is electrically connected to the second electrode of the first transistor T1 and the first electrode of the eighth transistor T8.

[0101] A gate of the third transistor T3 is electrically connected to the node N1 , a first electrode of the third transistor T3 is electrically connected to the node N2 , and a second electrode of the third transistor T3 is electrically connected to the node N3 .

[0102] A gate of the fourth transistor T4 is electrically connected to the scan line S1 , a first electrode of the fourth transistor T4 is electrically connected to the data line D1 , and a second electrode of the fourth transistor T4 is electrically connected to the node N2 .

[0103] The gate of the fifth transistor T5 is electrically connected to the light emitting control line E1, the first electrode of the fifth transistor T5 is electrically connected to the first voltage line V1, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The first voltage line is used to provide a high voltage VDD.

[0104] The gate of the sixth transistor T6 is electrically connected to the light emitting control line E1; the first electrode of the sixth transistor T6 is electrically connected to the node N3, that is, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3 and the second electrode of the second transistor T2; the second electrode of the sixth transistor T6 is electrically connected to the anode of the organic light emitting diode 100.

[0105] The gate of the seventh transistor T7 is electrically connected to the light-emitting element reset line R2, the first electrode of the seventh transistor T7 is electrically connected to the second initial voltage line Vi2, and the second electrode of the seventh transistor T7 is electrically connected to the node N4. That is, the second electrode of the seventh transistor T7 is electrically connected to the first electrode of the sixth transistor T6 and the anode of the organic light-emitting diode 100. For example, the second initial voltage line Vi2 is used to provide a second initial voltage. The signal provided by the light-emitting element reset line R2 will be described in further detail below.

[0106] A gate of the eighth transistor T8 is electrically connected to the second light emitting control line E2 , a first electrode of the eighth transistor T8 is electrically connected to the node N0 , and a second electrode of the eighth transistor T8 is electrically connected to the node N1 .

[0107] An anode of the organic light emitting diode 100 is electrically connected to the node N4 , and a cathode of the organic light emitting diode 100 is electrically connected to a second voltage line, which is used to provide a low voltage VSS.

[0108] In an embodiment of the present disclosure, the first light emitting control line E1 applies a first light emitting control signal to the gate of the fifth transistor T5 , the gate of the sixth transistor T6 , and the first plate C1 a of the first capacitor C1 .

[0109] In the embodiment of the present disclosure, Vi2 may be the same as Vi1 or different from Vi2.

[0110] In the embodiment of the present disclosure, the eighth transistor T8 may be an oxide thin film transistor, and the other transistors T1 to T7 may be low-temperature polysilicon thin film transistors, but the embodiment of the present disclosure is not limited thereto.

[0111] In at least one embodiment of the pixel driving circuit disclosed herein, the voltage value of Vi1 may be greater than or equal to -6V and less than or equal to -2V. For example, the voltage value of Vi1 may be -2V, -3V, -4V, -5V, or -6V, but is not limited thereto.

[0112] The threshold voltage Vth of the transistor may be greater than or equal to -5V and less than or equal to -0.5V; for example, Vth may be -2.5V or -3V;

[0113] The voltage value of the high voltage VDD provided by the first voltage line may be greater than or equal to 3V and less than or equal to 6V. For example, the voltage value of VDD may be 4.6V, but is not limited thereto.

[0114] The absolute value of the high voltage VDD may be greater than 1.5 times the absolute value of Vth. For example, the absolute value of the high voltage VDD may be 1.6 times, 1.8 times, or 2 times the absolute value of Vth.

[0115] Optionally, the voltage value of the low voltage VSS provided by the second voltage line may be greater than or equal to -6V and less than or equal to -3V; for example, the voltage value of VSS may be -5V, -4V or -3V.

[0116] In at least one embodiment of the present disclosure, the voltage value of Vi2 may be greater than or equal to -7 V and less than or equal to 0 V. For example, the voltage value of the second initialization voltage may be -6 V, -5 V, -4 V, -3 V, or -2 V, but is not limited thereto.

[0117] Optionally, the voltage difference between the voltage value of Vi2 and the voltage value of VSS needs to be smaller than the turn-on voltage of the light-emitting element, so that when the first electrode of the light-emitting element is connected to Vi2, the light-emitting element does not emit light.

[0118] Figure 5 yes Figure 4 The working timing diagram of at least one embodiment of the pixel driving circuit shown in FIG. Figures 3 to 5 When the pixel driving circuit according to the embodiment of the present disclosure is working, a display period may include an initialization phase t1, a data writing phase t2 and a light emitting phase t3 which are arranged in sequence.

[0119] In the initialization phase t1, the potential of the light-emitting control signal provided by the first light-emitting control line E1 is converted from a low voltage Vgl to a high voltage Vgh, the reset control line R1 provides a low voltage signal, the second light-emitting control line E2 provides a high voltage signal, and the scan line S1 provides a high voltage signal. Transistors T6 and T4 are turned on, Vi1 is written to the node N1, and the potential of the node N2 becomes VDD+(Vgh-Vgl). At this time, the gate-source voltage of the transistor T3 is less than the threshold voltage Vth of the transistor T3, and the transistor T3 is in a conductive bias state; the transistor T5 is turned on, Vi2 is written to the anode of the organic light-emitting diode 100, the organic light-emitting diode 100 does not emit light, and the residual charge on the anode of the organic light-emitting diode 100 is cleared.

[0120] In the data writing phase t2, the reset control line R1 provides a high voltage signal, the second light-emitting control line E2 provides a high voltage signal, the scan line S1 provides a low voltage signal, the first light-emitting control line E1 provides a high voltage signal, transistors T2, T4 and T8 are turned on, the data voltage Vdata on the data line D1 is written to the node N2, the nodes N1 and N3 are connected, and the second capacitor C2 is charged by Vdata to change the potential of the gate of the transistor T3 until the transistor T3 is turned off and the potential of the gate of the transistor T3 becomes Vdata+Vth.

[0121] In the light-emitting stage t3, the reset control line R1 provides a high voltage signal, the second light-emitting control line E2 provides a low voltage signal, the scan line S1 provides a high voltage signal, and the first light-emitting control line E1 provides a low voltage signal. Transistors T3, T5, and T6 are turned on, and transistor T3 drives the organic light-emitting diode 100 to emit light. At this time, the light-emitting current of the organic light-emitting diode 100 is 0.5K (Vdata-VDD). 2 ; Wherein, K is the current coefficient of transistor T3.

[0122] In an embodiment of the present disclosure, the pulse width of the first light-emitting control signal provided by the first light-emitting control line E1 may be the same as the pulse width of the second light-emitting control signal provided by the second light-emitting control line E2, or the pulse width of the first light-emitting control signal provided by the first light-emitting control line E1 may be longer than the pulse width of the second light-emitting control signal provided by the second light-emitting control line E2 by a predetermined time.

[0123] When the pulse width of the first light-emitting control signal provided by the first light-emitting control line E1 can be the same as the pulse width of the second light-emitting control signal provided by the second light-emitting control line E2, it may occur that during the initialization stage, the transistors T5 and T6 cannot be properly turned off. Based on this, in at least one embodiment of the present disclosure, the pulse width of the first light-emitting control signal provided by the first light-emitting control line E1 can be a predetermined time longer than the pulse width of the second light-emitting control signal provided by the second light-emitting control line E2, and the predetermined time can be less than or equal to 0.5H, and 1H is a line scanning time. In this way, during initialization, under the control of the first light-emitting control signal, the transistors T5 and T6 are turned off to disconnect the connection between the first voltage line and the first electrode of the transistor T3, and disconnect the connection between the second electrode of the transistor T3 and the anode of the organic light-emitting diode 100, so that the organic light-emitting diode 100 does not emit light so as not to affect the light emission.

[0124] In the embodiment of the present disclosure, the transistor T8 included in the on-off control circuit may be an oxide thin film transistor. This can reduce leakage at the control terminal of the driving circuit and ensure voltage stability at the control terminal of the driving circuit during low-frequency operation, thereby improving display quality, enhancing display uniformity, and reducing flicker.

[0125] In an embodiment of the present disclosure, the transistor T7 may be controlled by a separate GOA, which is electrically connected to the light emitting element reset line R2 , so that the organic light emitting diode 100 may be reset at a frequency of 60 Hz.

[0126] Figure 6A and Figure 6B Schematic diagrams of signals provided by the reset line of the light emitting element according to some exemplary embodiments of the present disclosure. Figure 6A and Figure 6BIn an embodiment of the present disclosure, the signal provided by the light emitting element reset line R2 may be a high frequency signal. For example, the frequency of the signal provided by the light emitting element reset line R2 may be higher than the frequency of the reset control signal provided by the reset control line R1. Figure 6B The frequency of the signal provided by the reset line R2 of the light emitting element shown in FIG is higher than Figure 6A The frequency of the signal provided by the light emitting element reset line R2 is shown in FIG. Figure 6A In the embodiment shown, the frequency of the signal provided by the light emitting element reset line R2 is substantially equal to the frequency of the reset control signal provided by the reset control line R1.

[0127] Figure 23 is used Figure 6B The luminous effect of the light-emitting element when the high-frequency signal is shown. Figure 23 By increasing the frequency of the signal provided by the light-emitting element reset line R2, the refresh frequency of the light-emitting element's anode reset can be increased, ensuring that the brightness build-up time during the refresh and hold phases of the light-emitting element remains consistent. This reduces the low-light component during the hold phase, minimizing visible brightness changes and improving flicker levels. At the same time, it reduces load and power consumption.

[0128] It should be noted that, in the embodiments of the present disclosure, each thin film transistor T1, T2, T3, T4, T5, T6, T7 and T8 may be a p-channel field effect transistor, but the embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6, T7 and T8 may be an n-channel field effect transistor.

[0129] Figure 7 is a schematic diagram illustrating a planar structure of a first semiconductor layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure. Figure 8 is a schematic diagram illustrating a planar structure of a first conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure. Figure 9 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer and a first conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure. Figure 10 FIG. 1 is a schematic diagram illustrating a planar structure of a second conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure. Figure 11 is a schematic diagram illustrating a planar structure of a second semiconductor layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure. Figure 12 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, and a second semiconductor layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure. Figure 13 is a schematic diagram illustrating a planar structure of a third conductive layer of a pixel driving circuit according to an exemplary embodiment of the present disclosure. Figure 14 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure. Figure 15 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure. Figure 14 is a schematic diagram illustrating a via hole in an insulating layer formed on the structure of Figure 16 is a schematic diagram illustrating a via hole in an insulating layer formed on the structure of Figure 15 is a schematic diagram illustrating a via hole in an insulating layer formed on the structure of Figure 17 is a schematic diagram illustrating a planar structure of a fourth conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure. Figure 18 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, and a fourth conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure. Figure 19 is a schematic diagram illustrating a planar structure of a fifth conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure. Figure 20 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer of a pixel driving circuit according to an example embodiment of the present disclosure. Figure 21 is a plan view schematically showing relative areas of a first capacitor and a second capacitor. Figure 22 is a schematic diagram illustrating a cross-sectional structure taken along a line AA’ in Figure 20 is a schematic diagram illustrating a cross-sectional structure taken along a line AA’ in

[0130] With reference to Figures 7 to 22 , the display substrate includes a substrate 1 and a plurality of film layers disposed on the substrate 1. In some embodiments, the plurality of film layers includes at least a first semiconductor layer 2, a first conductive layer 3, a second conductive layer 4, a second semiconductor layer 5, a third conductive layer 6, a fourth conductive layer 7, and a fifth conductive layer 8. The first semiconductor layer 2, the first conductive layer 3, the second conductive layer 4, the second semiconductor layer 5, the third conductive layer 6, the fourth conductive layer 7, and the fifth conductive layer 8 are disposed in sequence away from the substrate 1.

[0131] For example, the first semiconductor layer 2 can be formed of a semiconductor material such as low-temperature polysilicon, and its film thickness can be in the range of 400 to 800 angstroms, for example, 500 angstroms. The second semiconductor layer 5 can be formed of an oxide semiconductor material, such as a polycrystalline silicon oxide semiconductor material such as IGZO, and its film thickness can be in the range of 300 to 600 angstroms, for example, 400 angstroms. The first conductive layer 3, the second conductive layer 4, and the third conductive layer 6 can be formed of a conductive material that forms the gate of a thin film transistor, for example, the conductive material can be Mo, and its film thickness can be in the range of 2000 to 3000 angstroms, for example, 2500 angstroms. The fourth conductive layer 7 and the fifth conductive layer 8 can be formed of a conductive material that forms the source and drain of a thin film transistor, for example, the conductive material can include Ti, Al, etc. The fourth conductive layer 7 and the fifth conductive layer 8 can have a stacked structure formed of Ti / Al / Ti, and their film thickness can be in the range of 7000 to 9000 angstroms. For example, in the case where the fourth conductive layer 7 and the fifth conductive layer 8 have a stacked-layer structure formed of Ti / Al / Ti, the thickness of each layer of Ti / Al / Ti may be approximately 500 angstroms, 5500 angstroms, and 500 angstroms, respectively.

[0132] In the embodiment of the present disclosure, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 may be arranged along the following lines: Figure 7 The eighth transistor T8 may be formed along the first semiconductor layer 2 as shown in FIG. Figure 12 The second semiconductor layer 5 shown in FIG is formed.

[0133] like Figure 7 As shown, the first semiconductor layer 2 may have a curved or bent shape and may include a first active layer 20a corresponding to the first transistor T1, a second active layer 20b corresponding to the second transistor T2, a third active layer 20c corresponding to the third transistor T3, a fourth active layer 20d corresponding to the fourth transistor T4, a fifth active layer 20e corresponding to the fifth transistor T5, a sixth active layer 20f corresponding to the sixth transistor T6, and a seventh active layer 20g corresponding to the seventh transistor T7.

[0134] For example, the first semiconductor layer 2 may include polycrystalline silicon, such as low-temperature polycrystalline silicon. The active layer of each transistor may include a channel region, a source region, and a drain region. The channel region may not be doped or may have a different doping type from the source region and the drain region, and thus have semiconductor properties. The source region and the drain region are respectively located on either side of the channel region and are doped with impurities, and thus have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0135] The first transistor T1 includes a first active layer 20a and a first gate G1. The first active layer 20a includes a first source region 203a, a first drain region 205a, and a first channel region 201a connecting the first source region 203a and the first drain region 205a. The first source region 203a and the first drain region 205a extend in two opposite directions relative to the first channel region 201a.

[0136] The second transistor T2 includes a second active layer 20b and a second gate G2. The second active layer 20b includes a second source region 203b, a second drain region 205b, and a second channel region 201b connecting the second source region 203b and the second drain region 205b. The second source region 203b and the second drain region 205b extend in two opposite directions relative to the second channel region 201b.

[0137] The third transistor T3 includes a third active layer 20c and a third gate G3. The third active layer 20c includes a third source region 203c, a third drain region 205c, and a third channel region 201c connecting the third source region 203c and the third drain region 205c. The third source region 203c and the third drain region 205c extend in two opposite directions relative to the third channel region 201c.

[0138] The fourth transistor T4 includes a fourth active layer 20d and a fourth gate G4. The fourth active layer 20d includes a fourth source region 203d, a fourth drain region 205d, and a fourth channel region 201d connecting the fourth source region 203d and the fourth drain region 205d. The fourth source region 203d and the fourth drain region 205d extend in two opposite directions relative to the fourth channel region 201d.

[0139] The fifth transistor T5 includes a fifth active layer 20e and a fifth gate G5. The fifth active layer 20e includes a fifth source region 203e, a fifth drain region 205e, and a fifth channel region 201e connecting the fifth source region 203e and the fifth drain region 205e. The fifth source region 203e and the fifth drain region 205e extend in two opposite directions relative to the fifth channel region 201e.

[0140] The sixth transistor T6 includes a sixth active layer 20f and a sixth gate G6. The sixth active layer 20f includes a sixth source region 203f, a sixth drain region 205f, and a sixth channel region 201f connecting the sixth source region 203f and the sixth drain region 205f. The sixth source region 203f and the sixth drain region 205f extend in two opposite directions relative to the sixth channel region 201f.

[0141] The seventh transistor T7 includes a seventh active layer 20g and a seventh gate G7. The seventh active layer 20g includes a seventh source region 203g, a seventh drain region 205g, and a seventh channel region 201g connecting the seventh source region 203g and the seventh drain region 205g. The seventh source region 203g and the seventh drain region 205g extend in two opposite directions relative to the seventh channel region 201g.

[0142] Reference Figure 7 , the structures 21 and 22 located in the first semiconductor layer 2 are part of the active layers of adjacent sub-pixels, that is, Figure 7 What is mainly shown in FIG. 1 is a portion of the active layer of a sub-pixel.

[0143] like Figure 8 and Figure 9 As shown, the reset control line R1, scan line S1, first light-emitting control line E1, and light-emitting element reset line R2 are all located in the first conductive layer 3. The first conductive structure CG1 is also located in the first conductive layer 3. The portion of the first conductive structure CG1 that overlaps with the first semiconductor layer 2 forms the third gate G3 of the third transistor T3. The portion of the reset control line R1 that overlaps with the first semiconductor layer 2 forms the first gate G1 of the first transistor T1. The portion of the scan line S1 that overlaps with the first semiconductor layer 2 forms the second gate G2 of the second transistor T2, and the other portion of the scan line S1 that overlaps with the first semiconductor layer 2 forms the fourth gate G4 of the fourth transistor T4. The portion of the first light-emitting control line E1 that overlaps with the first semiconductor layer 2 forms the fifth gate G5 of the fifth transistor T5. The other portion of the first light-emitting control line E1 that overlaps with the first semiconductor layer 2 forms the sixth gate G6 of the sixth transistor T6. The portion of the light-emitting element reset line R2 that overlaps with the first semiconductor layer 2 forms the seventh gate G7 of the seventh transistor T7.

[0144] The first conductive structure CG1 also forms a plate of the second capacitor C2, for example, the first plate C2a. That is, the first conductive structure CG1 serves as the gate of the third transistor T3 and a plate of the second capacitor C2 at the same time.

[0145] The first light emitting control line E1 has a widened portion E1W, and the widened portion E1W is located between the fifth gate G5 and the sixth gate G6. Figure 9As shown, in the extension direction of the first light-emitting control line E1, that is, in the first direction X, the widened portion E1W is located between the fifth gate G5 and the sixth gate G6. The dimension of the widened portion E1W along the second direction Y is greater than the dimension of other portions of the first light-emitting control line E1 along the second direction Y. The dimension of the widened portion E1W along the second direction Y is greater than the dimension of each of the fifth gate G5 and the sixth gate G6 along the second direction Y. The first light-emitting control line E1 extends along the first direction X, and the second direction Y intersects the first direction X. For example, the second direction Y is perpendicular to the first direction X.

[0146] For example, the orthographic projection of the first plate C1a of the first capacitor on the substrate is located in the second direction Y between the orthographic projection of the first plate C2a of the second capacitor on the substrate and the orthographic projection of the light emitting element reset line R2 on the substrate.

[0147] like Figure 9 As shown, the distance PD1 between the first gate G1 and the first plate C1a of the first capacitor in the first direction X is smaller than the distance PD2 between the seventh gate G7 and the first plate C1a of the first capacitor in the first direction X. It should be noted that the distance PD1 between the first gate G1 and the first plate C1a of the first capacitor in the first direction X can be represented by the distance between the centerline of the first gate G1 in the first direction X and the centerline of the first plate C1a of the first capacitor in the first direction X. Similarly, the distance PD2 between the seventh gate G7 and the first plate C1a of the first capacitor in the first direction X can be represented by the distance between the centerline of the seventh gate G7 in the first direction X and the centerline of the first plate C1a of the first capacitor in the first direction X.

[0148] like Figure 10 As shown, the second light emitting control line E2 is located in the second conductive layer 4 . The second plate C1 b of the first capacitor C1 and the second plate C2 b of the second capacitor C2 are also located in the second conductive layer 4 .

[0149] For example, the orthographic projections of the second plate C1b of the first capacitor C1 and the widened portion E1W of the first light-emitting control line E1 on the substrate at least partially overlap. The overlapping portion of the first light-emitting control line E1 and the second plate C1b of the first capacitor C1 forms the first plate C1a of the first capacitor C1. In other words, at least a portion of the widened portion E1W constitutes the first plate C1a of the first capacitor C1.

[0150] For example, the second plate C2b of the second capacitor C2 and the orthographic projection of the first conductive structure CG1 on the substrate at least partially overlap, and the overlapping portion of the first conductive structure CG1 and the second plate C2b of the second capacitor C2 forms the second plate C2a of the second capacitor C2.

[0151] like Figure 21 , schematically shows the orthographic projection of the overlapping portion of the first plate C1a and the second plate C1b of the first capacitor C1 on the substrate, and the orthographic projection of the overlapping portion of the first plate C2a and the second plate C2b of the second capacitor C2 on the substrate.

[0152] In an embodiment of the present disclosure, the orthographic projection of the second plate C1b of the first capacitor on the base substrate substantially covers the orthographic projection of the widened portion E1W on the base substrate, and the orthographic projection area of ​​the first plate C2a of the second capacitor on the base substrate is greater than the orthographic projection area of ​​the widened portion E1W on the base substrate.

[0153] In the embodiments of the present disclosure, a first electrode plate C1a located in the first conductive layer 3 and a second electrode plate C1b located in the second conductive layer 4 are disposed opposite each other. It should be understood that an insulating layer or dielectric layer is formed between the first conductive layer 3 and the second conductive layer 4. Thus, a first capacitor C1 is formed between the first electrode plate C1a located in the first conductive layer 3 and the second electrode plate C1b located in the second conductive layer 4. Similarly, a second capacitor C2 is formed between the first electrode plate C2a located in the first conductive layer 3 and the second electrode plate C2b located in the second conductive layer 4.

[0154] like Figure 21As shown, the area of the orthogonal projection of the overlapping portion of the first plate C1a and the second plate C1b of the first capacitor C1 on the substrate is smaller than the area of the orthogonal projection of the overlapping portion of the first plate C2a and the second plate C2b of the second capacitor C2 on the substrate. In this way, the capacitance of the first capacitor C1 is smaller than the capacitance of the second capacitor C2. For example, the ratio of the capacitance of the second capacitor C2 to the capacitance of the first capacitor C1 can be in the range of 5-20, for example, in the range of 5-10, or in the range of 8-10, in the range of 8-9. In embodiments of the present disclosure, by setting the capacitance of the first capacitor, the first capacitor can maintain the potential at the node N2 constant, so that even when the frequency of the driving signal changes, flicker and / or ghosting can be prevented by controlling the voltage at the first electrode of the driving transistor. At the same time, the capacitance of the second capacitor C2 is set to be larger, which can improve the performance of the display panel and reduce the power consumption of the display panel. In embodiments of the present disclosure, by setting the ratio of the capacitance of the second capacitor C2 to the capacitance of the first capacitor C1 to be in the range of 5-20, in particular in the range of 8-10, the stability of the driving transistor can be improved, and when the driving frequency changes, the display device can prevent flicker and / or ghosting by controlling the voltage at the first electrode of the driving transistor.

[0155] With reference to Figure 10 and Figure 12 , the second plate C2b includes a via 4H that exposes a portion of the first conductive structure CG1 to facilitate electrical connection of the third gate G3 of the third transistor T3 to other components.

[0156] For example, the via 4H exposes at least a portion of the first plate C2a of the second capacitor. For example, the ratio of the area of the orthogonal projection of the second plate C1b of the first capacitor on the substrate to the area of the orthogonal projection of the via 4H on the substrate is in the range of 1.1-5. That is, the area of the orthogonal projection of the second plate C1b of the first capacitor on the substrate is slightly larger than the area of the orthogonal projection of the via 4H on the substrate.

[0157] As shown in Figures 9 to 12 , the widened portion E1W of the first light emission control line E1 forming the first plate C1a has a substantially rectangular shape in the orthogonal projection on the substrate, and the second plate C1b has a substantially rectangular shape in the orthogonal projection on the substrate. The "substantially rectangular" shape here includes a rectangular shape, a rectangular shape with at least one chamfer, a rectangular shape with at least one rounded corner, etc.

[0158] As shown in Figure 10 , one second light emission control line 42 is located in the second conductive layer 4.

[0159] For example, the orthographic projections of the second light-emitting control line 42, the second plate C2b of the second capacitor, and the second plate C1b of the first capacitor on the substrate are spaced apart along the second direction Y. The orthographic projection of the second plate C1b of the first capacitor on the substrate and the orthographic projection of the second light-emitting control line 42 on the substrate are respectively located on either side of the orthographic projection of the second plate C2b of the second capacitor on the substrate in the second direction.

[0160] like Figure 11 As shown, the second semiconductor layer 5 includes an eighth active layer 20h corresponding to the eighth transistor T8. For example, the eighth active layer 20h of the eighth transistor T8 extends substantially along the second direction Y in the figure. The eighth active layer 20h includes an eighth source region 203h, an eighth drain region 205h, and an eighth channel region 201h connecting the eighth source region 203h and the eighth drain region 205h. The eighth source region 203h and the eighth drain region 205h extend in two opposite directions relative to the eighth channel region 201h.

[0161] For example, the second semiconductor layer 5 may include an oxide semiconductor material, such as a low-temperature polycrystalline silicon oxide semiconductor material (abbreviated as LTPO). The active layer of each transistor may include a channel region, a source region, and a drain region. The channel region may not be doped or the doping type may be different from that of the source region and the drain region, and therefore has semiconductor properties. The source region and the drain region are respectively located on both sides of the channel region and are doped with impurities, and therefore have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0162] like Figure 13 As shown, another second light-emitting control line 62 is located in the third conductive layer 6. For example, one second light-emitting control line 42 and another second light-emitting control line 62 can both transmit a second light-emitting control signal. In some examples, one second light-emitting control line 42 and another second light-emitting control line 62 can be electrically connected in a peripheral area of ​​the display substrate to form the second light-emitting control line E2 shown.

[0163] Reference Figure 12 The portion where one second light-emission control line 42 overlaps with the second conductive layer 4 forms the bottom gate G81 of the eighth transistor T8, while the portion where the other second light-emission control line 62 overlaps with the second conductive layer 4 forms the top gate G82 of the eighth transistor T8. In other words, the eighth transistor T8 has a dual-gate structure. In the embodiment of the present disclosure, the eighth transistor T8 is configured as an oxide semiconductor transistor, and the dual-gate structure of the eighth transistor T8 is beneficial for reducing leakage current at the node N1, thereby stabilizing the potential of the node N1.

[0164] Reference Figure 13, the first initial voltage line Vi1 is located in the third conductive layer 6. That is, a portion of the second light-emission control line E2 and the first initial voltage line Vi1 are located in the same layer. In the embodiment of the present disclosure, by providing the second light-emission control line E2 in the third conductive layer 6, a separate light-emission control signal can be provided for the eighth transistor T8.

[0165] Reference Figure 17 The display substrate also includes a second initial voltage line Vi2 and a plurality of conductive components located in the fourth conductive layer 7. For example, the plurality of conductive components may include a first conductive component 71, a second conductive component 72, a third conductive component 73, a fourth conductive component 74, a fifth conductive component 75, a sixth conductive component 76 and a seventh conductive component 77.

[0166] Reference Figure 19 The display substrate further includes a data line D1 , a first voltage line V1 and a first conductive member 81 located in the fifth conductive layer 8 .

[0167] Reference Figures 15 to 20 , schematically illustrating multiple vias. One end of the first conductive component 71 is electrically connected to the source region 203a of the first transistor T1 through the via VH2. The other end of the first conductive component 71 is electrically connected to the first initial voltage line Vi1 through the via VH1. In this manner, the source of the first transistor T1 is electrically connected to the first initial voltage line Vi1. Thus, the first initial voltage can be applied to the source of the first transistor T1.

[0168] One end of the second conductive component 72 is electrically connected to the source region 203d of the fourth transistor T4 through a via VH3, and the other end of the second conductive component 72 is electrically connected to the data line D1 through a via VH4. In this way, the source of the fourth transistor T4 is electrically connected to the data line D1. In this way, a data signal can be applied to the source of the fourth transistor T4.

[0169] One end of the third conductive component 73 is electrically connected to the source region 203b of the second transistor T2 through the via VH5, and the other end of the third conductive component 73 is electrically connected to the drain region 205h of the eighth transistor T8 through the via VH6. In this way, the source of the second transistor T2 and the drain of the eighth transistor T8 can be electrically connected.

[0170] One end of the fourth conductive component 74 is electrically connected to the source region 203h of the eighth transistor T8 through the via hole VH7, and the other end of the fourth conductive component 74 is electrically connected to the third gate G3 through the via hole VH8 and the through hole 4H. Figure 4 The node N1 shown in FIG. 1 electrically connects the source of the eighth transistor T8 , the third gate G3 , and one plate C2 a of the second capacitor C2 .

[0171] For example, the orthographic projection of the via hole VH8 on the substrate falls within the orthographic projection of the through hole 4H on the substrate. In this way, a portion of the third gate G3 below is exposed through the via hole VH8 and the through hole 4H, thereby facilitating the electrical connection between the third gate G3 and the source of the eighth transistor T8.

[0172] One end of the fifth conductive component 75 is electrically connected to one plate C1b of the first capacitor through the via hole VH10, and the other end of the fifth conductive component 75 is electrically connected to the drain region 205d of the fourth transistor T4 and the drain region 205c of the third transistor T3 through the via hole VH9. Figure 4 Node N2 shown in FIG electrically connects the drain of the fourth transistor T4, the drain of the third transistor T3, and one plate C1b of the first capacitor C1. A first portion of the sixth conductive component 76 is electrically connected to the drain region 205e of the fifth transistor T5 via a via VH11. A second portion of the sixth conductive component 76 is electrically connected to one plate C2b of the second capacitor C2 via a via VH12. A third portion of the sixth conductive component 76 is electrically connected to the first voltage line V1 via a via VH13. In this manner, a high voltage VDD can be applied to the drain of the fifth transistor T5 and the plate C2b of the second capacitor C2.

[0173] Reference Figure 17 The orthographic projection of the fifth conductive component 75 on the substrate is located between the orthographic projection of the fourth conductive component 74 on the substrate and the orthographic projection of the sixth conductive component 76 on the substrate.

[0174] For example, the sixth conductive component 76 may include a first portion and a second portion, wherein the orthographic projection of the first portion on the substrate has an inverted L-shape, and the orthographic projection of the second portion on the substrate has an approximately rectangular, hexagonal, or octagonal shape. The first portion and the second portion of the sixth conductive component 76 are interconnected to form an integral structure.

[0175] For example, the orthographic projection of the fifth conductive component 75 on the substrate overlaps the orthographic projection of the first and second plates of the second capacitor C2 on the substrate. Thus, during the light-emitting phase, one plate of the second capacitor C2 is connected to a low potential, further lowering the potential of the N1 node, which is beneficial for light-emitting display.

[0176] In the embodiment of the present disclosure, the seventh conductive component 77 is electrically connected to the source region 203f of the sixth transistor T6 and the drain region 205g of the seventh transistor T7 through the via hole VH14. Figure 4Node N4 in the fourth conductive layer 7 is led upward. The seventh conductive component 77 in the fourth conductive layer 7 and the first conductive member 81 in the fifth conductive layer 8 are electrically connected via a via. The anode of the organic light-emitting diode 100 can be electrically connected to the first conductive member 81 through the via. In this way, the source of the sixth transistor T6 and the drain of the seventh transistor T7 can be electrically connected to the anode of the organic light-emitting diode 100.

[0177] For example, the orthographic projection of the first plate C1a of the first capacitor on the substrate is located between the orthographic projection of the sixth conductive component 76 on the substrate and the orthographic projection of the seventh conductive component 77 on the substrate in the first direction X. Furthermore, any two of the orthographic projection of the first plate C1a of the first capacitor on the substrate, the orthographic projection of the sixth conductive component 76 on the substrate, and the orthographic projection of the seventh conductive component 77 on the substrate are spaced apart. The orthographic projection of the second plate C1b of the first capacitor on the substrate partially overlaps with the orthographic projection of the seventh conductive component 77 on the substrate.

[0178] For example, the orthographic projection of the first voltage line V1 on the substrate covers the orthographic projection of the fourth conductive component 74 on the substrate; and / or, the orthographic projection of the first voltage line V1 on the substrate covers the orthographic projection of the active layer of the eighth transistor T8 on the substrate.

[0179] Below, we will combine the plan view (such as Figures 7 to 20 ) and cross-sectional views ( Figure 22 ) describes other film layers (such as insulating layers) of the display substrate according to an embodiment of the present disclosure.

[0180] In an exemplary embodiment, the display substrate may include a first semiconductor layer 2 disposed on a base substrate 1 and a first gate insulating layer 107 disposed on a side of the first semiconductor layer 2 away from the base substrate 1. For example, the first gate insulating layer 107 may be formed of silicon oxide and have a thickness of approximately 1000 to 2000 angstroms.

[0181] The display substrate may include a first conductive layer 3 disposed on a side of a first gate insulating layer 107 away from a base substrate 1 and a first interlayer dielectric layer 108 disposed on a side of the first conductive layer 3 away from the base substrate 1. For example, the first interlayer dielectric layer 108 may be formed of silicon nitride and have a thickness of approximately 1000 to 2000 angstroms.

[0182] The display substrate may include a second conductive layer 4 disposed on a side of the first interlayer dielectric layer 108 away from the base substrate 1 and a second interlayer dielectric layer 109 disposed on a side of the second conductive layer 4 away from the base substrate 1. For example, the second interlayer dielectric layer 109 may be formed of an insulating material such as silicon nitride.

[0183] The display substrate may include a buffer layer 110 disposed on a side of the second interlayer dielectric layer 109 away from the base substrate 1 ; a second semiconductor layer 5 disposed on a side of the buffer layer 110 away from the base substrate 1 ; and a second gate insulating layer 116 disposed on a side of the second semiconductor layer 5 away from the base substrate 1 .

[0184] The display substrate may include a third conductive layer 6 arranged on a side of the second gate insulating layer 116 away from the base substrate 1; a third interlayer dielectric layer 111 arranged on a side of the third conductive layer 6 away from the base substrate 1; a fourth conductive layer 7 arranged on a side of the third interlayer dielectric layer 111 away from the base substrate 1; a first planarizing layer 112 arranged on a side of the fourth conductive layer 7 away from the base substrate 1; a fifth conductive layer 8 arranged on a side of the first planarizing layer 112 away from the base substrate 1; a second planarizing layer 113 arranged on a side of the fifth conductive layer 8 away from the base substrate 1; an anode layer 208 arranged on a side of the second planarizing layer 113 away from the base substrate 1; and a pixel defining layer 114 arranged on a side of the anode layer 208 away from the base substrate 1.

[0185] For example, the planarization layer may be formed of polyimide (PI).

[0186] At least some embodiments of the present disclosure further provide a display panel, comprising the display substrate described above. For example, the display panel may be an OLED display panel.

[0187] Reference Figure 1 At least some embodiments of the present disclosure further provide a display device. The display device may include the display substrate described above.

[0188] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0189] It should be understood that the display panel and the display device according to the embodiments of the present disclosure have all the characteristics and advantages of the above-mentioned display substrate. For details, please refer to the above description and will not be repeated here.

[0190] Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the overall technical concept, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A display substrate, wherein: The display substrate comprises: substrate; A first semiconductor layer provided on the base substrate; A first conductive layer disposed on a side of the first semiconductor layer away from the base substrate; and a second conductive layer disposed on a side of the first conductive layer away from the base substrate; The display substrate further includes a pixel driving circuit disposed on the base substrate, the pixel driving circuit including a driving circuit, a storage circuit, and a reset circuit, the reset circuit being electrically connected to the first terminal of the driving circuit or the second terminal of the driving circuit and configured to initialize the potential of the first terminal of the driving circuit or the second terminal of the driving circuit during an initialization phase, the driving circuit being configured to control communication between the first terminal of the driving circuit and the second terminal of the driving circuit under the control of the potential of its control terminal, and the storage circuit being electrically connected to the control terminal of the driving circuit and configured to store electrical energy; The reset circuit includes a first capacitor, the storage circuit includes a second capacitor, the first capacitor includes a first plate and a second plate arranged opposite to each other, the second capacitor includes a first plate and a second plate arranged opposite to each other, the first plate of the first capacitor and the first plate of the second capacitor are located in the first conductive layer, the second plate of the first capacitor and the second plate of the second capacitor are located in the second conductive layer, the first plate of the first capacitor and the first plate of the second capacitor are arranged at an orthographic projection interval on the substrate, the second plate of the first capacitor and the second plate of the second capacitor are arranged at an orthographic projection interval on the substrate, and the first plate of the first capacitor and the second plate of the first capacitor are arranged at an orthographic projection interval on the substrate. The orthographic projections of the first plate of the second capacitor and the second plate of the second capacitor on the substrate at least partially overlap, the orthographic projections of the first plate of the second capacitor and the second plate of the second capacitor on the substrate at least partially overlap, the area of ​​the overlapping portion of the orthographic projections of the first plate of the first capacitor and the second plate of the first capacitor on the substrate is smaller than the area of ​​the overlapping portion of the orthographic projections of the first plate of the second capacitor and the second plate of the second capacitor on the substrate, and the ratio of the area of ​​the overlapping portion of the orthographic projections of the first plate of the second capacitor and the second plate of the second capacitor on the substrate to the area of ​​the overlapping portion of the orthographic projections of the first plate of the first capacitor and the second plate of the first capacitor on the substrate is in a range of 5 to 20.

2. The display substrate according to claim 1, wherein The display substrate further includes a first light emitting control line provided on the base substrate, the first light emitting control line being used to supply a first light emitting control signal to the pixel driving circuit; The first light emitting control line is located in the first conductive layer, and a portion where the first light emitting control line overlaps with the second plate of the first capacitor constitutes the first plate of the first capacitor.

3. The display substrate according to claim 2, wherein: The pixel driving circuit includes a first light-emitting control circuit and a second light-emitting control circuit, the first light-emitting control circuit includes a fifth transistor, the second light-emitting control circuit includes a sixth transistor, the fifth transistor includes a fifth gate, the sixth transistor includes a sixth gate, and the first light-emitting control line applies a first light-emitting control signal to the fifth gate, the sixth gate and the first plate of the first capacitor.

4. The display substrate according to claim 3, wherein: A portion of the first light-emitting control line overlapping with the first semiconductor layer constitutes the fifth gate, and another portion of the first light-emitting control line overlapping with the first semiconductor layer constitutes the sixth gate. The first light-emitting control line further includes a widened portion, the widened portion is located between the fifth gate and the sixth gate along the first direction, and a size of the widened portion along the second direction is larger than a size of each of the fifth gate and the sixth gate along the second direction. The first light-emitting control line extends along the first direction, and the second direction intersects the first direction. At least a portion of the widened portion constitutes a first plate of the first capacitor.

5. The display substrate according to claim 4, wherein: The orthographic projection of the second electrode plate of the first capacitor on the base substrate covers the orthographic projection of the widened portion on the base substrate; and / or The orthographic projection area of ​​the first electrode plate of the second capacitor on the base substrate is larger than the orthographic projection area of ​​the widened portion on the base substrate; and / or, An orthographic projection area of ​​the second electrode plate of the second capacitor on the base substrate is larger than an orthographic projection area of ​​the second electrode plate of the first capacitor on the base substrate.

6. The display substrate according to any one of claims 1 to 5, wherein: A ratio of an area of ​​an overlapping portion of an orthographic projection of the first plate of the second capacitor and the second plate of the second capacitor on the substrate to an area of ​​an overlapping portion of an orthographic projection of the first plate of the first capacitor and the second plate of the first capacitor on the substrate is in a range of 8 to 10.

7. The display substrate according to claim 6, wherein: The second plate of the second capacitor includes a through hole, which exposes at least a portion of the first plate of the second capacitor, and a ratio of an area of ​​an orthographic projection of the second plate of the first capacitor on the substrate to an area of ​​an orthographic projection of the through hole on the substrate is in a range of 1.1 to 5.

8. The display substrate according to any one of claims 1 to 5, wherein: The display substrate also includes a light-emitting element reset line located in the first conductive layer and a light-emitting element arranged on the base substrate. The pixel driving circuit includes a second initialization circuit, which is used to initialize the first electrode of the light-emitting element under the control of a signal provided by the light-emitting element reset line.

9. The display substrate according to claim 8, wherein: The display substrate further includes a reset control line located in the first conductive layer, and the pixel driving circuit includes a first initialization circuit, the first initialization circuit being configured to initialize the driving circuit under the control of a reset control signal provided by the reset control line; and The frequency of the signal provided by the light emitting element reset line is higher than the frequency of the reset control signal provided by the reset control line.

10. The display substrate according to any one of claims 1 to 5, wherein: The display substrate further includes a light-emitting element reset line located in the first conductive layer and a light-emitting element provided on the base substrate, the pixel driving circuit includes a second initialization circuit, the second initialization circuit includes a seventh transistor, and a portion of the light-emitting element reset line overlapping with the first semiconductor layer constitutes a seventh gate of the seventh transistor; as well as The orthographic projection of the first plate of the first capacitor on the base substrate is located in the second direction between the orthographic projection of the first plate of the second capacitor on the base substrate and the orthographic projection of the light emitting element reset line on the base substrate.

11. The display substrate according to claim 9, wherein: The display substrate further includes a light-emitting element reset line located in the first conductive layer and a light-emitting element provided on the base substrate, the pixel driving circuit includes a second initialization circuit, the second initialization circuit includes a seventh transistor, and a portion of the light-emitting element reset line overlapping with the first semiconductor layer constitutes a seventh gate of the seventh transistor; as well as The orthographic projection of the first plate of the first capacitor on the base substrate is located in the second direction between the orthographic projection of the first plate of the second capacitor on the base substrate and the orthographic projection of the light emitting element reset line on the base substrate.

12. The display substrate according to claim 11, wherein: The pixel driving circuit includes a first transistor, and a portion of the reset control line overlapping the first semiconductor layer constitutes a first gate of the first transistor; as well as A distance between the first gate and the first plate of the first capacitor in the first direction is smaller than a distance between the seventh gate and the first plate of the first capacitor in the first direction.

13. The display substrate according to any one of claims 1 to 5, wherein: The display substrate further includes a second light-emitting control line located in the second conductive layer, wherein the orthographic projections of the second light-emitting control line, the second electrode plate of the second capacitor, and the second electrode plate of the first capacitor on the base substrate are spaced apart along the second direction; as well as The orthographic projection of the second plate of the first capacitor on the base substrate and the orthographic projection of the second light-emitting control line on the base substrate are respectively located on both sides of the orthographic projection of the second plate of the second capacitor on the base substrate in the second direction.

14. The display substrate according to claim 13, wherein: The display substrate further comprises: a second semiconductor layer disposed on a side of the second conductive layer away from the base substrate; and a third conductive layer disposed on a side of the second semiconductor layer away from the base substrate, wherein the second semiconductor layer comprises an oxide semiconductor material; The display substrate includes another second light emitting control line located in the third conductive layer, and the one second light emitting control line is electrically connected to the another second light emitting control line; The pixel driving circuit includes an on-off control circuit, which includes an eighth transistor. The portion where one of the second light-emitting control lines overlaps with the second semiconductor layer constitutes a bottom gate of the eighth transistor, and the portion where another second light-emitting control line overlaps with the second semiconductor layer constitutes a top gate of the eighth transistor.

15. The display substrate according to claim 14, wherein: The display substrate further includes a fourth conductive layer provided on a side of the third conductive layer away from the base substrate, and the driving circuit includes a third transistor; and The display substrate includes a fifth conductive component located in the fourth conductive layer, one end of the fifth conductive component is electrically connected to the second plate of the first capacitor through a first via, and the other end of the fifth conductive component is electrically connected to the first electrode of the third transistor through a second via.

16. The display substrate according to claim 15, wherein: The display substrate includes a sixth conductive component located in the fourth conductive layer, the sixth conductive component including a first portion, a second portion, and a third portion; and The first portion of the sixth conductive component is electrically connected to the first electrode of the fifth transistor through the third via hole, and the second portion of the sixth conductive component is electrically connected to the second plate of the second capacitor through the fourth via hole.

17. The display substrate according to claim 16, wherein: The display substrate further includes a fifth conductive layer disposed on a side of the fourth conductive layer away from the base substrate, and the display substrate further includes a first voltage line disposed in the fifth conductive layer; and The third portion of the sixth conductive component is electrically connected to the first voltage line through a fifth via hole.

18. The display substrate according to claim 16, wherein: The display substrate includes a seventh conductive component located in the fourth conductive layer, the seventh conductive component being electrically connected to the first electrode of the sixth transistor; and The orthographic projection of the first plate of the first capacitor on the substrate is located in the first direction between the orthographic projection of the sixth conductive component on the substrate and the orthographic projection of the seventh conductive component on the substrate, and any two of the orthographic projection of the first plate of the first capacitor on the substrate, the orthographic projection of the sixth conductive component on the substrate, and the orthographic projection of the seventh conductive component on the substrate are arranged at intervals.

19. The display substrate according to claim 18, wherein: The orthographic projection of the second plate of the first capacitor on the base substrate partially overlaps with the orthographic projection of the seventh conductive component on the base substrate.

20. The display substrate according to claim 17, wherein The display substrate includes a fourth conductive component located in the fourth conductive layer, one end of the fourth conductive component is electrically connected to the first electrode of the eighth transistor through a sixth via hole, and the other end of the fourth conductive component is electrically connected to the third gate of the third transistor through a seventh via hole and a through hole.

21. The display substrate according to claim 20, wherein: The orthographic projection of the first voltage line on the substrate covers the orthographic projection of the fourth conductive component on the substrate; and / or, The orthographic projection of the first voltage line on the base substrate covers the orthographic projection of the active layer of the eighth transistor on the base substrate.

22. A display panel comprising the display substrate according to any one of claims 1 to 21.

23. A display device comprising the display substrate according to any one of claims 1 to 21 or the display panel according to claim 22.

Images