Line recognition device and display device

Abstract

A texture recognition device and a display device are disclosed. The texture recognition device has multiple pixel units and includes a substrate, a driving circuit layer, a first electrode layer, and a photosensitive element layer. The driving circuit layer is disposed on the substrate, the first electrode layer is disposed on the side of the driving circuit layer away from the substrate, and the photosensitive element layer is disposed on the side of the first electrode layer away from the substrate. At least one of the multiple pixel units includes a pixel driving circuit disposed in the driving circuit layer, a first electrode disposed in the first electrode layer, and multiple photosensitive elements disposed in the photosensitive element layer that are spaced apart from each other. The pixel driving circuit is electrically connected to the first electrode, and the multiple photosensitive elements are disposed on the side of the first electrode away from the substrate and electrically connected to the pixel driving circuit through the first electrode. This texture recognition device has a better texture recognition effect.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a texture recognition device and a display device. Background Technology

[0002] Due to the uniqueness of skin patterns such as fingerprints or palm prints, texture recognition technology combined with optical imaging is increasingly being adopted by various electronic products for functions such as identity verification and electronic payments. Current electronic products, such as mobile phones and tablets, are developing towards larger and full-screen displays. Therefore, how to design more optimized texture recognition devices and improve the user's texture recognition experience is a key focus in this field. Summary of the Invention

[0003] At least one embodiment of this disclosure provides a texture recognition device having a plurality of pixel units and including: a substrate, a driving circuit layer, a first electrode layer, and a photosensitive element layer; the driving circuit layer is disposed on the substrate, the first electrode layer is disposed on the side of the driving circuit layer away from the substrate, and the photosensitive element layer is disposed on the side of the first electrode layer away from the substrate, wherein at least one of the plurality of pixel units includes a pixel driving circuit disposed in the driving circuit layer, a first electrode disposed in the first electrode layer, and a plurality of photosensitive elements disposed in the photosensitive element layer spaced apart from each other, the pixel driving circuit being electrically connected to the first electrode, and the plurality of photosensitive elements being disposed on the side of the first electrode away from the substrate and electrically connected to the pixel driving circuit through the first electrode.

[0004] For example, at least one embodiment of the texture recognition device provided in this disclosure further includes an interlayer insulating layer disposed between the driving circuit layer and the first electrode layer, wherein the interlayer insulating layer includes a via, and the first electrode is electrically connected to the pixel driving circuit through the via; the orthographic projection of the via on the substrate does not overlap with the orthographic projection of the plurality of photosensitive elements on the substrate.

[0005] For example, in a texture recognition device provided in at least one embodiment of the present disclosure, the first electrode includes at least one first hollow portion disposed between two adjacent photosensitive elements among the plurality of photosensitive elements.

[0006] For example, in the texture recognition device provided in at least one embodiment of this disclosure, the length of each of the at least one first hollow portion ranges from 6μm to 40μm, and the width ranges from 2.5μm to 10μm.

[0007] For example, in the texture recognition device provided in at least one embodiment of this disclosure, at least one of the plurality of pixel units includes a plurality of photosensitive elements arranged in an M-shape. An array of N, where M is a positive integer greater than or equal to 1 and N is a positive integer greater than 1.

[0008] For example, in the texture recognition device provided in at least one embodiment of this disclosure, M is 2, N is 2, and the plurality of photosensitive elements are arranged in a 2:1 ratio. An array of 2.

[0009] For example, at least one embodiment of the texture recognition device provided in this disclosure further includes a second electrode layer disposed on the side of the photosensitive element layer away from the substrate, wherein the at least one pixel unit further includes a plurality of second electrodes disposed in the second electrode layer, the plurality of second electrodes being respectively disposed on the side of the plurality of photosensitive elements away from the substrate.

[0010] For example, in the texture recognition device provided in at least one embodiment of this disclosure, the orthographic projection of the plurality of second electrodes on the substrate does not overlap with the orthographic projection of the via on the substrate.

[0011] For example, at least one embodiment of the texture recognition device provided in this disclosure further includes a third electrode layer disposed on the side of the second electrode layer away from the substrate, wherein the plurality of second electrodes are electrically connected to the third electrode layer.

[0012] For example, in a texture recognition device provided in at least one embodiment of the present disclosure, the third electrode layer includes at least one second cutout portion disposed between two adjacent pixel units in the plurality of pixel units.

[0013] For example, in at least one embodiment of the texture recognition device provided in this disclosure, the driving circuit layer further includes a signal scanning line electrically connected to the pixel driving circuit, and the orthographic projection of the at least one second cutout portion on the substrate at least partially overlaps with the orthographic projection of the signal scanning line on the substrate.

[0014] For example, in at least one embodiment of the texture recognition device provided in this disclosure, the length of the second cutout portion that at least partially overlaps with the signal scanning line ranges from 20μm to 97μm, and the width ranges from 6μm to 20μm.

[0015] For example, in the texture recognition device provided in at least one embodiment of this disclosure, the driving circuit layer further includes a signal readout line electrically connected to the pixel driving circuit, and the orthographic projection of the at least one second cutout portion on the substrate at least partially overlaps with the orthographic projection of the signal readout line on the substrate.

[0016] For example, in the texture recognition device provided in at least one embodiment of this disclosure, the length of the second hollow portion that at least partially overlaps with the signal readout line ranges from 8μm to 97μm, and the width ranges from 2.5μm to 20μm.

[0017] For example, at least one embodiment of the texture recognition device provided in this disclosure further includes an electrostatic shielding layer disposed on the side of the third electrode layer away from the substrate, wherein the orthographic projection of the third electrode layer on the substrate is located within the orthographic projection of the electrostatic shielding layer on the substrate.

[0018] For example, at least one embodiment of the texture recognition device provided in this disclosure further includes a first aperture layer disposed on the side of the electrostatic shielding layer away from the substrate, wherein the first aperture layer includes a plurality of first light-transmitting openings, and in a direction perpendicular to the surface of the substrate, the plurality of first light-transmitting openings correspond one-to-one with and overlap with the plurality of photosensitive elements.

[0019] For example, at least one embodiment of the texture recognition device provided in this disclosure further includes a second aperture layer disposed on the side of the first aperture layer away from the substrate. The second aperture layer includes a plurality of second light-transmitting openings, which correspond one-to-one with and overlap with the plurality of photosensitive elements in a direction perpendicular to the surface of the substrate.

[0020] For example, in the texture recognition device provided in at least one embodiment of this disclosure, in a direction parallel to the surface of the substrate, the diameter of each of the plurality of first light-transmitting openings is D1, and the diameter of each of the plurality of second light-transmitting openings is D2, then 2μm≤D1≤D2≤50μm.

[0021] For example, at least one embodiment of the texture recognition device provided in this disclosure further includes a field aperture layer disposed between the electrostatic shielding layer and the first aperture layer, wherein the field aperture layer includes a plurality of third light-transmitting openings, and in a direction perpendicular to the surface of the substrate, the plurality of third light-transmitting openings correspond one-to-one with and overlap with the plurality of photosensitive elements.

[0022] For example, at least one embodiment of the texture recognition device provided in this disclosure further includes a light filter layer disposed between the field stop layer and the first stop layer, wherein the light filter layer is configured to transmit light with a wavelength of 580nm to 850nm.

[0023] For example, at least one embodiment of the texture recognition device provided in this disclosure further includes a lens layer disposed on the side of the second aperture layer away from the substrate, wherein the lens layer includes a plurality of lens units, and in a direction perpendicular to the surface of the substrate, the plurality of lens units correspond one-to-one with and overlap with the plurality of photosensitive elements.

[0024] For example, at least one embodiment of the texture recognition device provided in this disclosure further includes a planarization layer disposed on the side of the lens layer away from the substrate, wherein the refractive index of the material of the planarization layer is 1.35 to 1.45.

[0025] For example, in at least one embodiment of the texture recognition device provided in this disclosure, the pixel driving circuit includes a first thin-film transistor, a second thin-film transistor, and a third thin-film transistor; the control terminal of the first thin-film transistor is connected to a signal scan line, and the first source-drain terminal and the second source-drain terminal of the first thin-film transistor are respectively connected to a signal readout line and the first source-drain terminal of the second thin-film transistor; the control terminal of the second thin-film transistor is connected to the first source-drain terminal of the third thin-film transistor, and the second source-drain terminal D2 of the second thin-film transistor is connected to a power supply line; the control terminal of the third thin-film transistor is connected to a reset signal line, and the second source-drain terminal of the third thin-film transistor is connected to the power supply line.

[0026] For example, in the texture recognition device provided in at least one embodiment of this disclosure, for the pixel driving circuit of each of the plurality of pixel units, the first thin film transistor and the second thin film transistor are disposed on the first side of the via of the interlayer insulating layer, and the third thin film transistor is disposed on the second side, with the first side and the second side opposite to each other.

[0027] For example, in at least one embodiment of the texture recognition device provided in this disclosure, the orthographic projection of the power line on the substrate overlaps with the orthographic projection portion of at least a portion of the plurality of photosensitive elements on the substrate.

[0028] At least one embodiment of this disclosure also provides a display device, which includes a display panel and a texture recognition device provided in the embodiments of this disclosure. The display panel has a display side and a non-display side, and allows light to pass through from the display side to the non-display side. The texture recognition device is disposed on the non-display side of the display panel and configured to receive light passing through from the display side to the non-display side for texture recognition. The photosensitive element layer is closer to the display panel than the substrate layer. Attached Figure Description

[0029] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0030] Figure 1 A plan view of a texture recognition device provided in at least one embodiment of the present disclosure;

[0031] Figure 2 for Figure 1 A schematic diagram of the cross-section of the texture recognition device along the NN line;

[0032] Figure 3 Another plan view of the texture recognition device provided in at least one embodiment of the present disclosure;

[0033] Figure 4 This is a circuit diagram of the pixel driving circuit and the photosensitive element in a texture recognition device provided in at least one embodiment of the present disclosure;

[0034] Figure 5 Another plan view of the texture recognition device provided in at least one embodiment of the present disclosure;

[0035] Figures 6A-6K A plan view of each structural layer in a texture recognition device provided in at least one embodiment of the present disclosure;

[0036] Figure 7 A plan view of a texture recognition device provided for at least one embodiment of the present disclosure and a cross-sectional view along MM in the plan view; and

[0037] Figure 8 This is a cross-sectional schematic diagram of a display device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0039] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0040] In a display device, a texture recognition device can be integrated into the non-display side of the display panel. The display panel is at least partially transparent, allowing the texture recognition device to receive signal light through the panel. Thus, the display device simultaneously possesses display and texture recognition functions. Current display devices typically employ texture recognition devices with multiple pixel units for recognizing signal light and synthesizing texture images. Each pixel unit can utilize a collimating film with a microlens structure as its optical path system to collimate the light incident on the texture recognition device, making the collimated light easier to recognize and improving light utilization. For example, each pixel unit includes a photosensitive element with a corresponding microlens structure to collimate the light incident on it.

[0041] However, the inventors of this disclosure have discovered that traditional microlens structures are difficult to match with the photosensitive elements included in each pixel unit, making it difficult to effectively collimate the light incident on each pixel unit. Furthermore, since each pixel unit also has a corresponding pixel driving circuit, which is positioned below the photosensitive element to avoid affecting the photosensitive element's reception of signal light, and is electrically connected to the photosensitive element to drive itself, the pixel driving circuit is typically not flat. This unevenness, positioned below the photosensitive element, causes structural deformation of the photosensitive element, affecting its characteristics and leading to problems such as dark current generation, thus impacting the recognition performance of the texture recognition device.

[0042] At least one embodiment of this disclosure provides a texture recognition device and a display device. The texture recognition device has a plurality of pixel units and includes a substrate, a driving circuit layer, a first electrode layer, and a photosensitive element layer. The driving circuit layer is disposed on the substrate, the first electrode layer is disposed on the side of the driving circuit layer away from the substrate, and the photosensitive element layer is disposed on the side of the first electrode layer away from the substrate. At least one of the plurality of pixel units includes a pixel driving circuit disposed in the driving circuit layer, a first electrode disposed in the first electrode layer, and a plurality of photosensitive elements disposed in the photosensitive element layer that are spaced apart from each other. The pixel driving circuit is electrically connected to the first electrode, and the plurality of photosensitive elements are disposed on the side of the first electrode away from the substrate and are electrically connected to the pixel driving circuit through the first electrode.

[0043] In the texture recognition device provided in the embodiments of this disclosure, at least one pixel unit includes multiple photosensitive elements. These multiple photosensitive elements are connected to the same pixel driving circuit via the same first electrode. In this case, the first electrode can be electrically connected to the pixel driving circuit through a via to realize the electrical connection between the multiple photosensitive elements and the same pixel driving circuit. This reduces the number of vias used for electrical connection, facilitates the selection of via positions, and thus benefits the flatness of the pixel driving circuit. On the other hand, since the multiple photosensitive elements included in at least one pixel unit are driven by the same pixel driving circuit, they are in the same working state. The pixel unit can receive sufficient signal light through the multiple photosensitive elements and synthesize a texture image.

[0044] The texture recognition device and display device provided in this disclosure will be described in detail below through several specific embodiments.

[0045] Figure 1 This is a plan view of a texture recognition device provided in at least one embodiment of the present disclosure. Figure 2 It shows Figure 1 A schematic diagram of the cross-section of the texture recognition device along the NN line.

[0046] like Figure 1 and Figure 2 As shown, the texture recognition device has multiple pixel units PX, for example, the multiple pixel units PX are arranged in an array. Figure 1 The image shows a pixel unit PX as an example. Figure 2 As shown, the texture recognition device includes a substrate 10, a driving circuit layer 20, a first electrode layer, and a photosensitive element layer. The driving circuit layer 20 is disposed on the substrate 10, the first electrode layer is disposed on the side of the driving circuit layer 20 away from the substrate 10, and includes a plurality of first electrodes E1 for a plurality of pixel units PX. The photosensitive element layer is disposed on the side of the first electrode layer away from the substrate 10, and includes a plurality of photosensitive elements for a plurality of pixel units PX.

[0047] For example, at least one of the plurality of pixel units PX includes a pixel driving circuit disposed in the driving circuit layer 20, a first electrode E1 disposed in the first electrode layer, and a plurality of photosensitive elements P disposed in the photosensitive element layer that are spaced apart from each other. Figure 1 The array arrangement shown is 2 Taking the four photosensitive elements P of 2 as an example, the pixel driving circuit is electrically connected to the first electrode E1, and the multiple photosensitive elements P are disposed on the side of the first electrode E1 away from the substrate 10, and are electrically connected to the pixel driving circuit through the first electrode E1.

[0048] Therefore, at least one pixel unit PX includes multiple photosensitive elements P that are connected to the same pixel driving circuit via the same first electrode E1. In this case, the first electrode E1 can be electrically connected to the pixel driving circuit through a via (i.e., via V1 in the figure) to realize the electrical connection between multiple photosensitive elements P and the same pixel driving circuit. This reduces the number of vias V1 used for electrical connection, facilitates the selection of the position of vias V1, and thus benefits the flatness of the pixel driving circuit. On the other hand, since at least one pixel unit PX includes multiple photosensitive elements P that are driven by the same pixel driving circuit, they are in the same working state. The pixel unit PX can receive sufficient signal light through multiple photosensitive elements P and synthesize a texture image.

[0049] For example, in embodiments of this disclosure, at least one of the plurality of photosensitive elements P included in a plurality of pixel units can be arranged as M. An array of N, where M is a positive integer greater than or equal to 1, and N is a positive integer greater than 1. For example, Figure 3 A schematic diagram illustrating the arrangement of multiple photosensitive elements P provided in some embodiments of this disclosure is shown. For example... Figure 3 As shown, in some examples, multiple photosensitive elements P can be arranged in an array of M rows and N columns, for example, 2 rows and 3 columns (2 3) array, 3 rows and 3 columns (3 3) array or 4 rows and 4 columns (4 4) arrays, etc., are not specifically limited in the embodiments of this disclosure.

[0050] For example, in some embodiments, the pixel driving circuit of each pixel unit PX includes at least one thin-film transistor, and may also include structures such as capacitors. Figure 4 This diagram illustrates a pixel driving circuit connected to a photosensitive element P according to at least one embodiment of the present disclosure, such as... Figure 4 As shown, in this example, the pixel driving circuit includes a first thin-film transistor T1, a second thin-film transistor T2, a third thin-film transistor T3, and a capacitor C.

[0051] For example, such as Figure 4As shown, the first thin-film transistor T1 acts as a switching transistor, with its control terminal connected to the signal scan line Vr. Its first source-drain terminal S1 and second source-drain terminal D1 are connected to the signal readout line Vout and the first source-drain terminal S2 of the second thin-film transistor T2, respectively. The second thin-film transistor T2 acts as a driving transistor, with its control terminal connected to the first source-drain terminal S3 of the third thin-film transistor T3, the first capacitor plate C1 of capacitor C, and the first electrode E1 of photosensitive element P. Its second source-drain terminal D2 is connected to the power supply line Vdd. The third thin-film transistor T3 acts as a reset transistor, with its control terminal connected to the reset signal line Vrst. Its second source-drain terminal D3 is connected to the power supply line Vdd. The second capacitor plate C2 of capacitor C and the second electrode E2 of photosensitive element P are connected to the bias line Vb. For example, Figure 4 Only one photosensitive element P is shown as an example; in reality, multiple photosensitive elements P connected in parallel can be included here.

[0052] For example, in Figure 4 In the circuit shown, the operation of the photosensitive element P includes: First, in the reset phase, a reset signal is input to the control terminal of the third thin-film transistor T3 through the reset signal line Vrst, causing the third thin-film transistor T3 to conduct. The reset signal is written to the first electrode E1 of the photosensitive element P and the control terminal of the second thin-film transistor T2. Then, in the photosensitive phase, the photosensitive element P generates photogenerated carriers under the illumination of signal light, generating photogenerated leakage current and charging the capacitor C, so that the capacitor C generates and stores an electrical signal. Finally, in the detection phase, a scan signal is input to the control terminal of the first thin-film transistor T1 through the signal scan line Vr, causing the first thin-film transistor T1 to conduct. The texture recognition chip reads the electrical signal stored in the capacitor C from the first thin-film transistor T1 and the second thin-film transistor T2 through the signal readout line Vout, and then forms a texture image.

[0053] For example, Figure 2 Only one thin-film transistor is shown, for example, the second thin-film transistor T2 mentioned above, which includes an active layer AT, a gate G, a source S, and a drain D. For example, the gate G serves as the control terminal of the second thin-film transistor T2, the source S serves as the first source-drain terminal of the second thin-film transistor T2, and the drain D serves as the second source-drain terminal of the second thin-film transistor T2. For example, Figure 2 Another gate G2 is shown, which is the gate of the first thin-film transistor T1. The other structures of the first thin-film transistor T1 and the third thin-film transistor T3 are not shown. Figure 2 The structure is not shown in the figure. For example, the first thin-film transistor T1 and the third thin-film transistor T3 have a structure similar to that of the second thin-film transistor T2. The embodiments of this disclosure do not limit the specific structure of the first thin-film transistor T1, the second thin-film transistor T2 and the third thin-film transistor T3.

[0054] For example, in some embodiments, such as Figure 2 As shown, the texture recognition device further includes an interlayer insulating layer IL, which is disposed between the driving circuit layer 20 and the first electrode layer. The interlayer insulating layer IL includes a via V1, through which the first electrode E1 is electrically connected to the pixel driving circuit, for example, electrically connected to the gate G of the second thin-film transistor T2 in the pixel driving circuit. For example, the orthographic projection of the via V1 on the substrate 10 does not overlap with the orthographic projection of the plurality of photosensitive elements P on the substrate 10.

[0055] Since the location of the via V1 is relatively uneven, by setting the via V1 and multiple photosensitive elements P to not overlap in the direction perpendicular to the substrate 10, the uneven part can be avoided from being located below the photosensitive element P, which would cause the structure of the photosensitive element to be deformed. This ensures the structural accuracy of the photosensitive element and improves the photosensitive effect of the photosensitive element.

[0056] For example, in some embodiments, the interlayer insulating layer is a planarization layer used to planarize the pixel driving circuit so that the first electrode layer above it can be disposed. For example, in some embodiments, such as Figure 2 As shown, the interlayer insulation layer may include a stack of multiple insulator layers, such as a planarization layer IL1 and a first passivation layer IL2. The planarization layer IL1 has a via V10, and the first passivation layer IL2 has a via V11. The via V10 and the via V11 are connected to form the via V1 in the interlayer insulation layer IL. For example, in other embodiments, the interlayer insulation layer may also include a stack of more insulator layers. The embodiments of this disclosure do not limit the specific form of the interlayer insulation layer IL.

[0057] For example, in some embodiments, the first electrode E1 of each pixel unit PX is a monolithic structure disposed below multiple photosensitive elements; or, in other embodiments, such as Figure 1 As shown, the first electrode E1 includes at least one first cutout portion E10 disposed between two adjacent photosensitive elements P in a plurality of photosensitive elements P. For example, the first electrode E1 includes a plurality of first cutout portions E10 disposed between each pair of adjacent photosensitive elements P in a plurality of photosensitive elements P. The first cutout portion E10 can prevent the first electrode E1 from generating coupling capacitance with the circuit above or below it, thereby avoiding adverse phenomena such as signal crosstalk.

[0058] For example, in some embodiments, such as Figure 2As shown, the texture recognition device further includes a second electrode layer, which is disposed on the side of the photosensitive element layer away from the substrate 10. For example, at least one pixel unit PX further includes a plurality of second electrodes E2 disposed in the second electrode layer, and the plurality of second electrodes E2 are respectively disposed on the side of the plurality of photosensitive elements P away from the substrate 10. The first electrode E1 and the plurality of second electrodes E2 jointly drive the plurality of photosensitive elements P; on the other hand, the first electrode E1 can also form the capacitor C together with the plurality of second electrodes E2.

[0059] For example, in some embodiments, the orthographic projections of the plurality of second electrodes E2 on the substrate 10 do not overlap with the orthographic projections of the via V1 on the substrate 10. For example, the plurality of second electrodes E2 are spaced apart in the second electrode layer, and the orthographic projection of the second electrode E2 disposed on each photosensitive element P on the substrate 10 is located within the orthographic projection of the photosensitive element P on the substrate 10, so as to ensure the flatness of the second electrodes E2, thereby ensuring the accuracy of the electrical signals transmitted by the second electrodes E2.

[0060] For example, in some embodiments, such as Figure 2 As shown, the texture recognition device may further include a third electrode layer E3, which is disposed on the side of the second electrode layer away from the substrate 10. A plurality of second electrodes E2 are electrically connected to the third electrode layer E3. For example, the third electrode layer E3 is connected to a bias line Vb, thereby allowing each second electrode E2 to obtain the same electrical signal from the bias line Vb through the third electrode layer E3.

[0061] For example, in some embodiments, the third electrode layer E3 includes at least one second cutout portion E30 disposed between two adjacent pixel units PX in the plurality of pixel units PX. For example, the third electrode layer E3 includes a plurality of second cutout portions E30 disposed between every two adjacent pixel units PX in the plurality of pixel units PX. The second cutout portion E30 can prevent the third electrode layer E3 from generating coupling capacitance with the circuit above or below it, thereby avoiding adverse phenomena such as signal crosstalk.

[0062] For example, such as Figure 2 As shown, the texture recognition device may further include a first buffer layer 101 disposed on the substrate 10, a first gate insulating layer 102 disposed on the active layer AT, a second gate insulating layer 103 disposed on the gate G, a second buffer layer 104 disposed on the second electrode layer, an organic insulating layer 105 disposed on the second buffer layer 104, a second passivation layer 106 disposed on the organic insulating layer 105, and a third passivation layer 107 disposed on the third electrode layer E3. For example, the second buffer layer 104, the organic insulating layer 105, and the second passivation layer 106 have multiple vias V2, and multiple second electrodes E2 are connected to the third electrode layer E3 through the multiple vias V2 respectively.

[0063] For example, in some embodiments, such as Figure 2 As shown, the texture recognition device may further include an electrostatic shielding layer 108, which is disposed on the side of the third electrode layer E3 away from the substrate 10. The orthographic projection of the third electrode layer E3 on the substrate 10 lies within the orthographic projection of the electrostatic shielding layer 108 on the substrate 10. The electrostatic shielding layer 108 can provide electrostatic shielding for the third electrode layer E3 and the circuit below it.

[0064] For example, in some embodiments, such as Figure 2 As shown, the electrostatic shielding layer 108 can be formed on the entire surface of the third electrode layer E3, or it can have the same pattern as the third electrode layer E3. For example, the electrostatic shielding layer 108 can have a third cutout between adjacent pixel units PX, which is not shown in the figure.

[0065] For example, Figure 5 A plan view of a texture recognition device provided in at least one embodiment of this disclosure is shown. Figure 5 As shown, the driving circuit layer includes a pixel driving circuit and signal lines such as signal scan lines Vr and signal readout lines Vout electrically connected to the pixel driving circuit. The area shown by the dashed box is a pixel unit, and the signal scan line Vr and signal readout line Vout are not included within the area of ​​a pixel unit. For example, the signal scan line Vr extends laterally between adjacent pixel units, and the signal readout line Vout extends vertically between adjacent pixel units. For example, the orthographic projection of at least one second cutout portion E30 on the substrate 10 at least partially overlaps with the orthographic projection of the signal scan line Vr on the substrate 10, and the orthographic projection of at least one second cutout portion E30 on the substrate 10 at least partially overlaps with the orthographic projection of the signal readout line Vout on the substrate 10. This avoids the third electrode layer E3 from generating large parasitic capacitances with the signal lines such as signal scan line Vr and signal readout line Vout, thereby avoiding adverse phenomena such as signal crosstalk.

[0066] For example, such as Figure 5 As shown, for the pixel driving circuit of each pixel unit, the first thin film transistor T1, the second thin film transistor T2 and the third thin film transistor T3 have the arrangement shown in the figure, that is, the first thin film transistor T1 and the second thin film transistor T2 are disposed on the first side (the lower side in the figure) of the via V1 included in the interlayer insulating layer, and the third thin film transistor T3 is disposed on the second side (the upper side in the figure), with the first side and the second side opposite to each other.

[0067] For example, the orthographic projection of the power line Vdd onto the substrate overlaps with the orthographic projection portions of at least a portion of the plurality of photosensitive elements onto the substrate, for example, in Figure 5In the example shown, the power line Vdd overlaps with the two photosensitive elements P on the right side of the pixel unit.

[0068] For example, Figure 6A Figure 6L shows Figure 5 A planar schematic diagram of each functional layer of the texture recognition device.

[0069] For example, Figure 6A This is a schematic diagram of the semiconductor layer containing the active layers of the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3 in the pixel driving circuit.

[0070] Figure 6B This is a schematic diagram of the gate metal layer containing the gates of the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3. For example, the portion where the gate metal layer overlaps with the semiconductor layer constitutes the gate of the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3. For example, the gate metal layer also includes signal lines such as signal scan line Vr and reset signal line Vrst, which extend laterally.

[0071] For example, Figure 6C This is a schematic diagram of the source and drain metal layers containing the source and drain electrodes of the first thin-film transistor T1, the second thin-film transistor T2, and the third thin-film transistor T3. For example, the source and drain metal layers also include signal lines such as the signal readout line Vout. For instance, the extension direction of the signal readout line Vout intersects with, or is perpendicular to, the extension directions of the signal scan line Vr and the reset signal line Vrst. Figure 6C Extending longitudinally.

[0072] For example, Figure 6D This is a schematic diagram of the planarization layer IL1, which contains vias V10. Figure 6E This is a planar schematic diagram of the first passivation layer IL2, which contains a via V11. For example, the planarization layer IL1 and the first passivation layer IL2 constitute the interlayer insulating layer IL between the pixel driving circuit and the first electrode layer. The via V10 is connected to the via V11, forming the via V1 in the interlayer insulating layer IL.

[0073] For example, Figure 6FThis is a planar schematic diagram of the first electrode layer. The first electrode layer includes multiple first electrodes E1 for multiple pixel units PX. Multiple photosensitive elements P are disposed on the first electrode E1 of each pixel unit PX. Each first electrode E1 includes a first cutout portion E10 located between the multiple photosensitive elements P. For example, the length L of the first cutout portion E10 ranges from 6μm to 40μm, such as 10μm, 20μm, or 30μm, and the width W ranges from 2.5μm to 10μm, such as 3μm, 5μm, or 7μm.

[0074] Figure 6G This is a planar schematic diagram of multiple photosensitive elements P, which are spaced apart on the first electrode E1.

[0075] Figure 6H This is a planar schematic diagram of the second electrode layer, which includes multiple second electrodes E2. The multiple second electrodes E2 are respectively disposed on multiple photosensitive elements P to drive the multiple photosensitive elements P together with the first electrode E1. On the other hand, the multiple second electrodes E2 can also form the aforementioned capacitor C together with the first electrode E1.

[0076] For example, Figure 6I This is a planar schematic diagram of the second buffer layer 104, the organic insulating layer 105, and the second passivation layer 106. The second buffer layer 104, the organic insulating layer 105, and the second passivation layer 106 have multiple vias V2.

[0077] Figure 6J This is a planar schematic diagram of the third electrode layer E3. Multiple second electrodes E2 are connected to the third electrode layer E3 through multiple vias V2. The third electrode layer E3 includes multiple second cutouts E30 located between adjacent pixel units PX. For example, Figure 6J The second hollow portion E30 extending laterally in the middle at least partially overlaps with the signal scan line Vr, and the length L2 of the second hollow portion ranges from 20μm to 97μm, such as 30μm, 40μm or 50μm, and the width ranges from 6μm to 20μm, such as 8μm, 10μm or 15μm. Figure 6J The second hollow portion E30 extending longitudinally in the middle partially overlaps with the signal readout line Vout, and the length L1 of the second hollow portion ranges from 8μm to 97μm, such as 10μm, 20μm or 50μm, and the width W1 ranges from 2.5μm to 20μm, such as 5μm, 10μm or 15μm.

[0078] Figure 7K is a planar schematic diagram of the electrostatic shielding layer 108. In this example, the electrostatic shielding layer 108 has a pattern similar to the third electrode layer E3, for example, it has a plurality of third cutouts 1081 located between adjacent pixel units PX. In the direction perpendicular to the surface of the substrate 10, the plurality of third cutouts 1081 correspond one-to-one with and overlap with a plurality of second cutouts E30.

[0079] For example, in some embodiments, Figure 7 A plan view of a texture recognition device provided in at least one embodiment of this disclosure, and a cross-sectional view along MM in the plan view, as shown below. Figure 7 As shown, the texture recognition device also includes a first aperture layer 50, which is disposed on the side of the electrostatic shielding layer 108 away from the substrate 10, for clear imaging purposes. Figure 7 The structure between the photosensitive element P and the electrostatic shielding layer 108 (including the electrostatic shielding layer 108) is omitted. For example... Figure 7 As shown, the first aperture layer 50 includes a plurality of first light-transmitting openings 501. In a direction perpendicular to the surface of the substrate 10, the plurality of first light-transmitting openings 501 correspond one-to-one with and overlap with a plurality of photosensitive elements P. The plurality of first light-transmitting openings 501 are respectively used to transmit signal light incident on the plurality of photosensitive elements P, and to block light at a certain angle (a certain large angle with the surface of the substrate 10) and unnecessary light such as signal light for adjacent photosensitive elements P, for example... Figure 7 The light indicated by the dashed line further prevents adverse phenomena such as signal crosstalk.

[0080] For example, in some embodiments, as shown in Figure 7, in a direction parallel to the surface of the substrate 10, the diameter of each first light-transmitting opening 501 is D1, then 2μm≤D1≤50μm, for example, D1 is 10μm, 20μm or 30μm, etc.

[0081] For example, in a direction parallel to the surface of the substrate 10, the shape of the plurality of first light-transmitting openings 501 can be rectangular, square, or circular. For example, when the shape of the plurality of first light-transmitting openings 501 is square, the aforementioned D1 can be the side length of the square; when the shape of the plurality of first light-transmitting openings 501 is rectangular, the aforementioned D1 can be the diagonal length of the rectangle; when the shape of the plurality of first light-transmitting openings 501 is circular, the aforementioned D1 can be the diameter of the circle.

[0082] For example, in some embodiments, the material of the first aperture layer 50 can be a light-absorbing material, such as a black matrix material, or a black light-absorbing material formed by adding black dye to a resin material. This can reduce or even eliminate the reflection of light by the first aperture layer 50, thereby avoiding adverse effects of reflected light on texture recognition. For example, the plurality of first light-transmitting openings 501 are filled with transparent resin material to prevent deformation or other adverse phenomena inside the texture recognition device due to air gaps.

[0083] For example, in some embodiments, such as Figure 7 As shown, in the direction perpendicular to the surface of the substrate 10, the thickness H1 of the first aperture layer 50 is 1μm-3μm, such as 1.5μm, 2μm, or 2.5μm. The distance between the first aperture layer 50 and the photosensitive element layer 30 is 5μm-20μm, that is, the distance between the lower surface of the first aperture layer 50 and the upper surface of the photosensitive element layer 30 is 5μm-20μm, such as 10μm, 15μm, or 18μm. With the above configuration, the first aperture layer 50 can effectively achieve the crosstalk prevention function.

[0084] For example, in some embodiments, such as Figure 7 As shown, the texture recognition device further includes a second aperture layer 60, which is disposed on the side of the first aperture layer 50 away from the substrate 10. The second aperture layer 60 includes a plurality of second light-transmitting openings 601. In a direction perpendicular to the surface of the substrate 10, the plurality of second light-transmitting openings 601 correspond one-to-one with and overlap with a plurality of photosensitive elements P. The plurality of second light-transmitting openings 601 are respectively used to transmit signal light incident on the plurality of photosensitive elements P, and to block light at a certain angle (at a certain angle to the surface of the substrate) and unnecessary light such as signal light for adjacent photosensitive elements, for example... Figure 1 The light indicated by the dashed line can further prevent adverse phenomena such as signal crosstalk.

[0085] For example, in the direction parallel to the surface of the substrate 10, the diameter of each second light-transmitting opening 601 is D2, then 2μm≤D1≤D2≤50μm, for example, D2 can be 20μm, 30μm or 40μm, etc.

[0086] Similarly, in the direction parallel to the surface of the substrate 10, the shape of the second light-transmitting opening 601 can be rectangular, square, or circular, etc. For example, when the shape of multiple second light-transmitting openings 601 is square, the aforementioned D2 can be the side length of the square; when the shape of the second light-transmitting opening 601 is rectangular, the aforementioned D2 can be the diagonal length of the rectangle; when the shape of the second light-transmitting opening 601 is circular, the aforementioned D2 can be the diameter of the circle.

[0087] For example, in some embodiments, the material of the second aperture layer 60 can be a light-absorbing material, such as a black matrix material, or a black light-absorbing material formed by adding black dye to a resin material. This can reduce or even eliminate the reflection of light by the second aperture layer 60, thereby preventing reflected light from affecting texture recognition. For example, the plurality of second light-transmitting openings 601 are filled with transparent resin material to prevent deformation or other adverse phenomena inside the texture recognition device due to air gaps.

[0088] For example, in some embodiments, the thickness H2 of the second aperture layer 60 is 1μm-3μm in the direction perpendicular to the surface of the substrate 10, such as 1.5μm, 2μm or 2.5μm, and the distance between the second aperture layer 60 and the first aperture layer 50 is 5μm-20μm, such as 10μm, 15μm or 18μm.

[0089] For example, in some embodiments, such as Figure 7 As shown, the texture recognition device may further include a field-of-view aperture layer 80 disposed between the electrostatic shielding layer 108 and the first aperture layer 50. The field-of-view aperture layer 80 includes a plurality of third light-transmitting openings 801. In a direction perpendicular to the surface of the substrate 10, the plurality of third light-transmitting openings 801 correspond one-to-one with and overlap with a plurality of photosensitive elements P. The plurality of third light-transmitting openings 801 are respectively used to transmit signal light incident on the plurality of photosensitive elements P and to block unnecessary light at large angles (large angles with respect to the surface of the substrate), such as... Figure 7 The light indicated by the dashed line further prevents adverse phenomena such as signal crosstalk.

[0090] For example, in the direction parallel to the surface of the substrate 10, the diameter of each third light-transmitting opening 801 is D3, then 2μm≤D3≤10μm, for example, D3 is 5μm, 7μm or 9μm, etc.

[0091] For example, in some embodiments, the thickness H3 of the field stop layer 80 is 300 nm to 500 nm in the direction perpendicular to the surface of the substrate 10, such as 350 nm, 400 nm or 450 nm.

[0092] For example, in some embodiments, the field stop layer 80 is made of a metallic material, such as molybdenum, aluminum, titanium, or their alloys. In this case, during the fabrication of the texture recognition device, the field stop layer 80 can be formed together with the driving circuit layer 20 and the photosensitive element layer 30, thereby simplifying the fabrication process of the texture recognition device.

[0093] During fingerprint recognition, in addition to the signal light used for fingerprint recognition, the photosensitive element P may also sense ambient light passing through the finger. Since the photosensitive element P passively receives light and does not actively distinguish between signal light and ambient light, ambient light can interfere with fingerprint recognition. For example, when ambient light shines directly above the finger, it can pass through the finger and excite pigment light emitted by the finger's biological tissue. This pigment light may interfere with fingerprint recognition. Detection revealed that this pigment light primarily includes light with wavelengths in the range of 580nm to 850nm.

[0094] For example, in some embodiments, such as Figure 7 As shown, the texture recognition device also includes a light filter layer 70 disposed between the field stop layer 80 and the first stop layer 50. The light filter layer 70 is configured to transmit light with wavelengths of 580nm to 850nm, that is, to prevent light with wavelengths of 580nm to 850nm from passing through, thereby preventing the aforementioned pigment light from affecting texture recognition and enabling its use in strong light scenarios such as outdoors. For example, the light filter layer 70 can have high transmittance for signal light that can be used for texture recognition. For example, the light filter layer 70 can have high transmittance for visible light with wavelengths of 400nm to 560nm, so that the photosensitive element P can fully receive the signal light. For example, in some embodiments, the light filter layer 70 is a green photoresist layer.

[0095] For example, in some embodiments, such as Figure 7 As shown, the texture recognition device further includes a lens layer 40, which is disposed on the side of the second aperture layer 60 away from the substrate 10. The lens layer 40 includes a plurality of lens units 401, which correspond one-to-one with and overlap with a plurality of photosensitive elements P in a direction perpendicular to the surface of the substrate 10. Thus, each photosensitive element P has a corresponding lens unit 401, allowing each lens unit 401 to be more precisely matched with its corresponding photosensitive element P for more accurate light collimation. This enables more precise control of the propagation direction of the signal light incident on each photosensitive element, avoiding crosstalk and other adverse phenomena between adjacent pixel units PX, and improving the texture recognition effect of the texture recognition device.

[0096] For example, in some embodiments, such as Figure 7As shown, the planar shape of the multiple lens units 401 can be circular. In this case, the radius of curvature R of each lens unit 401 can be 5μm~20μm, such as 7μm, 10μm or 15μm, and the diameter D0 of each lens unit 401 can be 25μm-35μm, such as 27μm, 30μm or 32μm. For example, in other embodiments, the planar shape of the multiple lens units 401 can also be rectangular or square, etc. The embodiments of this disclosure do not limit the specific form of the multiple lens units 401.

[0097] For example, in some embodiments, the refractive index of the material of the lens layer 40 is 1.6 to 1.7, such as 1.65. Therefore, the multiple lens units 401 can sufficiently refract the light incident upon them, thereby achieving an effective collimation effect and improving the utilization rate of the incident light.

[0098] For example, in some embodiments, such as Figure 7 As shown, the texture recognition device may further include a planarization layer 90 disposed on the side of the lens layer 40 away from the substrate 10. The planarization layer 90 can flatten the unevenness caused by the lens layer 40 and facilitates the bonding of the texture recognition device to other devices, such as to a display panel. For example, in some examples, the planarization layer 90 can be bonded to the display panel using optically transparent adhesive. In this case, because the planarization layer 90 is relatively flat, the optically transparent adhesive has a stronger adhesion to the planarization layer 90 and the display panel.

[0099] For example, the planarization layer 90 is made of a material with a refractive index of 1.35 to 1.45, such as 1.40. For example, the planarization layer 90 may comprise an organic material with a refractive index of 1.35 to 1.45. In the embodiments of this disclosure, by using a material with a low refractive index to form the planarization layer 90, adverse effects on the propagation of signal light can be avoided, such as preventing unnecessary refraction and reflection of the signal light.

[0100] For example, in the embodiments of this disclosure, each photosensitive element P is island-shaped, and its planar shape can be square, rectangular, or other shapes. For example, when the planar shape of the photosensitive element P is square, the side length of the square can be 10μm-20μm, such as 12μm, 15μm, or 18μm.

[0101] For example, the photosensitive element P can be a photodiode, which can be PN type or PIN type. For example, when the photodiode is PN type, the photosensitive element P includes a stacked P-type semiconductor layer and an N-type semiconductor layer; when the photodiode is PIN type, the photosensitive element P includes a stacked P-type semiconductor layer, an intrinsic semiconductor layer, and an N-type semiconductor layer. For example, the semiconductor material used in the photosensitive element P can be silicon, germanium, selenium, gallium arsenide, etc., and the embodiments of this disclosure are not limited in this regard.

[0102] For example, in embodiments of this disclosure, the substrate 10 may include flexible insulating materials such as polyimide (PI) or rigid insulating materials such as a glass substrate. For example, the first buffer layer 101 and the second buffer layer 104 may include inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride. The active layer AT may be made of materials such as polycrystalline silicon and metal oxides. The first gate insulating layer 102 and the second gate insulating layer 103 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The gate G may be made of metallic materials such as copper, aluminum, titanium, or cobalt, and may be formed as a single-layer structure or a multi-layer structure, such as titanium / aluminum / titanium, molybdenum / aluminum / molybdenum, etc. The first passivation layer IL2, the second passivation layer 106, and the third passivation layer 107 may be made of inorganic insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. The source / drain electrodes S / D may be made of metallic materials such as copper, aluminum, titanium, or cobalt, and may be formed as a single-layer structure or a multi-layer structure, such as titanium / aluminum / titanium, molybdenum / aluminum / molybdenum, etc. The first electrode layer may include, for example, metal oxides such as ITO and IZO, or metals such as Ag, Al, and Mo, or their alloys. The second electrode layer and the electrostatic shielding layer 108 may include, for example, transparent metal oxides such as ITO and IZO. The planarization layer IL1 may be made of organic insulating materials such as polyimide. The embodiments of this disclosure do not specifically limit the materials of each functional layer.

[0103] For example, the texture recognition device provided in the embodiments of this disclosure may also have other structures, which can be referred to in the relevant technology, and will not be described in detail here.

[0104] At least one embodiment of this disclosure also provides a display device. Figure 8 A cross-sectional schematic diagram of the display device is shown, as follows: Figure 8 As shown, the display device includes a panel 200 and a texture recognition device provided in this embodiment. The display panel 200 has a display side 201 and a non-display side 202, and allows light to pass through from the display side 201 to the non-display side 202. The texture recognition device is disposed on the non-display side 202 of the display panel 200 and configured to receive light passing through from the display side 201 to the non-display side 202 for texture recognition. When the texture recognition device is disposed, the photosensitive element layer 30 is closer to the display panel 200 relative to the substrate 10 layer.

[0105] The display device provided in this embodiment uses the texture recognition device provided in this embodiment to perform texture recognition, which has a better texture recognition effect, such as higher texture recognition speed and texture recognition accuracy.

[0106] The following points also need to be explained:

[0107] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure, and other structures can be referred to the general design.

[0108] (2) For clarity, the thickness of layers or regions is enlarged or reduced in the drawings used to describe embodiments of the present disclosure, i.e., these drawings are not drawn to scale. It will be understood that when an element such as a layer, film, region or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element or there may be intermediate elements.

[0109] (3) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0110] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure shall be determined by the scope of the claims.

Claims

1. A texture recognition device having multiple pixel units, and comprising: Substrate A driving circuit layer is disposed on the substrate. The first electrode layer is disposed on the side of the driving circuit layer away from the substrate. A photosensitive element layer is disposed on the side of the first electrode layer away from the substrate. Wherein, at least one of the plurality of pixel units includes a pixel driving circuit disposed in the driving circuit layer, a first electrode disposed in the first electrode layer, and a plurality of photosensitive elements disposed in the photosensitive element layer that are spaced apart from each other. The pixel driving circuit is electrically connected to the first electrode. The plurality of photosensitive elements are disposed on the side of the first electrode away from the substrate and are electrically connected to the pixel driving circuit through the first electrode; The first electrode includes at least one first cutout portion disposed between two adjacent photosensitive elements among the plurality of photosensitive elements.

2. The texture recognition device according to claim 1 further includes an interlayer insulating layer disposed between the driving circuit layer and the first electrode layer, wherein, The interlayer insulating layer includes vias, and the first electrode is electrically connected to the pixel driving circuit through the vias; The orthographic projection of the via on the substrate does not overlap with the orthographic projection of the plurality of photosensitive elements on the substrate.

3. The texture recognition device according to claim 1, wherein, The length of each of the at least one first hollow portion ranges from 6μm to 40μm, and the width ranges from 2.5μm to 10μm.

4. The texture recognition device according to claim 1 or 2, wherein, At least one of the plurality of pixel units includes a plurality of photosensitive elements arranged in an M-shape. An array of N, Where M is a positive integer greater than or equal to 1, and N is a positive integer greater than 1.

5. The texture recognition device according to claim 4, wherein, M is 2, N is 2, and the plurality of photosensitive elements are arranged in a 2:1 ratio. An array of 2.

6. The texture recognition device according to claim 2 further includes a second electrode layer disposed on the side of the photosensitive element layer away from the substrate. in, The at least one pixel unit further includes a plurality of second electrodes disposed in the second electrode layer, the plurality of second electrodes being disposed on the side of the plurality of photosensitive elements away from the substrate.

7. The texture recognition device according to claim 6, wherein, The orthographic projections of the plurality of second electrodes on the substrate do not overlap with the orthographic projections of the vias on the substrate.

8. The texture recognition device according to claim 6 or 7 further includes a third electrode layer disposed on the side of the second electrode layer away from the substrate, wherein, The plurality of second electrodes are electrically connected to the third electrode layer.

9. The texture recognition device according to claim 8, wherein, The third electrode layer includes at least one second cutout portion disposed between two adjacent pixel units in the plurality of pixel units.

10. The texture recognition device according to claim 9, wherein, The driving circuit layer also includes signal scan lines electrically connected to the pixel driving circuit. The orthographic projection of at least one second cutout on the substrate at the same time as the orthographic projection of the signal scan line on the substrate at least partially overlaps.

11. The texture recognition device according to claim 10, wherein, The length of the second cutout portion, which at least partially overlaps with the signal scan line, ranges from 20μm to 97μm, and the width ranges from 6μm to 20μm.

12. The texture recognition device according to claim 9, wherein, The driving circuit layer also includes a signal readout line electrically connected to the pixel driving circuit. The orthographic projection of at least one second cutout on the substrate at the same time as the orthographic projection of the signal readout line on the substrate at least partially overlaps.

13. The texture recognition device according to claim 12, wherein, The length of the second cutout portion, which at least partially overlaps with the signal readout line, ranges from 8μm to 97μm, and the width ranges from 2.5μm to 20μm.

14. The texture recognition device according to claim 8 further includes an electrostatic shielding layer disposed on the side of the third electrode layer away from the substrate. in, The orthographic projection of the third electrode layer on the substrate lies within the orthographic projection of the electrostatic shielding layer on the substrate.

15. The texture recognition device according to claim 14, further comprising a first aperture layer disposed on the side of the electrostatic shielding layer away from the substrate, wherein, The first aperture layer includes a plurality of first light-transmitting openings. In a direction perpendicular to the surface of the substrate, the plurality of first light-transmitting openings correspond one-to-one with and overlap with the plurality of photosensitive elements.

16. The texture recognition device according to claim 15 further includes a second aperture layer disposed on the side of the first aperture layer away from the substrate, wherein, The second aperture layer includes a plurality of second light-transmitting openings. In a direction perpendicular to the surface of the substrate, the plurality of second light-transmitting openings correspond one-to-one with and overlap with the plurality of photosensitive elements.

17. The texture recognition device according to claim 16, wherein, In a direction parallel to the surface of the substrate, the diameter of each of the plurality of first light-transmitting openings is D1, and the diameter of each of the plurality of second light-transmitting openings is D2, then 2μm≤D1≤D2≤50μm.

18. The texture recognition device according to claim 15, further comprising a field-of-view aperture layer disposed between the electrostatic shielding layer and the first aperture layer, wherein, The field-of-view aperture layer includes multiple third light-transmitting openings. In a direction perpendicular to the surface of the substrate, the plurality of third light-transmitting openings correspond one-to-one with and overlap with the plurality of photosensitive elements.

19. The texture recognition device according to claim 18, further comprising a light filter layer disposed between the field-of-view aperture layer and the first aperture layer, wherein, The optical filter layer is configured to allow light with wavelengths of 580nm to 850nm to pass through.

20. The texture recognition device according to claim 16 further includes a lens layer disposed on the side of the second aperture layer away from the substrate. in, The lens layer includes multiple lens units, which correspond one-to-one with and overlap with the multiple photosensitive elements in a direction perpendicular to the surface of the substrate.

21. The texture recognition device according to claim 20, further comprising a planarization layer disposed on the side of the lens layer away from the substrate, wherein, The refractive index of the material of the planarization layer is 1.35~1.

45.

22. The texture recognition device according to claim 2, wherein, The pixel driving circuit includes a first thin-film transistor, a second thin-film transistor, and a third thin-film transistor; The control terminal of the first thin-film transistor is connected to the signal scan line, and the first source-drain terminal and the second source-drain terminal of the first thin-film transistor are respectively connected to the signal readout line and the first source-drain terminal of the second thin-film transistor; the control terminal of the second thin-film transistor is connected to the first source-drain terminal of the third thin-film transistor, and the second source-drain terminal D2 of the second thin-film transistor is connected to the power supply line; the control terminal of the third thin-film transistor is connected to the reset signal line, and the second source-drain terminal of the third thin-film transistor is connected to the power supply line.

23. The texture recognition device according to claim 22, wherein, For each of the plurality of pixel units, the interlayer insulating layer includes a via on a first side where the first thin-film transistor and the second thin-film transistor are disposed, and on a second side where the third thin-film transistor is disposed, with the first side and the second side opposite to each other.

24. The texture recognition device according to claim 22 or 23, wherein, The orthographic projection of the power line on the substrate overlaps with the orthographic projection of at least a portion of the plurality of photosensitive elements on the substrate.

25. A display device, comprising: A display panel having a display side and a non-display side, and allowing light to pass through from the display side to the non-display side, and The texture recognition device according to any one of claims 1-24 is disposed on the non-display side of the display panel and configured to receive light transmitted from the display side to the non-display side for texture recognition. The photosensitive element layer is closer to the display panel than the substrate layer.

Images