Memory wafer and method of manufacturing a memory wafer

Abstract

Increase the proportion of qualified chips on a wafer. A storage wafer of one embodiment has: a first semiconductor (71W); a first element layer (72W) provided on an upper surface of the first semiconductor; a first pad (11a) provided on an upper surface of a first region of the first element layer; a second pad (11a) provided on an upper surface of a second region of the first element layer different from the first region; an adhesive film (73) provided on an upper surface of the second region of the first element layer including the second pad; a second semiconductor (74) provided on an upper surface of the adhesive film; a second element layer (75) provided on an upper surface of the second semiconductor; and a third pad (11b) provided on an upper surface of the second element layer.

Description

Technical Field

[0001] The embodiments relate to memory wafers and methods for manufacturing memory wafers. Background Technology

[0002] It is known that a wafer is provided with multiple NAND flash memory wafers as semiconductor memory and a probe station for contacting the pad electrodes on the wafer with probe electrodes.

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: U.S. Patent Application Publication No. 2014 / 0181376 Summary of the Invention

[0006] The problem that the invention aims to solve

[0007] This increases the proportion of qualified chips on the wafer.

[0008] Methods used to solve problems

[0009] The memory system of this embodiment includes: a first semiconductor; a first element layer disposed on the upper surface of the first semiconductor; a first pad disposed on the upper surface of a first region of the first element layer; a second pad disposed on the upper surface of a second region of the first element layer different from the first region; an adhesive film disposed on the upper surface of the second region of the first element layer including the second pad; a second semiconductor disposed on the upper surface of the adhesive film; a second element layer disposed on the upper surface of the second semiconductor; and a third pad disposed on the upper surface of the second element layer. The first element layer includes a first memory chip cell electrically connected to the first pad and a second memory chip cell electrically connected to the second pad. The second element layer includes an element electrically connected to the third pad and electrically insulated from the first and second pads. Attached Figure Description

[0010] Figure 1 This is a block diagram used to explain the configuration of the storage system according to the first embodiment.

[0011] Figure 2 This is a side view used to explain the structure of the probe station according to the first embodiment.

[0012] Figure 3 This is a top view used to explain the configuration of the probe card according to the first embodiment.

[0013] Figure 4 This is a top view used to explain the configuration of the memory wafer according to the first embodiment.

[0014] Figure 5 It is along Figure 4 A cross-sectional view of a storage wafer with VV lines.

[0015] Figure 6 This is a block diagram used to illustrate the connection between the probe station and the memory wafer according to the first embodiment.

[0016] Figure 7 This is a block diagram used to explain the configuration of the NAND chip cell according to the first embodiment.

[0017] Figure 8 This is a circuit diagram used to explain the configuration of the memory cell array according to the first embodiment.

[0018] Figure 9 This is a cross-sectional view used to explain the configuration of the memory cell array according to the first embodiment.

[0019] Figure 10 This is a flowchart used to explain the method for manufacturing a memory wafer according to the first embodiment.

[0020] Figure 11 This is a cross-sectional view of the second wafer used to explain the cutting process of the second wafer according to the first embodiment.

[0021] Figure 12 This is a cross-sectional view of the second wafer used to explain the cutting process of the second wafer according to the first embodiment.

[0022] Figure 13 This is a cross-sectional view of the second wafer used to explain the cutting process of the second wafer according to the first embodiment.

[0023] Figure 14 This is a cross-sectional view of the second wafer used to explain the cutting process of the second wafer according to the first embodiment.

[0024] Figure 15 This is a schematic diagram illustrating the mounting process of the NAND chip cell according to the first embodiment.

[0025] Figure 16 This is a cross-sectional view used to illustrate the configuration of the memory wafer according to the second embodiment.

[0026] Figure 17 This is a flowchart used to explain the method for manufacturing a memory wafer according to the second embodiment.

[0027] Figure 18This is a top view used to explain the configuration of the memory wafer according to the third embodiment.

[0028] Figure 19 This is a flowchart used to explain the method for manufacturing a memory wafer according to the third embodiment.

[0029] Figure 20 This is a cross-sectional view used to illustrate the configuration of the memory wafer according to the fourth embodiment.

[0030] Figure 21 This is a flowchart used to explain the method for manufacturing a memory wafer according to the fourth embodiment.

[0031] Figure 22 This is a cross-sectional view used to illustrate the configuration of the memory wafer involved in the first modified example.

[0032] Figure 23 This is a cross-sectional view used to illustrate the structure of the memory wafer involved in the second variation.

[0033] Figure 24 This is a flowchart illustrating the reassembly process in the memory wafer involved in the third variation. Detailed Implementation

[0034] Hereinafter, embodiments will be described with reference to the accompanying drawings. In this description, components having the same function and configuration will be given common reference numerals. Furthermore, when multiple components with common reference numerals are to be distinguished, a subscript will be assigned to the common reference numerals for differentiation. Additionally, when multiple components do not need to be particularly distinguished, only common reference numerals may be assigned to the multiple components without assigning a subscript.

[0035] 1. First Implementation Method

[0036] The storage system according to the first embodiment will be described. Hereinafter, a storage system having a storage wafer and a probe station will be described, wherein the storage wafer has a plurality of NAND chip cells (as storage devices for NAND flash memory), and the probe station includes a probe card on which a plurality of NAND controller chips are mounted, and is configured to electrically connect the storage wafer to the probe card in physical contact.

[0037] 1.1 Composition

[0038] The configuration of the storage system according to the first embodiment will be described.

[0039] 1.1.1 Composition of the storage system

[0040] First, use Figure 1A summary description of the configuration of the storage system according to the first embodiment will be given. Figure 1 As shown, the storage system 1 operates based on instructions from the host device 2. The storage system 1 includes a probe station 3, a wafer transporter 4, and a wafer stocker 5.

[0041] The probe station 3 includes a probe card 20 and a control unit 30, and is configured with a storage wafer 10 or a cleaning wafer 10c. The storage wafer 10 is an uncut wafer or a wafer to which rewiring has been performed, including multiple NAND flash memory chips (hereinafter referred to as "NAND chip cells" - not shown) arranged in chip units, and has multiple pad electrodes 11 disposed on its surface. The cleaning wafer 10c is used in a cleaning process, which is a process to improve the electrical characteristics of the multiple probe electrodes 21 disposed on the probe card 20 when the electrodes deteriorate.

[0042] The probe card 20 includes a plurality of probe electrodes 21. The plurality of probe electrodes 21 are electrically connected to a memory controller (hereinafter referred to as "NAND controller chip"). Not shown) of a chip unit mounted on the probe card 20.

[0043] The control unit 30 includes, for example, a temperature control system 31, a drive control system 32, and an interface control system 33, which control the overall operation of the probe station 3.

[0044] The temperature control system 31 controls the temperature environment exposed to the probe card 20 and the storage wafer 10 or cleaning wafer 10c within the probe station 3. In this embodiment, for example, the temperature control system 31 controls the temperature of the probe card 20 and the storage wafer 10 or cleaning wafer 10c to not change from a predetermined temperature.

[0045] The drive control system 32 has a mechanism that enables the storage wafer 10 to be freely displaced in three dimensions relative to the probe card 20. Furthermore, the drive control system 32 has the function of controlling this mechanism to bring a plurality of pad electrodes 11 on the storage wafer 10 into contact with a plurality of probe electrodes 21 on the corresponding probe card 20.

[0046] The interface control system 33 controls the communication between the host device 2 and the probe card 20. Furthermore, based on the control results of this communication, the interface control system 33 controls the temperature control system 31, the drive control system 32, and the wafer transporter 4, etc.

[0047] The wafer transporter 4 has the function of transporting and storing wafers 10 or cleaning wafers 10c between the probe station 3 and the wafer storage library 5.

[0048] The wafer storage library 5 stores multiple storage wafers 10 that are not set on the probe station 3, as well as cleaning wafers 10c.

[0049] 1.1.2 Composition of the probe station

[0050] Next, use Figure 2 The configuration of the probe station of the storage system according to the first embodiment will be described.

[0051] Figure 2 This is a side view schematically showing the configuration of the probe station 3 with the storage wafer 10 set thereon. Hereinafter, the setting surface of the storage wafer 10 relative to the probe station 3 will be defined as the XY plane, and the direction perpendicular to the XY plane and from the storage wafer 10 toward the probe card 20 will be defined as the Z direction (or the upward direction). Furthermore, the surface of the storage wafer 10 that faces the probe card 20 will also be referred to as the "surface" or "upper surface" of the storage wafer 10.

[0052] like Figure 2 As shown, the probe station 3 includes a base 41, multiple worktables 42 (42-1, 42-2, and 42-3), a wafer chuck 43, a head worktable 44, a stiffener 45, a retainer 46, a fixture 47, and a support 48.

[0053] A worktable 42-1 is mounted on the upper surface of the base 41 via an X-displacement mechanism (not shown). The worktable 42-1 is configured to move freely relative to the base 41 in the X direction via the X-displacement mechanism. A worktable 42-2 is mounted on the upper surface of the worktable 42-1 via a Y-displacement mechanism (not shown). The worktable 42-2 is configured to move freely relative to the worktable 42-1 in the Y direction via the Y-displacement mechanism. A worktable 42-3 is mounted on the upper surface of the worktable 42-2 via a Zθ-displacement mechanism (not shown). The worktable 42-3 is configured to move freely relative to the worktable 42-2 in the Z direction via the Zθ-displacement mechanism and can rotate freely in the XY plane. Worktables 42-1 to 42-3 are included in the drive control system 32 and are part of a mechanism that enables the storage wafer 10 to be freely displaced relative to the probe card 20.

[0054] A wafer chuck 43 is disposed on the upper surface of the stage 42-3 to hold the stored wafer 10. The wafer chuck 43 includes, for example, a temperature sensor and a heater and cooler (not shown) capable of controlling the temperature of the stored wafer 10. A temperature control system 31 controls the heater and cooler based on information from the temperature sensor, thereby controlling the temperature of the stored wafer 10 via the wafer chuck 43. The temperature sensor, heater, and cooler are included in the temperature control system 31.

[0055] The head stage 44, for example, has a ring shape and is supported above the wafer chuck 43 by a support column 48. In the space inside the ring of the head stage 44, a ring-shaped reinforcing plate 45 and a retainer 46 are respectively provided, supported by the head stage 44. The reinforcing plate 45 is disposed on the upper part of the probe card 20 and clamps the probe card 20 between itself and the retainer 46. The retainer 46 supports the probe card 20 in the space inside the ring of the retainer 46. The probe card 20 is fixed to the reinforcing plate 45 and the retainer 46 by a fixing device 47, thereby fixing its position relative to the wafer chuck 43 (and the storage wafer 10 on the wafer chuck 43) and suppressing displacement caused by thermal expansion, etc.

[0056] In addition, a camera (not shown) may be provided on the head stage 44 for detecting representative positions (e.g., the outer edge of the wafer, alignment marks provided on the wafer, etc.) on the storage wafer 10 (or cleaning wafer 10c). The drive control system 32 can more accurately identify the reference position based on the information from the camera, enabling precise alignment.

[0057] Figure 3 This is a top view of the probe card 20 fixed inside the probe station 3.

[0058] like Figure 3 As shown, the probe card 20 has its outer periphery fixed by a ring-shaped reinforcing plate 45, and multiple NAND controller chips 200 are provided in the central part of the probe card 20. In the storage system 1 according to this embodiment, the probe station 3 is maintained at a substantially constant temperature by a temperature control system 31, preventing large temperature variations. Therefore, the displacement of the probe card 20 due to thermal expansion is suppressed to a small amount. Thus, the reinforcing plate 45 only needs to fix the outer periphery of the probe card 20 to cope with this displacement, eliminating the need to fix the central part of the probe card 20. This allows for the mounting of more chips on the probe card 20.

[0059] Figure 4 This is a top view of the storage wafer 10 held by the wafer chuck 43.

[0060] like Figure 4 As shown, the storage wafer 10 includes a plurality of NAND chip cells 100 and at least one NAND chip cell 100'. The NAND chip cells 100 and 100' have identical configurations and functions, each functioning as the smallest unit of storage device capable of being controlled based on control signals from the NAND controller chip 200. Additionally, a plurality of alignment marks 12 are provided in areas on the storage wafer 10 where NAND chip cells 100 and 100' are not located.

[0061] Multiple NAND chip cells 100 are arranged in a matrix on the upper surface of the storage wafer 10 when viewed from above. On the other hand, a NAND chip cell 100' is disposed on the upper surface of one of the multiple NAND chip cells 100 arranged in the matrix. The NAND chip cell 100' is selectively disposed on the upper surface of NAND chip cells 100 that are determined to be defective during the manufacturing of the storage wafer 10. Therefore, the number and position of the NAND chip cells 100' disposed on the storage wafer 10 will vary for each storage wafer 10.

[0062] use Figure 5 The cross-sectional structure of the portion of the memory wafer 10, including the NAND chip cell 100 and 100', will be further described. Figure 5 It is along Figure 4 A cross-sectional view of the VV line storage wafer 10.

[0063] like Figure 5 As shown, the memory wafer 10 includes a semiconductor substrate 71W, a device layer 72W, a die attach film (DAF) 73, a semiconductor layer 74, and a device layer 75.

[0064] The semiconductor substrate 71W serves as the base material for multiple NAND chip cells 100, and may contain, for example, silicon (Si). An element layer 72W is formed on the upper surface of the semiconductor substrate 71W. Various circuits functioning as NAND flash memory are formed on the semiconductor substrate 71W and the element layer 72W. Thus, multiple NAND chip cells 100 arranged in a matrix are formed across the upper surface of the storage wafer 10 by the element layer 72W, which is a continuous film. Multiple pad electrodes 11a are formed on the upper surface of each of the multiple NAND chip cells 100. Therefore, each of the multiple NAND chip cells 100 is configured to communicate with the probe card 20 via probe electrodes 21.

[0065] On the upper surface of a defective NAND chip cell 100 among the multiple NAND chip cells 100, a structure in which an adhesive film 73, a semiconductor layer 74, and a component layer 75 are sequentially stacked is provided. That is, the multiple pad electrodes 11a provided on the upper surface of the defective NAND chip cell 100 are sealed by the adhesive film 73.

[0066] The adhesive film 73 has the function of bonding the component layer 72W and the semiconductor layer 74 together. The adhesive film 73 is non-conductive and can electrically insulate the pad electrodes 11a on the component layer 72W from the semiconductor layer 74.

[0067] Semiconductor layer 74 is the substrate of NAND chip cell 100', and may contain, for example, silicon (Si). Component layer 75 is disposed on the upper surface of semiconductor layer 74. Various circuits functioning as NAND flash memory are formed on semiconductor layer 74 and component layer 75, for example. Semiconductor layer 74 and component layer 75 have a configuration equivalent to the portion of semiconductor substrate 71W and component layer 72W that functions as a NAND chip cell 100. That is, a NAND chip cell 100' is formed from semiconductor layer 74 and component layer 75.

[0068] Multiple pad electrodes 11b are formed on the upper surface of the NAND chip cell 100'. Thus, the NAND chip cell 100' is configured to communicate with the probe card 20 via the probe electrode 21, replacing the NAND chip cell 100 directly below it.

[0069] The NAND chip cell 100' is formed, for example, by cutting from a semiconductor substrate (not shown) different from the semiconductor substrate 71W, similar to the plurality of NAND chip cells 100 formed on the semiconductor substrate 71W. In the following description, the semiconductor substrate 71W on which the plurality of NAND chip cells 100 are formed is referred to as the "first wafer", and the semiconductor substrate different from the semiconductor substrate 71W on which the plurality of NAND chip cells 100' are formed is referred to as the "second wafer", and the distinction is made as needed.

[0070] 1.1.3 Communication Functional Structure of Probe Station and Memory Wafer

[0071] Next, use Figure 6 The block diagram shown illustrates the structure of the communication function between the probe station and the memory wafer according to the first embodiment. Figure 6 The diagram shows an example of the connection relationship when the probe card 20 is electrically connected to the storage wafer 10 by the drive control system 32.

[0072] like Figure 6 As shown, the interface control system 33 is connected to the host device 2 via a host bus. The host device 2 is, for example, a personal computer, and the host bus is, for example, compliant with PCIe (PCI Express). TM (Peripheral component interconnect express) bus.

[0073] The interface control system 33 includes, for example, a host interface circuit 331, a CPU (Central Processing Unit) 332, a ROM (Read Only Memory) 333, and a RAM (Random Access Memory) 334. The functions of each part 331-334 of the interface control system 33, as described below, can be implemented through any combination of hardware structure or hardware resources and firmware.

[0074] The host interface circuit 331 is connected to the host device 2 via the host bus, and transmits commands and data received from the host device 2 to any one of the multiple NAND controller chips 200 according to the instructions from the CPU 332. In addition, in response to commands from the CPU 332, it transmits data from the NAND controller chip 200 to the host device 2.

[0075] CPU 332 primarily controls the interfaces related to data transmission within probe station 3. For example, when CPU 332 receives a write command from host device 2, it determines the NAND controller chip 200 that controls the write process and transmits the write data DAT to the determined NAND controller chip 200. The same applies to read and delete processes. Additionally, CPU 332 performs various controls on other control systems within probe station 3 (temperature control system 31 and drive control system 32).

[0076] ROM333 stores firmware used to control the temperature control system 31, the drive control system 32, and multiple NAND controller chips 200.

[0077] RAM 334 is, for example, DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory), temporarily holding write data DAT and read data DAT. Additionally, RAM 334 is used as a working area for CPU 332, maintaining various management tables, etc. An example of a management table could be a probe management table that manages information related to how many times the probe electrode 21 has been contacted and removed from the pad electrode 11 on the storage wafer 10.

[0078] Multiple NAND controller chips 200 on probe card 20 are electrically connected to multiple NAND chip units 100 in storage wafer 10.

[0079] exist Figure 6In this example, k NAND chip cells 100_1 to 100_k are connected in parallel with a NAND controller chip 200. The multiple NAND controller chips 200, each connected to one of the k NAND chip cells 100_1 to 100_k, control the k NAND chip cells 100_1 to 100_k in parallel based on instructions from the interface control system 33.

[0080] Among them, several of the k NAND chip cells 100_1 to 100_k connected to the NAND controller chip 200 can be replaced by NAND chip cell 100'. Figure 6 In the example, it is shown that in one of the two NAND controller chips 200 illustrated, each of the k NAND chip cells 100_1 to 100_k is not replaced by NAND chip cell 100'. Additionally, it is shown that in the other of the two NAND controller chips 200 illustrated, NAND chip cell 100_2 out of the k NAND chip cells is replaced by NAND chip cell 100'_2. In this case, the NAND chip cell 100_2 replaced by NAND chip cell 100'_2 is not connected to the NAND controller chip 200.

[0081] The NAND controller chip 200 is, for example, a SoC (System-on-a-chip) with FPGA (Field Programmable Gate Array) functionality, and includes a CPU 210, ROM 220, RAM 230, ECC circuitry 240, and NAND interface circuitry 250. The functions of each part 210-250 of the NAND controller chip 200, as described below, can be implemented using either a hardware structure or a combination of hardware resources and firmware.

[0082] CPU 210 controls the overall operation of NAND controller chip 200. For example, when CPU 210 receives a write command from host device 2 via interface control system 33, it issues a write command to NAND interface circuit 250 in response. The same applies to read and delete processes. In addition, CPU 210 performs various processes for controlling NAND chip cells 100 and 100'.

[0083] ROM220 stores firmware and other data used to control NAND chip cells 100 and 100'.

[0084] RAM230, for example, is DRAM, which temporarily holds data written and read (DAT). Additionally, RAM230 is also used as a working area for CPU210, holding various management tables, etc.

[0085] The ECC circuit 240 performs error detection and correction processing related to the data stored in the NAND chip cells 100 and 100'. Specifically, the ECC circuit 240 generates an error correction symbol during data writing and assigns it to the written data DAT, and decodes it during data reading to detect the presence or absence of error bits. Furthermore, when an error bit is detected, its position is determined, and the error is corrected. Error correction methods include, for example, hard bit decoding and soft bit decoding. Hard bit decoding symbols used for hard bit decoding can include, for example, BCH (Bose-Chaudhuri-Hocquenghem) symbols, RS (Reed-Solomon) symbols, etc., while soft bit decoding symbols used for soft bit decoding can include, for example, LDPC (Low Density Parity Check) symbols, etc.

[0086] The NAND interface circuit 250 is connected to NAND chip cells 100 and 100' via the NAND bus, controlling communication with NAND chip cells 100 and 100'. Furthermore, it outputs various signals to NAND chip cells 100 and 100' based on commands received from the CPU 210. During write processing, it transmits write commands issued by the CPU 210 and write data DAT from RAM 230 as input / output signals to NAND chip cells 100 and 100'. During read processing, it transmits read commands issued by the CPU 210 as input / output signals to NAND chip cells 100 and 100', and receives data DAT read from NAND chip cells 100 and 100' as input / output signals, transmitting it to RAM 230.

[0087] Based on the above configuration, all NAND chip cells 100 and 100' disposed within the storage wafer 10 can be controlled in parallel.

[0088] 1.1.4 Composition of NAND Chip Units

[0089] Next, the configuration of the NAND chip cell according to the first embodiment will be described.

[0090] Figure 7 This is a block diagram illustrating the functional structure of the NAND chip cell according to the first embodiment. Figure 7 In, it is shown Figure 6 The details pertain to the connection relationship between a NAND controller chip 200 and a NAND chip cell 100 or 100'. Specifically, regarding... Figure 7 The connection relationships shown do not apply to NAND chip cells 100 that are replaced by NAND chip cells 100' and are not connected to the NAND controller chip 200.

[0091] like Figure 7 As shown, NAND chip units 100 and 100' are connected to the NAND controller chip 200 in the probe card 20 via the NAND bus. The NAND bus is a transmission path for transmitting and receiving signals conforming to the NAND interface, including probe electrodes 21 and pad electrodes 11.

[0092] Specific examples of signals used in a NAND interface include the chip enable signal CEn, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, read enable signal REn, idle / busy signal RBn, and input / output (I / O) signals. In the following explanation, when a signal name is appended with "n", it indicates negative logic; that is, it signifies that the signal is asserted at an "L" (Low) level.

[0093] The signal CEn is used to enable NAND chip cells 100 and 100', and is asserted at an "L" level. Signals CLE and ALE notify NAND chip cells 100 and 100' that the input I / O signals are CMD and ADD, respectively. The signal WEn is asserted at an "L" level to read the input I / O signals from NAND chip cells 100 and 100'. The signal REn is also asserted at an "L" level and is used to read the output I / O signals from NAND chip cells 100 and 100'. The idle / busy signal RBn indicates whether NAND chip cells 100 and 100' are in an idle state (e.g., able to receive commands from NAND controller chip 200) or a busy state (e.g., unable to receive commands from NAND controller chip 200), with an "L" level indicating a busy state. The input / output I / O signals are, for example, 8-bit signals. Furthermore, the input / output signal I / O is the entity of the data sent and received between the NAND chip cell 100 and the NAND controller chip 200, including instruction CMD, address ADD, and data DAT such as write data and read data.

[0094] Additionally, NAND chip cells 100 and 100' are supplied with voltages VCC and VSS from the NAND controller chip 200 via a connection between probe electrodes 21 and pad electrodes 11. Voltages VCC and VSS are the power supply voltage and ground voltage in NAND chip cells 100 and 100', respectively.

[0095] NAND chip cells 100 and 100' have a memory cell array 110 and peripheral circuitry 120.

[0096] The storage cell array 110 includes multiple block BLKs, each comprising multiple non-volatile storage cells corresponding to rows and columns. A block BLK is, for example, a unit for data deletion. Figure 7 The diagram illustrates four blocks BLK0 to BLK3 as an example. Furthermore, the memory cell array 110 stores data assigned by the NAND controller chip 200.

[0097] The peripheral circuitry 120 includes an I / F circuit 121, an instruction register 126, an address register 127, a data register 128, a driver 129, a line decoder 130, a sense amplifier module 131, and a sequencer 132.

[0098] The I / F circuit 121 is a circuit group inside the NAND chip cell 100 and 100' that mainly manages the interface between the pad electrode 11 and other peripheral circuits 120, and includes an input / output circuit 122, a logic control circuit 123, a timing adjustment circuit 124, and an ECC circuit 125.

[0099] Input / output circuit 122 transmits and receives I / O signals with NAND controller chip 200. Upon receiving an I / O signal from NAND controller chip 200, input / output circuit 122 categorizes the I / O signal into instruction (CMD), address (ADD), and data (DAT) based on information from logic control circuit 123. Input / output circuit 122 transfers instruction (CMD) to instruction register 126 and address (ADD) to address register 127. Furthermore, input / output circuit 122 transmits and receives write data and read data (DAT) from data register 128.

[0100] The logic control circuit 123 receives signals CEn, CLE, ALE, WEn, and REn from the NAND controller chip 200, and sends information used to identify the instruction CMD, address ADD, and data DAT within the signal I / O to the input / output circuit 122. Additionally, the logic control circuit 123 transmits signal RBn to the NAND controller chip 200 to notify the NAND controller chip 200 of the status of the NAND chip cells 100 and 100'.

[0101] The timing adjustment circuit 124, for example a latch circuit, is located between the pad electrode 11 and the input / output circuit 122 and the logic control circuit 123 to adjust the timing of various signals.

[0102] ECC circuit 125 is provided, for example, between input / output circuit 122 and instruction register 126, address register 127, and data register 128, to perform error detection and correction processing related to the data stored in NAND chip cells 100 and 100'. ECC circuit 125 has the same configuration as ECC circuit 240, and is configured to decode data encoded by ECC circuit 240. That is, during data writing, the write data DAT, for which error correction characters have been assigned by ECC circuit 240, is decoded to detect the presence or absence of error bits. Furthermore, when an error bit is detected, its position is determined, and the error is corrected. Similarly, during data reading, the read data DAT, for which error correction characters have been assigned by ECC circuit 240, is decoded to detect the presence or absence of error bits. Furthermore, when an error bit is detected, its position is determined, and after error correction, the read data DAT is re-encoded and sent to NAND controller chip 200.

[0103] Instruction register 126 holds the instruction CMD received from NAND controller chip 200. Address register 127 holds the address ADD received from NAND controller chip 200. This address ADD includes the block address BA and the page address PA. Data register 128 holds the write data DAT received from NAND controller chip 200 or the read data DAT received from sense amplifier module 131.

[0104] For the selected block BLK, driver 129 supplies voltage to line decoder 130 based on page address PA in address register 127.

[0105] The line decoder 130 selects any one of the blocks BLK0 to BLK3 based on the block address BA in the address register 127, and selects the word line in the selected block BLK.

[0106] The sensing amplifier module 131 reads data by sensing the threshold voltage of the memory cell transistors in the memory cell array 110 during data reading. Furthermore, it outputs the read data DAT to the NAND controller chip 200 via the data register 128. During data writing, the write data DAT received from the NAND controller chip 200 via the data register 128 is transmitted to the memory cell array 110.

[0107] The sequencer 132 controls the operation of the NAND chip cell 100 and 100' as a whole based on the instruction CMD held by the instruction register 126.

[0108] 1.1.5 Composition of Storage Cell Array

[0109] Next, the configuration of the aforementioned storage cell array 110 will be described.

[0110] Figure 8 This is a circuit diagram of any block BLK in the storage cell array 110.

[0111] like Figure 8 As shown, a block BLK includes, for example, four string units SU (SU0 to SU3). Furthermore, each string unit SU includes multiple NAND strings NS. The number of blocks within the storage cell array 110 and the number of string units within the block BLK are arbitrary.

[0112] Each NAND string NS includes, for example, eight memory cell transistors MT (MT0 to MT7) and select transistors ST1 and ST2. The memory cell transistors MT have a control gate and a charge storage film to retain data in a non-volatile manner. Furthermore, the memory cell transistors MT are connected in series between the source of select transistor ST1 and the drain of select transistor ST2.

[0113] The gates of the select transistors ST1 in each of the multiple NAND strings NS of each of the string units SU0 to SU3 are respectively connected to select gate lines SGD0 to SGD3. Conversely, the gates of the select transistors ST2 in each of the multiple NAND strings NS of each of the string units SU0 to SU3 are, for example, commonly connected to the select gate line SGS. Alternatively, the gates of the select transistors ST2 in each of the multiple NAND strings NS of each of the string units SU0 to SU3 may be connected to different select gate lines SGS0 to SGS3 for each string unit. Furthermore, the control gates of the memory cell transistors MT0 to MT7 in the multiple NAND strings NS within the same BLK are commonly connected to word lines WL0 to WL7.

[0114] Furthermore, the drains of the select transistors ST1 in the same column of multiple blocks BLK within the memory cell array 110 are all connected to the bit line BL (BL0 to BLm, where m is a natural number greater than 2). That is, the bit line BL connects the NAND strings NS in the same column among multiple blocks BLK. Also, the sources of multiple select transistors ST2 are all connected to the source line SL.

[0115] That is, a string cell SU is a collection of NAND strings NS connected to different bit lines BL and connected to the same select gate line SGD. A collection of memory cell transistors MT in a string cell SU that are commonly connected to the same word line WL is also called a cell unit CU (or memory cell group). Furthermore, a block BLK is a collection of multiple string cells SU that share the word line WL. Moreover, the memory cell array 110 is a collection of multiple blocks BLK that share the bit line BL.

[0116] Figure 9 This is a cross-sectional view of a block BLK, illustrating eight NAND strings NS arranged along the Y direction. The four groups of two NAND strings NS arranged along the Y direction from the eight NAND strings NS correspond to string units SU0, SU1, SU2, and SU3, respectively.

[0117] like Figure 9 As shown, multiple NAND strings NS are formed above the conductor 51, which functions as the source line SL. Specifically, above the conductor 51, there are sequentially stacked conductors 52 (serving as the select gate line SGS), eight layers of conductors 53-60 (serving as word lines WL0-WL7), and conductor 61 (serving as the select gate line SGD). An insulator (not shown) is formed between the stacked conductors. Conductors 52-61 are cut off between blocks BLK by an insulator SLT (not shown). Furthermore, conductor 61 is cut off between string cells SU by an insulator SHE (not shown). Thus, conductor 61 is shorter in the Y direction compared to conductors 52-60.

[0118] Furthermore, a columnar conductor 64 is formed, passing through these conductors 61-52 and reaching conductor 51. A tunnel insulating film 65, a charge storage film 66, and a bulk insulating film 67 are sequentially formed on the side of the conductor 64, from which memory cell transistors MT, select transistors ST1, and ST2 are formed. The conductor 64, for example, contains polysilicon and functions as a current path for the NAND string NS, becoming the region for forming the channels of each transistor. The tunnel insulating film 65 and the bulk insulating film 67, for example, contain silicon oxide (SiO2), and the charge storage film 66, for example, contains silicon nitride (SiN). Furthermore, a conductor 63, functioning as a bit line BL, is disposed above the conductor 64. The conductors 64 and 63 are electrically connected, for example, via a conductor 62, functioning as a contact plug. Figure 9 The example shows an example where four NAND strings NS, which correspond to string units SU0 to SU3 respectively, and a conductor 63 are electrically connected to eight NAND strings NS arranged along the Y direction.

[0119] The above configuration has multiple NAND strings NS arranged in the X direction, forming a block BLK. Furthermore, a memory cell array 110 is formed by arranging multiple such blocks BLK along the Y direction.

[0120] 1.2 Manufacturing Method

[0121] Next, the method for manufacturing a memory wafer according to the first embodiment will be described.

[0122] 1.2.1 Flowchart

[0123] Figure 10 This is a flowchart illustrating the method for manufacturing a memory wafer according to the first embodiment. Figure 10 The diagram illustrates a method for manufacturing a memory wafer 10 using a predetermined first wafer for forming a plurality of NAND chip cells 100 and a predetermined second wafer for forming a plurality of NAND chip cells 100'.

[0124] like Figure 10 As shown, in step ST10, multiple chip cells are formed for the first wafer and the second wafer respectively. Specifically, multiple NAND chip cells 100 are formed on the first wafer, and multiple NAND chip cells 100' are formed on the second wafer.

[0125] In step ST20, by performing a process such as a probing procedure on each of the formed multiple chip cells, defective chip cells are detected on both the first and second wafers. This allows for the identification of NAND chip cells 100 that should be assembled as qualified NAND chip cells 100' from among the multiple NAND chip cells 100 on the first wafer. The qualification of a NAND chip cell can be determined, for example, based on predetermined conditions such as whether the capacity of the memory capable of performing normal write and read operations is above a threshold.

[0126] In step ST30, the second wafer is diced, separating the multiple NAND chip cells 100' independently. The NAND chip cells 100' that were deemed qualified in step ST20 from the independently separated NAND chip cells 100' are extracted for use in subsequent steps.

[0127] In step ST40, qualified NAND chip cells 100' cut from the second wafer are assembled onto the upper surface of defective NAND chip cells 100 formed in a plurality of chip cells 100 on the first wafer.

[0128] The manufacturing of storage wafer 10 is completed through the above processes.

[0129] 1.2.2 Cutting Process

[0130] Next, use Figures 11-14 The dicing process in the manufacturing method of the memory wafer according to the first embodiment will be described. Figures 11-14 This is a cross-sectional view of the second wafer during the dicing process of the second wafer in the manufacturing of the memory wafer according to the first embodiment. The second wafer is, for example, a wafer using a silicon (Si)-containing semiconductor substrate 74W as the base material. Furthermore, in Figure 10 In step ST10, multiple NAND chip units 100' are formed by depositing a component layer 75W on the semiconductor substrate 74W. Figure 5 The semiconductor layer 74 and the element layer 75 mentioned above are portions of the semiconductor substrate 74W and the element layer 75W, respectively.

[0131] like Figure 11 As shown, a protective film 76W is attached to the upper surface of the component layer 75W. This covers the multiple exposed pad electrodes 11b on the upper surface, protecting the multiple NAND chip cells 100'. Then, the back side of the semiconductor substrate 74W is ground. Thus, the semiconductor substrate 74W achieves thin-film fabrication while maintaining planarity.

[0132] Next, as Figure 12 As shown, an adhesive film 73W is bonded to the back of the semiconductor substrate 74W. Regarding the adhesive film 73W, Figure 5 The adhesive film 73 mentioned above is a portion of the adhesive film 73W.

[0133] Next, as Figure 13 As shown, the back side of the adhesive film 73W is adhered to the upper surface of the ring tape RT, which secures the second wafer. The ring tape RT includes a substrate 77 and an adhesive film 78 adhered to the substrate 77. The substrate 77 is, for example, a plastic film, with its outer periphery supported by a ring frame (not shown). The adhesive film 78 has the property of securing the second wafer so that the NAND chip cells 100', which are to be independently separated by a subsequent dicing process of the second wafer, do not scatter, and of enabling the diced NAND chip cells 100' to be easily peeled off in a subsequent pick-up process.

[0134] Next, as Figure 14 As shown, the second wafer is cut by the dicing ...

[0135] The cutting process for the second wafer is now complete after the above steps.

[0136] Specifically, the back side of the adhesive film 73, after being peeled off from the adhesive film 78, is adhered to the upper surface of a defective NAND chip cell 100 on a separately prepared first wafer. This process manufactures... Figure 5 The storage wafer 10 shown.

[0137] 1.3 Effects of this implementation method

[0138] According to the first embodiment, the proportion of qualified chips on a wafer can be increased. (Using...) Figure 15 The effect is explained below.

[0139] Figure 15 This is a schematic diagram illustrating the assembly process of the NAND chip cell according to the first embodiment. Figure 15 As shown on the left, a component layer 72W is formed over the entire surface of the upper surface of the semiconductor substrate 71W in the same process. Thus, multiple NAND chip cells 100 are formed in the same process. Therefore, due to manufacturing deviations, qualified NAND chip cells 100-g and defective NAND chip cells 100-b may be formed at uncertain locations.

[0140] When multiple NAND chip cells 100 are used independently and separately on a chip-by-chip basis, defective NAND chip cells 100-b can be selected and removed. However, since the memory wafer 10 according to the first embodiment is used on a wafer-by-wafer basis, it is not possible to remove defective NAND chip cells 100-b from the qualified NAND chip cells 100-g for use. Therefore, there is a possibility that the number of qualified NAND chip cells 100 that can actually be used as memory is less than the total number of NAND chip cells 100 formed on the same wafer, which is not preferable.

[0141] According to the first embodiment, a qualified NAND chip cell 100'-g from a plurality of NAND chip cells 100' formed on another semiconductor substrate 74W is mounted on the upper surface of a defective NAND chip cell 100-b from a plurality of NAND chip cells 100 formed on a semiconductor substrate 71W. Thus, as... Figure 15 As shown on the right, the probe electrode 21 can access a qualified NAND chip cell 100' instead of a defective NAND chip cell 100. Therefore, the reduction in the yield of the memory wafer 10 can be suppressed in a simulated manner. Consequently, the proportion of qualified chips on the wafer can be increased.

[0142] 2. Second Implementation Method

[0143] Next, the storage system according to the second embodiment will be described.

[0144] In the first embodiment, the case of mounting a NAND chip cell 100' onto the upper surface of a defective NAND chip cell 100 was described. The second embodiment differs from the first embodiment in that the NAND chip cell 100' is mounted on the upper surface of an area where the defective NAND chip cell 100 has been removed. In the following description, configurations and manufacturing methods equivalent to those in the first embodiment will be omitted; instead, descriptions of configurations and manufacturing methods different from those in the first embodiment will be primarily provided.

[0145] 2.1 Composition of memory wafers

[0146] Figure 16 This is a cross-sectional view used to explain the structure of the memory wafer according to the second embodiment, corresponding to the first embodiment. Figure 5 .

[0147] like Figure 16 As shown, the semiconductor substrate 71W includes a first region and a second region different from the first region. The height of the upper surface of the second region is lower along the Z direction compared to the upper surface of the first region. A component layer 72W is disposed on the upper surface of the first region of the semiconductor substrate 71W. A plurality of NAND chip cells 100 are formed in the first region of the semiconductor substrate 71W and the component layer 72W. Figure 16 One of a plurality of NAND chip cells 100 is shown in the figure. A plurality of pad electrodes 11a are formed on the upper surface of each of the plurality of NAND chip cells 100.

[0148] A structure formed by sequentially stacking an adhesive film 73, a semiconductor layer 74, and a component layer 75 is provided on the upper surface of the second region of the semiconductor substrate 71W. The adhesive film 73 functions to bond the upper surface of the second region of the semiconductor substrate 71W to the semiconductor layer 74. Figure 16 The adhesive film 73 is represented as an insulator, but it does not necessarily have to be non-conductive.

[0149] NAND chip cells 100' are formed on semiconductor layer 74 and device layer 75. Multiple pad electrodes 11b are formed on the upper surface of device layer 75. The configuration of semiconductor layer 74, device layer 75, and pad electrodes 11b is similar to... Figure 5 The semiconductor layer 74, the component layer 75, and the pad electrode 11b are identical in structure.

[0150] Specifically, it is desirable that the height difference between the pad electrode 11a in the Z direction on the upper surface of component layer 72W and the height difference between the pad electrode 11b in the Z direction on the upper surface of component layer 75 is small, and even more desirable that the difference is "0" (i.e., the pad electrodes 11a and 11b are formed in the same plane).

[0151] 2.2 Manufacturing Method of Memory Wafers

[0152] Next, the method for manufacturing a memory wafer according to the second embodiment will be described.

[0153] Figure 17 This is a flowchart illustrating the method for manufacturing a memory wafer according to the second embodiment, corresponding to the method in the first embodiment. Figure 10 .exist Figure 17 In China, Figure 10 Step ST25 is added between steps ST20 and ST30, and step ST40A is included instead of step ST40.

[0154] like Figure 17 As shown, due to steps ST10 and ST20 and Figure 10 Since they are the same, the explanation is omitted.

[0155] In step ST25, defective NAND chip cells 100 formed by laser on the first wafer are selectively removed, for example, by irradiation. As a result, portions of the pad electrodes 11a, the element layer 72W, and the semiconductor substrate 71W in the region (second region) on the first wafer where the defective NAND chip cells 100 are formed are removed. Consequently, the height of the upper surface of the second region of the first wafer becomes lower than the height of the upper surface of the first region.

[0156] In step ST30, the second wafer is diced, and multiple NAND chip cells 100' are separated independently. The NAND chip cells 100' that were determined to be qualified in step ST20 are extracted from the multiple independently separated NAND chip cells 100' and used in subsequent steps.

[0157] In step ST40A, qualified NAND chip cells 100' cut from the second wafer are assembled onto the upper surface of the second region of the first wafer.

[0158] The manufacturing of storage wafer 10 is completed through the above processes.

[0159] 2.3 Effects of this implementation method

[0160] According to the second embodiment, defective NAND chip cells 100 among the plurality of NAND chip cells 100 formed on the semiconductor substrate 71W are selectively removed from the semiconductor substrate 71W. Furthermore, qualified NAND chip cells 100' cut from the semiconductor substrate 74W are assembled onto the upper surface of the second region of the semiconductor substrate 71W from which the defective NAND chip cells 100 have been selectively removed. As a result, NAND chip cells 100 not accessed by the probe electrode 21 connected to the probe card 20 are removed, enabling height alignment of the plurality of NAND chip cells 100 and 100' on the storage wafer 10 along the Z direction. Therefore, during the probe card 20 inspection process, it is possible to avoid situations where the distance to the probe electrode 21 differs between the NAND chip cells 100 and NAND chip cells 100', reducing the load on the probe card 20 during the inspection process.

[0161] 3. Third Implementation Method

[0162] Next, the storage system according to the third embodiment will be described.

[0163] The third embodiment differs from the first and second embodiments in that a qualified chip cell having a different function from the NAND chip cell is assembled onto the upper surface of the defective NAND chip cell 100. In the following description, the configuration and manufacturing method equivalent to those in the first embodiment will be omitted, and the configuration and manufacturing method different from those in the first embodiment will be described in detail.

[0164] 3.1 Composition of memory wafers

[0165] Figure 18 This is a top view illustrating the configuration of the memory wafer according to the third embodiment, corresponding to the first embodiment. Figure 4 .

[0166] like Figure 18 As shown, the storage wafer 10 includes a plurality of NAND chip cells 100 and at least one chip cell 100". The NAND chip cells 100 and the chip cell 100" have different configurations and functions.

[0167] Specifically, for example, chip cell 100” can be a memory device other than NAND flash memory such as DRAM or SRAM, and can be configured similarly to NAND chip cell 100 to be controllable based on control signals from NAND controller chip 200. Alternatively, chip cell 100” can also be NAND controller chip 200 that controls NAND chip cell 100 via probe card 20. Furthermore, chip cell 100” can include any circuitry that complements the functionality of NAND flash memory, such as FPGA, PCIe switches, relay circuits, arithmetic circuits, ECC circuits, and capacitors used for the control of storage system 1.

[0168] Multiple NAND chip cells 100 are arranged in a matrix on the upper surface of the storage wafer 10 when viewed from above. Additionally, a chip cell 100” is disposed at a predetermined position on the upper surface of the NAND chip cell 100 among the multiple NAND chip cells 100 arranged in the matrix. Whether the NAND chip cell 100 formed at the predetermined position of the chip cell 100” is qualified or defective is predetermined. Therefore, the number and position of the chip cells 100” disposed on the storage wafer 10 do not change due to the storage wafer 10. Thus, the chip cell 100” is electrically isolated from other NAND chip cells 100 within the single storage wafer 10, but multiple NAND chip cells 100 within a predetermined area R including the predetermined position can be accessed by means of a probe card 20.

[0169] 3.2 Manufacturing method of memory wafers

[0170] Next, the method for manufacturing a memory wafer according to the third embodiment will be described.

[0171] Figure 19 This is a flowchart illustrating the method for manufacturing a memory wafer according to the third embodiment, corresponding to the method in the first embodiment. Figure 10 .exist Figure 19 In, replacement Figure 10 Steps ST10 and ST40 include steps ST10B and ST40B.

[0172] like Figure 19 As shown, in step ST10B, a plurality of first chip units are formed on the first wafer, and a second chip unit different from the first chip units is formed on the second wafer. Specifically, a plurality of NAND chip units 100 are formed on the first wafer, and a plurality of chip units 100 are formed on the second wafer.

[0173] In step ST20, for example, defective chip cells are detected on the first wafer and the second wafer by performing probing on the multiple chip cells formed.

[0174] In step ST30, the second wafer is diced, and multiple chip units 100” are separated independently. The chip units 100” that were determined to be qualified in step ST20 are extracted from the multiple chip units 100” that have been separated independently, and used in subsequent steps.

[0175] In step ST40B, qualified chip cells 100 cut from the second wafer are assembled onto the upper surface of NAND chip cells 100 at predetermined positions in a plurality of chip cells 100 formed on the first wafer.

[0176] The manufacturing of storage wafer 10 is completed through the above processes.

[0177] 3.3 Effects of this implementation method

[0178] According to the third embodiment, a chip cell 100 having a different function from the NAND chip cell 100 is mounted on the upper surface of the NAND chip cell 100 formed on the semiconductor substrate 71W. Therefore, a chip cell 100 having a function not present in the NAND chip cell 100 can be accessed relative to the NAND chip cell 100 via the probe card 20. Thus, the control load on the NAND chip cell 100 in the storage wafer 10 can be reduced.

[0179] Furthermore, the chip cell 100” is mounted on the upper surface of the NAND chip cell 100 formed at a predetermined position among a plurality of NAND chip cells 100. Thus, even if the storage wafer 10 is replaced with other storage wafers 10 in the wafer storage library 5, the configuration and structure of the probe card 20 and probe electrodes 21 can be changed to give the NAND chip cell 100” its function.

[0180] Furthermore, in the above example, the case where the chip cell 100” is mounted on the upper surface of the NAND chip cell 100 in the same manner as in the first embodiment is described, but it is not limited to this. For example, even if the chip cell 100” is mounted in the area where the NAND chip cell 100 is removed, just as in the second embodiment, the same effect as described above can be achieved.

[0181] 4. Fourth Implementation Method

[0182] Next, the storage system according to the fourth embodiment will be described.

[0183] In the first to third embodiments, it was described that the chip cells were mounted on the upper surface of a portion of the semiconductor substrate 71W on which a plurality of NAND chip cells 100 were formed. The fourth embodiment differs from the first to third embodiments in that all the chip cells included in the storage wafer 10 are mounted on the upper surfaces of different regions of the same support. In the following description, the configuration and manufacturing method equivalent to those in the first embodiment will be omitted; the description will mainly focus on the configuration and manufacturing method different from those in the first embodiment.

[0184] 4.1 Composition of memory wafers

[0185] Figure 20 This is a cross-sectional view illustrating the structure of the memory wafer according to the fourth embodiment, corresponding to the first embodiment. Figure 5 .

[0186] like Figure 20 As shown, the storage wafer 10 includes a support 81W, multiple adhesive films 70 and 73, multiple semiconductor layers 71 and 74, and multiple device layers 72 and 75.

[0187] The support 81W is a substrate used to support multiple NAND chip cells 100, and can be any support such as a silicon wafer, a glass substrate, or an annular strip. Furthermore, the support 81W does not have to be circular; it can be rectangular.

[0188] Multiple first structures and multiple second structures are respectively provided on the upper surfaces of several different regions of the support body 81W. Figure 20 In the diagram, one instance of the first construct and one instance of the second construct are shown.

[0189] The plurality of first structures each include an adhesive film 70, a semiconductor layer 71, and a device layer 72 stacked sequentially. The plurality of second structures each include an adhesive film 73, a semiconductor layer 74, and a device layer 75 stacked sequentially.

[0190] Multiple adhesive films 70 and 73 are respectively and separately disposed from each other. Among them, in Figure 20 In this context, multiple adhesive films 70 and 73 are represented as insulators, but they do not necessarily have to be non-conductive.

[0191] NAND chip cells 100 are formed on semiconductor layer 71 and device layer 72. NAND chip cells 100' are formed on semiconductor layer 74 and device layer 75. The configuration of NAND chip cells 100 and 100' is similar to... Figure 5 The NAND chip units 100 and 100' in the middle are identical in structure.

[0192] Multiple pad electrodes 11a are formed on the upper surface of each of the multiple component layers 72. Multiple pad electrodes 11b are formed on the upper surface of each of the multiple component layers 75. It is desirable that the multiple pad electrodes 11a and 11b on the support 81W have the same height along the Z direction.

[0193] 4.2 Manufacturing methods for memory wafers

[0194] Next, the method for manufacturing a memory wafer according to the fourth embodiment will be described.

[0195] Figure 21 This is a flowchart illustrating the method for manufacturing a memory wafer according to the fourth embodiment, corresponding to the method in the first embodiment. Figure 10 .exist Figure 21 In, replacement Figure 10 Steps ST30 and ST40 include steps ST30C and ST40C.

[0196] like Figure 21 As shown, due to steps ST10 and ST20 and Figure 10 They are equivalent, so the explanation is omitted.

[0197] In step ST30C, dicing is performed on the first wafer and the second wafer respectively, separating multiple NAND chip cells 100 and 100' independently. The NAND chip cells 100 and 100' that were determined to be qualified in step ST20 are extracted from the independently separated NAND chip cells 100 and 100' for use in subsequent steps.

[0198] In step ST40C, qualified NAND chip cells 100 and 100' cut from the first wafer and the second wafer respectively are assembled onto the upper surfaces of different regions of the support 81W.

[0199] The manufacturing of storage wafer 10 is completed through the above processes.

[0200] 4.3 Effects of this implementation method

[0201] According to the fourth embodiment, multiple NAND chip cells 100 are respectively mounted onto the same support 81W using different adhesive films 70. Additionally, multiple NAND chip cells 100' are respectively mounted onto the same support 81W using different adhesive films 73. Therefore, a predetermined number of NAND chip cells 100 and 100' manufactured from multiple wafers can be freely selected for mounting onto the support 81W. Thus, for example, it is possible to manufacture the memory wafer 10 by selecting only those NAND chip cells 100 and 100' with particularly high storage capacity (e.g., fewer bad blocks) from among the qualified NAND chip cells 100 and 100'.

[0202] Furthermore, in the above example, the case where NAND chip cell 100 and NAND chip cell 100' are mounted on the same support 81W as in the first embodiment has been described, but this is not a limitation. For example, NAND chip cell 100 and chip cell 100' having different functions from NAND chip cell 100' may also be mounted on the same support 81W as in the third embodiment. According to this configuration, since chip cell 100' is used without replacing qualified NAND chip cell 100, the space on the wafer can be used more efficiently.

[0203] 5. Variations, etc.

[0204] The first to fourth embodiments described above are not limited to the examples described above, and various modifications can be made.

[0205] 5.1 First Variation

[0206] For example, in the first to fourth embodiments described above, the case where the probe electrode 21 is in direct contact with the plurality of pad electrodes 11a and the plurality of pad electrodes 11b was described, but this is not a limitation. For example, for the plurality of pad electrodes 11a and the plurality of pad electrodes 11b, pads can be redistributed on the storage wafer 10 by rewiring. Moreover, the probe electrode 21 can be configured to contact the redistributed pads. In the following description, the configuration and manufacturing method equivalent to those in the first embodiment will be omitted, and the configuration and manufacturing method different from those in the first embodiment will be described mainly.

[0207] Figure 22 This is a cross-sectional view illustrating the structure of the memory wafer involved in the first modified example.

[0208] like Figure 22As shown, an insulating layer 82W is provided, for example, on the upper surface of the component layers 72W and 75. The insulating layer 82W contains, for example, polyimide and is configured to be aligned at the height of the upper surface of the NAND chip cell 100' above the NAND chip cell 100.

[0209] A plurality of contacts 83 are provided within the insulating layer 82W, each extending along the Z direction and contacting the upper surface of the corresponding pad electrode 11a. A conductive layer 84 is provided on the upper surface of each of the plurality of contacts 83. The conductive layer 84 extends, for example, along the Y direction and functions as a redistribution layer. A pad electrode 11ar is provided on the upper surface of each of the plurality of conductive layers 84, exposed above the insulating layer 82W.

[0210] Similarly, a plurality of contacts 85 are provided within the insulating layer 82W, each extending along the Z direction and contacting the upper surface of the corresponding pad electrode 11b. A conductive layer 86 is provided on the upper surface of each of the plurality of contacts 85. The conductive layer 86 extends, for example, along the Y direction and functions as a redistribution layer. A pad electrode 11br is provided on the upper surface of each of the plurality of conductive layers 86, exposed above the insulating layer 82W.

[0211] Pad electrodes 11ar and 11br are the pads obtained by reconfiguring the corresponding pad electrodes 11a and 11b on the memory wafer 10. Figure 22 In the example, for ease of illustration, pad electrodes 11ar and 11br are shown as one each.

[0212] By configuring it as described above, the positions of the pad electrodes 11ar and 11br, which can be observed from the probe card 20 side, can be reconfigured to any position on the storage wafer 10 that is independent of the positions of the NAND chip cells 100 and 100'.

[0213] Furthermore, by ensuring uniform height of the upper surface of the insulating layer 82W across the entire surface, the distances between the reconfigured pad electrodes 11ar and 11br and the probe electrode 21 can be aligned. This reduces the workload of the probing process.

[0214] 5.2 Second Variation

[0215] Furthermore, in the first modification described above, it was explained that separate independent pad electrodes 11ar were configured for each of the multiple pad electrodes 11a, and separate independent pad electrodes 11br were configured for each of the multiple pad electrodes 11b, but this is not a limitation. For example, the reconfigured pads can be shared among multiple NAND chip cells. In the following description, the configuration and manufacturing method equivalent to the first modification will be omitted, and the configuration and manufacturing method different from the first modification will be mainly described.

[0216] Figure 23 This is a cross-sectional view illustrating the structure of the memory wafer involved in the second modification example, corresponding to the first modification example. Figure 22 .

[0217] like Figure 23 As shown, a contact 87 extending in the Z direction is provided on the upper surface of each of the plurality of conductive layers 84. Additionally, a contact 88 extending in the Z direction is provided on the upper surface of each of the plurality of conductive layers 86.

[0218] A conductive layer 89 is provided in such a way that it is connected to the upper surfaces of the corresponding contacts 87 and 88. The conductive layer 89 extends, for example, along the X direction and functions as a second redistribution layer. A pad electrode 11abr is provided on the upper surface of the conductive layer 89, which is exposed above the insulating layer 82W.

[0219] By configuring it as described above, the pad electrodes 11abr can be shared among multiple NAND chip cells 100 and 100'. Therefore, when a common signal or power supply voltage is used among multiple NAND chip cells 100 and 100', the number of pads used can be reduced. Consequently, the number of probe electrodes 21 can be reduced, and the workload of the probing process can be decreased.

[0220] 5.3 Third Variation

[0221] Furthermore, in the first to fourth embodiments, as well as the first and second modifications described above, the chip cells were assembled during the manufacturing of the memory wafer. However, the timing of chip cell assembly is not limited to the manufacturing of the memory wafer. For example, chip cells may be reassembled (re-assembled) if a qualified chip cell becomes defective due to the use of the memory wafer. In the following description, the case of performing a re-assembly process on the memory wafer according to the first embodiment will be explained.

[0222] Figure 24 This is a flowchart illustrating the reassembly process of the memory wafer involved in the third variation.

[0223] like Figure 24 As shown, in step ST50, for example, using via Figure 10 The memory wafer 10 is manufactured by the manufacturing method shown. Due to continuous use, the memory wafer 10 deteriorates, and qualified NAND chip cells 100 or 100' may become defective.

[0224] In step ST60, for example, a probing process is performed to determine whether there are any defective NAND chip cells 100 or 100' formed in the NAND chip cell 100 formed on the storage wafer 10 and the assembled NAND chip cell 100'. If a defective NAND chip cell 100 or 100' is detected (step ST60; Yes), the process proceeds to step ST70; if no defective NAND chip cell 100 or 100' is detected (step ST60; No), the reassembly process ends.

[0225] In step ST70, it is determined whether to remove the defective NAND chip cell 100 or 100' from the storage wafer 10.

[0226] Without removing the defective NAND chip cell 100 or 100' from the storage wafer 10 (step ST70: No), the process proceeds to step ST80. In step ST80, a qualified NAND chip cell 100' is assembled on the upper surface of the defective NAND chip cell 100 or 100'.

[0227] On the other hand, if a defective NAND chip cell 100 or 100' is removed from the storage wafer 10 (step ST70: Yes), the process proceeds to step ST90. In step ST90, the defective NAND chip cell 100 or 100' is selectively removed, for example, by irradiating with a laser. Furthermore, if a defective NAND chip cell, such as NAND chip cell 100', is bonded by means of an adhesive film 73, the method is not limited to etching by irradiating with a laser; the NAND chip cell 100' can also be physically peeled off.

[0228] In step ST100, a qualified NAND chip cell 100' is reassembled on the upper surface of the area where the NAND chip cell 100 or 100' has been removed.

[0229] By performing the actions described above, whether or not defective NAND chip cells 100 or 100' are removed, all NAND chip cells 100 and 100' on the memory wafer 10 as observed from the probe card 20 can be made qualified. Therefore, even if NAND chip cells 100 or 100' deteriorate due to use of the memory wafer 10, by reassembling qualified NAND chip cells 100', a high proportion of qualified chips on the wafer can be maintained.

[0230] 5.4 Other

[0231] Several embodiments of the present invention have been described, but these embodiments are merely illustrative and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention as well as in the invention described in the technical solution and its equivalents.

Claims

1. A memory wafer, characterized by, have: The support is made of a glass substrate or an annular strip; The first adhesive film and the second adhesive film are respectively disposed separately on the upper surface of the support; The first semiconductor is disposed on the upper surface of the first adhesive film; The first element layer is disposed on the upper surface of the first semiconductor; The first pad is disposed on the upper surface of the first component layer; The second semiconductor is disposed on the upper surface of the second adhesive film; The second element layer is disposed on the upper surface of the second semiconductor; as well as The second pad is disposed on the upper surface of the second component layer. The first component layer includes a first memory chip unit electrically connected to the first pad. This first memory chip unit is a memory chip unit with a storage capacity of at least a specified capacity that is determined to be a qualified product from the memory chip units diced from the first wafer. The second element layer includes a second memory chip unit electrically connected to the second pad and electrically insulated from the first pad. The second memory chip unit is a memory chip unit whose storage capacity is determined to be qualified from memory chip units cut from a second wafer different from the first wafer, and is a memory chip unit with a storage capacity of more than a specified capacity.

2. A manufacturing method of a memory wafer, characterized by, have: The first plurality of memory chip units are formed on the first wafer; The second and a second plurality of memory chip units are formed on the second wafer; For each of the first plurality of memory chip units and the second plurality of memory chip units, determine whether the conditions are met; The first wafer is cut into each of the first plurality of memory chip units; The second wafer is cut into each of the second plurality of memory chip units; as well as The first plurality of cut memory chip units and the third plurality of memory chip units whose storage capacity is determined to meet the conditions and is above the specified capacity are assembled in a non-overlapping manner onto different areas on the upper surface of a support body made of a glass substrate or annular strip.

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