A register configuration control system suitable for radiation-resistant image sensors

Abstract

A register configuration control system suitable for an anti-irradiation image sensor belongs to the field of aerospace remote sensing technology. The present invention realizes the control of the control register of a large-target image sensor by area by designing a serial control multiplexer, an image sensor imaging area register configuration control bus, and an image sensor imaging area register configuration control module; the present invention realizes the synchronous refresh control of a complex register group by designing a shadow register module group control strategy; the present invention realizes the anti-single-particle upset of a large-target image sensor by designing a register code table triple-module redundancy control module and a register group layout gap control.

Description

Technical Field

[0001] The invention relates to a register configuration control system suitable for an anti-radiation image sensor, belonging to the technical field of aerospace remote sensing. Background Art

[0002] With the rapid development of microelectronics technology and the progress of aerospace technology, complementary metal oxide semiconductor (CMOS) integrated circuit (IC) technology has been widely used in various spacecraft and space platforms. Whether it is the control of equipment or the storage and processing of data, it depends to a large extent on integrated circuit technology, and the space environment in which these devices operate is a radiation environment full of various ion rays. When a spacecraft operates in such a radiation environment, the electronic devices in the equipment are easily affected by the radiation of various high-energy ions, causing the malfunction of its information processing system or even the damage of electronic devices, thereby greatly reducing the reliability of the spacecraft operation. How to improve the reliability of integrated circuits working in a radiation environment has become a research hotspot.

[0003] As a very important storage unit in integrated circuits, registers are particularly sensitive to radiation effects. The radiation resistance reinforcement of registers restricts the radiation resistance performance of digital storage and logic integrated circuits. Summary of the invention

[0004] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art, to provide a register configuration control system suitable for radiation-resistant image sensors, to solve the single particle flip problem of large-target image sensors, and to solve the problem of regional control of control registers of large-target image sensors.

[0005] The technical solution of the present invention is: a register configuration control system suitable for an anti-irradiation image sensor, comprising a reset control module, a clock signal equalization control module, a serial control multiplexer module, a serial control slave interface module, a register code table triple-module redundancy control module, a triple-module redundancy register module, a shadow register module, a status register module, a register refresh strategy control module, an external signal synchronization detection module, an image sensor imaging area register configuration control bus and an image sensor imaging area register configuration control module and an imaging signal generation control module;

[0006] The reset control module is used to receive the reset signal input from the external pin, refer to the external clock signal, generate the internal synchronous reset signal and the internal clock signal, and send them to the serial data read and write control slave interface module of the clock signal balance control module;

[0007] The clock signal balance control module performs driving capability and fan-out control on the internal synchronous reset signal and the internal clock signal, and sends out the internal synchronous reset signal and the internal clock signal after signal balance control;

[0008] The serial control multiplexer module completes the selection control of the external multi-channel serial control signals; receives the serial signal sent by the external serial control host interface, and sends the serial signal to the corresponding image sensor imaging area register configuration control module according to the internal register state; receives the serial input data signal fed back by the multiple image sensor imaging area register configuration control modules, and sends the serial input data signal to the serial control host interface according to the internal register state; and can perform read and write control on the external radiation-resistant hardened memory according to the internal register state;

[0009] The serial control slave interface module is used to detect the serial clock signal, serial enable signal and serial output data signal sent by the serial control multiplexer module under the control of the internal clock after the reset is completed, and send the register to the register code table triple-module redundancy control module after completing the register analysis;

[0010] The register code table triple-module redundancy control module is used to determine the special register state value after the register configuration is completed: if the triple-module redundancy control mode is turned on, the read and write control signals of the three register modules are generated according to the external input pulse trigger signal, and then the three read registers are operated with two out of three, and the results are output to the corresponding registers; if it is not the triple-module redundancy control mode, no operation is performed;

[0011] The triple-module redundant register module is configured with three independent register blocks, and the triple-module redundant control module outputs a read-write control timing according to the register code table to implement read-write control of the corresponding registers in the register block;

[0012] The shadow register module is used to cache the status register values ​​required by each circuit module;

[0013] The status register module is used to allocate address space to the status register of each circuit module and store the status value of each circuit module register;

[0014] The register refresh strategy control module is used to classify the state registers required by each circuit module, and classify and control the refresh of the state registers according to the type of the state registers;

[0015] The external signal synchronization detection module is used to detect the external input control signal and generate an internal control mark to complete the conversion from the external signal to the internal signal;

[0016] The image sensor imaging area register configuration control bus is used to serially control the multiplexer module to perform information exchange with the image sensor imaging area register configuration control module;

[0017] The image sensor imaging area register configuration control module is used to read, write and refresh the status register within the imaging area of ​​the image sensor;

[0018] The imaging signal generation control module generates the timing signal required by the imaging circuit, which is used to control the operation of the imaging circuit.

[0019] Furthermore, the clock signal balance control module receives the internal synchronous reset signal and the internal clock signal output by the reset control module, sets its driving capability and performs fan-out control, and sends out the internal synchronous reset signal and the internal clock signal after signal balance control.

[0020] Furthermore, the serial control multiplexer module receives a serial clock signal, a serial enable signal, a serial output data signal, a triple-mode redundant enable signal and a triple-mode redundant update signal sent by an external serial control host interface, and sends the serial clock signal, the serial enable signal, the serial output data signal, the triple-mode redundant enable signal and the triple-mode redundant update signal to the corresponding image sensor imaging area register configuration control module according to the internal register state; receives serial input data signals fed back by multiple image sensor imaging area register configuration control modules, and sends the serial input data signals to the serial control host interface according to the internal register state; and can write the image sensor imaging area register state value into the external anti-radiation hardened memory, or read the image sensor imaging area register state value from the external anti-radiation hardened memory according to the internal register state, and distribute it to the corresponding image sensor imaging area register configuration control module through the image sensor imaging area register configuration control bus.

[0021] Furthermore, the external input serial signal detected by the serial data read and write control slave interface module includes a serial clock signal, a serial enable signal and a serial input data signal.

[0022] Furthermore, if the serial data read and write control slave interface module detects that the serial enable signal is at a low level, it latches the serial input data signal into the shift register at the rising edge of the serial clock signal. If the serial enable signal is at a low level and contains 24 rising edges, then the reception of 24-bit data is completed, wherein the 24th to 10th bits are address bits, the 9th bit is a control flag, and the 8th to 1st bits are data bits; if the 9th bit is the control flag and is 1, then the external input 8-bit register value is received for the corresponding address; if it is 0, then the 8-bit internal register value is output to the serial output data signal.

[0023] Furthermore, the triple-module redundant register module is configured with three independent register blocks, and the three independent register blocks are the same register modules. When the image sensor layout is set, it is ensured that a gap greater than 0.5 mm is set between the three independent register blocks.

[0024] Furthermore, the shadow register module internally sets shadow register group 1 and shadow register group 2, the group 1 register is 8 bits wide, the group 2 register sets the register width according to the needs of each circuit module, and according to the status register type, the register group 1 is refreshed to the register group 2.

[0025] Furthermore, the address space includes four sections; the first section of the address space is allocated to the analog circuit; the second section of the address space is allocated to the timing control circuit; the third section of the address space is allocated to the register reservation; and the fourth section of the address space is allocated to the triple-module redundant refresh control.

[0026] Furthermore, the status register is classified into an immediate refresh register, a row refresh register, a frame refresh register and an external control refresh register; wherein the immediate refresh register is directly obtained from the shadow register, the row refresh register is obtained from the shadow register at the rising edge of the image sensor row signal, the frame refresh register is obtained from the shadow register at the rising edge of the image sensor frame signal, and the external control refresh register is obtained from the shadow register at the rising edge of the image sensor external trigger signal.

[0027] Furthermore, the image sensor imaging area register configuration control bus is set in multiple groups according to the size of the image sensor layout, and each group of buses includes a serial clock signal, a serial enable signal, a serial output data signal, a serial input data signal, a triple-mode redundant enable signal and a triple-mode redundant update signal;

[0028] The image sensor imaging area register configuration control module is configured with multiple groups according to the size of the image sensor layout, and each group of control modules includes a serial control slave interface module, a register code table triple-module redundancy control module, a triple-module redundancy register module, a shadow register module, a status register module, a register refresh strategy control module and an external signal synchronization detection module;

[0029] The imaging signal generation control module generates the timing signals required by the image sensor in real time according to the status register value, including pixel timing signals, exposure control signals, frame synchronization signals, line synchronization signals, quantization control signals and dynamically configurable control signals.

[0030] The advantages of the present invention compared with the prior art are:

[0031] (1) The present invention realizes the control of the control register of a large-area image sensor by different regions by designing a serial control multiplexer, an image sensor imaging region register configuration control bus, and an image sensor imaging region register configuration control module;

[0032] (2) The present invention implements synchronous refresh control of complex register groups by designing a shadow register module grouping control strategy;

[0033] (3) The present invention realizes the single-particle upset resistance of large-target image sensors through the register code table triple-module redundant control module and the register group layout design gap control. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 , 2 It is a schematic diagram of the system of the present invention;

[0035] Figure 3 It is a schematic diagram of the working process of the system of the present invention;

[0036] Figure 4 The serial control slave interface register of the present invention is written into the timing diagram;

[0037] Figure 5 The serial control slave interface register reads the timing diagram of the present invention;

[0038] Figure 6 It is a block diagram of controlling the analog circuit register update of the present invention;

[0039] Figure 7 This is a block diagram of controlling the digital circuit register update of the present invention. DETAILED DESCRIPTION

[0040] In order to better understand the above technical scheme, the technical scheme of the present application is described in detail below through the accompanying drawings and specific embodiments. It should be understood that the embodiments of the present application and the specific features in the embodiments are detailed descriptions of the technical scheme of the present application, rather than limitations on the technical scheme of the present application. In the absence of conflict, the embodiments of the present application and the technical features in the embodiments can be combined with each other.

[0041] The following is a further detailed description of a register configuration control system for an anti-irradiation image sensor provided by an embodiment of the present application in conjunction with the accompanying drawings. The specific implementation method may include (eg Figures 1 to 7As shown): reset control module, clock signal equalization control module, serial control multiplexer module, serial control slave interface module, register code table triple-module redundancy control module, triple-module redundancy register module, shadow register module, status register module, register refresh strategy control module, external signal synchronization detection module, image sensor imaging area register configuration control bus and image sensor imaging area register configuration control module and imaging signal generation control module. Among them:

[0042] The reset control module is used to receive the reset signal input from the external pin, refer to the external clock signal, generate the internal synchronous reset signal and the internal clock signal, and send them to the serial data read and write control slave interface module of the clock signal balance control module.

[0043] The clock signal balance control module performs driving capability and fan-out control on the internal synchronous reset signal and the internal clock signal, and sends out the internal synchronous reset signal and the internal clock signal after signal balance control;

[0044] The serial control multiplexer module completes the selection control of the external multi-channel serial control signals; receives the serial signal sent by the external serial control host interface, and sends the serial signal to the corresponding image sensor imaging area register configuration control module according to the internal register state; receives the serial input data signal fed back by the multiple image sensor imaging area register configuration control modules, and sends the serial input data signal to the serial control host interface according to the internal register state; can read and write the external radiation-resistant hardened memory according to the internal register state;

[0045] The serial control multiplexer module receives the serial clock signal, serial enable signal, serial output data signal, three-module redundant enable signal and three-module redundant update signal sent by the external serial control host interface, and sends the serial clock signal, serial enable signal, serial output data signal, three-module redundant enable signal and three-module redundant update signal to the corresponding image sensor imaging area register configuration control module according to the internal register state; receives the serial input data signal fed back by multiple image sensor imaging area register configuration control modules, and sends the serial input data signal to the serial control host interface according to the internal register state; can write the image sensor imaging area register state value into the external radiation-resistant hardened memory, or read the image sensor imaging area register state value from the external radiation-resistant hardened memory according to the internal register state, and distribute it to the corresponding image sensor imaging area register configuration control module through the image sensor imaging area register configuration control bus. The external input serial signal detected by the serial data read and write control slave interface module includes the serial clock signal, the serial enable signal and the serial input data signal.

[0046] If the serial data read and write control slave interface module detects that the serial enable signal is at a low level, it latches the serial input data signal into the shift register at the rising edge of the serial clock signal. If the serial enable signal is at a low level and contains 24 rising edges, the reception is completed for 24 bits of data, of which the 24th to 10th bits are address bits, the 9th bit is a control flag, and the 8th to 1st bits are data bits.

[0047] like Figure 4 As shown, the 9th bit is the control flag. If it is "1", the corresponding address receives the external input 8-bit register value; Figure 5 As shown, if it is "0", it outputs the 8-bit internal register value to the serial output data signal.

[0048] Register code table three-module redundant control module: After the register configuration is completed, the special register status value is judged. If the three-module redundant control is turned on, the control signal for reading and writing the three register modules is generated according to the external input pulse trigger signal, and then the three read registers are operated with two out of three, and the result is output to the corresponding register; if it is three-module redundant control, no operation is performed.

[0049] Register module: Register segmentation design, the first address space is allocated for analog circuits; the second address space is allocated for timing control circuits; the third address space is allocated for register reservation; the fourth address space is allocated for triple-module redundant refresh control. Register classification: analog circuit registers are updated immediately; timing partial register control refresh is achieved by setting special registers.

[0050] Register refresh strategy control module: classifies register refresh into immediate refresh register, row refresh register, frame refresh register and external control refresh register.

[0051] The external signal synchronization detection module is used to detect the external input control signal and generate the internal control mark to complete the conversion from external signal to internal signal.

[0052] The image sensor imaging area register configuration control bus is used for serially controlling the multiplexer module to perform information exchange with the image sensor imaging area register configuration control module;

[0053] The image sensor imaging area register configuration control module is used to read, write and refresh the status register within the imaging area of ​​the image sensor;

[0054] The imaging signal generation control module generates the timing signal required by the imaging circuit to control the operation of the imaging circuit.

[0055] The external signal synchronization detection module is used to detect the external input control signal and generate an internal control mark to complete the conversion from the external signal to the internal signal;

[0056] The image sensor imaging area register configuration control bus is used to serially control the multiplexer module to perform information exchange with the image sensor imaging area register configuration control module;

[0057] The image sensor imaging area register configuration control module is used to read, write and refresh the status register within the imaging area of ​​the image sensor;

[0058] The imaging signal generation control module generates the timing signal required by the imaging circuit, which is used to control the operation of the imaging circuit.

[0059] In the solution provided in the embodiment of the present application, a reset control module, a serial data read and write control slave interface module, a register code table triple-module redundancy control module, a register module, a register refresh strategy control module and an external signal synchronization detection module. Among them:

[0060] The reset control module: asynchronous reset, synchronous release, receives the reset signal input from the external pin, and references the clock signal to generate a local synchronous reset signal.

[0061] The serial control multiplexer module receives the serial clock signal, serial enable signal, serial output data signal, three-module redundant enable signal and three-module redundant update signal sent by the external serial control host interface, and sends the serial clock signal, serial enable signal, serial output data signal, three-module redundant enable signal and three-module redundant update signal to the corresponding image sensor imaging area register configuration control module according to the internal register state; receives the serial input data signal fed back by multiple image sensor imaging area register configuration control modules, and sends the serial input data signal to the serial control host interface according to the internal register state; can write the image sensor imaging area register state value into the external radiation-resistant hardened memory, or read the image sensor imaging area register state value from the external radiation-resistant hardened memory according to the internal register state, and distribute it to the corresponding image sensor imaging area register configuration control module through the image sensor imaging area register configuration control bus. The external input serial signal detected by the serial data read and write control slave interface module includes the serial clock signal, the serial enable signal and the serial input data signal.

[0062] If the serial data read and write control slave interface module detects that the serial enable signal is at a low level, it latches the serial input data signal into the shift register at the rising edge of the serial clock signal. If the serial enable signal is at a low level and contains 24 rising edges, the reception is completed for 24 bits of data, of which the 24th to 10th bits are address bits, the 9th bit is a control flag, and the 8th to 1st bits are data bits.

[0063] like Figure 4 As shown, the 9th bit is the control flag. If it is "1", the corresponding address receives the external input 8-bit register value; Figure 5 As shown, if it is "0", it outputs the 8-bit internal register value to the serial output data signal.

[0064] The register code table triple-module redundant control module: after the register configuration is completed, the special register status value is judged. If the triple-module redundant control is turned on, a control signal for reading and writing three register modules is generated according to an external input pulse trigger signal, and then a three-to-two operation is performed on the three read-in registers, and the result is output to the corresponding register; if it is triple-module redundant control, no operation is performed.

[0065] The register module is designed in segments, the first segment of the address space is allocated to the analog circuit; the second segment of the address space is allocated to the timing control circuit; the third segment of the address space is allocated to the register reservation; and the fourth segment of the address space is allocated to the triple-module redundant refresh control.

[0066] The register refresh strategy control module: classifies register refresh into immediate refresh register, row refresh register, frame refresh register and external control refresh register. The immediate refresh register is directly obtained from the shadow register, the row refresh register is obtained from the shadow register at the rising edge of the image sensor row signal, the frame refresh register is obtained from the shadow register at the rising edge of the image sensor frame signal, and the external control refresh register is obtained from the shadow register at the rising edge of the image sensor external trigger signal.

[0067] The external signal synchronization detection module is used to detect the external input control signal and generate an internal control mark to complete the conversion from the external signal to the internal signal;

[0068] The image sensor imaging area register configuration control bus is used to serially control the multiplexer module to perform information exchange with the image sensor imaging area register configuration control module;

[0069] The image sensor imaging area register configuration control module is used to read, write and refresh the status register within the imaging area of ​​the image sensor;

[0070] The imaging signal generation control module generates the timing signal required by the imaging circuit, which is used to control the operation of the imaging circuit. Figure 6 ,The analog circuit registers are immediate refresh registers and are updated directly;

[0071] like Figure 7 ,The digital circuit register is a control refresh register, which can be set as a row refresh register, a frame refresh register or an external control refresh according to specific needs.

[0072] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

[0073] The contents not described in detail in the specification of the present invention belong to the common knowledge of those skilled in the art.

Claims

1. A register configuration control system suitable for a radiation-resistant image sensor, characterized in that: It includes a reset control module, a clock signal equalization control module, a serial control multiplexer module, a serial control slave interface module, a register code table triple-module redundancy control module, a triple-module redundancy register module, a shadow register module, a status register module, a register refresh strategy control module, an external signal synchronization detection module, an image sensor imaging area register configuration control bus and an image sensor imaging area register configuration control module and an imaging signal generation control module; The reset control module is used to receive a reset signal input from an external pin, refer to an external clock signal, generate an internal synchronous reset signal and an internal clock signal, and send them to the clock signal equalization control module and the serial control slave interface module; The clock signal balance control module performs driving capability and fan-out control on the internal synchronous reset signal and the internal clock signal, and sends out the internal synchronous reset signal and the internal clock signal after signal balance control; The serial control multiplexer module completes the selection control of the external multi-channel serial control signals; receives the serial signal sent by the external serial control host interface, and sends the serial signal to the corresponding image sensor imaging area register configuration control module according to the internal register state; receives the serial input data signal fed back by the multiple image sensor imaging area register configuration control modules, and sends the serial input data signal to the serial control host interface according to the internal register state; and can perform read and write control on the external radiation-resistant hardened memory according to the internal register state; The serial control slave interface module is used to detect the serial clock signal, serial enable signal and serial output data signal sent by the serial control multiplexer module under the control of the internal clock after the reset is completed, and send the register to the register code table triple-module redundancy control module after completing the register analysis; The register code table triple-module redundancy control module is used to determine the special register state value after the register configuration is completed: if the triple-module redundancy control mode is turned on, the read and write control signals of the three register modules are generated according to the external input pulse trigger signal, and then the three read registers are operated with two out of three, and the results are output to the corresponding registers; if it is not the triple-module redundancy control mode, no operation is performed; The triple-module redundant register module is configured with three independent register blocks, and the triple-module redundant control module outputs a read-write control timing according to the register code table to implement read-write control of the corresponding registers in the register block; The shadow register module is used to cache the status register values ​​required by each circuit module; The status register module is used to allocate address space to the status register of each circuit module and store the status value of each circuit module register; The register refresh strategy control module is used to classify the state registers required by each circuit module, and classify and control the refresh of the state registers according to the type of the state registers; The external signal synchronization detection module is used to detect the external input control signal and generate an internal control mark to complete the conversion from the external signal to the internal signal; The image sensor imaging area register configuration control bus is used to serially control the multiplexer module to perform information exchange with the image sensor imaging area register configuration control module; The image sensor imaging area register configuration control module is used to read, write and refresh the status register within the imaging area of ​​the image sensor; The imaging signal generation control module generates the timing signal required by the imaging circuit, which is used to control the operation of the imaging circuit.

2. A register configuration control system suitable for a radiation-resistant image sensor according to claim 1, characterized in that: The clock signal balance control module receives the internal synchronous reset signal and the internal clock signal output by the reset control module, sets its driving capability and performs fan-out control, and sends out the internal synchronous reset signal and the internal clock signal after signal balance control.

3. A register configuration control system suitable for a radiation-resistant image sensor according to claim 1, characterized in that: The serial control multiplexer module receives a serial clock signal, a serial enable signal, a serial output data signal, a triple-mode redundant enable signal and a triple-mode redundant update signal sent by an external serial control host interface, and sends the serial clock signal, the serial enable signal, the serial output data signal, the triple-mode redundant enable signal and the triple-mode redundant update signal to the corresponding image sensor imaging area register configuration control module according to the internal register state; receives serial input data signals fed back by multiple image sensor imaging area register configuration control modules, and sends the serial input data signals to the serial control host interface according to the internal register state; and can write the image sensor imaging area register state value into the external anti-radiation hardened memory, or read the image sensor imaging area register state value from the external anti-radiation hardened memory according to the internal register state, and distribute it to the corresponding image sensor imaging area register configuration control module through the image sensor imaging area register configuration control bus.

4. The register configuration control system for a radiation-resistant image sensor according to claim 1, characterized in that: The external input serial signal detected by the serial control slave interface module includes a serial clock signal, a serial enable signal and a serial input data signal.

5. A register configuration control system suitable for a radiation-resistant image sensor according to claim 4, characterized in that: If the serial control slave interface module detects that the serial enable signal is at a low level, it latches the serial input data signal into the shift register at the rising edge of the serial clock signal. If the serial enable signal contains 24 rising edges during the low level period, the reception of 24-bit data is completed, wherein the 24th to 10th bits are address bits, the 9th bit is a control flag, and the 8th to 1st bits are data bits; if the 9th bit is the control flag and is 1, the external input 8-bit register value is received for the corresponding address; if it is 0, the 8-bit internal register value is output to the serial output data signal.

6. The register configuration control system for a radiation-resistant image sensor according to claim 1, characterized in that: The triple-module redundant register module is configured with three independent register blocks, and the three independent register blocks are the same register modules. When the image sensor layout is set, it is ensured that a gap greater than 0.5 mm is set between the three independent register blocks.

7. The register configuration control system for a radiation-resistant image sensor according to claim 1, characterized in that: The shadow register module internally sets shadow register group 1 and shadow register group 2. The register of group 1 is 8 bits wide, and the register of group 2 sets the register width according to the needs of each circuit module. According to the status register type, register group 1 is refreshed to register group 2.

8. The register configuration control system for a radiation-resistant image sensor according to claim 1, characterized in that: The address space includes four sections; the first section of the address space is allocated to the analog circuit; the second section of the address space is allocated to the timing control circuit; the third section of the address space is allocated to the register reservation; and the fourth section of the address space is allocated to the triple-module redundant refresh control.

9. The register configuration control system for a radiation-resistant image sensor according to claim 1, characterized in that: The status registers are classified into immediate refresh registers, row refresh registers, frame refresh registers and external control refresh registers; the immediate refresh registers are directly obtained from the shadow registers, the row refresh registers are obtained from the shadow registers at the rising edge of the image sensor row signal, the frame refresh registers are obtained from the shadow registers at the rising edge of the image sensor frame signal, and the external control refresh registers are obtained from the shadow registers at the rising edge of the image sensor external trigger signal.

10. The register configuration control system for a radiation-resistant image sensor according to claim 9, characterized in that: The image sensor imaging area register configuration control bus is set in multiple groups according to the size of the image sensor layout, and each bus group includes a serial clock signal, a serial enable signal, a serial output data signal, a serial input data signal, a triple-mode redundant enable signal and a triple-mode redundant update signal; The image sensor imaging area register configuration control module is configured with multiple groups according to the size of the image sensor layout, and each group of control modules includes a serial control slave interface module, a register code table triple-module redundancy control module, a triple-module redundancy register module, a shadow register module, a status register module, a register refresh strategy control module and an external signal synchronization detection module; The imaging signal generation control module generates the timing signals required by the image sensor in real time according to the status register value, including pixel timing signals, exposure control signals, frame synchronization signals, line synchronization signals, quantization control signals and dynamically configurable control signals.

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