Processor and operation processing method

Abstract

The invention relates to a processor and an operation processing method. The processor includes: a request issuing unit that issues an access request to a storage device; a data array that includes a storage body that stores sub-data, the sub-data being divided from data read from the storage device based on the access request; a switch that transmits the access request to one of the storage bodies; a first determination unit and a second determination unit. The first determination unit determines a cache hit when a tag address included in an access address matches a tag address stored in the first determination unit corresponding to an index address included in the access address. The second determination unit determines a cache hit when identification information corresponding to the first tag address included in the access address and a second tag address included in the access address match identification information and second tag addresses stored in the second determination unit. The cache controller accesses the data array or the storage device based on the determination result of the first determination unit or the second determination unit.

Description

Technical Field

[0001] The present invention relates to a processor and a processing method. A processor may also be sometimes referred to as an operation processing unit, a processing unit, etc. An operation processing method may also be sometimes simply referred to as a processing method. Background Art

[0002] A cache installed in a processor, such as a central processing unit (CPU), stores a portion of the data stored in the main memory. When the cache stores the target data of a memory access request issued by an arithmetic processing unit (CPU) and a cache hit occurs, the cache transfers the stored data to the arithmetic processing unit without issuing a memory access request to the main memory. This improves data access efficiency and enhances the CPU's processing performance.

[0003] For example, as proposed in Japanese Patent Application Publication No. 2007-504552, a cache includes a data array that stores data and a tag array that determines whether the target data to be accessed is stored in the data array. For example, as proposed in Japanese Patent Application Publication No. 2020-536308, a high-performance processor has a hierarchical cache, each of which includes multiple ways. In addition, as proposed in Japanese Patent Application Publication No. H08-320829, a processor may have multiple memory banks to improve cache throughput.

[0004] For example, if the data of a cache line (i.e., the management unit of the cache) is divided into multiple data and stored in multiple memory banks of the cache, the number of tag arrays increases as the number of memory banks increases, thereby increasing the ratio of the number of bits of the tag array to the data of a cache line. In addition, in processors capable of executing single instruction, multiple data (SIMD) operation instructions, the number of memory banks of the cache tends to increase. Summary of the Invention

[0005] According to one aspect, an object of the present invention is to reduce a ratio of a size of a determination unit that determines a cache hit of a cache including a plurality of memory banks relative to the size of the cache.

[0006] According to one aspect of the embodiment, a processor includes: a plurality of request issuing units, each of the request issuing units being configured to issue a memory access request to a memory device; a data array including a plurality of memory banks, each of the memory banks being configured to store sub-data, the sub-data being divided from data read from the memory device based on the memory access request; a switch configured to transmit the memory access request to one of the plurality of memory banks; and at least one first determining unit including a first saving unit that saves, for each value of an index address in an access address included in the memory access request, a tag address included in the access address, and the at least one first determining unit being configured to, when the tag address included in the access address matches the tag address stored in the first saving unit corresponding to the index address included in the access address. The method further comprises the steps of: 1) determining a cache hit when the access target data is matched, wherein the cache hit indicates that the access target data is stored in the data array; 2) at least one second determining unit including a second saving unit, wherein the second saving unit saves, for each value of the index address, identification information for identifying a first tag address included in the tag address and a second tag address included in the tag address, and the at least one second determining unit is configured to determine a cache hit when the identification information corresponding to the first tag address included in the access address and the second tag address included in the access address match the identification information and the second tag address stored in the second saving unit corresponding to the index address included in the access address, respectively; and 3) a cache controller configured to access the data array or the storage device based on the determination result of the first determining unit or the second determining unit.

[0007] The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims.

[0008] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is a block diagram showing an example of a processor according to the first embodiment;

[0010] Figure 2 It is used to describe the Figure 1 A diagram showing an example of data in a cache;

[0011] Figure 3 It is used to describe the Figure 1 A diagram illustrating another example of data in a cache is shown;

[0012] Figure 4 It shows Figure 1 A flowchart illustrating an example of a memory access operation of a processor is shown;

[0013] Figure 5 is a block diagram showing an example of a processor according to the second embodiment;

[0014] Figure 6 It shows Figure 5 A block diagram of an example of a sub-tag unit is shown;

[0015] Figure 7 It shows Figure 5 A flowchart illustrating an example of a memory access operation of a processor is shown;

[0016] Figure 8 is a block diagram showing an example of a sub-tag unit of a processor according to a third embodiment;

[0017] Figure 9 is a block diagram showing an example of a processor according to a fourth embodiment;

[0018] Figure 10 Is used to illustrate Figure 9 FIGURE 1 illustrates an example of address calculation in a load-store unit;

[0019] Figure 11 is a block diagram showing an example of the configuration of a main tag unit and a sub tag unit according to a fifth embodiment;

[0020] Figure 12 is a block diagram showing an example of the configuration of a main tag unit and a sub tag unit according to a sixth embodiment;

[0021] Figure 13 is a block diagram showing an example of the configuration of a main tag unit and a sub tag unit according to a seventh embodiment;

[0022] Figure 14 It shows that according to Figure 12 A block diagram of an example of a processor of configuration example 4 is shown;

[0023] Figure 15 is a block diagram showing an example of a main tag unit and a sub tag unit of a processor according to an eighth embodiment;

[0024] Figure 16 is a diagram for explaining an example of a tag array / data array ratio for each configuration of a cache; and

[0025] Figure 17 This is a diagram for explaining an example of the effect of improving the tag array / data array ratio when a tag array cache is provided. DETAILED DESCRIPTION

[0026] Preferred embodiments of the present invention will be described with reference to the accompanying drawings.

[0027] Figure 1 An example of the processor according to the first embodiment is shown. Figure 1 The processor 100 shown may be, for example, a central processing unit (CPU) that performs operations using single instruction multiple data (SIMD) operation instructions. The processor 100 may perform multiple product sum operations in parallel using SIMD operation instructions.

[0028] The processor 100 includes m+1 load store units LDST (LDST#0 to LDST#m), where m is an integer greater than or equal to 1, and a cache 60 connected to the main memory 50. The load store unit LDST is an example of a request issuing unit that issues a memory access request to the main memory 50. The main memory 50 is an example of a storage device. With respect to the load store unit LDST, the cache 60 operates as a level 1 (L1) data cache that stores a portion of the data stored in the main memory 50.

[0029] The cache 60 includes an arbitration unit 10, a switch 20, one main tag unit MTAG, n sub-tag units STAG (STAG#0 to STAG#n), a data array 30, and a cache controller 40, where n is an integer greater than or equal to 1. The cache controller 40 controls the overall operation of the cache 60. The cache controller 40 may be arranged outside the cache 60. The main tag unit MTAG is an example of a first determination unit, and the sub-tag unit STAG is an example of a second determination unit.

[0030] The data array 30 includes n+1 memory banks BK (BK#0 to BK#n) corresponding to each of the main tag unit MTAG and the sub tag unit STAG. By dividing the data array 30 into a plurality of memory banks BK, the so-called gather / scatter performance can be improved.

[0031] In addition, the cache 60 can be connected to the main memory 50 via a lower level cache (e.g., a level 2 (L2) cache, etc.). The cache 60 can include at least two memory banks BK#0 and BK#1. In this case, the cache 60 includes a main tag unit MTAG and a sub-tag unit STAG.

[0032] The processor 100 includes an instruction fetch unit, an instruction decoder, a reservation station, an arithmetic unit including various computing elements, a register file, and the like, which are not shown. Figure 1 Blocks or constituent elements mainly related to memory access are shown. For example, an instruction fetch unit, an instruction decoder, a reservation station, an arithmetic unit including various computing elements, a register file, and a load-store unit LDST are included in the CPU core not shown.

[0033] When a load instruction is executed, the load storage unit LDST outputs a memory access request to the memory bank BK indicated by the address AD via the switch 20, and receives read data from the memory bank BK via the switch 20. The address AD includes a tag address TAG, an index address IDX, an offset address, and a memory bank address BA. The address AD is an example of an access address included in the memory access request. The memory access request issued in response to the load instruction includes the address AD of the access target and read control information indicating a read request.

[0034] When executing a store instruction, the load store unit LDST outputs a memory access request to the memory bank BK indicated by the address AD via the switch 20. The memory access request issued in response to the store instruction includes the address AD of the access target, write data, and write control information indicating the write request.

[0035] The m+1 load-store units LDST receive load instructions or store instructions independently of each other and output memory access requests independently of each other. For this reason, competition for memory access requests may occur for one memory bank BK. When competition for memory access requests occurs, the arbitration unit 10 selects one of the memory access requests. In this embodiment and the embodiments to be described later, an example will be described in which the load-store unit LDST that executes a load instruction issues a memory access request (read request).

[0036] The switch 20 outputs a memory access request to the memory bank BK indicated by the bank address BA included in the memory access request. The switch 20 that outputs the memory access request in response to the load instruction receives read data DT from the memory bank BK and outputs the received read data DT to the load-store unit LDST that is the initiator or issuance source of the memory access request.

[0037] The master tag unit MTAG includes a tag array TGA and a comparator CMP1. The tag array TGA is an example of a first storage unit. The tag array TGA includes multiple entries for storing a tag address TAG for each value of the index address IDX. For example, when the index address IDX has 10 bits, the tag array TGA includes 1024 entries. The tag array TGA outputs the tag address TAG stored in the entry corresponding to the index address IDX received from the switch 20 to the comparator CMP1.

[0038] The comparator CMP1 compares the tag address TAG output from the tag array TGA with the tag address TAG output from the switch 20. When the two compared tag addresses TAG match, the comparator CMP1 outputs a hit signal HIT having a valid level (cache hit), and when the two compared tag addresses TAG do not match, the comparator CMP1 outputs a hit signal HIT having an invalid level (cache miss).

[0039] A cache hit indicates that the access target data of the memory access request is stored in the memory bank BK that is the access target of the data array 30. A cache miss indicates that the access target data of the memory access request is not stored in the memory bank BK that is the access target of the data array 30. In this case, the cache 60 reads the data, that is, the access target data, from the main memory 50.

[0040] The sub-tag unit STAG includes a tag conversion unit TCNV, a tag array cache TGAC, and a comparator CMP2. The tag conversion unit TCNV is an example of a third storage unit, and the tag array cache TGAC is an example of a second storage unit. The tag conversion unit TCNV includes a plurality of entries that can be identified by identification information ID. For example, when the identification information ID has 2 bits, the tag conversion unit TCNV includes 4 entries. The number of entries in the tag conversion unit TCNV is smaller than the number of entries in the tag array cache TGAC.

[0041] Each entry of the tag conversion unit TCNV stores a first tag address TAG1, which is a portion of the tag address TAG. When one of the entries of the tag conversion unit TCNV stores the first tag address TAG1 included in the memory access request, the tag conversion unit TCNV outputs the identification information ID of the entry to the comparator CMP2. Therefore, the tag conversion unit TCNV functions as a content addressable memory (CAM), which outputs the identification information ID indicating the entry storing the received first tag address TAG1. An element different from the tag conversion unit TCNV may be provided in the sub-tag unit STAG if a correspondence between the first tag address TAG1 and the identification information ID for identifying the first tag address TAG1 can be achieved.

[0042] The tag array cache TGAC includes a plurality of entries for storing identification information ID and a second tag address TAG2 for each value of the index address IDX. The second tag address TAG2 is indicated by a bit of the tag address TAG that is different from the bit of the first tag address TAG1. For example, the tag address TAG is formed by concatenating the bits of the first tag address TAG1 and the bits of the second tag address TAG2. The tag array cache TGAC outputs the identification information ID and the second tag address TAG2 stored in the entry corresponding to the index address IDX output from the switch 20 to the comparator CMP2.

[0043] The comparator CMP2 compares the identification information ID output from the tag conversion unit TCNV with the identification information ID output from the tag array cache TGAC. In addition, the comparator CMP2 compares the second tag address TAG2 output from the switch 20 with the second tag address TAG2 output from the tag array cache TGAC.

[0044] When the two compared identification information IDs match and the two compared second tag addresses TAG2 also match, the comparator CMP2 outputs a hit signal HIT having a valid level (cache hit). When the two compared identification information IDs do not match and the two compared second tag addresses TAG2 also do not match, or the two compared identification information IDs do not match, or the two compared second tag addresses TAG2 do not match, the comparator CMP2 outputs a hit signal HIT having an invalid level (cache miss).

[0045] Similar to a cache hit of the main tag unit MTAG, a cache hit of the sub tag unit STAG indicates that the access target data of the memory access request is stored in the memory bank BK that is the access target of the data array 30. Similar to a cache miss of the main tag unit MTAG, a cache miss of the sub tag unit STAG indicates that the access target data of the memory access request is not stored in the memory bank BK that is the access target of the data array 30.

[0046] For example, in one example, the tag address TAG has 36 bits, the first tag address TAG1 has 28 bits, the second tag address TAG2 has 8 bits, the identification information ID has 2 bits, and the index address IDX has 10 bits. In this case, the storage area of ​​the tag array cache TGAC can be reduced by approximately 26 kilobits ((28-2)*1024, where the symbol "*" represents multiplication) compared to the storage area of ​​the tag array TGA. The storage area of ​​the tag conversion unit TCNV is 120 bits ((28+2)*4).

[0047] Comparator CMP1 compares the 36-bit tag address TAG, while comparator CMP2 compares the 10-bit combination of the 2-bit identification information ID and the 8-bit second tag address TAG2. For this reason, the circuit scale of the sub-tag unit STAG becomes smaller than the circuit scale of the main tag unit MTAG. Therefore, compared with the case where the main tag unit MTAG is provided for each memory bank BK, the processor 100 can reduce the scale of the determination circuit for determining a cache hit. As a result, compared with a processor in which the main tag unit MTAG is provided for each memory bank BK, the manufacturing cost of the processor 100 can be reduced.

[0048] Each memory bank BK includes a plurality of entries for storing sub-data SDT for each value of the index address IDX. The sub-data SDT has a size obtained by dividing the cache line size by the number of memory banks BK. Figure 2 and Figure 3 To describe the size of the sub-data SDT.

[0049] When a cache hit occurs, each memory bank BK outputs the sub-data SDT stored in the entry corresponding to the index address IDX included in the memory access request to the switch 20 based on the control of the cache controller 40. On the other hand, when a cache miss occurs, each memory bank BK stores the sub-data SDT corresponding to the index address IDX included in the memory access request in the data DT of one cache line read from the main memory 50 in the entry corresponding to the index address IDX based on the control of the cache controller 40.

[0050] The cache controller 40 receives a hit signal HIT from the main tag unit MTAG and the sub tag unit STAG and controls the cache 60 as described above. The cache controller 40 performs data transfer between the memory bank BK and the main memory 50. In addition, in the case of updating the sub data stored in each memory bank BK, when a cache miss occurs, the cache controller 40 writes the sub data back to the main memory 50.

[0051] Figure 1 The cache 60 shown is a direct-mapped cache, but a set-associative cache having multiple ways can be used for the cache 60. In this case, the tag array TGA and the tag array cache TGAC are also divided into a number corresponding to the number of ways. The cache 60 shown in each embodiment described below is also a direct-mapped cache, but a set-associative cache can be used for the cache 60 in each embodiment described below.

[0052] Figure 2 and Figure 3 Shows the saved Figure 1An example of the data in the cache 60 is shown. Figure 2 and Figure 3 , the processor 100 includes four memory banks BK#0 to BK#3. Each of the memory banks BK#0 to BK#3 stores 64-bit sub-data SDT for each entry identified by an index address IDX.

[0053] exist Figure 2 In the four memory banks BK#0 to BK#3 shown, four sub-data SDT included in one entry identified by the index address IDX corresponds to one cache line CL. Figure 2 In the example shown, the data size of the cache line CL is 256 bits. In this case, Figure 1 The illustrated cache controller 40 performs a cache fill, which transfers data from the main memory 50 to the cache memory 60. During the cache fill, the sub-data SDT included in the cache line CL is stored in the entries of the memory banks BK#0 to BK#3 identified by the common index address IDX in order according to the address AD. Furthermore, the cache controller 40 performs a writeback, which transfers data from the cache memory 60 to the main memory 50. During the writeback, the four sub-data SDT stored in the entries of the memory banks BK#0 to BK#3 identified by the common index address IDX are stored in the main memory 50 in order according to the address.

[0054] exist Figure 3 In the four memory banks BK#0 to BK#3 shown, eight sub-data SDT included in two entries identified by two consecutive index addresses IDX correspond to one cache line CL. Figure 3 In the example shown, the data size of the cache line CL is 512 bits. In this case, the cache controller 40 performs a cache fill. During the cache fill, the sub-data SDT included in the two cache lines CL are stored in the two entries of the memory banks BK#0 to BK#3 identified by the two consecutive index addresses IDX in the order according to the address AD. In addition, during the write-back period, the cache controller 40 stores the eight sub-data SDT stored in the two entries of the memory banks BK#0 to BK#3 identified by the two consecutive index addresses IDX in the main memory 50 in the order according to the address.

[0055] For example, in the case where the cache 60 includes four memory banks BK having a bit width of 64 bits and the size of the cache line CL is 1024 bits, the cache controller 40 performs cache fill and write back for four entries of each of the four memory banks BK. In the case where the cache 60 includes eight memory banks BK having a bit width of 64 bits and the size of the cache line CL is 1024 bits, the cache controller 40 performs cache fill and write back for two entries of each of the eight memory banks BK.

[0056] Figure 4 Show Figure 1 An example of memory access operation of the processor 100 is shown. That is, Figure 4 FIG1 shows an example of an operation processing method of the processor 100. Based on the issuance of a memory access request corresponding to a load instruction from at least one load storage unit LDST of the plurality of load storage units LDST, the cache controller 40 executes Figure 4 The operation shown.

[0057] When a cache hit occurs for a memory access request from a plurality of load-store units LDST to memory banks BK different from each other, a cache hit is executed in each of the memory banks BK that are access targets. Figure 4 When a cache miss occurs in one of the memory access requests from the plurality of load-store units LDST to different memory banks BK, write-back associated with the cache miss and cache fill after the write-back are performed in common in all memory banks BK.

[0058] First, in step S10, the cache controller 40 uses the memory bank address BA to determine whether the memory access request indicates the memory bank BK corresponding to the main tag unit MTAG (BK#0 in this example). When the memory access request indicates the memory bank BK corresponding to the main tag unit MTAG, the operation of the cache controller 40 proceeds to step S20. In steps S22, S24, S26, and S28 included in step S20, the cache controller 40 performs access processing using the main tag unit MTAG.

[0059] When the memory access request does not indicate the memory bank BK corresponding to the main tag unit MTAG, the operation of the cache controller 40 proceeds to step S30. In steps S32, S34, S36 and S38 included in step S30, the cache controller 40 performs access processing using the sub tag unit STAG.

[0060] In step S22, the cache controller 40 accesses the main tag unit MTAG based on the index address IDX included in the memory access request and reads the tag address TAG. In addition, the cache controller 40 causes the comparator CMP1 to compare the tag address TAG included in the memory access request with the tag address TAG read from the main tag unit MTAG and output a hit signal HIT.

[0061] Next, in step S24, the cache controller 40 determines whether a cache hit occurs in the primary tag unit MTAG based on the hit signal HIT output from the comparator CMP1. When a hit occurs in the primary tag unit MTAG, the operation of the cache controller 40 proceeds to step S26, and when a cache miss occurs in the primary tag unit MTAG, the operation of the cache controller 40 proceeds to step S28.

[0062] In step S26, the cache controller 40 performs normal cache hit processing and outputs the data read from the memory bank BK where the cache hit occurs to the load store unit LDST as the initiator of the memory access request via the switch 20. Then, the cache controller 40 ends Figure 4 The operation shown.

[0063] In step S28, the cache controller 40 performs normal cache miss processing. That is, the cache controller 40 performs, for example, Figure 2 or Figure 3 The cache controller 40 performs a cache fill operation as shown, and updates the data stored in each memory bank BK. In addition, the cache controller 40 updates the main tag unit MTAG, the tag conversion unit TCNV and the tag array cache TGAC according to the update of the data in each memory bank BK. When the data in the memory bank BK is updated, the cache controller 40 performs a write-back operation. Then, the cache controller 40 ends Figure 4 The operation shown.

[0064] On the other hand, in step S32, the cache controller 40 accesses the sub-tag unit STAG corresponding to the memory bank BK indicated by the memory bank address BA included in the memory access request. The cache controller 40 accesses the tag conversion unit TCNV based on the tag address TAG1 included in the memory access request and reads the identification information ID. The cache controller 40 accesses the tag array cache TGAC based on the index address IDX included in the memory access request and reads the identification information ID and the tag address TAG2.

[0065] The cache controller 40 then causes the comparator CMP2 to compare the tag address TAG2 included in the memory access request with the tag address TAG2 read from the tag array cache TGAC. Furthermore, the cache controller 40 causes the comparator CMP2 to compare the identification information ID read from the tag conversion unit TCNV with the identification information ID read from the tag array cache TGAC. The cache controller 40 outputs a hit signal HIT based on the comparison result of the comparator CMP2.

[0066] Next, in step S34, the cache controller 40 determines whether a cache hit occurs in the sub-tag unit STAG based on the hit signal HIT output from the comparator CMP2. When a hit occurs in the sub-tag unit STAG, the operation of the cache controller 40 proceeds to step S36. When a cache miss occurs in the sub-tag unit STAG, the operation of the cache controller 40 proceeds to step S38.

[0067] In step S36, the cache controller 40 performs normal cache hit processing in a manner similar to step S26, and ends Figure 4 In step S38, the cache controller 40 performs normal cache miss processing similar to step S28, and ends Figure 4 The operation shown.

[0068] As described above, in this embodiment, the processor 100 can determine whether a cache hit occurs in the memory bank BK by storing the identification information ID identifying the first tag address TAG1 and the tag array cache TGAC of the second tag address TAG2. The bit width of the entry of the tag array cache TGAC is smaller than the bit width of the entry of the tag array TGA. As described above, the circuit scale of the sub-tag unit STAG including the tag conversion unit TCNV and the tag array cache TGAC is smaller than the circuit scale of the main tag unit MTAG including the tag array TGA.

[0069] For this reason, the processor 100 can use a sub-tag cell STAG having a smaller circuit scale than the main tag cell MTAG to determine whether a cache hit has occurred in the memory banks BK#1 to BK#n. In other words, compared to a case where a main tag cell MTAG is provided for each memory bank BK, the processor 100 can reduce the scale of the circuitry for determining whether a cache hit has occurred. As a result, the manufacturing cost of the processor 100 can be reduced, etc., compared to a processor in which a main tag cell MTAG is provided for each memory bank BK.

[0070] In this embodiment, the main tag unit MTAG or the sub tag unit STAG corresponding to each memory bank BK is provided on the side of the switch 20 closer to the memory bank BK. The switch 20 determines the memory bank BK as the access target based on the access address output from the load storage unit LDST, and outputs the access address to the main tag unit MTAG or the sub tag unit STAG corresponding to the determined memory bank BK. For this reason, the hit signal HIT output from the main tag unit MTAG or the sub tag unit STAG includes information of the memory bank BK. Therefore, the cache controller 40 can control the memory bank BK according to the hit signal HIT from the main tag unit MTAG and the sub tag unit STAG without using the memory bank address BA.

[0071] Figure 5 An example of a processor according to a second embodiment is shown. In this embodiment, the same constituent elements as those of the first embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. Figure 5 The processor 100A shown is, for example, a CPU or the like having a function of executing a plurality of product-sum operations in parallel using SIMD operation instructions.

[0072] In addition, the processor 100A includes a multiplexer MUX1 and provides a cache controller 40A instead of Figure 1 In addition to the cache controller 40 shown, the processor 100A has Figure 1 The configuration of the processor 100 shown in FIG. 1 is similar to that of the processor 100A. To simplify the description, it is assumed that the processor 100A includes four load-store units LDST (LDST#0 to LDST#3), three sub-tag units STAG (STAG#1 to STAG#3), and four memory banks BK (BK#0 to BK#3). In this embodiment, an example is also described in which a load instruction is issued from the load-store unit LDST.

[0073] A main tag unit MTAG is provided corresponding to the memory bank BK#0. Sub tag units STAG#1 to STAG#3 are provided corresponding to the memory banks BK#1 to BK#3, respectively. The multiplexer MUX1 receives the address AD for the main tag unit MTAG and the address AD for the sub tag unit STAG output from the switch 20, and outputs one of the received addresses AD to the main tag unit MTAG.

[0074] In addition to the tag conversion unit TCNV outputting the hit signal HIT1 and providing the multiplexer MUX2, the configuration of the sub-tag unit STAG is similar to Figure 1 The configuration of the sub-tag unit STAG is shown. The multiplexer MUX2 of each sub-tag unit STAG outputs one of the hit signal HIT2 output from the comparator CMP2 and the hit signal HIT output from the comparator CMP1 of the main tag unit MTAG. The operations of the multiplexers MUX1 and MUX2 are controlled by the cache controller 40A.

[0075] When receiving the hit signal HIT1 having an invalid level from one of the tag conversion units TCNV, the cache controller 40A determines whether a temporary cache miss occurs. A temporary cache miss is a cache miss determined by the tag conversion unit TCNV of the sub-tag unit STAG and has a possibility of a cache hit.

[0076] In addition, the cache controller 40A controls the multiplexer MUX1 and causes the multiplexer MUX1 to output the address AD provided to the sub-tag unit STAG in which the temporary cache miss occurs to the main tag unit MTAG. Therefore, the cache controller 40A can use the tag array TGA of the main tag unit MTAG to determine whether a cache hit or a cache miss occurs in the memory bank BK corresponding to the sub-tag unit STAG in which the temporary cache miss occurs.

[0077] The cache controller 40A causes the multiplexer MUX2 of the sub-tag unit STAG in which the temporary cache miss occurs to select the hit signal HIT output from the tag array TGA of the tag conversion unit TCNV and output the hit signal HIT as the hit signal HIT2. Therefore, the cache controller 40A can use the determination result of the tag array TGA to determine whether a true cache hit or a true cache miss has occurred in the memory bank BK corresponding to the sub-tag unit STAG in which the temporary cache miss has occurred. In addition, the cache controller 40A can control the operation of the cache 60 according to the determination result. When the tag conversion unit TCNV outputs the hit signal HIT1 with an invalid level, the hit signal HIT output from the comparator CMP2 always indicates an invalid level.

[0078] Figure 6 Shown Figure 5 An example of a sub-tag unit STAG is shown. Figure 5 The address AD output by the switch 20 shown includes a tag address TAG including a first tag address TAG1 and a second tag address TAG2, an index address IDX, and an offset address OFS. The offset address OFS includes a bank address BA (e.g., 2 bits) that identifies the memory bank BK. The first tag address TAG1 and the second tag address TAG2 are appended with one of the symbols "a" to "f" used to describe the operation.

[0079] For example, the tag conversion unit TCNV includes four entries ENT1 identified by identification information ID, comparators CMP3 , OR circuits OR, and encoders ENC respectively corresponding to the entries ENT1 . A first tag address TAG1 is stored in each entry ENT1 by the cache controller 40A that determines occurrence of a cache miss.

[0080] Each comparator CMP3 compares the first tag address TAG1 stored in the corresponding entry ENT1 with the first tag address TAG1 included in the memory access request, and outputs the comparison result to the OR circuit OR and the encoder ENC. For example, when the two compared first tag addresses TAG1 match, each comparator CMP3 outputs a logic (i.e., logic value or logic level) "1".

[0081] The OR circuit OR sets the hit signal HIT1 to a valid level when one of the outputs of the comparator CMP3 has logic “1”, and sets the hit signal HIT1 to an invalid level when all the outputs of the comparator CMP3 have logic “0”.

[0082] The encoder ENC outputs the identification information ID of the entry ENT1 corresponding to the comparator CMP3 outputting a logic "1." In other words, the encoder ENC outputs the identification information ID of the entry ENT1 that stores the first tag address TAG1 included in the memory access request. As described above, the tag conversion unit TCNV functions as a CAM. The identification information ID output from the encoder ENC and the second tag address TAG2 included in the memory access request are output to the comparator CMP2 as a simplified tag obtained by encoding the first tag address TAG1.

[0083] The tag array cache TGAC includes: a plurality of entries ENT2, which store a second tag address TAG2 and identification information ID for each value of the index address IDX; a comparator CMP4 corresponding to each entry ENT2; and a flag FLG corresponding to each entry ENT2. Each flag FLG is reset to logic "0" in an initial state, indicating that the corresponding entry ENT2 is invalid. Each flag FLG is set or reset by the cache controller 40A. The set state (logic "1") of each flag FLG indicates that the corresponding entry ENT2 stores a valid second tag address TAG2 and a valid identification information ID. The reset state (logic "0") of each flag FLG indicates that the corresponding entry ENT2 stores an invalid second tag address TAG2 or an invalid identification information ID.

[0084] When the identification information ID stored in the entry ENT2 matches the identification information ID output from the cache controller 40A along with the set signal SET, each comparator CMP4 sets the corresponding flag FLG to logic "1". When the identification information ID stored in the entry ENT2 matches the identification information ID output from the cache controller 40A along with the reset signal RESET, each comparator CMP4 resets the corresponding flag FLG to logic "0".

[0085] By setting the flag FLG for each entry ENT2 of the tag array cache TGAC, the cache controller 40A can simply reset the flag FLG to invalidate the entry ENT2 without having to rewrite the second tag address TAG2 or the identification information ID. Therefore, simple control can be used to reduce the number of false hit signals HIT2 output to the cache controller 40A.

[0086] Based on a cache miss, cache controller 40A uses Figure 5The main memory 50 shown in FIG. 5 updates each of the banks BK#0 to BK#3 by reading the sub-data SDT (cache line). The cache controller 40A updates the cache memory 50 in response to the updating of each of the banks BK#0 to BK#3. Figure 5 The tag array TGA of the main tag unit MTAG is shown, and the tag conversion unit TCNV and the tag array cache TGAC are updated. Because the operation of the tag array TGA when a cache miss occurs is the same as the normal cache miss processing, the update processing of the sub-tag unit STAG will be described below.

[0087] During the update process, the cache controller 40A stores the first tag address TAG1 included in the memory access request in one of the entries ENT1. The cache controller 40A outputs the identification information ID of the entry ENT1 storing the first tag address TAG1 and the reset signal RESET to the comparator CMP4. The cache controller 40A resets the flag FLG corresponding to the entry ENT2 storing the identification information ID output to the comparator CMP4.

[0088] The cache controller 40A stores the second tag address TAG2 included in the memory access request in the entry ENT2 corresponding to the index address IDX included in the memory access request. Furthermore, the cache controller 40A stores the identification information ID of the entry ENT1 storing the first tag address TAG1 in the entry ENT2 storing the second tag address TAG2. Furthermore, the cache controller 40A outputs the identification information ID of the entry ENT1 storing the first tag address TAG1 and a set signal SET to the comparator CMP4. The cache controller 40A sets the flag FLG corresponding to the entry ENT2 storing the identification information ID output to the comparator CMP4.

[0089] like Figure 6 As shown, it is assumed that the first tag addresses TAG1a, TAG1b, TAG1c and TAG1d are stored in four entries ENT1 of the tag conversion unit TCNV of one of the sub-tag units STAG. It is also assumed that the second tag addresses TAG2d, TAG2f, TAG2b, TAG2e, ..., TAG2a are stored in entry ENT2 of the tag array cache TGAC.

[0090] In this state, the sub-tag unit STAG receives a memory access request including, for example, a first tag address TAG1b and a second tag address TAG2b. It is assumed that the second tag address TAG2b and identification information ID="01" are stored in the entry ENT2 corresponding to the index address IDX included in the memory access request, and the corresponding flag FLG has a logic "1".

[0091] Because the identification information ID of the entry ENT1 storing the first tag address TAG1b included in the memory access request is "01," the tag conversion unit TCNV sets the hit signal HIT1 to an active level, and the encoder ENC outputs identification information ID="01." The simplified tag received by the comparator CMP2 from the tag conversion unit TCNV includes the identification information ID="01" and the second tag address TAG2b.

[0092] The tag array cache TGAC outputs the second tag address TAG2b and identification information ID="01" stored in the entry ENT2 corresponding to the index address IDX included in the memory access request as a simplified tag. In addition, the tag array cache TGAC outputs a logic "1" stored in the flag FLG corresponding to the index address IDX included in the memory access request.

[0093] The comparator CMP2 outputs a logic "1" to the AND circuit AND because the two compared simplified tags match. The AND circuit AND receives the logic "1" from the comparator CMP2 and the logic "1" from the flag FLG, and sets the hit signal HIT to a valid level. When a memory access request is issued, the cache controller 40A causes the multiplexer MUX2 to select the output of the AND circuit AND. For this reason, the multiplexer MUX2 outputs the hit signal HIT with a valid level as the hit signal HIT2 to the cache controller 40A. The cache controller 40A detects a cache hit in the memory bank BK corresponding to the sub-tag unit STAG based on the hit signal HIT2 with a valid level, and outputs the sub-data SDT stored in the memory bank BK to the load storage unit LDST.

[0094] On the other hand, although the first tag address TAG1 included in the memory access request is stored in entry ENT1, there are cases where the simplified tag corresponding to the tag conversion unit TCNV does not match the simplified tag output from entry ENT2. Alternatively, the two compared simplified tags may match, but there are cases where the flag FLG is reset to logic "0." In these cases, the cache controller 40A receives the hit signal HIT2 at an invalid level and performs cache miss processing. In addition, the cache controller 40A performs update processing for each memory bank BK, as well as update processing for the tag array cache TGAC and the tag conversion unit TCNV.

[0095] Furthermore, when the first tag address TAG1 included in the memory access request is not stored in the entry ENT1, the tag conversion unit TCNV sets the hit signal HIT1 to an invalid level (logic "0") as described above. When the cache controller 40A receives the hit signal HIT1 having an invalid level, the cache controller 40A detects a temporary cache miss and causes the cache controller 40A to Figure 5 The multiplexer MUX1 shown selects the address AD provided to the sub-tag unit STAG. In addition, the cache controller 40A causes the multiplexer MUX2 to select the hit signal HIT from the main tag unit MTAG.

[0096] The master tag unit MTAG receives the address AD generating the temporary cache miss via the multiplexer MUX1, determines whether a cache hit or cache miss occurs using the tag array TGA, and outputs a hit signal HIT. The cache controller 40A receives the hit signal HIT output from the master tag unit MTAG as a hit signal HIT2 via the multiplexer MUX2, and performs cache hit processing or cache miss processing according to the hit signal HIT2.

[0097] During a cache hit process, the cache controller 40A outputs the sub-data SDT stored in the memory bank BK to the load-store unit LDST. During a cache miss process, the cache controller 40A performs an update process for the data of each memory bank BK, as well as an update process for the tag array TGA, the tag conversion unit TCNV, and the tag array cache TGAC, as described above.

[0098] Figure 7 Shown Figure 5 An example of the memory access operation of the processor 100A shown in FIG. Figure 7 An example of the operation processing method of the processor 100A is shown. Figure 4 and Figure 6 Based on the issuance of a memory access request corresponding to a load instruction from at least one load storage unit LDST of the plurality of load storage units LDST, the cache controller 40A performs Figure 7 The operation shown.

[0099] First, in step S40, the cache controller 40A uses the bank address BA to determine whether the memory access request indicates the memory bank BK corresponding to the main tag unit MTAG (BK#0 in this example). When the memory access request indicates the memory bank BK corresponding to the main tag unit MTAG, the operation of the cache controller 40A proceeds to step S42. On the other hand, when the memory access request does not indicate the memory bank BK corresponding to the main tag unit MTAG, the operation of the cache controller 40A proceeds to step S44.

[0100] The processing of step S42 is similar to Figure 4 The access process of step S20 using the master tag unit MTAG is shown. After executing the process of step S42, the cache controller 40A ends. Figure 7 The operation shown.

[0101] In step S44, Figure 4 Similar to step S32 shown, the cache controller 40A accesses the sub-tag unit STAG corresponding to the memory bank BK indicated by the memory bank address BA included in the memory access request. In addition, the cache controller 40A causes the sub-tag unit STAG to determine whether a cache hit or cache miss occurs in the tag conversion unit TCNV and whether a cache hit or cache miss occurs in the tag array cache TGAC.

[0102] Next, in step S46, the cache controller 40A determines whether a cache hit occurs in the tag conversion unit TCNV based on the hit signal HIT1 output from the tag conversion unit TCNV. When a cache hit occurs in the tag conversion unit TCNV, the operation of the cache controller 40A proceeds to step S50, and when a cache miss occurs in the tag conversion unit TCNV, the operation of the cache controller 40A proceeds to step S48. The processing of step S48 is similar to Figure 4 The access process of step S20 using the master tag unit MTAG is shown. After executing the process of step S48, the operation of the cache controller 40A proceeds to step S56.

[0103] In step S50, the cache controller 40A determines whether a cache hit occurs in the tag array cache TGAC. When a cache hit occurs in the tag array cache TGAC, a cache hit occurs in both the tag conversion unit TCNV and the tag array cache TGAC, and therefore, the operation of the cache controller 40A proceeds to step S52 to perform normal cache hit processing. The processing of step S52 is similar to Figure 4 The process of step S36 is shown.

[0104] On the other hand, when a cache miss occurs in the tag array cache TGAC, the operation of the cache controller 40A proceeds to step S54. The processing of step S54 is similar to that of the step S54 except that the update processing of the tag conversion unit TCNV and the tag array cache TGAC is not included. Figure 4 The cache controller 40A performs the processing of step S56 after performing the processing of step S54. In step S56, the cache controller 40A performs the updating processing of the tag conversion unit TCNV and the tag array cache TGAC, and the cache controller 40A ends. Figure 7 The operation shown.

[0105] As described above, in this embodiment, similar effects as those obtainable in the first embodiment can be achieved. For example, compared to a case where a master tag unit MTAG is provided for each memory bank BK, the processor 100A can reduce the scale of the circuitry that determines whether a cache hit has occurred. As a result, the manufacturing cost of the processor 100A can be reduced, etc., compared to a processor in which a master tag unit MTAG is provided for each memory bank BK.

[0106] Furthermore, in this embodiment, when the tag conversion unit TCNV determines that a temporary cache miss has occurred, the cache controller 40A provides the access address to the primary tag unit MTAG via the multiplexer MUX1. Therefore, the cache controller 40A can use the tag array TGA of the primary tag unit MTAG to determine whether a cache hit or a cache miss has occurred in the memory bank BK corresponding to the temporary cache miss.

[0107] By setting the flag FLG for each entry ENT2 of the tag array cache TGAC, the cache controller 40A can simply reset the flag FLG to invalidate the entry ENT2 without having to rewrite the second tag address TAG2 or the identification information ID. Therefore, simple control can be used to reduce the number of false hit signals HIT2 output to the cache controller 40A.

[0108] Figure 8 An example of a sub-label unit of a processor according to a third embodiment is shown. Figure 6 The same constituent elements as shown are denoted by the same reference numerals, and detailed description thereof will be omitted. Figure 8 The processor 100B shown is, for example, a CPU having a function of executing a plurality of product-sum operations in parallel using SIMD operation instructions. The processor 100B includes a sub-tag unit STAG2 and a cache controller 40B instead of Figure 5The sub-tag unit STAG and cache controller 40A are shown. In the processor 100B, the configuration other than the sub-tag unit STAG2 and the cache controller 40B is the same as Figure 5 and Figure 6 The configuration shown is the same.

[0109] The sub-tag unit STAG2 includes a tag conversion part TCNV2, a tag array buffer TGAC2, a comparator CMP2, an AND circuit AND and a multiplexer MUX2. The tag conversion unit TCNV2 includes an entry ENT1 and a comparator CMP3 corresponding to the entry ENT1, and does not include Figure 6 The encoder ENC and the OR circuit OR are shown. When the first tag address TAG1 stored in the entry ENT1 matches the first tag address TAG1 included in the memory access request, the comparator CMP3 sets the hit signal HIT1 to the active level. When the first tag address TAG1 stored in the entry ENT1 does not match the first tag address TAG1 included in the memory access request, the comparator CMP3 sets the hit signal HIT1 to the inactive level. The hit signal HIT1 is output to the cache controller 40B.

[0110] The tag array cache TGAC2 has the same characteristics as the tag array cache TGAC2, except that the comparator CMP4 is not provided and the entry ENT2 does not store the identity information ID. Figure 6 The cache controller 40B sets the corresponding flag FLG to logic "1" by outputting the index address IDX and the set signal SET to the tag array cache TGAC2. The cache controller 40B also outputs the index address IDX and the reset signal RESET to the tag array cache TGAC2 to reset the corresponding flag FLG to logic "0."

[0111] When the second tag address TAG2 included in the memory access request matches the second tag address TAG2 output from the entry ENT2 corresponding to the index address IDX included in the memory access request, the comparator CMP2 outputs a logic "1". On the other hand, when the second tag address TAG2 included in the memory access request does not match the second tag address TAG2 output from the entry ENT2 corresponding to the index address IDX included in the memory access request, the comparator CMP2 outputs a logic "0". When the AND circuit AND receives a logic "1" from each of the comparator CMP2 and the flag FLG, the AND circuit AND sets the hit signal HIT to a valid level. The operation of the multiplexer MUX2 is the same as Figure 6 The operation of the multiplexer MUX2 shown is the same. When a memory access request is issued, the cache controller 40B causes the multiplexer MUX2 to select the output of the AND circuit AND.

[0112] The operation of the processor 100B according to this embodiment is similar to Figure 7 However, the number of entries ENT1 in the tag conversion unit TCNV2 is less than Figure 6 The number of entries ENT1 in the tag array cache TGAC2 does not include the comparator CMP4, and the entry ENT2 does not store the identification information ID. For this reason, the circuit scale of the sub-tag unit STAG2 can be made smaller than Figure 6 The circuit scale of the sub-tag unit STAG is shown.

[0113] As described above, in this embodiment, effects similar to those obtainable in the above embodiment can be achieved. Furthermore, in this embodiment, since the circuit scale of the sub-tag unit STAG2 can be made smaller than that of the sub-tag unit STAG, the circuit scale of the processor 100B can be made smaller than that of the processor 100A. As a result, the manufacturing cost of the processor 100B can be reduced.

[0114] Figure 9 An example of a processor according to a fourth embodiment is shown. In this embodiment, the same constituent elements as those of the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. Figure 9 The processor 100C shown is, for example, a CPU having a function of executing a plurality of product-sum operations in parallel using SIMD operation instructions. The processor 100C includes a tag conversion unit TCNV provided in common for the three sub-tag units STAG3#1 to STAG3#3. In other respects, the configuration of the processor 100C is similar to Figure 5 The configuration of the processor 100A is shown in FIG. The configuration of the tag conversion unit TCNV is similar to Figure 6 The configuration of the tag conversion unit TCNV is shown. Figure 9 As shown in FIG, however, the configuration of the cache 60 loads the storage unit LDST and the main memory 50 from Figure 9 Excluded from the configuration shown.

[0115] Figure 10 Shown Figure 9 An example of address calculation in the load-store unit LDST is shown. For example, each load-store unit LDST calculates the address AD of the memory access request by adding the value stored in the scalar register to the value stored in the SIMD register. For example, the 64-bit base address BASE_AD is stored in the scalar register, and the 32-bit index address INDEX_AD (corresponding to the lower bits) is stored in the SIMD register.

[0116] In this case, the tag address TAG corresponding to the upper bit of the address AD generated by each load-store unit LDST becomes the same except when a carry occurs due to addition. Therefore, the tag address TAG stored in Figure 9 The information in the tag conversion unit TCNV shown can be shared by the four load storage units LDST. As a result, the tag conversion unit TCNV can be provided in common for the plurality of sub-tag units STAG3.

[0117] As described above, this embodiment also achieves similar effects to those achieved in the above embodiment. Furthermore, in this embodiment, because the tag conversion unit TCNV is provided in common for multiple sub-tag units STAG3, the circuit scale of the sub-tag unit STAG3 can be made smaller than that of the sub-tag unit STAG2. As a result, the circuit scale of the processor 100C can be further reduced from that of the processor 100A, which can reduce the manufacturing cost of the processor 100C.

[0118] Figures 11 to 13 1 and 2 show examples of configurations of the main tag unit MTAG and the sub tag unit STAG according to the fifth, sixth and seventh embodiments. Figure 11 In the configuration example 1 shown, each of the plurality of master tag units MTAG is provided corresponding to a predetermined number of memory banks BK. Figure 7 As shown, when a cache miss occurs in the entry ENT1 of the tag conversion unit TCNV in step S22, the tag array TGA of the main tag unit MTAG is used to perform a cache hit or cache miss determination. For this reason, when a cache miss occurs in the entry ENT1 of the tag conversion unit TCNV of the plurality of sub-tag units STAG, contention occurs in the tag array TGA, thereby delaying the cache hit or cache miss determination.

[0119] Furthermore, during the determination of the main tag cell MTAG for memory bank BK#0, the main tag cell MTAG is made to wait for the determination of a cache hit or cache miss based on a temporary cache miss of entry ENT1 of the tag conversion unit TCNV. In configuration example 1, by providing a plurality of main tag cells MTAG, contention for the main tag cells MTAG caused by a temporary cache miss of entry ENT1 of the tag conversion unit TCNV can be reduced. Furthermore, the possibility of a conflict between the determination of a cache hit or cache miss for memory bank BK#0 and the determination of a cache hit or cache miss due to a cache miss of entry ENT1 of the tag conversion unit TCNV can be reduced.

[0120] exist Figure 11In the second configuration example shown, a sub-tag cell STAG is provided corresponding to each memory bank BK, and a main tag cell MTAG is provided independently of the multiple memory banks BK. Therefore, the sub-tag cells STAG and memory banks BK can be repeatedly arranged in pairs, and the design can be made by considering the symmetry of the circuit arrangement or layout. As a result, the layout design of the processor can be facilitated, and the electrical characteristics of the processor, such as frequency characteristics, can be improved.

[0121] exist Figure 12 and Figure 13 In the configuration examples 3 to 6 shown, the main tag unit MTAG and the sub tag unit STAG are arranged on the side of the switch closer to the load storage unit LDST. That is, before the memory access request is provided to the switch, the main tag unit MTAG and the sub tag unit STAG receive the memory access request from the plurality of load storage units LDST. Figure 12 and Figure 13 , the hit signal HIT supplied to the memory banks BK#1 to BK#n except the memory bank BK#0 indicates the hit signals HIT1 and HIT2.

[0122] For example, when the number m+1 of load storage units LDST is less than the number n+1 of memory banks BK, configuration examples 3 to 6 can reduce the total number of main tag units MTAG and sub tag units STAG compared to configuration examples 1 and 2. For this reason, configuration examples 3 to 6 can further reduce the circuit scale of the processor compared to configuration examples 1 and 2.

[0123] exist Figure 12 In the configuration example 3 shown, a master tag unit MTAG is provided corresponding to each of the load storage units LDST. Figure 12 In the illustrated configuration example 4, the main tag unit MTAG is provided corresponding to the load store unit LDST#0, and the sub tag unit STAG is provided corresponding to each of the load store units LDST#1 to LDST#m.

[0124] exist Figure 13 In the configuration example 5 shown, a plurality of master tag units MTAG are provided. Figure 12 The configuration example shown can reduce the possibility of conflicts among multiple memory access requests in the main tag unit MTAG. Figure 13In configuration example 6, a sub-tag cell STAG is provided corresponding to each load-store cell LDST, and a main tag cell MTAG is provided independently of the multiple load-store cells LDST. Therefore, the sub-tag cells STAG and load-store cells LDST can be repeatedly arranged in pairs, and the design can be made by considering the symmetry of the circuit arrangement or layout. As a result, the layout design of the processor can be facilitated, and the electrical characteristics of the processor, such as frequency characteristics, can be improved.

[0125] Figure 1 or Figure 5 The sub-tag unit STAG shown in Figure 8 The sub-tag unit STAG2 shown in Figure 9 The sub-tag unit STAG3 shown in FIG can be used for the sub-tag unit STAG in each of the configuration examples 1, 2, and 4 to 6. Figure 9 When the sub-tag unit STAG3 is shown, the tag conversion part TCNV is provided independently of the sub-tag unit STAG3.

[0126] Figure 14 Shown according to Figure 12 An example of a processor of the configuration example 4 shown. In this embodiment, the same constituent elements as those of the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted. Figure 14 In the processor 100D shown, the main tag unit MTAG, the sub-tag unit STAG, and the multiplexer MUX1 are arranged between the load-store unit LDST and the switch 20D. To simplify the description, it is assumed that the processor 100D includes three load-store units LDST#1 to LDST#3, three sub-tag units STAG#1 to STAG#3, and four memory banks BK#0 to BK#3. Although not shown in FIG. Figure 14 As shown in FIG, however, the cache 60 has a function of transferring the load storage unit LDST and the main memory 50 from Figure 14 The elements shown are excluded from the configuration.

[0127] like Figure 12 As shown in the configuration example 4, the main tag unit MTAG is provided corresponding to the load storage unit LDST#0. Sub tag units STAG#1 to STAG#3 are provided corresponding to the load storage units LDST#1 to LDST#3 respectively. The memory access operation of the processor 100D is similar to Figure 7 The memory access operations shown in .

[0128] In addition to receiving the address AD from the load-store unit LDST and the memory bank address BA from the arbitration unit 10, the switch 20D also receives the index address IDX and hit signal HIT from the main tag unit MTAG, and the index address IDX and hit signals HIT1 and HIT2 from the sub-tag unit STAG. The switch 20D outputs the received index address IDX and hit signal HIT or hit signals HIT1 and HIT2 to the corresponding memory bank BK of the cache 60 according to the memory bank address BA. In addition, the switch 20D outputs the control signals for the main tag unit MTAG and the sub-tag unit STAG generated by the cache controller 40 to the main tag unit MTAG and the sub-tag unit STAG.

[0129] Figure 15 An example of a main tag unit MTAG and a sub tag unit STAG in a processor according to an eighth embodiment is shown. The main tag unit MTAG and the sub tag unit STAG can be shared among a plurality of memory banks BK. The processor 100E according to this embodiment includes: a main tag unit MTAG4, which is shared by a pair of mutually adjacent memory banks BK; and a sub tag unit STAG4, which is shared by another pair of mutually adjacent memory banks BK in addition to the pair of mutually adjacent memory banks BK shared by the main tag unit MTAG4. In the processor 100E, the configuration not including the main tag unit MTAG4 and the sub tag unit STAG4 is similar to Figure 5 The configuration of processor 100A is shown. Figure 15 An example is shown in which the main tag unit MTAG is shared by a pair of mutually adjacent memory bodies BK, and the sub tag unit STAG is shared by another pair of mutually adjacent memory bodies BK, but each of the main tag unit MTAG and the sub tag unit STAG can be shared among any memory body BK.

[0130] For example, the main tag unit MTAG4 outputs a hit signal HIT for the memory banks BK#0 and BK#1. The sub-tag unit STAG4 outputs hit signals HIT1 and HIT(HIT2) for the memory banks BK#2 and BK#3. In the case where the processor 100E includes eight memory banks BK#0 to BK#7, sub-tag units STAG4 corresponding to the memory banks BK#4 and BK#5 and sub-tag units STAG4 corresponding to the memory banks BK#6 and BK#7 may be provided.

[0131] For example, the main tag unit MTAG4 is a multi-port type and can simultaneously receive the tag address TAG and index address IDX output from the two load-store units LDST. In addition, the main tag unit MTAG4 can output hit signals HIT corresponding to the two load-store units LDST independently of each other.

[0132] The sub-tag unit STAG4 is a multi-port type and can simultaneously receive the tag address TAG (TAG1, TAG2) and index address IDX output from the load-store unit LDST. In addition, the sub-tag unit STAG4 can output hit signals HIT1 and HIT (HIT2) corresponding to the two load-store units LDST independently of each other.

[0133] In this embodiment, a multi-port type main tag unit MTAG 4 and a multi-port type sub-tag unit STAG 4 are provided. For this reason, Figure 5 Compared with the total number of main tag units MTAG and sub-tag units STAG shown in FIG, the total number of main tag units MTAG4 and sub-tag units STAG4 can be reduced. Therefore, the circuit scale of main tag units MTAG4 and sub-tag units STAG4 can be reduced, thereby reducing the circuit scale of processor 100E.

[0134] The processor 100E may include Figure 15 The main tag unit MTAG 4 shown and Figure 5 In addition, the processor 100E may include Figure 5 The main tag unit MTAG and Figure 15 The sub-tag unit STAG4 is shown. In addition, the main tag unit MTAG4 can be arranged to replace the other main tag units MTAG in each of the above embodiments. The sub-tag unit STAG4 can be arranged to replace the other sub-tag units STAG, STAG2 and STAG3 in each of the above embodiments.

[0135] Can provide Figure 15 The main tag unit MTAG4 shown is used instead Figure 11 The configuration example shown in 1, Figure 12 Configuration examples 3 and 4 shown in Figure 13 The master tag unit MTAG in any one of the configuration examples 5 shown in FIG. Figure 15 The sub-tag unit STAG4 shown is replaced Figures 11 to 13 The sub-tag unit STAG in any one of the configuration examples 1 to 6 shown.

[0136] As described above, in this embodiment, effects similar to those obtainable in the above embodiment can be obtained. In this embodiment, the circuit scale of the processor 100E can be reduced by providing at least one of the multi-port type main tag unit MTAG4 and the multi-port type sub tag unit STAG4.

[0137] Figure 16Examples of tag array / data array ratios for each configuration of the cache are shown. Figure 16 shows a case where only the tag array TGA is used without Figure 1 The example of tag array cache TGAC is shown in the following. Figure 17 Reference numeral (A) indicating a cache line size is used in the description of FIG.

[0138] When a tag array TGA is provided corresponding to each of the memory banks BK, the ratio of the tag array TGA to the data array DTA for each memory bank BK becomes higher as the number of memory banks BK increases, and becomes higher as the cache line size becomes smaller. The ratio of the tag array TGA to the data array DTA becomes higher as the number of ways increases, and becomes higher as the number of bits F of the physical address increases. The number of bits (a) of the tag array TGA can be expressed by the following formula (1).

[0139] (a) = F + log2(number of ways) - log2(cache size) --- (1)

[0140] Furthermore, the ratio of the tag array TGA to the data array DTA becomes higher as the cache size decreases.

[0141] Figure 17 An example of the effect of improving the tag array / data array ratio when a tag array cache is provided is shown. Figure 16 In the cache configuration shown (A), the tag array / data array ratio is 56.3%. Figure 1 In the cache configuration shown, the tag array / data array ratio can be reduced to 16.9%, which is approximately Figure 16 The configuration (A) shown has a tag array / data array ratio of 1 / 3. In addition, when using the tag array cache TGAC Figure 12 In the configuration of the cache of Configuration Example 4 described above, the tag array / data array ratio can be reduced to 9.1%, which is approximately Figure 16 The configuration shown in (A) has a label array / data array ratio of 1 / 6.

[0142] According to the above-described embodiment, it is possible to reduce a ratio of the size of a determination unit that determines a cache hit of a cache including a plurality of memory banks relative to the size of the cache.

[0143] Although the embodiments are numbered, for example, as "first," "second," "third," ... and "eighth," the ordinal numbers do not imply priority of the embodiments. Many other variations and modifications will be apparent to those skilled in the art.

[0144] All examples and conditional language described herein are intended to be used for the purpose of teaching to help the reader understand the present invention and the concepts contributed by the inventor to promote this field, and should be interpreted as not being limited to such specific examples and conditions, and the organization of such examples in the specification is not related to the illustration of the advantages and disadvantages of the present invention. Although the embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions and modifications can be made thereto without departing from the spirit and scope of the present invention.

Claims

1. A processor, comprising: a plurality of request issuing units, each request issuing unit being configured to issue a memory access request to a storage device; a data array comprising a plurality of memory banks, each memory bank being configured to store sub-data divided from data read from the storage device based on the memory access request; a switch for transmitting the memory access request to one of the plurality of memory banks; at least one first determining unit including a first saving unit that saves, for each value of an index address in an access address included in the memory access request, a tag address included in the access address, and configured to: determine a cache hit when the tag address included in the access address matches the tag address saved in the first saving unit corresponding to the index address included in the access address, wherein the cache hit indicates that access target data is saved in the data array; at least one second determining unit, comprising a second storing unit, wherein the second storing unit stores, for each value of the index address, identification information identifying a first tag address included in the tag address and a second tag address included in the tag address, and the at least one second determining unit is configured to: determine a cache hit when the identification information corresponding to the first tag address included in the access address and the second tag address included in the access address match the identification information and the second tag address stored in the second storing unit corresponding to the index address included in the access address, respectively; as well as A cache controller is configured to access the data array or the storage device based on a determination result of the first determination unit or the second determination unit.

2. The processor according to claim 1, wherein: The second determining unit includes a third storing unit, wherein the third storing unit includes a plurality of entries storing the first tag address. The identification information for identifying the first tag address is identification information for identifying an entry of the third storage unit, and The second determination unit determines a cache hit when the identification information identifying the entry of the third saving unit storing the first tag address included in the access address and the second tag address included in the access address are stored in the second saving unit in correspondence with the index address included in the access address.

3. The processor according to claim 2, wherein: The third storage unit is provided in common to a plurality of second determination units.

4. The processor according to claim 2, wherein: When the first tag address included in the access address is not held in the third holding unit, the cache controller causes the first determination unit to determine the cache hit based on the access address.

5. The processor according to any one of claims 1 to 4, wherein: The second storage unit stores, for each value of the index address, a flag indicating that the identification information therein is valid.

6. The processor according to any one of claims 1 to 4, wherein: The first determination unit and the second determination unit receive the memory access request from each of the plurality of request issuing units via the switch.

7. The processor according to claim 6, wherein: The first determining unit is provided corresponding to each of the plurality of memory banks, and The second determining unit is provided corresponding to a memory bank that does not correspond to the first determining unit.

8. The processor according to claim 6, wherein: providing the first determining unit independently of the plurality of memory banks, and The second determining unit is provided corresponding to each of the plurality of memory banks.

9. The processor according to claim 6, wherein: The second determining unit is shared by two or more memory banks among the plurality of memory banks, and The first determination unit is provided corresponding to at least one memory bank among the plurality of memory banks except the two or more memory banks shared by the second determination unit.

10. The processor according to claim 6, wherein: The first determining unit is shared by two or more memory banks among the plurality of memory banks, and The second determination unit is provided corresponding to at least one memory bank among the plurality of memory banks except the two or more memory banks shared by the first determination unit.

11. The processor according to claim 9, wherein: The first determining unit is shared by two or more memory banks among the plurality of memory banks, and The second determination unit is provided corresponding to at least one memory bank among the plurality of memory banks except the two or more memory banks shared by the first determination unit.

12. The processor according to any one of claims 1 to 4, wherein: The first determination unit and the second determination unit receive the memory access request from each of the plurality of request issuing units before the memory access request is provided to the switch.

13. The processor according to claim 12, wherein: The first determining unit is provided corresponding to two or more request issuing units among the plurality of request issuing units, and The second determining unit is provided corresponding to a request issuing unit that does not correspond to the first determining unit.

14. The processor of claim 12, wherein: providing the first determining unit independently of the plurality of request issuing units, and The second determining unit is provided corresponding to each of the plurality of request issuing units.

15. The processor of claim 12, wherein: The second determining unit is shared by a pair of mutually adjacent request issuing units among the plurality of request issuing units, and The first determination unit is provided corresponding to at least one request issuing unit among the plurality of request issuing units except the pair of mutually adjacent request issuing units that share the second determination unit.

16. The processor of claim 12, wherein: The first determining unit is shared by a pair of mutually adjacent request issuing units among the plurality of request issuing units, and The second determination unit is provided corresponding to at least one request issuing unit among the plurality of request issuing units except the pair of mutually adjacent request issuing units sharing the first determination unit.

17. A calculation processing method, implemented in a processor, the processor comprising: a plurality of request issuing units, each request issuing unit being configured to issue a memory access request to a storage device; a data array comprising a plurality of memory banks, each memory bank being configured to store sub-data divided from data read from the storage device based on the memory access request; and a switch for transmitting the memory access request to one of the plurality of memory banks, the operation processing method comprising: determining, by at least one first determination unit of the processor, a cache hit when a tag address included in an access address included in the memory access request matches a tag address stored in a first storage unit corresponding to an index address included in the access address, wherein the cache hit indicates that access target data is stored in the data array, wherein the at least one first determination unit includes the first storage unit that stores the tag address included in the access address for each value of the index address in the access address; determining, by at least one second determining unit of the processor, a cache hit when identification information corresponding to a first tag address included in the access address and a second tag address included in the access address match identification information and a second tag address stored in a second storage unit corresponding to the index address included in the access address, respectively, wherein the at least one second determining unit includes the second storage unit that stores, for each value of the index address, the identification information identifying the first tag address included in the tag address and the second tag address included in the tag address; as well as The cache controller of the processor accesses the data array or the storage device based on the determination result of the first determination unit or the second determination unit.

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