Liquid crystal display device, display drive amplification circuit, and display drive amplification method

Abstract

The application discloses a liquid crystal display device, a display driving amplification circuit and a display driving amplification method. The display driving amplification circuit comprises: an input module configured to generate an input current in response to a voltage difference between input signals; a first transistor connected between a power supply end and an output node and a second transistor connected between the output node and a ground end; an amplification module configured to output a first control voltage for controlling a current flowing in the first transistor and a second control voltage for controlling a current flowing in the second transistor in response to the input current; and a pre-charge module connected between the amplification module and the output module, comprising a compensation capacitor for stabilizing a frequency characteristic of an output signal of the output node and a plurality of switch tubes, wherein the pre-charge module is configured to disconnect the compensation capacitor from a loop and pre-charge the compensation capacitor in a first time period in a driving amplification period. The display driving amplification circuit achieves fast response.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of liquid crystal display, and in particular to a liquid crystal display device, a display driving amplification circuit and a display driving amplification method. BACKGROUND

[0002] A liquid crystal display device is a display device that changes the light transmittance of a light source by using the phenomenon that the arrangement direction of liquid crystal molecules changes under an electric field. The liquid crystal display device has been widely applied to mobile terminals such as mobile phones and large-size display panels such as flat panel televisions. In the liquid crystal display device, a thin film transistor is usually selected through a gate scanning line, and a voltage corresponding to a gray scale is applied to a pixel capacitor C LC , so as to change the orientation of the liquid crystal molecules to achieve the brightness of the corresponding gray scale.

[0003] In the process in which the source driver applies the gray scale voltage to the pixel capacitor C LC , a display driving amplifier needs to provide a fast and stable voltage signal for the screen to ensure correct display of the screen, and therefore a driving amplification circuit with stable and fast response performance is a crucial core module in a display driving chip. In actual applications, with the gradual increase of the screen resolution and the refresh frequency, the equivalent electrical load of the screen is greatly increased, and the demand for the response time of the output signal of the display driving amplifier is further reduced. Due to the limitation of the conversion rate of the traditional display driving amplifier, it is difficult to meet the existing demand. SUMMARY

[0004] In view of the above problems, the purpose of the present application is to provide a liquid crystal display device, a display driving amplification circuit and a display driving amplification method, so as to improve the response speed of the display driving amplifier.

[0005] According to an aspect of the present application, a display driving amplification circuit is provided, comprising:

[0006] An input module configured to generate an input current in response to a voltage difference between input signals;

[0007] An output module comprising a first transistor connected between a power supply end and an output node and a second transistor connected between the output node and a ground end;

[0008] An amplification module configured to output a first control voltage for controlling a current flowing in the first transistor and a second control voltage for controlling a current flowing in the second transistor in response to the input current;

[0009] a pre-charge module connected between the amplification module and the output module, the pre-charge module comprising a compensation capacitor for stabilizing the output signal frequency characteristic of the output node, and a plurality of switch tubes,

[0010] The pre-charge module is configured to disconnect the compensation capacitor from the loop of the display driving amplification circuit and pre-charge the compensation capacitor in a first time period in a driving amplification cycle through the plurality of switch tubes.

[0011] Preferably, the pre-charge module is configured to connect the compensation capacitor to the loop of the display driving amplification circuit in a second time period in the driving amplification cycle through the plurality of switch tubes.

[0012] Preferably, the plurality of switch tubes comprises a first group of switch tubes, a second group of switch tubes, and a third group of switch tubes, the first group of switch tubes and the second group of switch tubes being controlled by a first control signal and a first complementary signal respectively, and the third group of switch tubes being controlled by a second control signal.

[0013] Preferably, the amplification module comprises a first common gate load, a diode-connected load, and a second common gate load cascaded in sequence between a power supply terminal and a ground terminal.

[0014] Preferably, the first group of switch tubes comprises:

[0015] a first switch tube connected between the first common gate load and the compensation capacitor;

[0016] a third switch tube connected between the second common gate load and the compensation capacitor;

[0017] a fifth switch tube connected between the diode-connected load and the gate of the first transistor;

[0018] a seventh switch tube connected between the diode-connected load and the gate of the second transistor;

[0019] The second group of switch tubes comprises:

[0020] a second switch tube connected between the power supply terminal and the compensation capacitor;

[0021] a fourth switch tube connected between the ground terminal and the compensation capacitor;

[0022] a sixth switch tube connected between the power supply terminal and the gate of the first transistor;

[0023] an eighth switch tube connected between the ground and the gate of the second transistor;

[0024] a tenth switch connected between the intermediate node of the compensation capacitor and the output node;

[0025] The third group of switches comprises:

[0026] a ninth switch connected between the input signal terminal and the output node.

[0027] Preferably, during the first time period, the first complementary control signal is active and the second control signal is inactive, and during the second time period, the first complementary control signal is active and the second control signal is active.

[0028] Preferably, the drive amplification period further comprises a third time period before the second time period, during which the first control signal and the second control signal are both changed from inactive to active, wherein the first control signal has a rising edge earlier than that of the second control signal.

[0029] According to another aspect of the present application, there is provided a display drive amplification method, comprising:

[0030] generating an input current in response to a voltage difference between input signals;

[0031] outputting a first control voltage for controlling a current flowing in a first transistor and a second control voltage for controlling a current flowing in a second transistor in response to the input current;

[0032] disconnecting the compensation capacitor from a loop of the display drive amplification circuit during a first time period in a drive amplification period and pre-charging the compensation capacitor through the switches.

[0033] Preferably, the display drive amplification method further comprises connecting the compensation capacitor to the loop of the display drive amplification circuit during a second time period in the drive amplification period through the switches.

[0034] According to still another aspect of the present application, there is provided a display device comprising the display drive amplification circuit as described above.

[0035] The display drive amplification circuit provided by the present application charges the compensation capacitor Cc when the output is in a high impedance state, and reconnects the compensation capacitor Cc to the loop of the display drive amplification circuit during the PH2 time period when the display drive amplification circuit is in a closed loop state. Since the compensation capacitor Cc has been pre-charged during the PH1 period, the output of the display drive amplification circuit can be established in a very short time, avoiding the influence of the charging process of the compensation capacitor Cc on the conversion rate of the display drive amplification circuit itself, and achieving fast response.

[0036] In the preferred embodiment, the time when the compensation capacitor Cc finishes charging the pre-charge period can be controlled to be earlier than the time when the compensation capacitor Cc is reconnected into the loop of the display drive amplification circuit, so as to achieve the best performance of the display drive amplification circuit. BRIEF DESCRIPTION OF DRAWINGS

[0037] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0038] Figure 1 An equivalent circuit diagram of a liquid crystal display device provided by an embodiment of the present application is shown;

[0039] Figure 2 An internal circuit structure schematic diagram of a source driver provided by an embodiment of the present application is shown;

[0040] Figure 3 A schematic diagram of a display drive amplification circuit of the prior art is shown;

[0041] Figure 4 A schematic diagram of a display drive amplification circuit provided by an embodiment of the present application is shown;

[0042] Figure 5a A timing diagram of control signals of a display drive amplification circuit provided by an embodiment of the present application is shown;

[0043] Figure 5b A timing diagram of control signals of a display drive amplification circuit provided by an embodiment of the present application is shown;

[0044] Figure 6 A comparison schematic diagram of signal conversion in a display drive amplification circuit of the present application and the prior art is shown. DETAILED DESCRIPTION

[0045] Various embodiments of the present application will be described in detail with reference to the drawings, below. In the various drawings, the same elements or modules are denoted by the same or similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale.

[0046] It should be understood that, in the following description, "circuitry" can include a single or multiple components of hardware, programmable circuitry, state machine circuitry, or elements that store instructions for execution by programmable circuitry. When an element or circuitry is referred to as being "connected to" another element or "connected between" two nodes, it can be directly coupled or connected to the other element or there can be intervening elements between the elements, the connection between the elements can be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it implies that there are no intervening elements.

[0047] Also, certain terms have been used herein for brevity, clarity and understanding. However, no limitation of the scope of embodiments to which such terms as used can suggest themselves. In this specification and in the claims that follow, unless the context requires otherwise, the word "comprise", and variations such as "comprises" and "comprising", will be understood to mean the inclusion of almost-all-stated and / or generally-implies elements or steps or the exclusion of some stated elements or steps or the inclusion of almost-all-stated elements or steps or the exclusion of some stated elements or steps but permits the inclusion or exclusion of other stated or unstated elements or steps.

[0048] Furthermore, the terms "first" and "second" are used herein only to differentiate one from another entity or action, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "include", "have", or any other similar terms are intended to encompass non-exclusive inclusions, such that a process, method, article, or apparatus that includes a list of elements is not limited to those elements, but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a... " does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0049] Figure 1 An equivalent circuit diagram of the liquid crystal display device provided by the embodiments of the present application is shown;

[0050] As shown in Figure 1 , the liquid crystal display includes a liquid crystal panel 110, source drivers 120 each having a plurality of source lines Sn, and a plurality of gate drivers 130 each having a plurality of gate lines Gn. The source lines are also referred to as data lines or data channels. Each source driver 120 drives a source line Sn provided on the liquid crystal panel 110; each gate driver 130 drives a gate line Gn provided on the liquid crystal panel 110.

[0051] The liquid crystal panel 110 includes a plurality of pixels 111. Each pixel 111 includes a switching transistor T, a storage capacitor Cs for reducing current leakage from the liquid crystal, and a liquid crystal capacitor C LC . The switching transistor T is turned on or off in response to a signal driving the gate line Gn, and a first input terminal of the switching transistor T is connected to the source line Sn, the storage capacitor Cs is connected between a second input terminal of the switching transistor T and a ground voltage VSS, and the liquid crystal capacitor C LC is connected between the second input terminal of the switching transistor T and a common voltage VCOM. Exemplarily, the common voltage VCOM can be half of the above-mentioned power supply voltage VDD.

[0052] The source driver 120 selects the switching transistor T through a gate scanning line, and the gate driver 130 applies a voltage corresponding to a gray scale to the pixel capacitor C through a source data line.LC , so as to change the orientation of liquid crystal molecules to achieve the brightness of the corresponding gray scale.

[0053] Figure 2 A schematic diagram of an internal circuit structure of a source driver provided by an embodiment of the present application is shown. The source driver 200 includes a digital-to-analog converter (DAC) 121, and display drive amplification circuits 122.

[0054] The digital-to-analog converter 121 converts digital image signals into analog image signals (A_DATA1, A_DATA2,..., A_DATAn) and outputs them, each of the analog image signals A_DATA1, A_DATA2,..., A_DATAn representing a gray scale voltage.

[0055] Each of the display drive amplification circuits 122 amplifies a corresponding one of the analog video signals (A_DAT1, A_DAT2,..., A_DATn) and transmits it to a corresponding source line as a source drive signal (one of Y1, Y2,..., Yn), which is provided to a load LD connected to the source line. The load LD can be modeled as a series combination of an equivalent resistance load RL and a capacitance load CL representing an off-screen screen.

[0056] Not shown in the figure, the digital-to-analog converter (DAC) 121 and the display drive amplification circuits 122 can further include output switches and charge sharing switches, and the analog video signal amplified by each of the display drive amplification circuits 122 is transmitted to a corresponding one of the output switches. The output switch outputs the amplified analog image signal as a source drive signal (one of Y1, Y2,..., Yn) in response to an output switch control signal. The charge sharing switch is used to share the charge stored in the loads connected to all the source lines, so as to convert the voltage of the source line drive signal into a predetermined precharge voltage (Precharge with precharge). The precharge voltage is set when the voltage polarities of adjacent source line drive signals are opposite to each other, for example, when the voltage of the first source line drive signal Y1 has a positive polarity voltage between VDD and VDD / 2, and the voltage of the second source line drive signal Y2 has a negative polarity voltage between VDD / 2 and VSS, the precharge voltage can be VDD / 2. This charge sharing method is mainly used for source drivers driving large liquid crystal panels, so as to alleviate the current supply burden of the display drive amplification circuits 122.

[0057] Figure 3 A schematic diagram of a display drive amplification circuit of the prior art is shown;

[0058] As Figure 3As shown, the prior art display drive amplification circuit 122 has an input module 10, an amplification module 20, and an output module 30. The specific circuit structure of each module in the prior art display drive amplification circuit 122 is well known to those skilled in the art, and will not be described here.

[0059] The input module 10 provides an input signal for the amplification module 20, the amplification module 20 provides high gain for amplifying the analog video signal to achieve high-precision voltage output; the output module 30 is used to output a source line driving signal in response to the signal amplified by the amplification module 20.

[0060] The output module 30 includes two capacitors Cc for stabilizing the frequency characteristics of the output signal, i.e., the capacitors Cc control the output signal OUT of the display drive amplification circuit 122 from oscillating, and the unit composed of the two capacitors Cc is also called a Miller compensation capacitor unit. The slew rate (SR) of the output voltage of the display drive amplification circuit is related to the capacitance value of the capacitor Cc.

[0061] The display drive amplification circuit of the prior art is limited by its own slew rate, and it is difficult to meet the demand for response time of the output signal.

[0062] Figure 4 A schematic diagram of the display drive amplification circuit provided by the embodiments of the present application is shown;

[0063] As Figure 4 shown, the display drive amplification circuit 122 provided by the embodiments of the present application has an input module 10, an amplification module 20, an output module 30, and a pre-charge module 40.

[0064] The input module 10 includes transistors Mn10 to Mn12, and the transistors Mn10 and Mn11 accept complementary first and second input signals Vinp and Vinn. The first input signal Vinp is connected to the gate of the transistor Mn10 as a positive input of the display drive amplification circuit 122, and the second input signal Vinn is connected to the gate of the transistor Mn11 as a negative input of the display drive amplification circuit 122. The transistor Mn10 is connected to the ground through the transistor Mn12. The transistor Mn12 is used as a current source, and its gate is connected to the voltage Vb generated by the bias circuit to control the amount of input current provided to the amplification module 20 in response to the voltage Vb generated by the bias circuit.

[0065] The output module 30 includes a transistor Mp9 connected between the power supply end and the output node, and a transistor Mn9 connected between the ground end and the output node, and receives the output signal of the amplification module to generate the output signal OUT of the display drive amplification circuit 122, which corresponds to the source line driving signal.

[0066] The amplification module 20 is configured to output, in response to the input current, a first control voltage for controlling the current flowing in the transistor Mp9 and a second control voltage for controlling the current flowing in the transistor Mn9.

[0067] The amplification module 20 includes transistors Mp1 to Mp8 and transistors Mn1 to Mn8 as a folded cascode part, and receives the input current of the input module 10 to amplify the first input signal Vinp and the second input signal Vinn.

[0068] Wherein the transistor Mp1, transistor Mp2, transistor Mp3, transistor Mp4 constitute a P-type common-source common-gate load 201, the gate of transistor Mp3 and transistor Mp4 is connected to the first positive bias voltage Vbp1 generated by the bias circuit, and the common-source common-gate load 201 is connected between the diode-connected load 203 and the power supply terminal VDD.

[0069] The transistor Mn1, transistor Mn2, transistor Mn3, transistor Mn4 constitute an N-type common-source common-gate load 202, the gate of transistor Mn3 and transistor Mn4 is connected to the first negative bias voltage Vbn1 generated by the bias circuit, and the common-source common-gate load 201 is connected between the diode-connected load 203 and the ground terminal VSS.

[0070] The transistor Mp5, transistor Mp6, transistor Mn5, transistor Mn6 and transistor Mp7, transistor Mp8, transistor Mn7, transistor Mn8 constitute a diode-connected load 203, which is used to further increase the open-loop gain of the amplification module 20, wherein the gates of transistor Mp5, transistor Mp7, transistor Mn6, transistor Mn8 are connected to the second positive bias voltage Vbp2, the third positive bias voltage Vbp3, the second negative bias voltage Vbn2, and the third negative bias voltage Vbn3 generated by the bias circuit, respectively.

[0071] In the display driving amplification circuit 122, a pre-charge module 40 is further included between the output module 30 and the amplification module 20, connected between the amplification module and the output module, the pre-charge module 40 includes a compensation capacitor for stabilizing the output signal frequency characteristic of the output node, and a plurality of switch tubes. The pre-charge module 40 includes two compensation capacitors Cc and first to tenth switches S1-S10, wherein the first switch S1 is arranged between the common-source common-gate load 201 and the first compensation capacitor Cc; the second switch S2 is arranged between the power supply terminal VDD and the first compensation capacitor Cc; the third switch S3 is arranged between the common-source common-gate load 202 and the second compensation capacitor Cc; the fourth switch S4 is arranged between the ground terminal GND and the second compensation capacitor Cc; the fifth switch S5 is arranged between the gate of the transistor Mp9 and the diode-connected load 203; the sixth switch S6 is arranged between the gate of the transistor Mp9 and the power supply terminal VDD; the seventh switch S7 is arranged between the gate of the transistor Mn9 and the diode-connected load 203; the eighth switch S8 is arranged between the gate of the transistor Mn9 and the ground terminal GND; the ninth switch S9 is arranged between the output node Vout of the output module 30 and the intermediate node of the two compensation capacitors Cc; and the tenth switch S10 is arranged between the output node Vout of the output module 30 and the first input signal Vinp.

[0072] Wherein the first switch S1, the third switch S3, the fifth switch S5, and the seventh switch S7 are a group, and their states are controlled by the first control signal MUX; the second switch S2, the fourth switch S4, the sixth switch S6, the eighth switch S8, and the tenth switch S10 are a group, and their switch states are controlled by the first complementary control signal MUXB; and the ninth switch S9 is a group, and its switch state is controlled by the second control signal PRE.

[0073] In an embodiment, the first to tenth switches S1-S10 described above can be MOS switch tubes of the smallest size, the power supply voltage VDD is set to 7.6V, the transistor Mn is an N-type thin film transistor, and the transistor Pn is a P-type thin film transistor.

[0074] Figure 5a A control signal timing diagram of the display driving amplification circuit provided by the embodiment of the application is shown;

[0075] As shown in Figure 5a , when the first control signal MUX, the first complementary control signal MUXB, and the second control signal PRE are high, it indicates that the switch is turned on; correspondingly, if they are low, the switch is turned off.

[0076] In the PH1 period, the first complementary control signal MUXB is effective, the fifth switch S5, the seventh switch S7, and the ninth switch S9 are turned off, the sixth switch S6 and the eighth switch S8 are turned on, and meanwhile, the first switch S1 and the third switch S3 are turned off, the second switch S2, the fourth switch S4, and the tenth switch S10 are turned on; the two compensation capacitors Cc are connected between the power supply terminal VDD and the ground terminal GND, at this time, the compensation capacitors Cc are disconnected from the loop of the display driving amplification circuit 122, and both of the compensation capacitors Cc are in a pre-charging state.

[0077] In the PH2 period, the first control signal MUX and the second control signal PRE are effective, the first switch S1 and the third switch S3 are turned on, the second switch S2, the fourth switch S4, and the tenth switch S10 are turned off, and meanwhile, the fifth switch S5 and the seventh switch S7 are turned on, the sixth switch S6, the eighth switch S8, and the ninth switch S9 are turned off, at this time, the two compensation capacitors Cc are connected into the loop of the display driving amplification circuit 122, and the display driving amplification circuit 122 works normally.

[0078] In the PH1 period, when the display driving amplification circuit 122 is in a high resistance state, the compensation capacitors Cc are charged to the potential of Vinp, which is called pre-charging; in the PH2 period, when the display driving amplification circuit 122 is in a closed loop state, the compensation capacitors Cc are connected back into the loop of the display driving amplification circuit 122. Since the compensation capacitors Cc have been pre-charged to the potential of Vinp in the PH1 period, the output of the display driving amplification circuit 122 only needs a very short time to be established at this time, which avoids the influence of the charging process of the compensation capacitors Cc by the conversion rate of the display driving amplification circuit itself, and realizes fast response.

[0079] Figure 5b A timing diagram of control signals of the display driving amplification circuit according to another embodiment of the present application is shown;

[0080] As Figure 5b shown, in a preferred embodiment, a PH3 period is included between the PH1 period and the PH2 period, in which the first control signal MUX and the second control signal PRE are both changed from an ineffective state to an effective state, wherein the jumping edge of the first control signal MUX is earlier than the jumping edge of the second control signal PRE, so that the time when the display driving amplification circuit 122 is in a closed loop state is later than the time when the pre-charging of the compensation capacitors Cc is completed in the PH1 period, to realize the best performance of the display driving amplification circuit.

[0081] Figure 6 A comparison diagram of signal conversion in the display driving amplification circuit according to the present application and the prior art is shown.

[0082] As Figure 6As shown, the driving amplification circuit provided by the present application has faster response speed of screen load end signal establishment compared with the display driving amplification circuit in the prior art, and effectively improves the response time of the display driving amplification circuit output signal.

[0083] It should be noted that those skilled in the art can understand that the words "during", "when" and "when" related to the operation of the circuit used in this paper are not strict terms of action that occurs immediately at the start of the start action, but there may be some small but reasonable one or more delays between them and the reaction initiated by the start action, such as various transmission delays, etc. The use of the word "about" or "essentially" in this paper means that the element value has a parameter close to the declared value or position. However, as known in the art, there is always a slight deviation so that the value or position is difficult to be strictly the declared value. It has been properly determined in the art that a deviation of at least ten percent (10%) (at least twenty percent (20%) for semiconductor doping concentration) is a reasonable deviation from the described accurate ideal target. When used in conjunction with signal states, the actual voltage value or logic state of the signal (for example, "1" or "0") depends on whether positive logic or negative logic is used.

[0084] In accordance with the embodiments of the present application as described above, these embodiments do not describe all the details and are not limited to the specific embodiments. Obviously, according to the above description, many modifications and changes can be made. The present description selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well utilize the present application and make modifications and uses on the basis of the present application. The scope of protection of the present application should be limited by the scope of the claims of the present application and their equivalents.

Claims

1. A display driving amplification circuit, comprising: an input module configured to generate an input current in response to a voltage difference between input signals; an output module comprising a first transistor connected between a power supply terminal and an output node and a second transistor connected between a ground terminal and the output node; an amplification module configured to output, in response to the input current, a first control voltage for controlling a current flowing in the first transistor and a second control voltage for controlling a current flowing in the second transistor; a pre-charge module connected between the amplification module and the output module, the pre-charge module comprising a compensation capacitor for stabilizing an output signal frequency characteristic of the output node, and a first group of switch tubes, a second group of switch tubes and a third group of switch tubes, wherein, in a first time period in a driving amplification cycle, the pre-charge module is configured to: close the second group of switch tubes to connect the compensation capacitor between the power supply terminal and the ground terminal and open the first transistor and the second transistor to pre-charge the compensation capacitor; and open the first group of switch tubes and the third group of switch tubes to disconnect the amplification module from the compensation capacitor and the output module. 2.The display driving amplification circuit of claim 1, wherein, in a second time period in the driving amplification cycle, the pre-charge module is configured to: open the second group of switch tubes to disconnect the compensation capacitor from the power supply terminal and the ground terminal; and close the first group of switch tubes and the third group of switch tubes to connect the amplification module and the output module through the compensation capacitor. 3.The display driving amplification circuit of claim 2, wherein the first group of switch tubes and the second group of switch tubes are controlled by a first control signal and a first complementary signal respectively, and the third group of switch tubes is controlled by a second control signal. The amplification module comprises a first common-gate load, a diode-connected load and a second common-gate load cascaded in sequence between the power supply terminal and the ground terminal.

4. The display driver amplification circuit of claim 3, wherein, 5.The display driving amplification circuit of claim 4, wherein the first group of switch tubes comprises: a first switch tube connected between the first common-gate load and the compensation capacitor; a third switch tube connected between the second common-gate load and the compensation capacitor; a fifth switch tube connected between the diode-connected load and a gate of the first transistor; a seventh switch tube connected between the diode-connected load and a gate of the second transistor; the second group of switch tubes comprises: a second switch tube connected between the power supply terminal and the compensation capacitor; a fourth switch tube connected between the ground terminal and the compensation capacitor; a sixth switch tube connected between the power supply terminal and the gate of the first transistor; an eighth switch tube connected between the ground terminal and the gate of the second transistor; a tenth switch tube connected between an intermediate node of the compensation capacitor and the output node; the third group of switch tubes comprises: a ninth switch tube connected between an input signal terminal and the output node. ​ 6. The display driving amplification circuit of claim 3, wherein during the first time period, the first complementary control signal is active and the second control signal is inactive; and during the second time period, the first complementary control signal is active and the second control signal is active.

7. The display driver amplification circuit of claim 6, the driver amplification period further comprising a third time period prior to the second time period, during which the first control signal and the second control signal are both changed from an inactive state to an active state, wherein, The first control signal has a leading edge earlier than a leading edge of the second control signal.

8. A display drive amplification method, wherein, For controlling the display driving amplification circuit of any one of claims 1-7, comprising: generating an input current in response to a voltage difference between the input signals; outputting a first control voltage for controlling a current flowing in the first transistor and a second control voltage for controlling a current flowing in the second transistor in response to the input current; and closing the second set of switches to connect the compensation capacitor between the supply terminal and the ground terminal and opening the first transistor and the second transistor to pre-charge the compensation capacitor during the first time period in a driving amplification cycle, wherein the first set of switches and the third set of switches are also opened during the first time period to stop outputting the first control voltage to the first transistor and to stop outputting the second control voltage to the second transistor.

9. The display driving amplification method of claim 8, further comprising: opening the second set of switches to disconnect the compensation capacitor from the supply terminal and the ground terminal during the second time period in a driving amplification cycle, wherein the first set of switches and the third set of switches are also closed during the second time period to provide the first control voltage to the first transistor through the compensation capacitor and to provide the second control voltage to the second transistor through the compensation capacitor.

10. A display device comprising the display driving amplification circuit of any one of claims 1-7.

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