IC structure including a porous semiconductor layer under a channel isolation adjacent to a source / drain region

Abstract

The present disclosure relates to IC structures including a porous semiconductor layer located beneath a channel isolation proximate to a source / drain region. An integrated circuit (IC) structure includes an active device located above a bulk semiconductor substrate, and an isolation structure in the bulk semiconductor substrate surrounding the active device. The active device includes a semiconductor layer having a central region, a first end region laterally spaced apart from the central region by a first trench isolation, a second end region laterally spaced apart from the central region by a second trench, a gate located above the central region, and a source / drain region located in each of the first and second end regions. The isolation structure includes a polysilicon isolation layer located beneath the active device, a third trench isolation surrounding the active device, and a porous semiconductor layer located between the first trench isolation and the polysilicon isolation layer and between the second trench isolation and the polysilicon isolation layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to integrated circuit (IC) structures, and more particularly to IC structures (e.g., radio frequency switches) that include a porous semiconductor layer beneath a trench isolation proximate to a source / drain region to provide additional isolation for an active device. BACKGROUND

[0002] In integrated circuit (IC) structures, active devices are electrically isolated by dielectrics such as trench isolation. In radio frequency (RF) device applications such as switches, power amplifiers, and other devices, additional isolation layers that reduce harmonic and parasitic losses are advantageous. One current approach is to use a high-resistivity polysilicon isolation layer rich in traps between a buried insulator and a semiconductor substrate in a silicon-on-insulator (SOI) substrate. The high-resistance polysilicon isolation layer is located beneath an RF active device to provide additional isolation for the device. This approach is effective for SOI substrates. However, bulk semiconductor substrates that include a high-resistivity polysilicon isolation layer exhibit higher harmonic and substrate leakage currents than SOI substrates. SUMMARY

[0003] One aspect of the present disclosure relates to an integrated circuit (IC) structure, comprising: an active device located above a bulk semiconductor substrate, the active device including a semiconductor layer having a central region, a first end region laterally spaced apart from the central region by a first trench isolation, a second end region laterally spaced apart from the central region by a second trench isolation, a gate located above the central region, and a source / drain region located in each of the first end region and the second end region; and an isolation structure in the bulk semiconductor substrate surrounding the active device, the isolation structure including: a polysilicon isolation layer located beneath the active device, a third trench isolation surrounding the active device, and a porous semiconductor layer located between the first trench isolation and the polysilicon isolation layer and between the second trench isolation and the polysilicon isolation layer.

[0004] Another aspect of the present disclosure includes an integrated circuit (IC) structure comprising: an active device located above a bulk semiconductor substrate, the active device comprising a semiconductor layer having a center region, a first end region laterally spaced apart from the center region by a first trench isolation, a second end region laterally spaced apart from the center region by a second trench isolation, a gate located above the center region, and a raised source / drain region located above each of the first trench isolation and the second trench isolation; and an isolation structure in the bulk semiconductor substrate surrounding the active device, the isolation structure comprising: a polycrystalline isolation layer located below the active device, a third trench isolation surrounding the active device, and a porous semiconductor layer located between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer.

[0005] An aspect of the present disclosure relates to a method comprising: forming a semiconductor layer above a bulk semiconductor substrate, the semiconductor layer comprising a center region, a first end region laterally spaced apart from the center region by a first opening, and a second end region laterally spaced apart from the center region by a second opening, wherein a protective cap layer extends above the center region, the first end region, and the second end region; forming a porous semiconductor layer in an exposed region of the bulk semiconductor substrate through the first opening and the second opening and adjacent to the first end region and the second end region; forming an insulator above the semiconductor layer to form a first trench isolation and a second trench isolation in the first opening and the second opening and to form a third trench isolation around the semiconductor layer; forming a polycrystalline isolation layer below the semiconductor layer; and forming an active device having the semiconductor layer.

[0006] The above-described and other features of the present disclosure will become apparent from the following more detailed description of the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0007] Embodiments of the present disclosure will be described in detail with reference to the following drawings, wherein like reference numerals indicate like elements, and wherein:

[0008] Figure 1 A cross-sectional view of an integrated circuit (IC) structure is shown in accordance with embodiments of the present disclosure.

[0009] Figures 2-8 A cross-sectional view of a method of forming an IC structure is shown in accordance with embodiments of the present disclosure.

[0010] Figure 9 and Figure 10 A cross-sectional view of a method of forming an IC structure is shown in accordance with embodiments of the present disclosure.

[0011] Figures 11-12A cross-sectional view of forming an IC structure is shown in accordance with another alternative embodiment of the present disclosure.

[0012] Note that the drawings of the present disclosure are not necessarily to scale. The drawings are intended to depict only typical aspects of the disclosure and therefore should not be considered as limiting the scope of the disclosure. In the drawings, like reference numerals indicate like elements among the drawings. DETAILED DESCRIPTION

[0013] In the following description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific exemplary embodiments in which the teachings can be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the teachings, and it is to be understood that other embodiments can be utilized and that changes can be made without departing from the scope of the present teachings. The following description is, therefore, not to be taken in a limiting sense.

[0014] It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or "over" another element, it can be directly on the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0015] References in the specification to “one embodiment” or “an embodiment” of the disclosure, or to “the” embodiment, and other variations thereof, mean that a particular feature, structure, characteristic, and so forth being described is included in at least one embodiment of the disclosure. Therefore, the phrase “in one embodiment” or “in an embodiment,” as well as any other variations thereof, are not necessarily referring to the same embodiment. It is appreciated that, for example, in the case of “A / B,” “A and / or B,” and “at least one of A and B,” any of these alternatives can be used with respect to each other. As another example, in the case of “A, B, and / or C” and “at least one of A, B, and C,” these phrases are intended to cover any of the following alternatives: only A, only B, only C, only A and B, only A and C, only B and C, or A and B and C. As will be apparent to those of ordinary skill in the art, this list of alternatives can be expanded to the case of any number of items.

[0016] Embodiments of the disclosure include an integrated circuit (IC) structure including an active device located over a bulk semiconductor substrate, and an isolation structure in the bulk semiconductor substrate surrounding the active device. The active device includes a semiconductor layer having a center region, a first end region laterally spaced apart from the center region by a first trench isolation, and a second end region laterally spaced apart from the center region by a second trench isolation. The active device also includes a gate over the center region, and a source / drain region in each of the first and second end regions or a raised source / drain region over the first and second trench isolations. The isolation structure includes a polycrystalline isolation layer located under the active device, a third trench isolation surrounding the active device, and a porous semiconductor layer between the first trench isolation and the polycrystalline isolation layer and between the second trench isolation and the polycrystalline isolation layer. The IC structure employs a lower cost low resistivity bulk semiconductor substrate instead of a semiconductor-on-insulator (SOI) substrate, and it has better radio frequency (RF) device performance characteristics than the SOI substrate. For example, the IC structure with the porous semiconductor layer under the trench isolation adjacent to the source / drain region exhibits better current leakage, harmonic distortion, cross-talk resistance, effective resistivity, effective dielectric constant, and attenuation than current SOI substrate devices.

[0017] Figure 1A cross-sectional view of an IC structure 100 according to embodiments of the present disclosure is shown. The IC structure 100 includes an active device 102 located above a bulk semiconductor substrate 104. The bulk semiconductor substrate 104 includes a low-resistivity semiconductor material that is relatively inexpensive to produce compared to a higher-resistivity SOI substrate. As described herein, the bulk semiconductor substrate 104 can include any semiconductor material that can be made porous, including but not limited to silicon. The bulk semiconductor substrate 104 is single crystalline. Portions or all of the bulk semiconductor substrate 104 can be strained.

[0018] The active device 102 can include any transistor now known or later developed. The IC structure 100 can have a variety of applications. For example, as described herein, it is found to be advantageous to use as a radio frequency (RF) switch 200 Figure 1 、 10 , 11). The active device 102 can include a semiconductor layer 106 having a central region 108, a first end region 110 laterally spaced apart from the central region 108 by a first trench isolation 112, a second end region 114 laterally spaced apart from the central region 108 by a second trench isolation 116. For example, the active device 102 can also include a gate 120 located above the central region 108, and source / drain regions 122S, 122D located in each of the first and second end regions 110, 114, respectively. Here, the central region 108 provides a channel region 124 for the active device 102. The source / drain regions 122S, 122D can include any suitable dopant located within the end regions 110, 114. The gate 120 can be a metal or polysilicon gate, and can include one or more conductive components for providing a transistor gate terminal. For example, the metal gate 120 can include a high dielectric constant (high-K) layer, a work function metal layer, and a gate conductor (not shown for clarity). A gate cap (not shown) can also be formed over the gate 120.

[0019] The gate dielectric layer 128 can include any gate dielectric material now known or later developed, such as but not limited to hafnium silicate (HfSiO), hafnium oxide (HfO2), zirconium silicate (ZrSiO x ), zirconium oxide (ZrO2), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k material, or any combination of these materials. The spacer 126 can include any spacer material now known or later developed, such as silicon nitride. A silicide layer 130 for contacts (not shown) can be provided over the source / drain 122S in the first end region 110 and the first trench isolation 112, and over the source / drain 122D in the second end region 114. The silicide layer 130 can also be provided over the gate 120.

[0020] In some embodiments, semiconductor layer 106 may include a semiconductor epitaxial layer in which source / drain regions 122S, 122D are formed. (Although the source / drain regions are indicated by reference numerals 122S, 122D, the location of the source or drain may differ from the location inferred from the letter symbols). Semiconductor layer 106 has a higher resistivity than the bulk semiconductor substrate 104. Therefore, the central region 108, the first end region 110, and the second end region 114 have higher resistivity than the bulk semiconductor substrate 104. In one example, the resistivity of the bulk semiconductor substrate 104 may be less than about 4.0 ohms per square centimeter (Ω / cm). 2 Furthermore, the resistivity of the central region 108, the first end region 110, and the second end region 114 can be greater than approximately 1000 Ω / cm. 2 The terms “epitaxy” and “epitaxy formation and / or growth” mean that the growth of semiconductor material on the deposition surface of the bulk semiconductor substrate 104 can have the same crystal properties as the semiconductor material on the deposition surface. During epitaxial growth, the chemical reactants provided by the source gas are controlled, and the system parameters can be set such that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy, thereby moving around on the surface and orienting themselves into a crystal arrangement of the deposited surface atoms.

[0021] The IC structure 100 also includes an isolation structure 140 surrounding the active device 102 in a bulk semiconductor substrate 104. The isolation structure 140 may include a polycrystalline isolation layer 142 located below the active device 102. As shown, a semiconductor layer 106 is located above the polycrystalline isolation layer 142. As will be described herein, the polycrystalline isolation layer 142 can be formed by introducing inert gas ions into the bulk semiconductor substrate 104 and then annealing. In one example, the resistivity of the bulk semiconductor substrate 104 may be less than about 4.0 Ω / cm. 2 Furthermore, the resistivity of the polycrystalline isolation layer 142 (and the semiconductor layer 106) can be greater than approximately 1000 Ω / cm. 2 Therefore, the polycrystalline isolation layer 142 exhibits a higher resistance compared to the bulk semiconductor substrate 104, and thus serves as the underside of the electrically isolated active device 102.

[0022] The isolation structure 140 also includes a third trench isolation 144 that surrounds the active device 102. The trench isolations (TIs) 112, 116, 144 include trenches etched into the semiconductor layer 106 and / or the bulk semiconductor substrate 104 and filled with an insulator. The TIs 112, 116, the end regions 110, 114, and the TI 144 isolate the active device 102 from adjacent regions of the substrate. Thus, as will be described, the TIs 112, 116, 144 can be formed simultaneously. As will also be described, a porous semiconductor layer 146 is formed in portions of the bulk semiconductor substrate 104 prior to forming the TIs 112, 116, 144, and thus is located beneath the first TI 112, the second TI 116, and the third TI 144. Each of the TIs 112, 116, 144 can be formed of an electrical insulator, for example, can include: silicon nitride (Si3N4), silicon oxide (SiO2), fluorinated SiO2(FSG), hydrogenated carbon-oxide silicon (SiCOH), borophosphosilicate glass (BPSG), silsesquioxane, carbon (C) doped oxides including atoms of silicon (Si), carbon (C), oxygen (O), and / or hydrogen (H) (i.e., organosilicates), thermoset poly(arylene ether), spin-on silicon-containing carbon polymer materials, near frictionless carbon (NFC), or layers constructed therefrom. The TIs 112, 116, 144 can be provided as shallow trench isolations (STIs) (shown) or deep trench isolations (DTIs). The first and second TIs 112, 116 separate the end regions 110, 114 from the center region 108, i.e., linearly into and out of the page. The third TI 144 surrounds the active device 102, and thus also couples with the ends of the first and second TIs 112, 116 at locations into and out of the page.

[0023] The isolation structure 140 also includes a porous semiconductor layer 146 between the first trench isolation 112 and the polysilicon isolation layer 142 and between the second trench isolation 116 and the polysilicon isolation layer 142. Notably, the porous semiconductor layer 146 includes portions 148, 150 between the respective trench isolations 112, 116. The portions 148, 150 are separated by a portion 152 of the bulk semiconductor substrate 104. Optionally, the porous semiconductor layer 146 can also include a portion 154 between the third trench isolation 144 and the bulk semiconductor substrate 104. The porous semiconductor layer 146 provides additional electrical resistance to electrically isolate the active devices 102 from the bulk semiconductor substrate 104. The porous semiconductor layer 146 allows the IC structure 100 to have as good or better electrical isolation as IC structures built on more expensive high-resistivity SOI substrates. The porous semiconductor layer 146 can include the same material as the bulk semiconductor substrate 104, but is made porous as described herein. In one example, the porous semiconductor layer 146 and the bulk semiconductor substrate 104 can include silicon (Si). In one example, the porous semiconductor layer 146 has a depth between 100 nanometers (nm) and 10 micrometers (pm). In some conventional applications, porous silicon has been used as trench isolation. However, according to embodiments of the present disclosure, the TIs 112, 116, 144 and the porous semiconductor layer 146 do not include the same material.

[0024] The polysilicon isolation layer 142 does not extend under the third TI 144. The polysilicon isolation layer 142 can include an end wall 160, but the end wall 160 contacts at least one of the third TI 144 and the portion 154 of the porous semiconductor layer 146, depending on, for example, the vertical positioning and / or depth of the polysilicon isolation layer 142, the third TI 144, and / or the portion 154 of the porous semiconductor layer 146. Similarly, the porous semiconductor layer 146 can include a side wall 162 that contacts the bulk semiconductor substrate 104 (portion 152) and possibly the polysilicon isolation layer 142.

[0025] The isolation structure 140 thus includes the polysilicon isolation layer 142 under the active devices 102. The isolation structure 140 also includes the TIs 112, 116, 144 and includes the porous semiconductor layer 146 between the first and second TIs 112, 116 and the polysilicon isolation layer 142 and possibly between the third TI 144 and the bulk semiconductor substrate 104. The TIs 112, 116, 144 do not include the same material as the porous semiconductor layer 146, e.g., the TIs 112, 116, 144 can include silicon oxide, whereas the porous semiconductor layer 146 includes porous silicon oxide.

[0026] Reference is made to Figures 2-8 , which shows a cross-sectional view of one embodiment of a method of forming the IC structure 100.

[0027] Figures 2-3 This illustrates the formation of a central region 108, a first end region 110, and a second end region 114 over a bulk semiconductor substrate 104 using a protective capping layer 172. Figure 3 ), thus generating an active region 168 ( Figure 8 ).exist Figure 2 In the example shown, forming the active region 168 includes forming a semiconductor layer 106 having a resistivity higher than that of the bulk semiconductor substrate 104. Figure 2 A semiconductor layer 106 is shown formed over a bulk semiconductor substrate 104. For example... Figure 3 As shown, the semiconductor layer 106 is ultimately formed to include a central region 108, a first end region 110 laterally spaced from the central region 108 via a first opening 180, and a second end region 114 laterally spaced from the central region 108 via a second opening 182. During some processing, a protective capping layer 172 will extend over the central region 108, the first end region 110, and the second end region 114. The semiconductor layer 146 can be formed by epitaxial growth, for example, in or above a bulk semiconductor substrate 104. As described above, the resistivity of the bulk semiconductor substrate 104 can be less than about 4.0 Ω / cm. 2 Furthermore, the resistivity of semiconductor layer 146 can be greater than approximately 1000 Ω / cm. 2 .

[0028] Figure 2 The formation of a protective capping layer 172 is also shown. In the example shown, the protective capping layer 172 comprises multiple sublayers 174, 176, which are composed, for example, of oxides in sublayer 174 and nitrides in sublayer 176; however, other materials are also possible. The protective capping layer 172 can be formed by any suitable deposition technique for the material being formed, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. A mask 178 can be used to pattern the active region 168 ( Figure 3 For example, by etching. Mask 178 may include any suitable mask material for the etching process and the material to be etched (e.g., silicon). Any suitable etching process can be used, such as RIE or wet etching. Figure 3 As shown, etching ( Figure 2 (The arrows in the image indicate that) a first opening 180 is formed between the first end region 110 and the central region 108, and a second opening 182 is formed between the second end region 114 and the central region 108. Etching also creates an opening 184 around the active region 168. Openings 180, 182, and 184 are connected, i.e., connected at the ends of openings 180 and 182. Forming openings 180, 182, and 184 also creates an exposed region 186 of the bulk semiconductor substrate 104. At this stage, any suitable technique, such as an ashing process, can be used to remove the mask 178 (…). Figure 2).

[0029] Figure 4 An optional step of forming a protective capping layer 172 along the sidewall 188 of the active region 168 is shown. More specifically, a portion 190 of the protective capping layer 172 extends over the sidewalls of the first end region 110 and the second end region 114. In the example shown, a single nitride layer is used; however, various materials and any number of layers can be used. The portion 190 of the protective capping layer 172 subsequently forms a porous semiconductor layer 146 ( Figure 6 This provides additional protection for the end regions 110 and 114 during the process. However, it should be noted that portion 190 of the protective layer 172 is not necessary because of the processing used to form the porous semiconductor layer 146. Figures 5-6 The process can be selective for the bulk semiconductor substrate 104. That is, the ends 110 and 114 are not affected by this process.

[0030] Figures 5-6 The exposed region 186 of the bulk semiconductor substrate 104 is shown through the first and second openings 180, 182 and adjacent to the first and second end regions 110, 114. Figure 5 A porous semiconductor layer 146 is formed in the process. For example... Figure 5 As shown, forming a porous layer may include exposing exposed region 186 to an electrolyte solution 192 and applying a voltage (V) across the semiconductor substrate 104. While various techniques can be used, in one example, the electrolyte solution 192 may include hydrofluoric acid (HF), which etches the semiconductor material and makes it porous. Other techniques for forming porous semiconductor layers are known and therefore do not require further details. Porous semiconductor layer 146 ( Figure 6 The depth and width of the porous semiconductor layer 146 can be controlled, for example, by the duration of exposure to the electrolyte solution 192, the electrolyte material and concentration, the width and / or depth of the openings 180 and 182, and the applied voltage. In one example, the porous semiconductor layer 146 ( Figure 6 The depth of the image can range from 100 nanometers (nm) to 10 micrometers (μm). For example... Figure 6As shown, a portion 148 of the porous semiconductor layer 146 is formed in the bulk semiconductor substrate 104 through an opening 180, and a portion 150 of the porous semiconductor layer 146 is formed in the bulk semiconductor substrate 104 through an opening 182. Portions 148 and 150 are separated by the (remaining) portion 152 of the bulk semiconductor substrate 104. Optionally, the porous semiconductor layer 146 may also include a portion 154 in the bulk semiconductor substrate 104. As shown, the porous semiconductor layer 146 may include end walls 162 (of the portion 154) that contact the bulk semiconductor substrate 104 (i.e., its portion 152). Therefore, the porous semiconductor layer 146 does not constitute the entire substrate 104, nor does it extend along the entire length of the substrate 104. At this stage, the protective capping layer 172 ( Figure 5 (including part of 190) Figure 5 If set, it can be removed using any appropriate technique (e.g., selective etching).

[0031] Figure 7 An insulator 194 is formed over a porous semiconductor layer 146 to form openings 180 and 182, respectively. Figure 5 A first TI 112 and a second TI 116 are generated in the semiconductor layer 106 (i.e., the active region 168), and a third TI 144 is generated around the semiconductor layer 106 (i.e., the active region 168). In the latter case, the insulator 194 surrounds the semiconductor layer 106, and therefore surrounds the active region 168 (i.e., the active region 168) to be formed therein. Figure 1 The first and second TI 112, 116 are connected at their ends to a third TI 144 (not shown, see next page). Insulator 194 may comprise any material previously listed herein for TI 112, 116, 144, such as silicon oxide, and may be formed by any suitable deposition technique, such as CVD, ALD, etc. Any necessary planarization steps, such as chemical mechanical planarization, may then be performed to remove any excess insulator 194.

[0032] Figure 8 This shows that a polycrystalline isolation layer 142 is formed beneath the semiconductor layer 106, and therefore it is located in the ultimately formed active region 168. Figure 1 Below. The polycrystalline isolation layer 142 can be formed, for example, by doping the region below the active region 168 (i.e., below the central region 108, the first end region 110, the second end region 114, and TI 112, 116). There are several ways to dope the desired region to form the polycrystalline isolation layer 142. In one example, this process may include implanting dopant ( Figure 8dopant) into a material. Ion implanters are typically used for the actual implantation. An inert carrier gas such as nitrogen gas is often used to introduce the impurity source (dopant). A dose and energy level appropriate for the particular bulk semiconductor substrate 104 and the desired doping can be specified and / or a final doping level can be specified. One example of a doping is implanting argon (Ar) with a dose between about 1E12 to 1E13 atoms / cm 2 and an energy of about 40 to 500 keV to produce a doping level of 1E17 to 1E18 atoms / cm 3 In this case, as shown in Figure 8 , the doping is performed to damage the single crystalline material to which it is applied.

[0033] Figure 8 One or more thermal cycles, such as an anneal indicated by the curved arrow, are also shown to rearrange the damaged and disordered crystalline material into a polycrystalline material. The thermal cycles can include one or more recrystallization anneals intentionally increased shortly after implantation, or conventional high temperature (>600°C) processes associated with semiconductor manufacturing. In this way, this process converts the single crystalline semiconductor substrate 104 (underneath the active region 168) into a polycrystalline isolation region 142. The implanted dopant can include any material capable of producing a polycrystalline material, including but not limited to: germanium (Ge); an inert gas such as argon (Ar) or xenon (Xe); or a combination of the materials listed above, such as Ge-Ar or Ge-Xe. The vertical position at which the polycrystalline isolation layer 142 begins and the depth of the layer 142 are controlled by the duration and energy of the ion implantation used. As noted, the end wall 162 of the porous semiconductor layer 146 can be in contact with the polycrystalline isolation layer 142 and the bulk semiconductor substrate 104. The polycrystalline isolation layer 142 does not extend under the third TI 144. In alternative embodiments, the polycrystalline isolation layer 142 can be formed in the bulk semiconductor substrate 104 prior to any of the processes shown in Figures 2-8 and the active region 169 and TIs 112, 116, 144 can be formed thereover. In any case, the resistivity of the polycrystalline isolation layer 142 can be, for example, greater than 1000 Ω / cm 2 , thereby providing a relatively strong resistance to current leakage from underneath the active device 102 Figure 1 .

[0034] Reference is made to Figure 1semiconductor manufacturing techniques, options for which are well known and will not be described in detail. In any case, forming the active device 102 can include forming a gate 120 over the central region 108, forming a first source / drain region 122S in the first end region 110, and forming a second source / drain region 122D in the second end region 114. The gate 120 can be formed using any now known or later developed process. In one non-limiting example, the gate 120 material can be deposited and patterned using photolithography, and spacers 126 can be formed around it, for example by depositing nitride and etching back. A nitride cap (not shown) can be formed over the gate 120. The gate 120 can include a dummy gate material, for example including a sacrificial material that is replaced with a final gate material after formation of the source / drain regions 122S, 122D, or can include a final gate material, for example a polysilicon or metal gate material. The source / drain regions 122S, 122D can be formed using any appropriate process, for example masked doping and annealing.

[0035] Figure 1 The process is also shown after forming silicide layers 130 over each of the pairs of source / drain regions 122S, 122D. The silicide layers 130 can include any silicide for coupling to contacts (not shown) through an interlayer dielectric (ILD) (not shown). The silicide layers 130 can be formed using any now known or later developed technique, for example performing an in-situ pre-clean, depositing a metal such as titanium, nickel, cobalt, platinum, etc., performing an anneal to cause the metal to react with the silicon of the end regions 110, 114, and removing the metal that did not react. Typically, the silicide layers 130 will not be formed over the first and second TIs 112, 116. However, the TIs 112, 116 are small enough that the silicide layers 130 span the TIs, and thus are shown as continuous layers. The ILD (not shown) can be deposited and include any now known or later developed ILD material. Any desired interconnects, for example contacts and wiring (not shown), can be formed through the ILD in known fashion.

[0036] Figure 9 and Figure 10 A cross-sectional view of forming an IC structure 100 according to an alternative embodiment of the disclosure is shown. More specifically, Figure 9 and Figure 10A first raised source / drain (RSD) region 198S is shown formed over the first TI 112, and a second raised source / drain (RSD) region 198D is shown formed over the second TI 116 (although the raised source / drain regions are denoted with reference numerals 198S, 198D, the location of the source or drain can be different than inferred from the letter designation). Figure 9 The process of Figure 8 is followed. The RSD regions 198S, 198D can be formed in any now known or later developed manner. In the example shown, a number of processes have occurred. Figure 9 The process of Figure 9 is followed. The RSD regions 198S, 198D can be formed in any now known or later developed manner. In the example shown, a number of processes have occurred. Figure 10 A first polysilicon portion 210 is shown formed over the first TI 112, a second polysilicon portion 212 is shown formed over the second TI 116, and a silicon layer 214 is shown formed over the semiconductor layer 106 between the first polysilicon portion 210 and the second polysilicon portion 212. This process can include epitaxially growing the first polysilicon portion 210 over the first TI 112, epitaxially growing the second polysilicon portion 212 over the second TI 116, and epitaxially growing the silicon layer 214 over the semiconductor layer 106. The locations where growth occurs on the TIs 112, 116, 144 forms polysilicon, and the location where growth occurs on the semiconductor layer 106 forms silicon. For example, by forming any necessary masks and performing etching to remove polysilicon over the third TI 144, one or more polysilicon portions 216 (dashed lines) that will be formed over the third TI 144 are removed. The width of the polysilicon portions 210, 212 is matched as closely as possible to the width of the RSD regions 198S, 198D (shown in

[0037] Figure 9 A first silicon portion 220 is also shown formed over the first polysilicon portion 210, and a second silicon portion 222 is shown formed over the second polysilicon portion 212. The silicon portions 220, 222 can be formed as a continuation of the epitaxial growth from the semiconductor layer 106 and the polysilicon portions 210, 212. The silicon portions 220, 222 can have any thickness required for the RSD regions 198S, 198D (shown in Figure 10 ). In one embodiment, the thickness of the silicon portions 220, 222 over the polysilicon portions 210, 212 is made close to the thickness of the SOI layer in the SOI substrate to obtain similar performance to the SOI substrate, even though the transistor 100 is formed over the bulk semiconductor substrate 104. In one non-limiting example, the silicon portions 220, 222 can have a thickness in the range of 10-60 nm.

[0038] Figure 10 A cross-sectional view showing formation of the active device 102 by forming the gate 120 over a region of the silicon layer 214 between the first silicon portion 220 and the second silicon portion 222 is shown. As shown, the upper surfaces of the first and second silicon portions 220, 222 (located below the silicide layer 130) are higher than the lower surface 230 of the gate 120. The silicon layer 214 provides a channel region 124 between the first RSD region 198S and the second RSD region 198D that are eventually formed. Figure 10 A cross-sectional view showing formation of the active device 102 including forming the RSD regions 198S, 198D over each of the first and second TIs 112, 116 is also shown. More specifically, formation of the active device 102 includes forming the first RSD region 198S in the first silicon portion 220 over the first TI 112, and forming the second RSD region 198D in the second silicon portion 222 over the second TI 116. The gate 120 and the RSD regions 198, 198D can be formed using any now known or later developed process, as previously described herein. For example, the RSD regions 198S, 198D can be formed by doping the silicon portions 220, 222 with an appropriate dopant (e.g., using ion implantation) and performing an anneal to drive in the dopant. The dopant used can vary depending on the type of transistor to be formed. As previously described herein, the silicide layer 130 can be formed. In Figure 10 In particular, the silicide layer 130 is located over the first RSD region 198S over the first TI 112, and over the second RSD region 198D over the second TI 116.

[0039] Figure 11 And Figure 12 A cross-sectional view showing formation of the IC structure 100 according to another alternative embodiment of the present disclosure is shown. In addition to the structure shown, Figure 10 the IC structure 100 in includes a first air gap 240 in the first TI 112 (i.e., below the RSD 198S) and a second air gap 242 in the second TI 116 (i.e., below the RSD 198D). The IC structure 100 also includes a nitride plug 244, 246 extending through each of the RSD regions 198S, 198D, i.e., to plug the air gap. Figure 11 In terms of process,

[0040] the IC structure 100 in includes a first air gap 240 in the first TI 112 (i.e., below the RSD 198S) and a second air gap 242 in the second TI 116 (i.e., below the RSD 198D). The IC structure 100 also includes a nitride plug 244, 246 extending through each of the RSD regions 198S, 198D, i.e., to plug the air gap. Figure 12 A cross-sectional view showing formation of the first air gap 240 in the first TI 112 (i.e., below the RSD 198S) Figure 11 and the second air gap 242 in the second TI 116 (i.e., below the second RSD 198D) Figure 11 is shown. In Figure 9Continue after the processing shown Figure 12 Forming air gaps 240, 242 beneath the first and second RSD regions 198S, 198D may include forming a first vent 250 through the first silicon portion 220 and the first polysilicon portion 210, and forming a second vent 252 through the second silicon portion 222 and the second polysilicon portion 212 (or through the RSD regions 198S, 198D, if the RSD regions 198S, 198D have already been formed in the silicon portions 220, 222). The vents 250, 252 may be formed using any process now known or developed later, for example, forming a patterned mask with small openings matching the positions of the vents 250, 252 and performing etching (e.g., RIE). Figure 12 It is also shown that a first portion of a first TI 112 beneath a first polysilicon portion 210 is removed through a first vent 250, and a second portion of a second TI 116 beneath a second polysilicon portion 212 is removed through a second vent 252. Removal may include etching multiple portions of the TI 112, 116 through vents 250, 252 using, for example, hot ammonia (NH3) and / or hydrochloric acid, as is known in the art. Semiconductor layer 106 may define an inner sidewall surface 254 for each vent 240, 242 (the right-hand vent 242 is shown for clarity only), and the TI 112, 116 may define a lower surface 256 for each vent 240, 242. Figure 11 As shown, the sides of the first air gap 240 and the second air gap 242 are aligned with the edges of the gate 120 (i.e., its spacer 126) and the channel region 124 in the silicon layer 214. After removing portions of the TI 112 and 116, optional thermal oxidation can be performed to passivate the air gap semiconductor surfaces. Removing multiple portions of the TI 112 and 116 leaves gas, such as air, in the spaces.

[0041] Return to Figure 11 Seal the first and second vent holes 250 and 252 ( Figure 12 Forming / completing the first air gap 240 and the second air gap 242 may include filling vent holes to form filled vent holes or plugs 244, 246. For example, sealing can be performed by depositing a dielectric such as nitride and / or spacer nitride. Sealing may occur simultaneously with the formation of spacer 126 of gate 120. As shown, forming the first and second air gaps 240, 242 may include forming nitride plugs 244, 246 extending through the first and second RSD regions 198S, 198D. It should be noted that, with the ultimately formed RSD regions 198S, 198D ( Figure 11 Compared to ), vent holes 250 and 252 ( Figure 12 It has a sufficiently small lateral dimension (span) Figure 12pages (e.g., the page from which the user navigated to the page or entered the page), so sealing them does not adversely affect the electrical performance of the RSD regions 198S, 198D Figure 11 As described with respect to Figure 10 active devices 102 can be formed, including forming the gates 120, the first RSD region 198S, and the second RSD region 198D. As previously described herein, a silicide layer 130 can be formed. However, in Figure 11 the nitride plugs 244, 246 extend through the silicide layer 130. That is, the silicide layer 130 is not formed on the nitride plugs 244, 246, it is only formed on the first RSD region 198S and the second RSD region 198D.

[0042] Embodiments of the present disclosure provide an IC structure 100 that uses a lower cost, low resistivity bulk semiconductor substrate 104, rather than a more expensive, higher resistivity SOI substrate. Despite the lower cost of the substrate, the IC structure 100 with the isolation structure 140 has performance characteristics that are superior to devices in SOI substrates, for example for radio frequency (RF) switches. For example, the IC structure 100 exhibits better current leakage, harmonic distortion, cross-talk resistance, effective resistivity, effective dielectric constant, and attenuation than current SOI substrate devices. One example SOI n-type field effect (NFET) RF switch including a high resistivity polysilicon isolation layer exhibits a "trench isolation under" resistance of about 1E6 ohms, a leakage current of about 10 microamperes (pA). In contrast, a similar NFET RF switch 200 employing the IC structure 100 according to embodiments of the present disclosure can exhibit a trench isolation under of about 300-400 nanometers (nm), and a leakage current of less than about 1.0 pA. The RSD regions 198S, 198D with or without air gaps 240, 242 under them can also be employed to further improve performance. The reduction in C DS of up to about 50%, which can reduce the off capacitance (C off ) by up to 25% to approach or match that value in SOI substrates. Although the air gaps 240, 242 provide this advantage, they are not located under the channel region 124 under the gate 120, thus eliminating any mechanical stress caused by such an arrangement. Other operating parameters exhibit similar improvements.

[0043] The methods and structures described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form (i.e., as a single wafer having many unpackaged chips), as bare chips, or in packaged form. In the latter case, the chips are mounted in single chip packages (e.g., plastic carriers, with leads that are affixed to the motherboard or other higher level carrier) or in multi-chip packages (e.g., ceramic carriers that have both surface interconnections and / or buried interconnections). In any case, the chips are then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having a display, a keyboard or other input device, and a central processor.

[0044] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Optional" or "optionally" means that the subsequently described event or circumstance can or can not occur, and that the description includes instances where the event occurs and instances where it does not.

[0045] Approximating language can be used herein for the purpose of conveying a spatial or temporal proximity between one or more events and / or one or more spatial or temporal descriptions of one or more events. Thus, as used herein, the terms "about" and "approximately” can describe an event or circumstance whose exact nature is not critical and / or an amount whose exact determination is not of significance. In at least some instances, the approximate language can correspond to the precision of an instrument used to measure the value. The use of the approximate language will depend on the context and / or the intended meaning, and can be used in various instances in this disclosure and throughout the specification and claims. In this context, a range limitation can be combined and / or interchanged, such ranges being identified and including all sub-ranges contained therein unless context or language indicates otherwise. "Approximately" applied to a range of values refers to both values, and unless otherwise dependent on the precision of an instrument used to measure the value, can indicate + / - 10% of the stated value.

[0046] Any structural, material, or act is meant to include any that performs the same function in an equivalent manner. The description of the disclosure is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. It is intended to cover any modifications and variations of this disclosure provided they come within the scope of the above disclosure and the appended claims.

Claims

1. An integrated circuit (IC) structure, comprising: An active device located above a bulk semiconductor substrate, the active device comprising a semiconductor layer having a central region, a first end region laterally spaced from the central region by a first trench isolation, a second end region laterally spaced from the central region by a second trench isolation, a gate located above the central region, and a source / drain region located in each of the first end region and the second end region. as well as The isolation structure surrounding the active device in the bulk semiconductor substrate, the isolation structure comprising: The polycrystalline isolation layer located beneath the active device. The third trench isolation surrounding the active device, and A porous semiconductor layer located between the first trench isolation and the polycrystalline isolation layer, and between the second trench isolation and the polycrystalline isolation layer.

2. The IC structure according to claim 1, wherein, The central region, the first end region, and the second end region have a resistivity higher than that of the bulk semiconductor substrate.

3. The IC structure according to claim 2, wherein, The bulk semiconductor substrate has a strength of less than 4Ω / cm 2 The resistivity is greater than 1000 Ω / cm, and the central region, the first end region, the second end region, and the polycrystalline isolation layer have a resistivity greater than 1000 Ω / cm. 2 The resistivity.

4. The IC structure according to claim 2 further includes: A silicide layer is located above the source / drain region and the first trench isolation in the first terminal region, and above the source / drain region and the second trench isolation in the second terminal region.

5. The IC structure according to claim 1, wherein, The active device includes a radio frequency (RF) switch.

6. The IC structure according to claim 1, wherein, The porous semiconductor layer further includes a portion located between the third trench isolation and the bulk semiconductor substrate, and the polycrystalline isolation layer includes an end wall that contacts the portion of the porous semiconductor layer.

7. The IC structure according to claim 6, wherein, Each portion of the porous semiconductor layer includes a sidewall that contacts the polycrystalline isolation layer and the bulk semiconductor substrate.

8. An integrated circuit (IC) structure, comprising: An active device located above a bulk semiconductor substrate, the active device comprising a semiconductor layer having a central region, a first end region laterally spaced from the central region by a first trench isolation, a second end region laterally spaced from the central region by a second trench isolation, a gate located above the central region, and a raised source / drain region located above each of the first trench isolation and the second trench isolation; as well as The isolation structure surrounding the active device in the bulk semiconductor substrate, the isolation structure comprising: The polycrystalline isolation layer located beneath the active device. The third trench isolation surrounding the active device, and A porous semiconductor layer located between the first trench isolation and the polycrystalline isolation layer, and between the second trench isolation and the polycrystalline isolation layer.

9. The IC structure according to claim 8, wherein, The central region, the first end region, and the second end region have a resistivity higher than that of the bulk semiconductor substrate.

10. The IC structure according to claim 9, wherein, The bulk semiconductor substrate has a strength of less than 4Ω / cm 2 The resistivity is greater than 1000 Ω / cm, and the central region, the first end region, the second end region, and the polycrystalline isolation layer have a resistivity greater than 1000 Ω / cm. 2 The resistivity.

11. The IC structure according to claim 8, further comprising: A silicide layer is located above the raised source / drain region above the first trench isolation and above the raised source / drain region above the second trench isolation.

12. The IC structure according to claim 8, wherein, The porous semiconductor layer further includes a portion located between the third trench isolation and the bulk semiconductor substrate, and the polycrystalline isolation layer includes an end wall that contacts the portion of the porous semiconductor layer.

13. The IC structure of claim 8, further comprising an air gap located in the first trench isolation and the second trench isolation, and a nitride plug extending through each of the raised source / drain regions.

14. The IC structure according to claim 8, wherein, The active device includes a radio frequency (RF) switch.

15. A method for forming an integrated circuit (IC) structure, comprising: A semiconductor layer is formed over a bulk semiconductor substrate, the semiconductor layer including a central region, a first end region laterally spaced from the central region through a first opening, and a second end region laterally spaced from the central region through a second opening, wherein a protective capping layer extends over the central region, the first end region, and the second end region; A porous semiconductor layer is formed in the exposed area of ​​the bulk semiconductor substrate through the first opening and the second opening and adjacent to the first end region and the second end region; An insulator is formed over the semiconductor layer to form a first trench isolation and a second trench isolation in the first opening and the second opening, and a third trench isolation is formed around the semiconductor layer; A polycrystalline isolation layer is formed beneath the semiconductor layer; and An active device having the semiconductor layer is formed.

16. The method according to claim 15, wherein, Forming the active device includes: forming a gate above the central region, forming a first source / drain region in the first terminal region, and forming a second source / drain region in the second terminal region.

17. The method according to claim 15, wherein, The active device is formed by forming a first raised source / drain region above the first trench isolation and a second raised source / drain region above the second trench isolation.

18. The method of claim 17, further comprising: A first air gap is formed in the first trench isolation, and a second air gap is formed in the second trench isolation.

19. The method according to claim 18, wherein, Forming the first air gap and the second air gap includes forming a nitride plug extending through the first raised source / drain region and the second raised source / drain region.

20. The method of claim 15, wherein, The protective cap extends above the sidewalls of the first end region and the second end region.

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