A battery protection circuit and battery protection system supporting multiple working modes

Abstract

The present invention relates to a battery protection circuit and a battery protection system supporting multiple working modes, comprising a working mode detection control circuit, an input end for acquiring a control signal, an output end for identifying each working mode according to the control signal, and outputting a corresponding working mode signal, including a shipping mode signal, a restart mode signal, a discharge prohibition mode signal or a charging prohibition mode signal; a logic control circuit, a substrate selection circuit, a drive circuit and a battery charging circuit, wherein the working mode detection control circuit is used to control the driving circuit through the logic control circuit to control the state of a charge and discharge control switch tube, and to control the substrate selection circuit through the logic control circuit to switch the substrate selection switch tube, so as to realize rapid switching of various working modes of the battery protection circuit, such as a shipping mode, a restart mode, a discharge prohibition mode or a charging prohibition mode, so as to meet various functional requirements and facilitate customers to flexibly use the battery protection circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of battery protection, and in particular to a battery protection circuit and a battery protection system supporting multiple working modes. Background Art

[0002] The battery protection circuit in the prior art includes a voltage detection circuit, a charge and discharge overcurrent protection circuit, a logic control circuit, a drive circuit, a substrate selection circuit, and a charge and discharge control switch tube M1, substrate selection tubes M2 and M3 on the battery charging circuit. Among them, the voltage detection circuit is used to detect the voltage of the battery during the charge and discharge process, and protect the battery when the battery voltage is lower than the over-discharge voltage or exceeds the over-charge voltage. The charge and discharge overcurrent protection circuit is used to detect the charging current and discharge current of the battery; the logic control circuit controls the drive circuit after performing logic processing on the outputs of the voltage detection circuit and the charge and discharge overcurrent protection circuit; the drive circuit realizes the control of the switch state of the charge and discharge switch tube; the substrate selection circuit is used to switch the substrate of the switch tube M1 through the substrate selection tubes M2 and M3 according to the charge and discharge state, so as to realize the function of protecting the battery.

[0003] However, the above-mentioned battery protection circuit is always in working state when the product needs to be transported at sea for a long time, and the power consumption is relatively large. In addition, the battery protection circuit cannot meet the functional requirements such as power-off restart, separate prohibition of charging and separate prohibition of discharging, etc., which is not convenient for production line analysis and testing. Therefore, how to provide a battery protection circuit that meets the above requirements has become an urgent problem to be solved. Summary of the invention

[0004] In view of the above technical problems, the present invention provides a battery protection circuit and a battery protection system supporting multiple working modes to solve the problems that the existing battery protection circuit has high power consumption and cannot be restarted after power failure, and cannot individually prohibit charging and discharging.

[0005] In a first aspect, the present invention provides a battery protection circuit supporting multiple working modes, comprising:

[0006] an operating mode detection control circuit, wherein an input end of the operating mode detection control circuit is used to obtain a control signal, and an output end of the operating mode detection control circuit is used to identify each operating mode according to the control signal and output a corresponding operating mode signal, wherein the operating mode signal includes a shipping mode signal, a restart mode signal, a discharging prohibition mode signal or a charging prohibition mode signal;

[0007] A logic control circuit, a substrate selection circuit, a drive circuit and a battery charging loop, wherein the input end of the logic control circuit is connected to the output end of the working mode detection control circuit, the first output end of the logic control circuit is connected to the input end of the substrate selection circuit, the second output end of the logic control circuit is connected to the input end of the drive circuit, the output end of the drive circuit is connected to the charge and discharge control switch tube arranged in series in the battery charging loop; the output end of the substrate selection circuit is connected to the substrate selection switch tube of the charge and discharge control switch tube;

[0008] The working mode detection control circuit is used to control the driving circuit through the logic control circuit to control the state of the charge and discharge control switch tube, and to control the substrate selection circuit through the logic control circuit to switch the substrate selection switch tube, so as to control the working mode switching of the battery protection circuit.

[0009] Optionally, the working mode detection control circuit includes:

[0010] A filtering circuit, a wide and narrow pulse width detection circuit and a pattern recognition circuit, wherein the filtering circuit is used to perform signal filtering processing to obtain the control signal that meets preset conditions; the input end of the wide and narrow pulse width detection circuit is connected to the output end of the filtering circuit to detect the wide pulse signal and / or narrow pulse signal in the control signal; the input end of the pattern recognition circuit is connected to the output end of the wide and narrow pulse width detection circuit to output the working mode signal according to the wide pulse signal and / or narrow pulse signal.

[0011] Optionally, the filtering circuit includes:

[0012] A first capacitor charge and discharge control circuit, wherein an input end of the first capacitor charge and discharge control circuit is used to input a control signal that has not been filtered, and an output end of the first capacitor charge and discharge control circuit is connected to a first capacitor to charge and discharge the first capacitor;

[0013] A first Schmitt trigger, wherein the input end of the first Schmitt trigger is connected to the output end of the first capacitor charge and discharge control circuit, and the output end of the first Schmitt trigger is connected to a first D trigger, for outputting a control signal whose preset condition is that the signal duration is greater than a set first time.

[0014] Optionally, the first capacitor charge and discharge control circuit includes:

[0015] A first inverter, a first P-type switch tube, a first N-type switch tube and a first current source, wherein the input end of the first inverter is used to input the unfiltered control signal, the output end of the first inverter is respectively connected to the control ends of the first P-type switch tube and the first N-type switch tube, the input end of the first P-type switch tube is connected to the first current source, the output end of the first P-type switch tube is connected to the input end of the first N-type switch tube, and the output end of the first N-type switch tube is grounded.

[0016] Optionally, the filtering circuit further includes:

[0017] A second inverter and a third inverter, wherein the input end of the second inverter is connected to the output end of the first Schmitt trigger, the input end of the third inverter is connected to the output end of the second inverter, and the output end of the third inverter is connected to the clock input end of the first D flip-flop.

[0018] Optionally, the wide and narrow pulse width detection circuit includes:

[0019] A second capacitor charge and discharge control circuit, wherein an input end of the second capacitor charge and discharge control circuit is connected to an output end of the filter circuit, and an output end of the second capacitor charge and discharge control circuit is connected to a second capacitor, for charging and discharging the second capacitor;

[0020] A second Schmitt trigger, wherein the input end of the second Schmitt trigger is connected to the output end of the second capacitor charge and discharge control circuit, the output end of the second Schmitt trigger is connected to the data input end of the second D trigger, the output end of the second D trigger is connected to the data input end of the third D trigger, the output end of the third D trigger is connected to the data input end of the fourth D trigger, and the output ends of the second D trigger, the third D trigger and the fourth D trigger are used to identify the wide pulse signal and / or the narrow pulse signal.

[0021] Optionally, the second capacitor charge and discharge control circuit includes: a first NAND gate, a second P-type switch tube, a second N-type switch tube and a second current source, wherein the first input end of the first NAND gate is connected to the output end of the filter circuit, and the second input end of the first NAND gate is used to input the control signal that has not been filtered; the output end of the first NAND gate is respectively connected to the control ends of the second P-type switch tube and the second N-type switch tube, the input end of the second P-type switch tube is connected to the second current source, the output end of the second P-type switch tube is connected to the input end of the second N-type switch tube, and the output end of the second N-type switch tube is grounded;

[0022] Clock input terminals of the second D flip-flop, the third D flip-flop and the fourth D flip-flop are respectively connected to output terminals of the first NAND gate.

[0023] Optionally, the pattern recognition circuit includes:

[0024] A shipping mode identification branch, wherein a first logic gate circuit is serially connected to the shipping mode identification branch, an input end of the first logic gate circuit is connected to an output end of the wide and narrow pulse width detection circuit, and an output end of the first logic gate circuit is used to output the shipping mode signal;

[0025] A restart mode identification branch, wherein a second logic gate circuit is serially connected to the restart mode identification branch, an input end of the second logic gate circuit is connected to an output end of the wide and narrow pulse width detection circuit, and an output end of the second logic gate circuit is used to output the restart mode signal;

[0026] a discharge mode prohibiting branch, wherein a third logic gate circuit is serially connected to the discharge mode prohibiting branch, an input end of the third logic gate circuit is connected to an output end of the wide and narrow pulse width detection circuit, and an output end of the third logic gate circuit is used to output the discharge mode prohibiting signal;

[0027] A charging mode prohibition branch is provided with a fourth logic gate circuit in series, the input end of the fourth logic gate circuit is connected to the output end of the wide and narrow pulse width detection circuit, and the output end of the fourth logic gate circuit is used to output the charging mode prohibition signal.

[0028] Optionally, the first logic gate circuit, the second logic gate circuit, the third logic gate circuit, and the fourth logic gate circuit have the same structure, and all include a second NAND gate and a fourth inverter connected in series.

[0029] In a second aspect, the present invention further provides a battery protection system, comprising a main control system and the battery protection circuit described in the first aspect, wherein a control output end of the main control system is connected to an input end of an operating mode detection control circuit in the battery protection circuit to output a control signal to the operating mode detection control circuit.

[0030] The above scheme has the following beneficial effects:

[0031] The battery protection system and battery protection circuit of the present invention can realize rapid detection and identification of multiple working modes through the additional working mode detection control circuit, and output the identified shipping mode signal, restart mode signal, discharge prohibition mode signal or charging prohibition mode signal to the logic control circuit. The driving circuit and the substrate selection circuit are controlled by the logic control circuit, and then the switch tube on the battery charging circuit and the substrate selection switch tube are controlled to perform corresponding actions, so as to realize rapid switching of various working modes (shipping mode, restart mode, discharge prohibition mode or charging prohibition mode) of the battery protection circuit, which can meet various functional requirements and facilitate customers to flexibly use the battery protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a structural block diagram of a battery protection circuit provided in one embodiment of the present invention;

[0033] Figure 2 is a structural block diagram of another battery protection circuit provided in other embodiments of the present invention;

[0034] Figure 3 is a circuit block diagram of a working mode detection control circuit provided in other embodiments of the present invention;

[0035] Figure 4 is a circuit diagram of a filter circuit provided in other embodiments of the present invention;

[0036] Figure 5 is a circuit diagram of a wide and narrow pulse detection circuit provided in other embodiments of the present invention;

[0037] Figure 6 is a circuit diagram of another wide and narrow pulse detection circuit provided in other embodiments of the present invention;

[0038] Figure 7 is a circuit diagram of a pattern recognition circuit in other embodiments of the present invention;

[0039] Figure 8 is a timing diagram of a shipping mode in other embodiments of the present invention;

[0040] Fig. 9 is a timing diagram of the restart mode provided in other embodiments of the present invention;

[0041] Fig.10 is a timing diagram of a discharge prohibition mode provided in other embodiments of the present invention;

[0042] Fig.11 is a timing diagram of a charging prohibition mode provided in other embodiments of the present invention;

[0043] Fig.12 is a structural block diagram of a battery protection system provided in other embodiments of the present invention;

[0044] The symbols are explained as follows:

[0045] 1. Working mode detection control circuit; 2. Logic control circuit; 3. Substrate selection circuit; 4. Driving circuit; 5. Voltage detection circuit; 6. Charge and discharge overcurrent protection circuit; 11. Filter circuit; 12. Wide and narrow pulse detection circuit; 13. Mode recognition circuit; 14. First capacitor charge and discharge control circuit; 15. Second capacitor charge and discharge control circuit; 130. First logic gate circuit; 131. Second logic gate circuit; 132. Third logic gate circuit; 133. Fourth logic gate circuit; 16. Main control system; 17. Load; 18. Charger. DETAILED DESCRIPTION

[0046] In order to make the technical problems, technical solutions and beneficial effects solved by the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0047] It should be understood that the embodiments set forth below represent the necessary information to enable those skilled in the art to implement the embodiments and illustrate the best mode for implementing the embodiments. After reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0048] It should also be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element without departing from the scope of the present disclosure. As used herein, the term "and / or" includes any and all combinations of one or more related listed items.

[0049] It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0050] It should also be understood that the terms "upper", "lower", "left", "right", "front", "back", "bottom", "middle", "middle", "top", etc. may be used herein to describe various elements, and the indicated orientation or position relationship is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore these elements should not be limited by these terms.

[0051] These terms are only used to distinguish one element from another element. For example, a first element can be referred to as an "upper" element, and similarly, a second element can be referred to as an "upper" element according to the relative orientation of these elements without departing from the scope of the present disclosure.

[0052] It is further understood that the terms “comprises,” “includes,” “including” and / or “comprising” when used herein specify the presence of stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0053] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the relevant technology, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0054] In one embodiment, a method is provided as follows Figure 1 The battery protection circuit shown supports multiple working modes, including:

[0055] The working mode detection control circuit 1 has an input end for acquiring a control signal, and an output end for identifying each working mode according to the control signal and outputting a corresponding working mode signal, wherein the working mode signal includes a shipping mode signal, a restart mode signal, a discharging prohibition mode signal or a charging prohibition mode signal.

[0056] The battery protection circuit also includes a logic control circuit 2, a substrate selection circuit 3, a drive circuit 4 and a battery charging circuit (i.e. Figure 1 The circuit is a branch between the negative terminal VSS and VM of the middle capacitor C1, and is connected in series with the battery VBAT to form a loop), wherein the input end of the logic control circuit 2 is connected to the output end of the working mode detection control circuit 1, the first output end of the logic control circuit 2 is connected to the input end of the substrate selection circuit 3, the second output end of the logic control circuit 2 is connected to the input end of the drive circuit 4, and the output end of the drive circuit 4 is connected to the charge and discharge control switch tube M1 (SW1) arranged in series in the battery charging circuit; the output end of the substrate selection circuit 3 is connected to the substrate selection switch tubes M2 (i.e. SW2) and M3 (i.e. SW3) of the charge and discharge control switch tube M1.

[0057] In this embodiment, the working mode detection and control circuit 1 is used to control the state of the charge and discharge control switch tube M1 through the logic control circuit 2 to control the driving circuit 4, and to control the substrate selection circuit 3 to switch the substrate selection switch tubes M2 and M3 through the logic control circuit 2, so as to control the working mode switching of the battery protection circuit.

[0058] The specific working principle for implementing the working mode switching in the above battery protection circuit is as follows:

[0059] (1) Under normal circumstances, the main control system of the battery protection chip (including the battery protection circuit and the main control system) controls the CNT pin to be at a low level. Therefore, Figure 1 the control signal CNT obtained by the working mode detection and control circuit 1 in is at a low level. At this time, the battery protection chip operates in the normal working state, and the power consumption is the normal working power consumption of the chip.

[0060] (2) When the product needs to be transported for a long time, the control signal output by the main control system to the CNT pin includes a period of high level (high level time > T1), and then continuously outputs three wide pulse signals of high level (high level time > T2). At this time, the working mode detection and control circuit 1 recognizes the shipping mode, outputs the shipping mode signal, controls the driving circuit 4 to turn off the switch tube M1 through the logic control circuit 2, controls the substrate selection circuit 3 to turn on the substrate selection switch tube M2, and turns off the substrate selection switch tube M3, so that the battery stops discharging, and the entire system enters the ultra-low power consumption mode; when it is necessary to exit the ultra-low power consumption mode, the system can be reactivated by inserting the charger.

[0061] (3) When the product needs to restart the main control system, the control signal output by the main control system to the CNT pin includes a period of high level (high level time > T1), and then continuously outputs two wide pulse signals of high level (high level time > T2) and one narrow pulse signal of high level (high level time < T2). At this time, the working mode detection and control circuit 1 recognizes the restart mode, outputs the restart mode signal, and controls the driving circuit 4 to turn off the switch tube M1 for a period of time and then turn it on through the logic control circuit 2, so as to restart the main control system.

[0062] (4) When the product needs to prohibit discharging, the control signal output by the main control system to the CNT pin includes a high level for a period of time (high level time > T1), and then successively outputs a wide pulse signal with a high level (high level time > T2), a narrow pulse signal with a high level (high level time < T2), and a wide pulse signal with a high level (high level time > T2). At this time, the working mode detection and control circuit 1 recognizes the discharging prohibition mode, outputs a discharging prohibition mode signal, controls the driving circuit 4 through the logic control circuit 2, and turns off the switching tube M1, thereby entering the discharging-off mode.

[0063] (5) When the product needs to prohibit charging, the control signal output by the main control system to the CNT pin includes a high level for a period of time (high level time > T1), and then successively outputs a wide pulse signal with a high level (high level time > T2) and two narrow pulse signals with a high level (high level time < T2). At this time, the working mode detection and control circuit 1 recognizes the charging prohibition mode, outputs a charging prohibition mode signal, controls the driving circuit 4 through the logic control circuit 2 to turn off the switching tube M1, controls the substrate selection switching tube M2 to turn off through the substrate selection circuit 3, and turns on the substrate selection switching tube M3, thereby entering the charging-off mode.

[0064] The battery protection circuit of this embodiment can quickly detect and identify multiple working modes through the added working mode detection and control circuit, output the identified shipping mode signal, restart mode signal, discharging prohibition mode signal, or charging prohibition mode signal to the logic control circuit, control the driving circuit and the substrate selection circuit through the logic control circuit, and then control the switching tube and the substrate selection switching tube on the battery charging circuit to perform corresponding actions, realizing the quick switching of the working mode of the battery protection circuit, and can meet various functional requirements (such as low power consumption, power-off restart, charge prohibition, and discharge prohibition), facilitating the flexible use of the battery protection circuit by customers.

[0065] In other embodiments, the above battery protection circuit may further include a voltage detection circuit 5 and a charge and discharge overcurrent protection circuit 6. As Figure 2 shown, the input end of the voltage detection circuit 5 is connected to the high-voltage side VDD port of the battery, and the output end of the voltage detection circuit 5 is connected to the logic control circuit 2. The voltage detection circuit 5 is used to detect the battery voltage during the charge and discharge process of the battery. When the battery voltage is lower than the over-discharge voltage threshold or exceeds the over-charge voltage threshold, the logic control circuit 2 outputs an over-voltage protection signal or an under-voltage protection signal to perform over-voltage protection or under-voltage protection on the battery.

[0066] Figure 2In the figure, the input end of the charge and discharge overcurrent protection circuit 6 is connected to the charge and discharge port VM, and the output end of the charge and discharge overcurrent protection circuit 6 is connected to the logic control circuit 2. The charge and discharge overcurrent protection circuit 6 is used to detect the charging current and discharging current of the battery. When the charging current or the discharging current exceeds the set current threshold, the logic control circuit 2 outputs an overcurrent protection signal to protect the battery from overcurrent.

[0067] In other embodiments, Figure 3 As shown, the working mode detection control circuit 1 of the battery protection circuit may include:

[0068] A filter circuit 11, a wide and narrow pulse width detection circuit 12 and a pattern recognition circuit 13, wherein the filter circuit 11 is used to perform signal filtering processing to obtain a control signal that meets preset conditions; the input end of the wide and narrow pulse width detection circuit 12 is connected to the output end of the filter circuit 11 to detect the wide pulse signal and / or narrow pulse signal in the control signal; the input end of the pattern recognition circuit 13 is connected to the output end of the wide and narrow pulse width detection circuit 12 to output a working mode signal according to the wide pulse signal and / or narrow pulse signal.

[0069] In this embodiment, the preset condition of the control signal may be: the effective duration of the control signal is greater than the set first time T1. For example, the time when the control signal is continuously at a high level is the effective duration. After setting this preset condition, when the high level time of the control signal that has not been filtered is less than the first time T1, the high level will be filtered out, and only when the high level time is greater than the first time T1 will it be considered effective.

[0070] In one example, the number of wide pulse signals and narrow pulse signals that the wide and narrow pulse width detection circuit 12 can identify can be set accordingly according to the number of working modes. For example, if it is necessary to set the four modes of shipping mode, restart mode, discharge prohibition mode or charging prohibition mode, then the wide and narrow pulse width detection circuit 12 is set to be able to identify four groups of three signals respectively, and the three signals in each group are used as a combination signal, and the combination signals of each group cannot be the same. For example, when the control signal contains 3 consecutive wide pulse signals, the combination signal recognized by the wide and narrow pulse width detection circuit 12 is Q <2> ,Q <1> ,Q <0> When the control signal contains two consecutive wide pulse signals and one narrow pulse signal, the combination signal recognized by the wide and narrow pulse width detection circuit 12 is Q <2> ,Q <1> ,NQ <0> When the control signal contains a wide pulse signal, a narrow pulse signal, and a wide pulse signal in succession, the combination signal recognized by the wide and narrow pulse width detection circuit 12 is Q <2> ,NQ <1> ,Q <0> When the control signal contains one wide pulse signal and two narrow pulse signals in succession, the combination signal recognized by the wide and narrow pulse width detection circuit 12 is Q <2> ,NQ <1> ,NQ <0> As another implementation, four groups of two signals may be provided, with the two signals in each group serving as a signal combination, and the combination signals of each group cannot be the same.

[0071] The working mode detection control circuit of this embodiment obtains a control signal that meets the requirements through a filtering circuit, filters out interference signals, and then effectively identifies the wide pulse signal and narrow pulse signal contained in the control signal through a wide and narrow pulse width detection circuit. Finally, the mode recognition circuit realizes rapid recognition of the working mode signals under various working modes.

[0072] In other embodiments, Figure 4 As shown, the filter circuit 11 in the above working mode detection control circuit 1 includes:

[0073] A first capacitor charge and discharge control circuit 14, wherein an input end of the first capacitor charge and discharge control circuit 14 is used to input a control signal that has not been filtered, and an output end of the first capacitor charge and discharge control circuit 14 is connected to the first capacitor C1 to charge and discharge the first capacitor C1;

[0074] The first Schmitt trigger I2, the input end of the first Schmitt trigger I2 is connected to the output end of the first capacitor charge and discharge control circuit 14, and the output end of the first Schmitt trigger I2 is connected to the first D trigger I5, which is used to output a control signal with a preset condition that the signal duration is greater than the set first time.

[0075] In one example, the first capacitor charge and discharge control circuit 14 may include:

[0076] A first inverter I1, a first P-type switch tube PM1, a first N-type switch tube NM1 and a first current source L1, wherein the input end of the first inverter I1 is used to input a control signal that has not been filtered, the output end of the first inverter I1 is respectively connected to the control ends of the first P-type switch tube PM1 and the first N-type switch tube NM1, the input end of the first P-type switch tube PM1 is connected to the first current source L1, the output end of the first P-type switch tube PM1 is connected to the input end of the first N-type switch tube NM1, and the output end of the first N-type switch tube NM1 is grounded.

[0077] The working process of the above filtering circuit is as follows:

[0078] Under normal circumstances, the control signal CNT is pulled down by the resistor R1, so that the control signal CNT is at a low level. After passing through the first inverter I1 in the first capacitor charge and discharge control circuit 14, a high level is output, thereby controlling the first P-type switch tube PM1 to be turned off and the first N-type switch tube NM1 to be turned on, so that the N1 node is at a low level. After passing through the first Schmitt trigger I2, the signal CNT_DELAY1 output is at a low level. The low level signal is used as the input signal of the clock input terminal CLK in the first D flip-flop I5. At this time, the control signal EN_CNT output from the output terminal of the first D flip-flop I5 is at a low level; when the main control system pulls up the control signal CNT, the control signal CNT changes from a low level to a high level, and after passing through the first inverter I1, a low level is output, thereby controlling the first P-type switch tube PM1 to be turned on and the first N-type switch tube NM1 to be turned off. At this time, the current output by the first current source I1 charges the first capacitor C1, so that the charging voltage VN1 of the N1 node is:

[0079]

[0080] Wherein, I1 is the current value output by the first current source, t is the charging time of the first capacitor, and C1 is the capacitance of the first capacitor.

[0081] Therefore, it can be seen from the above formula that the charging voltage VN1 of the N1 node rises linearly. When the charging voltage VN1 rises to exceed the flip threshold voltage VTH of the first Schmitt trigger I2, the time is the first time T1. At this time, after passing through the Schmitt trigger I2, the output signal CNT_DELAY1 becomes a high level, and the control signal EN_CNT output after passing through the first D trigger I5 is a high level.

[0082] The above-mentioned filtering circuit, through the cooperation between the first capacitor charging and discharging control circuit and the first Schmitt trigger and the D trigger, can achieve effective filtering of the control signal and quickly obtain a control signal whose signal duration is greater than the set first time.

[0083] In other embodiments, Figure 5As shown, the filter circuit 11 in the working mode detection control circuit may also include: a second inverter I3 and a third inverter I4, the input end of the second inverter I3 is connected to the output end of the first Schmitt trigger I2, the output end of the second inverter I3 is connected to the input end of the third inverter I4, and the output end of the third inverter I4 is connected to the clock input end CLK of the first D trigger I5.

[0084] The purpose of setting two inverters after the first Schmitt trigger in the filtering circuit is that when the output signal of the first Schmitt trigger is not a standard level signal, the output signal is adjusted to a standard level signal by adding two inverters to shape the waveform of the signal.

[0085] In other embodiments, Figure 6 As shown, the above-mentioned wide and narrow pulse width detection circuit 12 may include:

[0086] The second capacitor charge and discharge control circuit 15 has an input end connected to the output end of the filter circuit 11, and an output end connected to the second capacitor C2, for charging and discharging the second capacitor C2.

[0087] The second Schmitt trigger I8, the input end of the second Schmitt trigger I8 is connected to the output end of the second capacitor charge and discharge control circuit 15, the output end of the second Schmitt trigger I8 is connected to the data input end of the second D trigger I9, the output end of the second D trigger I9 is ​​connected to the data input end of the third D trigger I10, the output end of the third D trigger I10 is connected to the data input end of the fourth D trigger I11, and the output ends of the second D trigger I9, the third D trigger I10 and the fourth D trigger I11 are used to identify wide pulse signals and / or narrow pulse signals.

[0088] In one example, the second capacitor charge and discharge control circuit 15 includes: a first NAND gate I6, a second P-type switch tube PM2, a second N-type switch tube NM2 and a second current source L7, wherein the first input end of the first NAND gate I6 is connected to the output end of the filter circuit 11, and the second input end of the first NAND gate I6 is used to input the unfiltered control signal CNT; the output end of the first NAND gate I6 is respectively connected to the control ends of the second P-type switch tube PM2 and the second N-type switch tube NM2, the input end of the second P-type switch tube PM2 is connected to the second current source L7, the output end of the second P-type switch tube PM2 is connected to the input end of the second N-type switch tube NM2, and the output end of the second N-type switch tube NM2 is grounded.

[0089] The clock input terminals CLK of the second D flip-flop I9 , the third D flip-flop I10 and the fourth D flip-flop I11 are respectively connected to the output terminal of the first NAND gate I6 .

[0090] The specific working process of the above-mentioned wide and narrow pulse width detection circuit 12 is as follows:

[0091] The control signal CNT is at a low level during normal operation, and the control signal EN_CNT output after passing through the filtering circuit is also at a low level. Then, after passing through the first NAND gate I6 in the second capacitor charge and discharge control circuit 15, the output signal CNTI is at a high level, thereby controlling the second N-type switch tube NM2 to be turned on and the second P-type switch tube PM2 to be turned off, so that the N2 node is at a low level, and the signal D1 output after passing through the second Schmitt trigger I8 is at a low level. At this time, the signal Q output by the second D flip-flop I9, the third D flip-flop I10 and the fourth D flip-flop I11 is <0> , Q <1> and Q <2> All are low level.

[0092] When the control signal CNT becomes high level and exceeds the first time T1, the control signal EN_CNT output after passing through the filter circuit is high level. At this time, the output signal CNTI after passing through the first NAND gate I6 in the second capacitor charge and discharge control circuit 15 is low level, thereby controlling the second P-type switch tube PM2 to be turned on and the second N-type switch tube NM2 to be turned off. At this time, the current output by the second current source I7 charges the second capacitor C2, and the charging voltage VN2 of the node N2 is:

[0093]

[0094] Wherein, I7 is the current value output by the second current source, t is the charging time of the second capacitor, and C2 is the capacitance of the second capacitor.

[0095] Therefore, it can be seen from the above formula that the charging voltage VN2 of the N2 node rises linearly. When the charging voltage VN2 rises to exceed the flip threshold voltage VTH of the second Schmitt trigger I8, the time is T2, that is, when the CNT high level time is greater than T2, the signal D1 output by the second Schmitt trigger I8 is high level, and at the falling edge of the control signal CNT, the output Q of the second D flip-flop I9 is ​​high level. <0> On the contrary, when the CNT high level time is less than T2, the signal D1 output by the second Schmitt trigger I8 is low level, and the output Q of the second D flip-flop I9 is ​​at the falling edge of the control signal CNT. <0> is low level.

[0096] Take the restart mode as an example: when the first high level time of the control signal CNT exceeds T2 and the falling edge of CNT comes, the output Q of the second D flip-flop I9 <0> is high, the output Q of the third D flip-flop I10 <1> is low level, the output Q of the fourth D flip-flop I11 <2> is low level; when the second high level time of the control signal CNT exceeds T2, when the falling edge of CNT comes, the output Q <0> and Q <1> Both are high level, Q <2> is low level; when the third high level time of the control signal CNT is lower than T2, when the falling edge of the control signal CNT comes, Q <0> is low level, Q <1> and Q <2> is high level.

[0097] In other embodiments, Figure 7 As shown, the above-mentioned pattern recognition circuit 13 may include:

[0098] A shipping mode identification branch, wherein a first logic gate circuit 130 is serially connected to the shipping mode identification branch, wherein an input end of the first logic gate circuit 130 is connected to an output end of the wide and narrow pulse width detection circuit 12, and an output end of the first logic gate circuit 130 is used to output the shipping mode signal;

[0099] A restart mode identification branch, wherein a second logic gate circuit 131 is serially connected to the restart mode identification branch, an input end of the second logic gate circuit 131 is connected to an output end of the wide and narrow pulse width detection circuit 12, and an output end of the second logic gate circuit 131 is used to output the restart mode signal;

[0100] A discharge mode prohibiting branch, wherein a third logic gate circuit 132 is serially connected to the discharge mode prohibiting branch, an input end of the third logic gate circuit 132 is connected to an output end of the wide and narrow pulse width detection circuit 12, and an output end of the third logic gate circuit 132 is used to output a discharge mode prohibiting signal;

[0101] The charging mode prohibition branch has a fourth logic gate circuit 133 in series, the input end of the fourth logic gate circuit 133 is connected to the output end of the wide and narrow pulse width detection circuit 12, and the output end of the fourth logic gate circuit 133 is used to output a charging mode prohibition signal.

[0102] In one example, the first logic gate circuit 130, the second logic gate circuit 131, the third logic gate circuit 132, and the fourth logic gate circuit 133 have the same structure, and all include second NAND gates I13, I15, I17, I18 and fourth inverters I14, I16, I18, I120 connected in series.

[0103] The specific working process of the above-mentioned pattern recognition circuit 13 is as follows:

[0104] (1) When the wide and narrow pulse width detection circuit 12 detects that the three consecutive high voltage times of the control signal EN_CNT are greater than the second time T2, the signal Q output by the wide and narrow pulse width detection circuit 12 <0> ,Q <1> and Q <2> All are high level. At this time, after passing through the NAND gate I13 and the inverter I14 in the first logic gate circuit 130, the output shipping mode signal EN_SM is high level. After passing through the logic control circuit 2, the chip enters the shipping mode. Figure 8 This is a timing diagram of entering the shipping mode provided by this embodiment. If a charger is inserted into the shipping mode, the shipping mode can be exited and returned to the normal working mode.

[0105] (2) When the wide and narrow pulse width detection circuit 12 detects that only the third high level time of the control signal EN_CNT is less than the second time T2 among the three consecutive high voltage times, the wide and narrow pulse width detection circuit 12 outputs the signal NQ <0> ,Q <1> and Q <2> is high level, at this time, after passing through the NAND gate I15 and the inverter I16 in the second logic gate circuit 131, the output restart mode signal EN_RS is high level, and after passing through the logic control circuit 2, the chip enters the restart mode. Fig. 9 This is a timing diagram of entering the restart mode provided in this embodiment. After entering the restart mode, the chip will cut off the power supply to the main control for a period of time and then restore the power supply, that is, restart the main control system.

[0106] (3) When the wide and narrow pulse width detection circuit 12 detects that only the second high level time of the control signal EN_CNT is less than the second time T2 among the three consecutive high voltage times, the wide and narrow pulse width detection circuit 12 outputs the signal Q <0> ,NQ <1> and Q <2> is high level, at this time, after passing through the NAND gate I17 and the inverter I18 in the third logic gate circuit 132, the outputted discharge prohibition mode signal EN_NDI is high level, and after passing through the logic control circuit 2, the chip enters the discharge shutdown mode. Fig.10 1 is a timing diagram of entering the prohibited discharge mode provided in this embodiment. After entering the prohibited discharge mode, the battery will be prohibited from discharging, and the normal working state can be restored when the load is removed.

[0107] (4) When the wide and narrow pulse width detection circuit 12 detects that only the first high level time of the control signal EN_CNT is greater than the second time T2 among the three consecutive high voltage times, the wide and narrow pulse width detection circuit 12 outputs a signal NQ <0> ,NQ <1> and Q <2> is high level, at this time, after passing through the NAND gate I19 and the inverter I20 in the fourth logic gate circuit 133, the output charging prohibition mode signal EN_NCI is high level, and after passing through the logic control circuit 2, the chip enters the charging shutdown mode. Fig.11 This is a timing diagram of entering the charging prohibition mode provided in this embodiment. After entering the charging prohibition mode, the battery will be prohibited from charging, and the normal working state can be restored when the charger is removed.

[0108] In other examples, the structures of the first logic gate circuit, the second logic gate circuit, the third logic gate circuit, and the fourth logic gate circuit may also be different. For example, one part of the logic gate circuit includes a second NAND gate and a fourth inverter connected in series; another part of the logic gate circuit is composed only of AND gates.

[0109] In one embodiment, if Fig.12 As shown, a battery protection system is provided, including a main control system 16, and the battery protection circuit mentioned in any of the above embodiments, wherein the control output end of the main control system 16 is connected to the input end of the working mode detection control circuit 1 in the battery protection circuit, so as to output a control signal containing a wide pulse signal and / or a narrow pulse signal to the working mode detection control circuit 1. Exemplarily, the battery protection system may also include a battery VBAT, a resistor R1, a capacitor C1, a load 17, and a charger 18.

[0110] The battery protection system of this embodiment can realize the free switching and control of the chip's shipping mode, restart mode, charging mode off, and discharging mode off through a CNT pin, which can greatly reduce the system power consumption while facilitating customers' flexible use. It is comprehensive in functions and suitable for market promotion.

Claims

1. A battery protection circuit supporting multiple working modes, characterized in that: include: an operating mode detection control circuit, wherein an input end of the operating mode detection control circuit is used to obtain a control signal, and an output end of the operating mode detection control circuit is used to identify each operating mode according to the control signal and output a corresponding operating mode signal, wherein the operating mode signal includes a shipping mode signal, a restart mode signal, a discharging prohibition mode signal or a charging prohibition mode signal; A logic control circuit, a substrate selection circuit, a drive circuit and a battery charging loop, wherein the input end of the logic control circuit is connected to the output end of the working mode detection control circuit, the first output end of the logic control circuit is connected to the input end of the substrate selection circuit, the second output end of the logic control circuit is connected to the input end of the drive circuit, the output end of the drive circuit is connected to the charge and discharge control switch tube arranged in series in the battery charging loop; the output end of the substrate selection circuit is connected to the substrate selection switch tube of the charge and discharge control switch tube; The working mode detection control circuit is used to control the driving circuit through the logic control circuit to control the state of the charge and discharge control switch tube, and to control the substrate selection circuit through the logic control circuit to switch the substrate selection switch tube, so as to control the working mode switching of the battery protection circuit; The working mode detection control circuit comprises: A filter circuit, a wide and narrow pulse width detection circuit and a pattern recognition circuit, wherein the filter circuit is used to perform signal filtering processing to obtain the control signal that meets the preset conditions; the input end of the wide and narrow pulse width detection circuit is connected to the output end of the filter circuit to detect the wide pulse signal and / or the narrow pulse signal in the control signal; the input end of the pattern recognition circuit is connected to the output end of the wide and narrow pulse width detection circuit to output the working mode signal according to the wide pulse signal and / or the narrow pulse signal; The wide and narrow pulse width detection circuit comprises: A second capacitor charge and discharge control circuit, wherein an input end of the second capacitor charge and discharge control circuit is connected to an output end of the filter circuit, and an output end of the second capacitor charge and discharge control circuit is connected to a second capacitor, for charging and discharging the second capacitor; A second Schmitt trigger, wherein the input end of the second Schmitt trigger is connected to the output end of the second capacitor charge and discharge control circuit, the output end of the second Schmitt trigger is connected to the data input end of the second D trigger, the output end of the second D trigger is connected to the data input end of the third D trigger, the output end of the third D trigger is connected to the data input end of the fourth D trigger, and the output ends of the second D trigger, the third D trigger and the fourth D trigger are used to identify the wide pulse signal and / or the narrow pulse signal.

2. The battery protection circuit according to claim 1, characterized in that: The filtering circuit comprises: A first capacitor charge and discharge control circuit, wherein an input end of the first capacitor charge and discharge control circuit is used to input a control signal that has not been filtered, and an output end of the first capacitor charge and discharge control circuit is connected to a first capacitor to charge and discharge the first capacitor; A first Schmitt trigger, wherein the input end of the first Schmitt trigger is connected to the output end of the first capacitor charge and discharge control circuit, and the output end of the first Schmitt trigger is connected to a first D trigger, for outputting a control signal whose preset condition is that the signal duration is greater than a set first time.

3. The battery protection circuit according to claim 2, characterized in that: The first capacitor charge and discharge control circuit comprises: A first inverter, a first P-type switch tube, a first N-type switch tube and a first current source, wherein the input end of the first inverter is used to input the unfiltered control signal, the output end of the first inverter is respectively connected to the control ends of the first P-type switch tube and the first N-type switch tube, the input end of the first P-type switch tube is connected to the first current source, the output end of the first P-type switch tube is connected to the input end of the first N-type switch tube, and the output end of the first N-type switch tube is grounded.

4. The battery protection circuit according to claim 2, characterized in that: The filter circuit also includes: A second inverter and a third inverter, wherein the input end of the second inverter is connected to the output end of the first Schmitt trigger, the input end of the third inverter is connected to the output end of the second inverter, and the output end of the third inverter is connected to the clock input end of the first D flip-flop.

5. The battery protection circuit according to claim 1, characterized in that: The second capacitor charge and discharge control circuit comprises: a first NAND gate, a second P-type switch tube, a second N-type switch tube and a second current source, wherein the first input end of the first NAND gate is connected to the output end of the filter circuit, and the second input end of the first NAND gate is used to input the control signal that has not been filtered; the output end of the first NAND gate is respectively connected to the control ends of the second P-type switch tube and the second N-type switch tube, the input end of the second P-type switch tube is connected to the second current source, the output end of the second P-type switch tube is connected to the input end of the second N-type switch tube, and the output end of the second N-type switch tube is grounded; Clock input terminals of the second D flip-flop, the third D flip-flop and the fourth D flip-flop are respectively connected to output terminals of the first NAND gate.

6. The battery protection circuit according to claim 1, characterized in that: The pattern recognition circuit comprises: A shipping mode identification branch, wherein a first logic gate circuit is serially connected to the shipping mode identification branch, an input end of the first logic gate circuit is connected to an output end of the wide and narrow pulse width detection circuit, and an output end of the first logic gate circuit is used to output the shipping mode signal; A restart mode identification branch, wherein a second logic gate circuit is serially connected to the restart mode identification branch, an input end of the second logic gate circuit is connected to an output end of the wide and narrow pulse width detection circuit, and an output end of the second logic gate circuit is used to output the restart mode signal; a discharge mode prohibiting branch, wherein a third logic gate circuit is serially connected to the discharge mode prohibiting branch, an input end of the third logic gate circuit is connected to an output end of the wide and narrow pulse width detection circuit, and an output end of the third logic gate circuit is used to output the discharge mode prohibiting signal; A charging mode prohibition branch is provided with a fourth logic gate circuit in series, the input end of the fourth logic gate circuit is connected to the output end of the wide and narrow pulse width detection circuit, and the output end of the fourth logic gate circuit is used to output the charging mode prohibition signal.

7. The battery protection circuit according to claim 6, characterized in that: The first logic gate circuit, the second logic gate circuit, the third logic gate circuit, and the fourth logic gate circuit have the same structure, and all include a second NAND gate and a fourth inverter connected in series.

8. A battery protection system, characterized in that: It comprises a main control system and a battery protection circuit as described in any one of claims 1 to 7, wherein a control output end of the main control system is connected to an input end of an operating mode detection control circuit in the battery protection circuit to output a control signal to the operating mode detection control circuit.

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