Semiconductor structure manufacturing method and semiconductor structure

Abstract

This disclosure provides a method for manufacturing a semiconductor structure and the semiconductor structure itself. The method includes: providing a substrate, including a substrate and a stacked structure covering the top surface of the substrate, the substrate including a first active region, a memory array region, and a predetermined region; removing the stacked structure covering the memory array region and the predetermined region to expose a portion of the top surface of the substrate; forming a conductive layer covering the stacked structure of the first active region and the substrate exposed by the memory array region and the predetermined region; patterning the stacked structure and the conductive layer to form a gate in the first active region and a power line in the predetermined region; and forming an interconnect structure covering a portion of the surface of the power line and a first source / drain covering the first active region. This disclosure provides a single interconnect structure to connect the power line and the first active region; furthermore, since the power line and the gate are made of the same conductive layer, the process flow is simplified, and production efficiency and yield are improved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] In the field of semiconductor technology, the size of semiconductor structures is getting smaller and smaller, but the number of traces in semiconductor structures has not decreased. As the size gradually shrinks, the fabrication process of traces is also approaching the process limit, making it very difficult to make the size of traces smaller, which makes it difficult to set more traces in a limited area. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure.

[0005] A first aspect of this disclosure provides a method for manufacturing a semiconductor structure, comprising:

[0006] A substrate is provided, including a substrate and a stacked structure covering the top surface of the substrate, the substrate including a first active region, a memory array region and a predetermined region;

[0007] Remove the stacked structure covering the storage array area and the preset area to expose a portion of the top surface of the substrate;

[0008] A conductive layer is formed, which covers the stacked structure of the first active region and the substrate exposed by the memory array region and the preset region;

[0009] The stacked structure and the conductive layer are graphically represented to form a gate in the first active region and a power line in the preset region.

[0010] An interconnect structure is formed, the interconnect structure covering a portion of the surface of the power line and a first source-drain electrode covering the first active region.

[0011] In some embodiments, forming the interconnect structure includes:

[0012] A first dielectric layer is formed, which covers the top surface of the conductive layer and the first active region;

[0013] A portion of the first dielectric layer is removed to form a contact hole in the first dielectric layer, the contact hole exposing at least a portion of the sidewalls and top surface of the power line, as well as exposing the first source and drain electrodes of the first active region;

[0014] The interconnect structure is formed in the contact hole.

[0015] In some embodiments, an interconnect structure is formed in the contact hole, including:

[0016] A barrier layer is formed, which covers the bottom wall and sidewalls of the contact hole;

[0017] A conductive structure is formed, which covers the bottom and sidewalls of the barrier layer.

[0018] In some embodiments, prior to forming the first dielectric layer, the method further includes:

[0019] A protective layer is formed to cover the sidewalls of the gate and the sidewalls of the power lines.

[0020] In some embodiments, forming a contact hole in the first dielectric layer includes:

[0021] An initial contact hole is formed in the first dielectric layer, the initial contact hole exposing a protective layer located on the sidewall of the power line;

[0022] Remove the protective layer exposed by the initial contact hole to expose the sidewall of the power line and form a contact hole.

[0023] In some embodiments, the method for manufacturing the semiconductor structure further includes:

[0024] A portion of the first dielectric layer is removed, and a via is formed in the first dielectric layer, wherein the via exposes only a portion of the first source and drain electrodes of the first active region;

[0025] A conductive pillar is formed in the through hole.

[0026] In some embodiments, the provided substrate includes:

[0027] A shallow trench is formed in the substrate, the shallow trench being located between the first active region and the preset region;

[0028] Fill the shallow trench with an isolation structure;

[0029] The interconnect structure covers the top surface of the isolation structure.

[0030] In some embodiments, the method further includes the following steps prior to forming the conductive layer:

[0031] A dielectric layer is formed, which covers the top surface of the predetermined region of the substrate.

[0032] In some embodiments, prior to forming the conductive layer, the method further includes:

[0033] The memory array region is patterned to form plug holes in the memory array region;

[0034] A contact structure is formed within the plug hole;

[0035] The conductive layer covers the top surface of the contact structure;

[0036] When graphically representing the stacked structure and the conductive layer, the method further includes:

[0037] The contact structure and conductive layer located in the memory array region are patterned to form bit lines in the memory array region.

[0038] A second aspect of this disclosure provides a semiconductor structure, comprising:

[0039] The substrate includes a substrate having a predetermined region and a first active region;

[0040] A gate, the gate being located on the first active region;

[0041] A power cord, which is located in the preset area;

[0042] An interconnection structure connects the power line to the first source and drain of the first active region;

[0043] The gate and the power line both include conductive layers formed using the same process.

[0044] In some embodiments, the semiconductor structure further includes a first dielectric layer that covers a portion of the top surface of the power line and the first active region;

[0045] The first dielectric layer has a contact hole, and the interconnect structure is located in the contact hole;

[0046] The interconnect structure includes a barrier layer covering the bottom and sidewalls of the contact hole, and a conductive structure covering the bottom and sidewalls of the barrier layer.

[0047] In some embodiments, the substrate further includes a shallow trench isolation structure located between the first active region and the preset region;

[0048] The interconnect structure covers the top surface of the shallow trench isolation structure.

[0049] In some embodiments, the substrate further includes a memory array region, which is spaced apart from the preset region and the first active region;

[0050] The top surface of the storage array region is sequentially provided with a contact structure, a bit line conductive layer and the first dielectric layer, wherein the bit line conductive layer and the power line are conductive layers formed by the same process.

[0051] In some embodiments, the gate further includes a high-k dielectric layer and a polysilicon layer stacked sequentially below the conductive layer.

[0052] In some embodiments, the preset region extends along the length direction and is located on one side of a plurality of first active regions, and the interconnection structure comprises a plurality of interconnections and respectively connects the power line to the first source and drain of at least one of the first active regions.

[0053] The semiconductor structure manufacturing method and semiconductor structure disclosed herein, in which...

[0054] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0055] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0056] Figure 1 This is a flowchart illustrating a method for manufacturing a semiconductor structure according to an exemplary embodiment.

[0057] Figure 2 This is a schematic diagram of a semiconductor structure in its initial state, according to an exemplary embodiment.

[0058] Figure 3 This is a schematic diagram of a semiconductor structure after removing a portion of the stacked structure, according to an exemplary embodiment.

[0059] Figure 4 This is a schematic diagram illustrating a semiconductor structure after the formation of a contact structure, according to an exemplary embodiment.

[0060] Figure 5 This is a schematic diagram illustrating a semiconductor structure after the formation of a conductive layer, according to an exemplary embodiment.

[0061] Figure 6 This is a schematic diagram illustrating a semiconductor structure after the formation of a power line, according to an exemplary embodiment.

[0062] Figure 7 This is a schematic diagram illustrating a semiconductor structure after the formation of a protective layer, according to an exemplary embodiment.

[0063] Figure 8 This is a schematic diagram illustrating a semiconductor structure after the formation of a first dielectric layer, according to an exemplary embodiment.

[0064] Figure 9 This is a top view of a semiconductor structure.

[0065] Figure 10 yes Figure 9 Sectional view at point AA.

[0066] Figure 11 yes Figure 9 Sectional view at point BB.

[0067] Figure label:

[0068] 10. Base;

[0069] 11. Substrate; 11a. First active region; 111a. First source / drain; 11b. Memory array region; 111b. Contact structure; 11c. Preset region; 111c. Dielectric layer;

[0070] 12. Layered structure; 121. High-K dielectric layer; 122. Polycrystalline silicon layer;

[0071] 20. Conductive layer; 21. Gate electrode; 22. Bit line; 23. Power line;

[0072] 30. Interconnection structure; 31. Barrier layer; 32. Conductive structure;

[0073] 40. Protective layer;

[0074] 50. Protective capping layer;

[0075] 60. First dielectric layer;

[0076] 70. Conductive post; 71. First conductive post; 72. Second conductive post;

[0077] 80. Isolation structure.

[0078] 90. Photoresist layer. Detailed Implementation

[0079] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0080] In the field of semiconductor technology, the size of semiconductor structures is getting smaller and smaller, but the number of traces in semiconductor structures has not decreased. As the size gradually shrinks, the fabrication process of traces is also approaching the process limit, making it very difficult to make the size of traces smaller, which makes it difficult to set more traces in a limited area.

[0081] To address the aforementioned problems, this disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method for manufacturing the semiconductor structure includes: providing a substrate, including a substrate and a stacked structure covering the top surface of the substrate, the substrate including a first active region, a memory array region, and a preset region; removing the stacked structure covering the memory array region and the preset region to expose a portion of the top surface of the substrate; forming a conductive layer covering the stacked structure of the first active region and the substrate exposed by the memory array region and the preset region; patterning the stacked structure and the conductive layer to form a gate in the first active region and a power line in the preset region; and forming an interconnect structure covering a portion of the surface of the power line and a first source / drain covering the first active region. In this disclosure, the interconnect structure covers a portion of the surface of the power line and the first source and drain of the first active region to connect the power line and the first active region, thereby enabling power to be supplied to the first active region through the power line and the interconnect structure. Only one interconnect structure is needed to electrically connect the power line and the first active region. Furthermore, the power line and the gate can be made of conductive layers formed by the same process, which simplifies the process flow and improves production efficiency and yield.

[0082] This disclosure provides a method for manufacturing a semiconductor structure in exemplary embodiments. Figure 1 A flowchart illustrating a method for manufacturing a semiconductor structure according to an exemplary embodiment of the present disclosure is shown. Figures 2-11 This is a schematic diagram of the various stages of semiconductor structure manufacturing. The following section combines... Figures 2-11 The manufacturing methods of semiconductor structures are introduced.

[0083] This disclosure does not limit the semiconductor structure. The following description uses Dynamic Random Access Memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0084] like Figure 1 As shown, an exemplary embodiment of this disclosure provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0085] Step S100: Provide a substrate, including a substrate and a stacked structure covering the top surface of the substrate, wherein the substrate includes a first active region, a memory array region and a preset region.

[0086] In this step, such as Figure 2 As shown, the substrate 10 includes a substrate 11 and a stacked structure 12 covering the top surface of the substrate 11.

[0087] Reference Figure 2 The substrate 11 can be any one of silicon substrate, germanium substrate, silicon-germanium substrate, silicon-on-insulator (SOI) substrate, and germanium-on-insulator (GOI) substrate.

[0088] Reference Figure 2 Multiple material layers can be sequentially formed on substrate 11 using a deposition process. The projections of these multiple material layers onto substrate 11 coincide with the top surface of substrate 11, and the multiple material layers constitute a stacked structure 12. (Refer to...) Figure 2 The stacked structure 12, from bottom to top, can consist of a high-k dielectric layer 121 and a polysilicon layer 122. The high-k dielectric layer 121 can be a single-layer or multi-layer structure; for example, the high-k dielectric layer 121 can be a multi-layer structure of materials such as AlO, TiN, LaO, and HfO2. It should be noted that a gate dielectric layer (not shown in the figure) is also formed between the high-k dielectric layer 121 and the substrate 11.

[0089] The deposition processes include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma deposition (HDP), plasma-enhanced deposition, and spin-on dielectric (SOD).

[0090] In this step, refer to Figure 2 The substrate 11 includes a first active region 11a, a memory array region 11b, and a preset region 11c. The first active region 11a can be the active region of a core control transistor in a semiconductor device, or the active region of an equalization transistor in a sensing amplifier circuit, etc., but this embodiment does not impose excessive limitations. The memory array region 11b can be a region where multiple memory cells have already been formed, or a region used to form multiple memory cells in subsequent processes, but this embodiment does not impose excessive limitations. The preset region 11c can be a region in a semiconductor device used to set power lines. The first source / drain 111a of the first active region 11a and the preset region 11c can be isolated by an isolation structure 80.

[0091] Step S200: Remove the stacked structure covering the storage array area and the preset area to expose part of the top surface of the substrate.

[0092] In this step, such as Figure 3 As shown, and in combination Figure 2 The stacked structure 12 covering the top surface of the memory array region 11b and the preset region 11c can be removed by photolithography, etching and other processes, so that the preset region 11c and the memory array region 11b of the substrate 11 are exposed to the top surface, which is convenient for subsequent processing at the preset region 11c and the memory array region 11b.

[0093] The step of removing part of the stacked structure 12 may include: forming a photoresist layer 90 on the top surface of the stacked structure 12, removing the photoresist on the memory array region 11b and the preset region 11c by exposure and development processes, so that the stacked structure 12 located on the memory array region 11b and the preset region 11c exposes the top surface. In the subsequent etching process, since this part of the stacked structure 12 is no longer protected by the photoresist layer 90, it can be removed by etching process to expose part of the top surface of the substrate 11.

[0094] Step S300: Form a conductive layer that covers the stacked structure of the first active region and the substrate exposed by the memory array region and the preset region.

[0095] In this step, refer to Figure 5 The conductive layer 20 can be formed using a deposition process. Part of the conductive layer 20 is formed on the top surface of the stacked structure 12 on the first active region 11a, and another part forms on the top surface of the memory array region 11b and the preset region 11c of the substrate 11. The material of the conductive layer 20 can be a metal such as tungsten (W), copper (Cu), or cobalt (Co).

[0096] It should be noted that in the subsequent process, the conductive layers 20 formed at different positions on the substrate 11 can have different functions. Since the conductive layers 20 with multiple functions can be formed in a single step in this disclosure, the process flow is greatly simplified.

[0097] Step S400: Patterning the stacked structure and conductive layer to form a gate in the first active region and a power line in the preset region.

[0098] In this step, refer to Figure 6 and combined Figure 5 The stacked structure 12 and the conductive layer 20 can be patterned using photolithography, etching and other processes. The patterned conductive layer 20 on the stacked structure 12 in the first active region 11a is retained as the gate electrode 21, so that the stacked structure 12 and the gate electrode 21 on the first active region 11a together constitute the gate. The patterned conductive layer 20 on the memory array region 11b is retained as the bit line 22, and the patterned conductive layer 20 on the preset region 11c is used as the power line 23, wherein the power line 23 is a long strip extending in the horizontal direction.

[0099] Step S500: Form an interconnect structure that covers a portion of the surface of the power line and the first source / drain electrode that covers the first active region.

[0100] In this step, refer to Figure 9 and Figure 10 Interconnect structure 30 can be formed by deposition process. Part of interconnect structure 30 covers part of the surface of power line 23 and part of interconnect structure 30 covers the top surface of the first source-drain electrode 111a of the first active region 11a.

[0101] It should be noted that the first active region 11a is used to form a transistor, including a source region, a drain region, and a channel region. The first source-drain 111a of the first active region 11a refers to either the source region or the drain region of the first active region 11a. In this embodiment, the interconnect structure 30 covers the source region of the first active region 11a as an example. The gate is formed on the trench region of the first active region 11a.

[0102] In this embodiment of the present disclosure, the interconnect structure covers a portion of the surface of the power line and the first source and drain of the first active region to connect the power line and the first active region, thereby enabling power supply to the first active region through the power line and the interconnect structure. Only one interconnect structure is needed to electrically connect the power line and the first active region. Furthermore, the power line and the gate can be made of conductive layers formed by the same process, which simplifies the process flow and improves production efficiency and yield.

[0103] In an exemplary embodiment, this embodiment is a further description of step S500 in the above embodiment. In step S500, forming the interconnection structure 30 may include the following steps:

[0104] Step S510: Form a first dielectric layer, which covers the top surface of the conductive layer and the first active region.

[0105] In this step, refer to Figure 8 and combined Figure 7 A first dielectric layer 60 can be formed on the first source / drain electrode 111a of the conductive layer 20 and the first active region 11a using a deposition process.

[0106] In subsequent processes, contact holes (described in detail below) can be formed in the first dielectric layer 60, and interconnect structures 30 can be formed in the contact holes. On the one hand, this can improve the setting accuracy of interconnect structures 30; on the other hand, the sidewalls of the contact holes can also prevent the material of interconnect structures 30 from diffusing outward, thereby improving the performance of semiconductor devices.

[0107] Step S520: Remove a portion of the first dielectric layer to form a contact hole in the first dielectric layer, the contact hole exposing at least a portion of the sidewalls and top surface of the power line, and exposing the first source and drain electrodes of the first active region.

[0108] In this step, such as Figure 10 As shown, photolithography and etching processes can be used to remove part of the structure of the first dielectric layer 60 to form contact holes in the first dielectric layer 60.

[0109] Among them, reference Figure 10 The contact hole can expose at least part of the sidewall and top surface of the power line 23, as well as the first source drain 111a of the first active region 11a.

[0110] Understandably, the location where the first dielectric layer 60 is removed can be adaptively adjusted according to actual needs, so that the formed contact hole exposes different areas of the power line 23. For example, the contact hole may expose only the sidewall of the power line 23, only the top surface of the power line 23, or both the sidewall and the top surface of the power line 23.

[0111] In this embodiment, the specific shape of the contact hole is not limited. The contact hole can be cylindrical, prism, frustum, etc., as long as the contact hole can expose at least part of the sidewall and top surface of the power line 23 and expose the first source-drain electrode 111a of the first active region 11a.

[0112] Step S530: Form an interconnect structure in the contact hole.

[0113] In this step, such as Figure 9 and Figure 11 As shown, an interconnect structure 30 can be formed in the contact hole using a deposition process. The interconnect structure 30 can be made of a material with good electrical conductivity, such as tungsten (W) or copper (Cu).

[0114] Understandably, since the contact hole exposes at least a portion of the surface of the power line 23 and the first source-drain 111a of the first active region 11a, when the interconnect structure 30 fills the contact hole, the interconnect structure 30 can be connected to both the power line 23 and the first source-drain 111a simultaneously, so that an electrical connection is formed between the power line 23 and the first source-drain 111a, and a voltage can be applied to the first active region 11a through the power line 23 and the interconnect structure 30.

[0115] It should be noted that the interconnect structure 30 can fill the contact hole completely, or it can only fill part of the space of the contact hole. For example, the interconnect structure 30 can be formed only in the lower half of the contact hole, as long as the interconnect structure 30 is connected to the power line 23 and the first source-drain electrode 111a.

[0116] In an exemplary embodiment, this embodiment is a further explanation of step S530 in the above embodiment. Forming the interconnect structure 30 in the contact hole may include the following steps:

[0117] Step S531: Form a barrier layer that covers the bottom and side walls of the contact hole.

[0118] In this step, such as Figure 10 As shown, a barrier layer 31 can be formed in the contact hole using a deposition process. The barrier layer 31 covers the bottom wall and sidewalls of the contact hole and is used to prevent the material of the conductive structure 32 (described in detail below) in the interconnect structure 30 from diffusing outward.

[0119] In one example, a titanium nitride (TiN) film can be formed in the contact hole using techniques such as metal-organic chemical vapor deposition (MOCVD), and the titanium nitride film constitutes the barrier layer 31.

[0120] Step S532: Form a conductive structure that covers the bottom and sidewalls of the barrier layer.

[0121] In this step, such as Figure 10 As shown, a conductive structure 32 can be formed on the barrier layer 31 using a deposition process. The conductive structure 32 is electrically connected to the power line 23 and the first source / drain electrode 111a through the barrier layer 31. The material of the conductive structure 32 can be a metal such as tungsten (W) or copper (Cu).

[0122] In this embodiment, a barrier layer 31 is formed in the contact hole. The barrier layer 31 can effectively prevent the diffusion and migration of metal in the conductive structure 32 into the substrate 11, effectively prevent the substrate 11 from being contaminated, and improve the performance and yield of the semiconductor structure.

[0123] In an exemplary embodiment, before forming the first dielectric layer 60, the method for manufacturing the semiconductor structure may further include the following steps:

[0124] A protective layer is formed, which covers the sidewalls of the gate and the power lines.

[0125] In this step, refer to Figure 7 and combined Figure 6 Multiple sidewalls can be formed using processes such as deposition and epitaxial growth. These multiple sidewalls cover the sidewalls of the gate and power lines 23, forming a protective layer 40. The structure of the protective layer 40 can be, for example, an ONO (oxide-nitride-oxide) structure.

[0126] In one alternative implementation, refer to Figure 7 and combined Figure 6Before forming the protective layer 40, a protective capping layer 50 can be formed on the top surface of the gate electrode 21, bit line 22 and power line 23. The protective capping layer 50 can be made of insulating material and is used to protect the gate, bit line 22 and power line 23 together with the protective layer 40.

[0127] In an exemplary embodiment, this embodiment is a further explanation of step S520 in the above embodiment. Forming a contact hole in the first dielectric layer 60 may specifically include the following steps:

[0128] Step S521: An initial contact hole is formed in the first dielectric layer, the initial contact hole exposing the protective layer located on the sidewall of the power line.

[0129] In this step (not shown in the figures), an etching process can be used to remove part of the structure of the first dielectric layer 60 to form an initial contact hole in the first dielectric layer 60.

[0130] It is understandable that the etching reactant has a high etching selectivity for the first dielectric layer 60, but a low etching selectivity for the protective layer 40. Therefore, the protective layer 40 located on the sidewall of the power line 23 can be retained.

[0131] In some alternative implementations, the initial contact hole may also expose the top surface and sidewalls of the power line 23, so that the interconnect structure 30 formed in subsequent processes can be connected to both the top surface and sidewalls of the power line 23 simultaneously.

[0132] Step S522: Remove the protective layer exposed by the initial contact hole to expose the sidewall of the power line and form a contact hole.

[0133] In this step, a material with a high selectivity to the protective layer 40 can be selected as the etching reactant, and the protective layer 40 exposed by the initial contact hole can be removed by the etching process to expose the sidewall of the power line 23.

[0134] In this step, an initial contact hole is formed, which exposes at least a portion of the surface of the first source / drain 111a and the power line 23, thereby enabling the first source / drain 111a and the power line 23 to form an electrical connection through the interconnection structure 30.

[0135] In one exemplary embodiment, the method for manufacturing a semiconductor structure may further include the following steps:

[0136] Step S610: Remove part of the first dielectric layer and form a via in the first dielectric layer. The via only exposes the first source and drain electrodes of the first active region.

[0137] In this step, refer to Figure 9 and Figure 11Photolithography and etching processes can be used to remove part of the structure of the first dielectric layer 60 to form vias in the first dielectric layer 60. The vias can expose at least part of the top surface of the first source / drain electrode 111a of the first active region 11a.

[0138] Step S620: Form a conductive pillar in the through hole.

[0139] In this step, refer to Figure 9 and Figure 11 Conductive pillars can be formed in through-holes using a deposition process. The materials for the conductive pillars can be metals with good electrical conductivity, such as copper and tungsten.

[0140] To electrically connect the power line 23 to the first active region 11a, conductive posts need to be connected to the power line 23. For ease of explanation of the technical solution of this disclosure, the conductive post directly connected to the first active region 11a is defined as the first conductive post 71, and the conductive post directly connected to the power line 23 is defined as the second conductive post 72. The top surfaces of the first conductive post 71 and the second conductive post 72 are flush, and an interconnecting trace (not shown in the figure) can be provided between the first conductive post 71 and the second conductive post 72. Thus, voltage can be applied to the first active region 11a through the power line 23, the second conductive post 72, the interconnecting trace, and the first conductive post 71.

[0141] It should be noted that in the semiconductor structure manufacturing method provided in this disclosure, the power line 23 can be electrically connected to a portion of the first active region 11a through the interconnect structure 30, and the power line 23 can also be electrically connected to a portion of the first active region 11a through conductive pillars and interconnect traces.

[0142] In an exemplary embodiment, this embodiment is a further explanation of step S100 in the above embodiments, and providing the substrate may specifically include the following steps:

[0143] Step S110: A shallow trench is formed in the substrate, the shallow trench being located between the first active region and the preset region.

[0144] In this step, an anisotropic etching method can be used to etch from the top surface of the substrate 11 downwards to form a shallow trench in the substrate 11. The shallow trench is located between the first active region 11a and the preset region 11c to separate the first active region 11a and the preset region 11c.

[0145] Step S120: Fill the shallow trench with an isolation structure, wherein the interconnect structure covers the top surface of the isolation structure.

[0146] In this step, an insulating structure 80 can be deposited and filled in a shallow trench. For example, an oxide layer can be formed on the sidewall of the shallow trench first, and then an insulating material can be formed on the oxide layer. The insulating material and the oxide layer together constitute the insulating structure 80.

[0147] In this embodiment of the present disclosure, the isolation structure 80 is used to isolate the preset region 11c and the first active region 11a. Since the top surface of the isolation structure 80 is covered by the interconnect structure 30, and one side of the interconnect structure 30 is connected to the power line 23 on the preset region 11c of the substrate 11, and the other side of the interconnect structure 30 is connected to the first source-drain electrode 111a of the first active region 11a of the substrate 11, the power line 23 can apply voltage to the first active region 11a through the interconnect structure 30.

[0148] In one exemplary embodiment, the method for manufacturing a semiconductor structure prior to forming the conductive layer 20 may include the following steps:

[0149] Step S710: Form a dielectric layer that covers the top surface of a predetermined region of the substrate.

[0150] In this step, a dielectric material layer can be deposited on the substrate 11 first, and then a conductive layer 20 can be formed on the dielectric material layer, as shown in the reference. Figure 5 and Figure 6 By patterning the conductive layer 20 and the dielectric material layer, the dielectric material layer retained on the predetermined region 11c of the substrate 11 forms the dielectric layer 111c, and the conductive layer 20 retained on the predetermined region 11c of the substrate 11 forms the power line 23. The dielectric layer 111c can be an insulating material such as silicon dioxide (SiO2).

[0151] In one exemplary embodiment, the method for manufacturing a semiconductor structure may further include the following steps before forming the conductive layer 20:

[0152] Step S810: Pattern the storage array area to form plug holes in the storage array area.

[0153] In this step, multiple repeating memory cells are formed in the memory array region 11b. The memory array region 11b can be patterned using photolithography and etching processes to form multiple plug holes in the memory array region 11b. The multiple plug holes are correspondingly arranged with multiple memory cells. The plug holes can expose at least part of the structure of the memory cell, for example, the plug holes can expose the source or drain of the memory cell.

[0154] It should be noted that each memory cell includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain of the transistor is connected to the bit line, and the source of the transistor is connected to the capacitor. The switching on and off of the transistor is controlled by the voltage signal on the word line, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line. In practical applications, transistors, word lines, bit lines, and capacitors are sequentially formed within the array region. Therefore, transistors and word lines are already formed in the array region before the bit line plugs are formed, while the bit lines are formed after the bit line plugs are formed within the array region.

[0155] Step S820: A contact structure is formed in the plug hole, wherein a conductive layer covers the top surface of the contact structure.

[0156] In this step, a deposition process can be used to form a contact structure 111b in the plug hole. The conductive layer 20 formed in step S300 can cover the top surface of the contact structure 111b, so that the conductive layer 20 can be electrically connected to the memory cell through the contact structure 111b.

[0157] In an exemplary embodiment, this embodiment is a further explanation of step S400 in the above embodiment. The patterned stacked structure 12 and conductive layer 20 may include the following steps:

[0158] Step S410: Graphicalize the contact structure and conductive layer located in the memory array region to form bit lines in the memory array region.

[0159] In this step, such as Figure 4 and Figure 5 As shown, photolithography and etching processes can be used to remove part of the contact structure 111b and conductive layer 20 to pattern the contact structure 111b and conductive layer 20 located in the memory array region 11b. The conductive layer 20 remaining on the memory array region 11b forms bit lines 22. The projection of bit lines 22 on the substrate 11 intersects with the projection of word lines on the substrate 11. The angle of intersection can be, for example, 45°, 60°, 90°, etc.

[0160] According to exemplary embodiments of this disclosure, such as Figures 9 to 11 As shown, this disclosure provides a semiconductor structure, which includes a substrate 10, a gate, a power line 23, and an interconnect structure 30.

[0161] In this embodiment, as Figure 8 As shown, the substrate 10 includes a substrate 11, which is used to support components disposed thereon. The substrate 11 includes one of the following: silicon substrate, germanium substrate, silicon-germanium substrate, silicon-on-insulator (SOI) substrate, germanium-on-insulator (GOI) substrate, and glass substrate.

[0162] Among them, reference Figure 8 The substrate 11 has a preset region 11c and a first active region 11a, which can be peripheral regions on the substrate 11. For example, the first active region 11a can be the active region of the core control transistor in a semiconductor device, or the active region of the equalization transistor in a sensing amplifier circuit, etc. The preset region 11c can be, for example, the region in the semiconductor device used to set the power line 23.

[0163] like Figure 8 As shown, the gate of the semiconductor structure is located on the first active region 11a. By controlling the gate, the opening and closing of the channel region of the first active region 11a can be controlled, so that the first active region 11a has the function of controlling the semiconductor device.

[0164] like Figure 8 and Figure 10 As shown, the power line 23 of the semiconductor structure is located on a predetermined region 11c of the substrate 11. One end of the interconnect structure 30 is connected to the power line 23, and the other end of the interconnect structure 30 is connected to the first source-drain 111a of the first active region 11a. Thus, the current in the power line 23 can flow into the first active region 11a through the interconnect structure 30 to apply a voltage to the first active region 11a.

[0165] Among them, reference Figure 5 and Figure 6 In conjunction with the semiconductor structure manufacturing method provided in the above embodiments of this disclosure, it can be determined that in the embodiments of this disclosure, the gate and power line 23 are made of conductive layer 20 formed by the same process, so the semiconductor structure manufacturing process provided by this disclosure is simple, with high production efficiency and high yield.

[0166] In this embodiment, the interconnect structure 30 covers a portion of the surface of the power line 23 and the first source / drain 111a of the first active region 11a to connect the power line 23 and the first active region 11a. This allows power to be supplied to the first active region 11a through the power line 23 and the interconnect structure 30. Only one interconnect structure 30 is needed to electrically connect the power line 23 and the first active region 11a. Furthermore, the power line 23 and the gate can be made of the same conductive layer 20, which simplifies the process flow and improves production efficiency and yield.

[0167] In one exemplary embodiment, such as Figure 8 and Figure 10 As shown, the semiconductor structure includes a substrate 10, a gate, a power line 23, and an interconnect structure 30.

[0168] In this embodiment, as Figure 8 As shown, the semiconductor structure includes a first dielectric layer 60, which covers a portion of the top surface of the power line 23 and the first active region 11a.

[0169] Reference Figure 10 The first dielectric layer 60 has contact holes, and the interconnect structure 30 is located in the contact holes. The interconnect structure 30 includes a barrier layer 31 covering the bottom wall and sidewalls of the contact holes, and the interconnect structure 30 also includes a conductive structure 32 covering the bottom wall and sidewalls of the barrier layer 31.

[0170] In some embodiments, such as Figure 10 As shown, the semiconductor structure also includes a shallow trench isolation structure 80, which is located between the first active region 11a and the preset region 11c. The shallow trench isolation structure 80 may be made of an insulating material and is used to separate the first active region 11a and the preset region 11c.

[0171] Among them, reference Figure 10 The interconnect structure 30 covers the top surface of the shallow trench isolation structure 80, so that the interconnect structure 30 can electrically connect the separated first active region 11a and the power line 23, thereby enabling the power line 23 to supply power to the first active region 11a through the interconnect structure 30.

[0172] In some embodiments, such as Figure 8 As shown, the substrate 11 also includes a memory array region 11b, which is spaced apart from the preset region 11c and the first active region 11a.

[0173] In this semiconductor structure, the top surface of the memory array region 11b is sequentially provided with a contact structure 111b, a bit line 22, and a first dielectric layer 60. The bit line 22 and the power line 23 are formed by a conductive layer 20 manufactured using the same process. In the manufacturing process of the semiconductor structure provided by this disclosure, the bit line 22 and the power line 23 can be completed in one step, simplifying the process flow and improving production efficiency and yield.

[0174] It should be noted that the memory array region 11b includes multiple memory cells, each of which includes a capacitor and a transistor. The gate of the transistor is connected to the word line, the drain of the transistor is connected to the bit line, and the source of the transistor is connected to the capacitor. The switching on and off of the transistor is controlled by the voltage signal on the word line, thereby reading data information stored in the capacitor through the bit line, or writing data information into the capacitor for storage through the bit line.

[0175] In some embodiments, such as Figure 8As shown, a high-k dielectric layer 121 and a polysilicon layer 122 are further disposed between the first active region 11a of the substrate 11 and the gate electrode 21. The high-k dielectric layer 121 can be a single-layer or multi-layer structure. When the high-k dielectric layer 121 is a multi-layer structure, it can be, for example, a combination of metal layers, pad layers, wetting layers, adhesive layers, metal alloys, or metal silicides with selected work functions to enhance device performance. The thickness of the high-k dielectric layer 121 can depend on the specific requirements for the gate tunneling current.

[0176] Ions can be doped into the polysilicon layer 122, so that the resistance of the polysilicon layer 122 can be flexibly adjusted.

[0177] In some embodiments, such as Figure 9 As shown, the preset region 11c of the substrate 11 extends along the length direction and is located on one side of a plurality of first active regions 11a. The interconnect structure 30 consists of a plurality of first source and drain electrodes 111a that are respectively connected to the power line 23 and at least one first active region 11a, so that the interconnect structure 30 can supply power to each first active region 11a individually.

[0178] In some alternative implementations, refer to Figure 9 and Figure 11 The power line 23 can supply power to the first active region 11a through the conductive post, as explained in the foregoing embodiments, and will not be repeated here.

[0179] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0180] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0181] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0182] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0183] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0184] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a stacked structure covering the top surface of the substrate, the substrate including a first active region, a memory array region and a predetermined region; Remove the stacked structure covering the storage array area and the preset area to expose a portion of the top surface of the substrate; A conductive layer is formed, which covers the stacked structure of the first active region and the substrate exposed by the memory array region and the preset region; The stacked structure and the conductive layer are graphically represented to form a gate in the first active region and a power line in the preset region. An interconnect structure is formed, the interconnect structure covering a portion of the surface of the power line and a first source-drain electrode covering the first active region.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, The formation of the interconnect structure includes: A first dielectric layer is formed, which covers the top surface of the conductive layer and the first active region; A portion of the first dielectric layer is removed to form a contact hole in the first dielectric layer, the contact hole exposing at least a portion of the sidewalls and top surface of the power line, as well as exposing the first source and drain electrodes of the first active region; The interconnect structure is formed in the contact hole.

3. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, An interconnection structure is formed in the contact hole, including: A barrier layer is formed, which covers the bottom wall and sidewalls of the contact hole; A conductive structure is formed, which covers the bottom and sidewalls of the barrier layer.

4. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, Before forming the first dielectric layer, the method further includes: A protective layer is formed to cover the sidewalls of the gate and the sidewalls of the power lines.

5. The method for manufacturing a semiconductor structure according to claim 4, characterized in that, Forming contact holes in the first dielectric layer includes: An initial contact hole is formed in the first dielectric layer, the initial contact hole exposing a protective layer located on the sidewall of the power line; Remove the protective layer exposed by the initial contact hole to expose the sidewall of the power line and form a contact hole.

6. The method for manufacturing a semiconductor structure according to claim 2, characterized in that, The method for manufacturing the semiconductor structure further includes: A portion of the first dielectric layer is removed, and a via is formed in the first dielectric layer, wherein the via exposes only a portion of the first source and drain electrodes of the first active region; A conductive pillar is formed in the through hole.

7. The method for manufacturing a semiconductor structure according to any one of claims 1-6, characterized in that, The substrate provided includes: A shallow trench is formed in the substrate, the shallow trench being located between the first active region and the preset region; Fill the shallow trench with an isolation structure; The interconnect structure covers the top surface of the isolation structure.

8. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Before forming the conductive layer, the following steps are also included: A dielectric layer is formed, which covers the top surface of the predetermined region of the substrate.

9. The method for manufacturing a semiconductor structure according to claim 1, characterized in that, Before forming the conductive layer, the process also includes: The memory array region is patterned to form plug holes in the memory array region; A contact structure is formed within the plug hole; the conductive layer covers the top surface of the contact structure; When graphically representing the stacked structure and the conductive layer, the method further includes: The contact structure and conductive layer located in the memory array region are patterned to form bit lines in the memory array region.

10. A semiconductor structure, characterized in that, include: The substrate includes a substrate having a predetermined region and a first active region; A gate, the gate being located on the first active region; A power cord, which is located in the preset area; An interconnection structure connects the power line to the first source and drain of the first active region; The gate and the power line both include conductive layers formed using the same process.

11. The semiconductor structure according to claim 10, characterized in that, The semiconductor structure further includes a first dielectric layer, which covers a portion of the top surface of the power line and the first active region. The first dielectric layer has a contact hole, and the interconnect structure is located in the contact hole; The interconnect structure includes a barrier layer covering the bottom and sidewalls of the contact hole, and a conductive structure covering the bottom and sidewalls of the barrier layer.

12. The semiconductor structure according to claim 10, characterized in that, The substrate further includes a shallow trench isolation structure, which is located between the first active region and the preset region; The interconnect structure covers the top surface of the shallow trench isolation structure.

13. The semiconductor structure according to claim 11, characterized in that, The substrate further includes a memory array region, which is spaced apart from the preset region and the first active region; The top surface of the storage array region is sequentially provided with a contact structure, a bit line conductive layer and the first dielectric layer, wherein the bit line conductive layer and the power line are conductive layers formed by the same process.

14. The semiconductor structure according to claim 10, characterized in that, The gate also includes a high-k dielectric layer and a polysilicon layer stacked sequentially below the conductive layer.

15. The semiconductor structure according to claim 10, characterized in that, The preset region extends along the length direction and is located on one side of multiple first active regions. The interconnection structure consists of multiple interconnections and is respectively connected to the power line and the first source and drain of at least one first active region.

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