Display panel, display device

Abstract

The present disclosure provides a display panel and a display device. The display panel comprises a substrate, a plurality of first electrodes are arranged on the substrate, and the substrate further comprises a conductive adapter line having a first connection surface and a second connection surface which do not overlap with each other. The display panel further comprises a pixel definition layer, an organic light-emitting layer, a second electrode, a first insulating layer and a conductive trace layer arranged on the substrate in sequence. The pixel definition layer is provided with a first via hole and a second via hole, the second electrode is overlapped with the first connection surface through the first via hole, the first insulating layer is provided with a third via hole located in a region outside the second electrode, and the conductive trace layer comprises a first conductive trace overlapped with the second connection surface through the third via hole and the second via hole, and the first conductive trace is further connected with a first power line. The technical scheme of the present disclosure can reduce the product impedance and will not damage the second electrode, thereby improving the brightness uniformity of the product.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device. BACKGROUND

[0002] Organic Light-Emitting Diode (OLED) is a display and lighting technology that has gradually developed in recent years, especially in the display industry. OLED display is considered to have broad application prospects due to its high response, high contrast, and flexibility. Top-emitting OLED display devices have become the main research direction due to their higher aperture ratio. For top-emitting OLED structures, the top electrode, i.e., the cathode, as the light-emitting surface of the OLED must have good light transmittance. Currently, thin metals, indium tin oxide, and indium zinc oxide are commonly used for top-emitting electrodes.

[0003] The top-emitting electrode is usually a full-surface electrode, and the top-emitting electrode is connected to the power supply trace Vss in the frame area of the display panel. In order to achieve high transmittance of the top-emitting electrode, the thickness of the top-emitting electrode is relatively thin, which results in high resistance impedance of the top-emitting electrode. This leads to a large IR drop of the product, and thus poor brightness uniformity of the product, which is particularly evident in medium and large-sized products. SUMMARY

[0004] Embodiments of the present disclosure provide a display panel and a display device to solve or alleviate one or more technical problems in the prior art.

[0005] As a first aspect of the embodiments of the present disclosure, a display panel is provided, comprising a display area and a frame area outside the display area, the display panel comprising:

[0006] a substrate, a plurality of first electrodes are disposed on one side surface of the substrate, the substrate further comprising a conductive adapter line, the conductive adapter line having a first connection surface and a second connection surface on the side facing the first electrodes, the first connection surface and the second connection surface not overlapping each other;

[0007] a pixel definition layer disposed on the side of the substrate where the first electrodes are disposed, the pixel definition layer being provided with a plurality of openings through which the first electrodes are exposed, the pixel definition layer further being provided with a first via and a second via, at least part of the first connection surface being exposed through the first via, and at least part of the second connection surface being exposed through the second via;

[0008] an organic light-emitting layer disposed on the side of the pixel definition layer facing away from the substrate, the organic light-emitting layer being located in the openings, a projection of the organic light-emitting layer on the substrate not overlapping with projections of the first via and the second via on the substrate;

[0009] The second electrode is located on the side of the organic light-emitting layer away from the substrate, and a projection of at least one of the openings on the substrate is located within a projection range of the second electrode on the substrate. The second electrode is connected to the first connection surface through the first via. A projection of the second via on the substrate is located outside the projection of the second electrode on the substrate.

[0010] The first insulating layer is located on the side of the second electrode away from the substrate. The first insulating layer is located in the display area. The first insulating layer is provided with a third via. A projection of the third via on the substrate is located outside the projection of the second electrode on the substrate. At least part of the second connection surface is exposed through the third via.

[0011] The conductive trace layer is located on the side of the first insulating layer away from the substrate. The conductive trace layer includes a first conductive trace. The first conductive trace is connected to the second connection surface through the third via and the second via. The first conductive trace is connected to the first power line located in the frame area.

[0012] In an embodiment, the conductive jumper includes a first jumper and a second jumper connected to each other. An extension direction of the first jumper is parallel to an extension direction of the first conductive trace. A projection of the second jumper on the substrate intersects a projection of the first conductive trace on the substrate. The first connection surface is located on the first jumper. The second connection surface is located on the second jumper.

[0013] In an embodiment, a surface of the first jumper on the side facing the second electrode is exposed through the first via. The second electrode is connected to the surface of the first jumper on the side facing the second electrode through the first via.

[0014] In an embodiment, one opening corresponds to one sub-pixel area. The display panel includes a plurality of pixel areas. Each pixel area includes a plurality of sub-pixel areas. A projection of the second electrode on the substrate includes at least one pixel area.

[0015] In an embodiment, the conductive trace further includes a plurality of second conductive traces. The first conductive trace extends in a first direction. The second conductive trace extends in a second direction. The plurality of second conductive traces and the plurality of first conductive traces intersect each other to form a plurality of windows. At least one second electrode is arranged in each window.

[0016] In an embodiment, a minimum distance between a boundary of the projection of the second electrode on the substrate and a boundary of the sub-pixel area located in the second electrode is greater than or equal to 30 μm.

[0017] In an embodiment, a minimum distance between a boundary of the projection of the conductive jumper on the substrate and a boundary of the sub-pixel area is greater than or equal to 20 μm.

[0018] In an embodiment,

[0019] The orthographic projection of the first via on the substrate is located within the orthographic projection of the second electrode on the substrate, and the minimum distance between the boundary of the orthographic projection of the first via on the substrate and the boundary of the orthographic projection of the second electrode on the substrate is greater than or equal to 30 μm; and / or,

[0020] The distance between the boundary of the orthographic projection of the third via on the substrate and the boundary of the orthographic projection of the second electrode on the substrate is greater than or equal to 5 μm.

[0021] In one embodiment,

[0022] The conductive adapter line is arranged in the same layer as a source electrode or a drain electrode in the thin film transistor; or

[0023] The conductive adapter line is arranged in the same layer as the first electrode; or

[0024] The substrate includes a base, a thin film transistor located on one side of the base, and a second insulating layer located on a side of the thin film transistor away from the base, the conductive adapter line is located on a side of the second insulating layer away from the base, and the substrate further includes a third insulating layer located on a side of the conductive adapter line away from the base, and the first electrode is located on a side of the third insulating layer away from the base.

[0025] In one embodiment, the substrate further includes a third conductive trace, the conductive adapter line is further connected to the third conductive trace, and the third conductive trace is connected to the first power line.

[0026] In one embodiment, the third conductive trace is arranged in the same layer as the conductive adapter line, and the extension direction of the third conductive trace is parallel to the extension direction of the first conductive trace.

[0027] In one embodiment, the substrate includes a thin film transistor, the conductive adapter line is arranged in the same layer as a source electrode or a drain electrode in the thin film transistor, the substrate further includes a gate line, and the extension direction of the first adapter line is parallel to the extension direction of the gate line.

[0028] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device including the display panel in the embodiments of the present disclosure.

[0029] The technical scheme of the embodiment of the present disclosure is that the conductive adapter line is arranged in the substrate, the second electrode is connected with the first connecting surface of the conductive adapter line through the first via hole, and the first conductive trace is connected with the second connecting surface of the conductive adapter line through the third via hole and the second via hole, so that the second electrode can be connected with the first power line through the conductive adapter line and the first conductive trace. Compared with the second electrode layer with a relatively thin whole surface, the impedance of the conductive adapter line and the first conductive trace is smaller, so that the second electrode is connected with the first power line through the conductive adapter line and the first conductive trace, the impedance between the second electrode and the first power line can be reduced, the product impedance is reduced, and the brightness uniformity of the product is improved. In addition, the orthographic projection of the third via hole on the substrate is located outside the orthographic projection of the second electrode on the substrate, so that the first insulating layer can completely cover the second electrode and protect the second electrode, and the second electrode will not be damaged in the process of etching the first insulating layer to form the third via hole, so the OLED device will not be damaged.

[0030] The above summary is intended to illustrate only and is not intended to limit in any way. Further aspects, embodiments and features of the present disclosure will be readily apparent from the following detailed description, taken in conjunction with the accompanying drawings and claims, by which all parties are to be treated as fully supported. BRIEF DESCRIPTION OF DRAWINGS

[0031] In the drawings, like reference numerals will be used to represent like elements throughout the several views. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the present disclosure. It should be understood that the drawings are merely depictions of some embodiments of the present disclosure and should not be construed as limiting the present disclosure in any way.

[0032] Figure 1 A schematic diagram of a planar structure of a display panel in an embodiment of the present disclosure is shown in FIG. 1.

[0033] Figure 2 A schematic diagram of a cross section of B-B in FIG. 1 in an embodiment is shown in FIG. 2. Figure 1

[0034] A schematic diagram of a cross section of A-A in FIG. 1 in an embodiment is shown in FIG. 3. Figure 3 Figure 1 A schematic diagram of a planar structure of a display panel in another embodiment of the present disclosure is shown in FIG. 4.

[0035] Figure 4A A schematic diagram of a planar structure of a display panel in another embodiment of the present disclosure is shown in FIG. 4. Figure 1 A schematic diagram of a planar structure of a display panel in another embodiment of the present disclosure is shown in FIG. 4.

[0036] Figure 4B A schematic diagram of a planar structure of a display panel in another embodiment of the present disclosure is shown in FIG. 4.

[0037] Figure 5 A schematic diagram of a planar structure of a display panel in another embodiment of the present disclosure is shown in FIG. 4. A schematic diagram of a planar structure of a display panel in another embodiment of the present disclosure is shown in FIG. 4.

[0038] Figure 6A is a schematic view of a C-C cross section in the display panel of the present disclosure; Figure 5

[0039] Figure 6B is a schematic view of a D-D cross section in the display panel of the present disclosure; Figure 5

[0040] Figure 7 is a schematic view of a planar structure of a display panel in another embodiment of the present disclosure;

[0041] Figure 8A is a schematic view of a structure after forming a substrate in a display panel of an embodiment of the present disclosure;

[0042] Figure 8B is a schematic view of a structure after forming a second electrode in a display panel of an embodiment of the present disclosure;

[0043] Figure 8C is a schematic view of a structure after forming a conductive trace layer in a display panel of an embodiment of the present disclosure.

[0044] BRIEF DESCRIPTION OF DRAWINGS

[0045] 10, substrate; 11, first electrode; 12, conductive jumper; 121, first jumper; 122, second jumper; 123, third conductive trace; 131, source electrode; 132, drain electrode; 14, third insulating layer; 141, fourth via hole; 142, fifth via hole; 15, second insulating layer; 16, base; 17, interlayer insulating layer; 21, pixel definition layer; 210, opening; 211, first via hole; 212, second via hole; 22, organic light emitting layer; 23, second electrode; 24, first insulating layer; 241, third via hole; 251, first conductive trace; 252, second conductive trace; 26, fourth insulating layer; 27, fifth insulating layer. DETAILED DESCRIPTION

[0046] In the following, only certain example embodiments are simply described. As those skilled in the art can recognize, the described embodiments can be modified in various different ways without departing from the spirit or scope of the present disclosure, and different embodiments can be combined arbitrarily without conflict. Therefore, the drawings and the description are considered to be exemplary in nature rather than limiting.

[0047] ​​Related technologies employ auxiliary cathodes to reduce the in-plane impedance of the cathode in OLED display panels, thereby reducing product voltage drop. There are two main methods: First, metal traces are placed in the substrate, and the cathode is connected to these traces via vias, reducing cathode impedance. Second, an inorganic encapsulation layer is placed above the cathode, with metal traces placed on this layer and vias formed within it. The metal traces are then connected to the cathode vias, further reducing cathode impedance. In the first method, there are many traces in the substrate, and these traces must be located in non-sub-pixel areas, limiting their area. In the second method, to achieve the connection between the metal traces and the cathode, the cathode needs to be directly exposed through vias, which can damage the cathode layer during the etching process of forming the vias, causing damage to the OLED device.

[0048] To address the issue of excessive cathode impedance in OLED products, this disclosure provides a display panel.

[0049] Figure 1 This is a schematic diagram of the planar structure of the display panel according to one embodiment of the present disclosure. Figure 2 for Figure 1 A cross-sectional schematic diagram of BB in one embodiment. Figure 3 for Figure 1 A cross-sectional schematic diagram of AA in one embodiment. (See figure) Figure 1 As shown, the display panel includes a display area and a bezel area located outside the display area. The display panel also includes a first power line Vss located in the bezel area, which may be arranged around the display area. The first power line Vss may be a cathode signal line of the substrate 10, for example, the voltage of the first power line Vss may be -2V to -5V.

[0050] like Figure 1 , Figure 2 and Figure 3 As shown, the display panel includes a substrate 10, and a plurality of first electrodes 11 are disposed on one side surface of the substrate 10. The substrate 10 also includes conductive connection lines 12, each having a first connection surface and a second connection surface on the side facing the first electrodes 11, the first connection surface and the second connection surface not overlapping each other. For example, as... Figure 2 and Figure 3 In the substrate 10, the first electrode 11 is located on the upper surface of the substrate 10, and both the first connection surface and the second connection surface are exposed to the upper side. That is to say, in the substrate 10, there is no shielding film layer on the upper side of the first connection surface and the second connection surface.

[0051] The display panel further comprises a pixel definition layer 21 located on the side of the substrate 10 where the first electrode 11 is provided, and the pixel definition layer 21 is provided with a plurality of openings 210. The plurality of openings 210 can correspond to the plurality of first electrodes 11 one by one. The first electrode 11 is exposed through the corresponding opening 210. The pixel definition layer 21 is further provided with a first via hole 211 and a second via hole 212, at least part of the first connection surface is exposed through the first via hole 211, and at least part of the second connection surface is exposed through the second via hole 212. The first via hole 211 and the second via hole 212 can both be located in a region outside the opening 210.

[0052] The display panel further comprises an organic light-emitting layer 22 and a second electrode 23. The organic light-emitting layer 22 is located on the side of the first electrode 11 and the pixel definition layer 21 away from the substrate 10. The organic light-emitting layer 22 is located in the opening 210. Exemplarily, the organic light-emitting layer 22 can cover the exposed surface of the first electrode 11. The orthographic projection of the organic light-emitting layer 22 on the substrate 10 can include the orthographic projection of the opening 210 on the substrate 10. The orthographic projection of the organic light-emitting layer 22 on the substrate 10 does not overlap with the orthographic projection of the first via hole 211 and the second via hole 212 on the substrate 10, that is, the orthographic projection of the first via hole 211 and the second via hole 212 on the substrate 10 is located outside the orthographic projection of the organic light-emitting layer 22 on the substrate 10.

[0053] The second electrode 23 is located on the side of the organic light-emitting layer 22 away from the substrate 10, and the orthographic projection of at least one opening 210 on the substrate 10 is located within the orthographic projection of the second electrode 23 on the substrate 10. The orthographic projection of the second electrode 23 on the substrate 10 includes the orthographic projection of the first via hole 211 on the substrate 10, so that the second electrode 23 is connected to the first connection surface through the first via hole 211. The orthographic projection of the second via hole 212 on the substrate 10 is located outside the orthographic projection of the second electrode 23 on the substrate 10, which makes the second electrode 23 not connected to the second connection surface through the second via hole 212. Exemplarily, the OLED device can comprise the first electrode 11, the organic light-emitting layer 22 and the second electrode 23 which are arranged in a stack. The first electrode 11 can be an anode of the OLED device, and the second electrode 23 can be a cathode of the OLED device.

[0054] The display panel further comprises a first insulating layer 24 and a conductive trace layer. The first insulating layer 24 is located on the side of the second electrode 23 away from the substrate 10. The first insulating layer 24 can be located in the display area. The first insulating layer 24 is provided with a third via hole 241, and the orthographic projection of the third via hole 241 on the substrate 10 is located outside the orthographic projection of the second electrode 23 on the substrate 10. At least part of the second connection surface is exposed through the third via hole 241, that is, at least part of the second connection surface is exposed through the second via hole 212 and the third via hole 241.

[0055] The conductive trace layer is located on the side of the first insulating layer 24 facing away from the substrate 10. The conductive trace layer includes a first conductive trace 251, which is connected to the second connection surface via a third via 241 and a second via 212. The first conductive trace 251 is connected to a first power line Vss located in the frame area, thereby allowing the second electrode 23 to be connected to the first conductive trace 251 via the conductive adapter 12, and subsequently to the first power line Vss.

[0056] In this embodiment of the display panel, a conductive adapter line 12 is provided in the substrate 10. A second electrode 23 is connected to the first connection surface of the conductive adapter line 12 through a first via 211, and a first conductive trace 251 is connected to the second connection surface of the conductive adapter line 12 through a third via 241 and a second via 212. Thus, the second electrode 23 can be connected to the first power line Vss through the conductive adapter line 12 and the first conductive trace 251. Compared to a thinner second electrode layer, the conductive adapter line 12 and the first conductive trace 251 have lower impedance. Therefore, connecting the second electrode 23 to the first power line Vss through the conductive adapter line 12 and the first conductive trace 251 reduces the impedance between the second electrode 23 and the first power line Vss, lowers the product impedance, and improves the brightness uniformity of the product.

[0057] In addition, the orthogonal projection of the third via 241 on the substrate 10 is outside the orthogonal projection of the second electrode 23 on the substrate 10. Therefore, the first insulating layer 24 can completely cover the second electrode 23 and protect the second electrode 23. The second electrode 23 will not be damaged during the etching of the first insulating layer 24 to form the third via 241, and thus the OLED device will not be damaged.

[0058] In one embodiment, the conductive adapter wire 12 can be made of a conductive material, such as a conductive metal, indium tin oxide, indium zinc oxide, etc. Figure 1 As shown, the conductive adapter line 12 may include a first adapter line 121 and a second adapter line 122 that are interconnected. The orthographic projection of the first adapter line 121 on the substrate 10 does not overlap with the orthographic projection of the first conductive trace 251 on the substrate 10. The orthographic projection of the second adapter line 122 on the substrate 10 intersects with the orthographic projection of the first conductive trace 251 on the substrate 10.

[0059] For example, such as Figure 1 As shown, the extension direction of the first adapter line 121 can be parallel to the extension direction of the first conductive trace 251. The orthographic projection of the second adapter line 122 on the substrate 10 intersects the orthographic projection of the first conductive trace 251 on the substrate 10. For example, in Figure 1In this configuration, the orthographic projection of the second adapter line 122 on the substrate 10 is perpendicular to and intersects with the orthographic projection of the first conductive trace 251 on the substrate 10. A first connecting surface is located on the first adapter line 121, allowing the second electrode 23 to be connected to the first adapter line 121 via the first connecting surface. A second connecting surface is located on the second adapter line 122, allowing the second adapter line 122 to be connected to the first conductive trace 251 via the second connecting surface. This structure of the conductive adapter line 12 facilitates the formation of non-overlapping first and second connecting surfaces, and makes it easier to achieve a connection where the second electrode 23 overlaps with the first connecting surface without overlapping with the second connecting surface, thus reducing manufacturing complexity.

[0060] In one implementation, such as Figure 2 and Figure 3 As shown, the first adapter cable 121 is located within the orthographic projection range of the first via 211 on the substrate. Therefore, the surface of the first adapter cable 121 facing the second electrode 23 is exposed through the first via 211, and the second electrode 23 is connected to the surface of the first adapter cable 121 facing the second electrode 23 through the first via 211. With this structure, the surface of the first adapter cable 121 facing the second electrode 23 is entirely the first connection surface, and this first connection surface can be fully exposed through the first via 211. This increases the contact area between the second electrode 23 and the first adapter cable 121, further reducing the impedance between the second electrode 23 and the first power line Vss, lowering the product impedance, and further improving the brightness uniformity of the product.

[0061] In one implementation, such as Figure 3 As shown, the orthographic projection of the second via 212 on the substrate 10 includes the orthographic projection of the second connecting surface on the substrate 10, and the orthographic projection of the third via 241 on the substrate 10 may include the orthographic projection of the second via 212 on the substrate 10. Therefore, the entire second connecting surface can be connected to the first conductive trace 251, increasing the contact area between the first conductive trace 251 and the second adapter line 122, further reducing the impedance between the second electrode 23 and the first power line Vss, lowering the product impedance, and further improving the brightness uniformity of the product.

[0062] In one implementation, such as Figure 1As shown in FIG. 1, one opening 210 corresponds to one sub-pixel region. The display panel can include a plurality of pixel regions, and each pixel region includes a plurality of sub-pixel regions. The orthographic projection of the second electrode 23 on the substrate 10 includes at least one pixel region, that is, at least one pixel region is located within the orthographic projection range of the second electrode 23 on the substrate 10. If one second electrode 23 corresponds to one sub-pixel region, the number of second electrodes 23 in the display panel is the same as the number of sub-pixel regions, and the area of the second electrode 23 is relatively small, which increases the process difficulty of the second electrode 23. By setting the orthographic projection of the second electrode 23 on the substrate 10 to include at least one pixel region, the area of the second electrode 23 can be increased, the number of second electrodes 23 in the display panel can be reduced, and the process difficulty of the second electrode 23 can be reduced. In addition, each sub-pixel in the same pixel region corresponds to the same second electrode 23, so that the brightness of each sub-pixel in the same pixel is consistent, the brightness uniformity of the pixel is improved, and the brightness uniformity of the entire display area is improved.

[0063] Figure 4A For Figure 1 a plan view of one second electrode in another embodiment, Figure 4B a plan view of one second electrode in another embodiment. In an embodiment, as Figure 4A shown in FIG. 1, the orthographic projection of the second electrode 23 on the substrate 10 includes one pixel region. The first sub-pixel R, the second sub-pixel G, and the third sub-pixel B are arranged in the pixel region.

[0064] In an embodiment, as Figure 4A shown in FIG. 1, the minimum distance d between the boundary of the orthographic projection of the second electrode 23 on the substrate 10 and the boundary of the sub-pixel region located in the second electrode 23 is greater than or equal to 30 μm. For example, in Figure 4A the embodiment shown in FIG. 1, among the boundaries of the orthographic projection of the second electrode 23 on the substrate 10, the distance between the upper boundary of the second electrode 23 and the upper boundaries of the first sub-pixel R and the third sub-pixel B is greater than or equal to 30 μm; the distance between the right boundary of the second electrode 23 and the right boundary of the third sub-pixel B is greater than or equal to 30 μm; the distance between the left boundary of the second electrode 23 and the left boundaries of the first sub-pixel R and the second sub-pixel G is greater than or equal to 30 μm; and the distance between the lower boundary of the second electrode 23 and the lower boundaries of the second sub-pixel G and the third sub-pixel B is greater than or equal to 30 μm. It can be understood that there is a process error in the process of forming the second electrode 23. By setting d to be greater than or equal to 30 μm, it can be ensured that the formed second electrode 23 covers each sub-pixel in the pixel region, and the influence of the process error is avoided.

[0065] In an embodiment, as Figure 4AAs shown, the minimum distance 'a' between the orthographic projection boundary of the conductive adapter line 12 on the substrate 10 and the boundary of the sub-pixel region is greater than or equal to 20 μm. For example, in Figure 4A In this configuration, the second adapter line 122 is located on the side of the first adapter line 121 away from the sub-pixel region. The minimum distance 'a' between the orthographic projection boundary of the conductive adapter line 12 on the substrate 10 and the boundary of the sub-pixel region is the distance between the upper boundary of the first adapter line 121 and the lower boundary of the third sub-pixel B. Alternatively, the minimum distance 'a' between the orthographic projection boundary of the conductive adapter line 12 on the substrate 10 and the boundary of the sub-pixel region is the distance between the upper boundary of the first adapter line 121 and the lower boundary of the second sub-pixel G. This configuration avoids the organic light-emitting layer 22 from covering the first adapter line 121 due to process errors, ensuring that the organic light-emitting layer 22 can avoid the first adapter line 121.

[0066] In one embodiment, such as Figure 4A As shown, the orthographic projection of the first via 211 on the substrate 10 lies within the orthographic projection of the second electrode 23 on the substrate 10. The minimum distance between the boundary of the orthographic projection of the second electrode 23 on the substrate 10 and the boundary of the orthographic projection of the first via 211 on the substrate 10 is greater than or equal to 30 μm. For example, as... Figure 4A As shown, the surface of the first adapter cable 121 facing the second electrode 23 is the first connection surface. When the second electrode 23 is fully connected to the first connection surface through the first via 211, the minimum distance between the orthographic projection boundary of the second electrode 23 on the substrate 10 and the orthographic projection boundary of the first via 211 on the substrate 10 is the distance e between the lower boundary of the second electrode 23 and the lower boundary of the first adapter cable 121, and the distance e is greater than or equal to 30 μm. This method allows the second electrode 23 to cover the first via 211, thereby ensuring that the second electrode 23 can be fully connected to the first connection surface exposed through the second via 212, reducing the contact resistance between the second electrode 23 and the conductive adapter cable 12.

[0067] In one implementation, such as Figure 4A As shown, the minimum distance between the orthographic projection boundary of the second via 212 on the substrate 10 and the orthographic projection boundary of the second electrode 23 on the substrate 10 is greater than or equal to 5 μm. Figure 4A In this process, the minimum distance between the orthographic projection boundary of the second via 212 on the substrate 10 and the orthographic projection boundary of the second electrode 23 on the substrate 10 is the distance f between the upper boundary of the second via 212 and the lower boundary of the second electrode 23, and the distance f is greater than or equal to 5 μm. Setting the minimum distance between the orthographic projection boundary of the second via 212 on the substrate 10 and the orthographic projection boundary of the second electrode 23 on the substrate 10 to be greater than or equal to 5 μm ensures that the second electrode 23 will not be damaged when etching to form the third via 241.

[0068] The width b of the first conductive connection line 121, that is, the dimension of the first conductive connection line 121 perpendicular to its extending direction, can be 2.5 - 3.5 μm. For example, b can be 3 μm. The length of the first conductive connection line 121 can be equal to the size of the pixel. For example, the left boundary of the first conductive connection line 121 is flush with the left boundary of the first sub-pixel R or the second sub-pixel G, and the right boundary of the first conductive connection line 121 can be flush with the right boundary of the third sub-pixel B.

[0069] It should be noted that Figure 1 and Figure 4A In the pixel region shown in, the arrangement of the sub-pixels is in a "pin" shape. It can be understood that the arrangement manner of the sub-pixels in the pixel region can be set as required and is not limited to the "pin" shape.

[0070] In one embodiment, the display panel includes multiple pixel regions. The orthographic projection of the conductive connection line 12 on the substrate is located between adjacent pixel regions and close to one side of the pixel region. For example, in Figure 1 , the orthographic projection of the conductive connection line 12 on the substrate is located between two adjacent pixel regions in the same column; the conductive connection line 12 can be close to the pixel region towards which the first conductive connection line 121 faces. For example, in Figure 1 , the first conductive connection line 121 faces the pixel region on the upper side. Therefore, the conductive connection line 12 is close to the pixel region on the upper side, which is beneficial to realizing the lap connection between the second electrode corresponding to the pixel region on the upper side and the first conductive connection line.

[0071] In one embodiment, as in Figure 1 and Figure 4A , Figure 4B shown, the pixel region is provided with a first sub-pixel R, a second sub-pixel G, and a third sub-pixel B. In the pixel region, the first sub-pixel R and the second sub-pixel G are arranged along the column direction, and the third sub-pixel B is located on the same side of the first sub-pixel R and the second sub-pixel G. The conductive connection line 12 is located on the side of the second sub-pixel G away from the first sub-pixel R. For example, in Figure 4A , the first sub-pixel R is located above the second sub-pixel G, and the conductive connection line 12 is located below the second sub-pixel G.

[0072] In one embodiment, the second conductive connection line 122 is connected to one end of the first conductive connection line 121. Exemplarily, as in Figure 4A shown, the second conductive connection line 122 is perpendicularly connected to one end of the first conductive connection line 121. Thus, the conductive connection line 12 is in an "L" shape.

[0073] In another embodiment, the second conductive connection line 122 is connected to a non-endpoint position of the first conductive connection line 121. Exemplarily, as in Figure 4BAs shown, the second adapter wire 122 is perpendicularly connected to the non-endpoint position of the first adapter wire 121, so that the conductive adapter wire 12 is in the shape of a "T".

[0074] In one embodiment, such as Figure 2 As shown, the orthographic projections of the third via 241 and the second via 212 on the substrate 10 coincide.

[0075] like Figure 1 As shown, the conductive trace may further include a second conductive trace 252. The first conductive trace 251 extends along a first direction X, and the second conductive trace 252 may extend along a second direction Y. The second conductive trace 252 is connected to a first power line Vss located in the border area. Exemplarily, the second direction Y may be perpendicular to the first direction X. Figure 1 In the illustrated embodiment, the first direction X can be a row direction, and the second direction Y can be a column direction. The second conductive traces 252 can be located between adjacent pixel areas. There are multiple first conductive traces 251, arranged along the second direction. There are also multiple second conductive traces 252, arranged along the first direction. The multiple second conductive traces 252 and multiple first conductive traces 251 are interconnected to form multiple windows. Each window contains at least one second electrode 23. Each second electrode 23 is connected to a corresponding conductive adapter line 12. The first conductive traces 251 are connected to the conductive adapter lines 12 corresponding to each second electrode 23 in the same row. With this conductive trace structure, the first conductive traces 251 and second conductive traces 252 are located between adjacent pixel areas, which does not affect the display. Furthermore, the grid-like conductive traces increase the number of conductive traces, further reducing the connection impedance between the second electrode 23 and the first power line Vss.

[0076] It should be noted that, Figure 1 In one embodiment, a second electrode 23 is provided in a window. In other embodiments, two or more second electrodes 23 may be provided in a window.

[0077] In one embodiment, the conductive adapter line 12 can be disposed in the same layer as the first electrode 11. Therefore, before the pixel definition layer 21 is formed, the upper surface of the conductive adapter line 12 is exposed. The first connection surface can be a part of the upper surface of the conductive adapter line 12, and the second connection surface can be another part of the upper surface of the conductive adapter line 12.

[0078] For example, the conductive adapter line 12 can be disposed in the same layer as the first electrode 11. It can be understood that the conductive adapter line 12 can be formed with the first electrode 11 in one process. That is, the conductive adapter line 12 is formed at the same time as the first electrode 11 is formed.

[0079] The conductive adapter line 12 can be disposed in the same layer as the first electrode 11. Alternatively, it can be understood that the conductive adapter line 12 and the first electrode 11 are disposed on the surface of the same film layer. The conductive adapter line 12 can be located in a region outside the first electrode 11. The conductive adapter line 12 and the first electrode 11 can be formed using different processes. The material of the conductive adapter line 12 can be different from that of the first electrode 11.

[0080] In one embodiment, such as Figure 2 As shown, a thin-film transistor is disposed in the substrate 10, and the conductive connection line 12 can be disposed in the same layer as the source electrode 131 or drain electrode 132 in the thin-film transistor. Exemplarily, the conductive connection line 12 is formed with the source electrode 131 and drain electrode 132 in a single process, so that the placement of the conductive connection line 12 does not increase the number of masks on the substrate 10. The substrate 10 may also include a third insulating layer 14 located above the thin-film transistor, such as the source electrode 131 and drain electrode 132. Exemplarily, the third insulating layer 14 can be made of a resin material, thereby forming a planar film layer. The third insulating layer 14 may be provided with a fourth via 141 and a fifth via 142 that do not overlap. The surface of the conductive connection line 12 exposed through the fourth via 141 can be a first connection surface, and the surface of the conductive connection line 12 exposed through the fifth via 142 can be a second connection surface.

[0081] For example, when the conductive transition line 12 is disposed on the same layer as the source electrode 131 or drain electrode 132 in the thin-film transistor, the extension direction of the first transition line 121 of the conductive transition line 12 can be set as needed. For example, the extension direction of the first transition line 121 can be parallel to the extension direction of the gate line in the substrate 10. The extension direction of the first conductive trace 251 can be parallel to the extension direction of the gate line in the substrate 10.

[0082] In other embodiments, the conductive adapter line 12 can also be disposed on the same layer as the gate electrode of the thin-film transistor. By forming a via in the insulating layer above the gate metal layer, the second electrode 23 can also be connected to the conductive adapter line 12, and the first conductive trace 251 can be connected to the conductive adapter line 12.

[0083] Figure 5 This is a schematic diagram of the planar structure of the display panel in another embodiment of the present disclosure. Figure 6A for Figure 5 Schematic diagram of the CC section in the diagram; Figure 6B for Figure 5 A schematic diagram of the DD section. In one embodiment, such as... Figure 2 and Figure 6A As shown, substrate 10 may include substrate 16 and a thin-film transistor located on one side of substrate 16. Figure 6AIn this structure, the substrate 10 may further include a second insulating layer 15 located on the side of the thin-film transistor facing away from the substrate 16, and the conductive connection line 12 is located on the side of the second insulating layer 15 facing away from the substrate 16. The substrate 10 also includes a third insulating layer 14 located on the side of the conductive connection line 12 facing away from the substrate 16, and the first electrode 11 is located on the side of the third insulating layer 14 facing away from the substrate 16. The third insulating layer 14 may be made of a resin material, thereby forming a planar film layer. The second insulating layer 15 may be made of silicon nitride, silicon oxide, silicon oxynitride, or resin. In this structure, the conductive connection line 12 is disposed in a separate metal layer, and the shape and size of the conductive connection line 12 can be set as needed.

[0084] In one embodiment, such as Figure 5 and Figure 6B As shown, the substrate 10 may further include a third conductive trace 123, and the conductive adapter line 12 may be connected to the third conductive trace 123. The third conductive trace 123 is connected to the first power line Vss. In this way, the impedance between the second electrode 23 and the first power line Vss can be further reduced, thereby further improving the brightness uniformity.

[0085] For example, such as Figure 5 and Figure 6B As shown, the third conductive trace 123 can be disposed on the same layer as the conductive adapter line 12. For example, the third conductive trace 123 can be formed with the conductive adapter line 12 in a single process. The extension direction of the third conductive trace 123 can be parallel to the extension direction of the first conductive trace 251. Exemplarily, the first adapter line 121 can be a part of the third conductive trace 123. Figure 5 and Figure 6A In the illustrated embodiment, the extension direction of the third conductive trace 123 can be set as needed. In the BB section of the display panel... Figure 2 In the embodiment shown, the third conductive trace 123 must avoid the data lines of the display panel.

[0086] In one embodiment, such as Figure 2 and Figure 6A As shown, the display panel may further include a fourth insulating layer 26 and a fifth insulating layer 27. The fourth insulating layer 26 may be located on the side of the first insulating layer 24 and the conductive wiring layer facing away from the substrate 10. The fourth insulating layer 26 may be made of an organic material. The fifth insulating layer 27 is located on the side of the fourth insulating layer 26 facing away from the substrate 10, and the fifth insulating layer 27 may be made of an inorganic material. Thus, the first insulating layer 24, the fourth insulating layer 26, and the fifth insulating layer 27 can form an encapsulation layer to protect the OLED devices in the display panel.

[0087] Figure 7This is a schematic diagram of the planar structure of the display panel according to another embodiment of this disclosure. Figure 7 In the illustrated embodiment, the first direction X can be a column direction, and the second direction Y can be a row direction. The orthographic projection of the conductive adapter line 12 on the substrate is located between two adjacent pixel regions in the same row.

[0088] In an exemplary embodiment, the first insulating layer 24, the fifth insulating layer 27, and the interlayer insulating layer may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers. The second insulating layer 15 and the third insulating layer 14 may be made of resin material. The gate electrode, source electrode, drain electrode, and conductive traces may be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The pixel defining layer may be made of polyimide, acrylic, or polyethylene terephthalate, etc. The active layer of a thin-film transistor can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. In other words, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0089] The following is through Figure 2 The fabrication process of the display panel shown further illustrates the technical solution of the embodiments of this disclosure. It is understood that the term "patterning" as used herein includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping when the patterning material is inorganic or metallic; and processes such as mask exposure and development when the patterning material is organic. Evaporation, deposition, coating, and plating as mentioned herein are all mature fabrication processes in related technologies.

[0090] A thin-film transistor is formed on one side of the substrate 16. The process of forming the source electrode 131 and drain electrode 132 of the thin-film transistor may include: depositing source and drain metal layers on the side of the interlayer insulating layer 17 facing away from the substrate 16; patterning the source and drain metal layers to form the source electrode 131, drain electrode 132, and conductive transition line 12, such as... Figure 8A As shown, Figure 8A This is a schematic diagram of the structure of a display panel after a substrate has been formed, according to an embodiment of the present disclosure.

[0091] A second insulating layer 15 is formed on the side of the thin-film transistor facing away from the substrate 16. The second insulating layer 15 has a fourth via 141 and a fifth via 142. The portion of the conductive adapter 12 exposed through the fourth via 141 is the first connection surface, and the portion of the conductive adapter 12 exposed through the fifth via 142 is the second connection surface. Figure 8A As shown.

[0092] A plurality of first electrodes 11 are formed on the side of the second insulating layer 15 opposite to the substrate 16.

[0093] A pixel definition layer 21 is formed on the side of the first electrode 11 facing away from the substrate 10, such as Figure 8B As shown, Figure 8B This is a schematic diagram of the structure of a display panel after the second electrode has been formed according to an embodiment of the present disclosure. The pixel definition layer 21 is provided with a plurality of openings 210, through which the first electrode 11 is exposed. The pixel definition layer 21 is also provided with a first via 211 and a second via 212, with at least a portion of the first connecting surface exposed through the first via 211 and at least a portion of the second connecting surface exposed through the second via 212. Exemplarily, the orthographic projection of the first via 211 onto the substrate 16 coincides with the orthographic projection of the fourth via 141 onto the substrate 16; the orthographic projection of the second via 212 onto the substrate 16 coincides with the orthographic projection of the fifth via 142 onto the substrate 16.

[0094] An organic light-emitting layer 22 is formed on the side of the pixel definition layer 21 facing away from the substrate 10. The organic light-emitting layer 22 is located at the opening 210 and avoids the first via 211 and the second via 212. Figure 8B As shown.

[0095] A second electrode 23 is formed on the side of the organic light-emitting layer 22 facing away from the substrate 10. The orthogonal projection of the second electrode 23 onto the substrate 10 includes at least one orthogonal projection of an opening 210 onto the substrate 10. The second electrode 23 is connected to the first connecting surface via a first via 211. The orthogonal projection of the second via 212 onto the substrate 10 is located outside the orthogonal projection of the second electrode 23 onto the substrate 10. Figure 8B As shown.

[0096] A first insulating layer 24 is formed on the side of the second electrode 23 facing away from the substrate 10. The first insulating layer 24 is located in the display area. A third via 241 is provided in the first insulating layer 24. The orthographic projection of the third via 241 on the substrate 10 is outside the orthographic projection of the second electrode 23 on the substrate 10. At least a portion of the second connection surface is exposed through the third via 241. Figure 8C As shown, Figure 8C This is a schematic diagram of the structure of a display panel after a conductive trace layer has been formed, according to an embodiment of this disclosure.

[0097] A conductive trace layer is formed on the side of the first insulating layer 24 facing away from the substrate 10. The conductive trace layer includes a first conductive trace 251. The first conductive trace 251 is connected to the second connection surface through a third via 241 and a second via 212. The first conductive trace 251 is connected to a first power line located in the frame area. Figure 8C As shown.

[0098] Based on the inventive concept of the foregoing embodiments, this disclosure also provides a display device, which includes a display panel employing the foregoing embodiments. The display device can be any product or component with display functionality, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0099] The technical solution disclosed herein involves providing conductive adapter lines in a substrate. A second electrode is connected to the first connection surface of the conductive adapter lines via a first via, and a first conductive trace is connected to the second connection surface of the conductive adapter lines via a third and a second via. Thus, the second electrode can be connected to the first power line Vss via the conductive adapter lines and the first conductive trace. Compared to a thinner second electrode layer, the conductive adapter lines and the first conductive trace have lower impedance. Therefore, connecting the second electrode to the first power line Vss via the conductive adapter lines and the first conductive trace reduces the impedance between the second electrode and the first power line Vss, lowering the product impedance and improving the brightness uniformity of the product.

[0100] In the description of this specification, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0101] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "multiple" means two or more, unless otherwise explicitly specified.

[0102] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection, an electrical connection, or a communication connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0103] In this disclosure, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0104] The foregoing disclosure provides many different implementations or examples for carrying out different structures of this disclosure. To simplify this disclosure, the components and arrangements of specific examples are described above. Of course, these are merely examples and are not intended to limit this disclosure. Furthermore, reference numerals and / or reference letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various implementations and / or arrangements discussed.

[0105] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any person skilled in the art can easily conceive of various variations or substitutions within the technical scope disclosed in this disclosure, and these should all be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, characterized in that, The display panel includes a display area and a border area located outside the display area. A substrate, wherein a plurality of first electrodes are disposed on one side surface of the substrate, and the substrate further includes a conductive adapter line, wherein the conductive adapter line has a first connection surface and a second connection surface that do not overlap with each other on the side facing the first electrodes. A pixel definition layer is located on the side of the substrate where the first electrode is disposed. The pixel definition layer is provided with a plurality of openings through which the first electrode is exposed. The pixel definition layer is also provided with a first via and a second via. At least a portion of the first connection surface is exposed through the first via, and at least a portion of the second connection surface is exposed through the second via. An organic light-emitting layer is located on the side of the pixel definition layer opposite to the substrate. The organic light-emitting layer is located at the opening. The orthographic projection of the organic light-emitting layer on the substrate does not overlap with the orthographic projections of the first via and the second via on the substrate. The second electrode is located on the side of the organic light-emitting layer opposite to the substrate. At least one of the openings is projected onto the substrate within the projection range of the second electrode onto the substrate. The second electrode is connected to the first connecting surface via the first via. The projection of the second via onto the substrate is outside the projection range of the second electrode onto the substrate. A first insulating layer is located on the side of the second electrode facing away from the substrate. The first insulating layer is provided with a third via. The orthographic projection of the third via on the substrate is outside the orthographic projection of the second electrode on the substrate. At least a portion of the second connection surface is exposed through the third via. A conductive trace layer is located on the side of the first insulating layer opposite to the substrate. The conductive trace layer includes a first conductive trace, which is connected to the second connection surface through the third via and the second via. The first conductive trace is connected to a first power line located in the frame area.

2. The display panel according to claim 1, characterized in that, The conductive adapter wire includes a first adapter wire and a second adapter wire that are connected to each other. The extension direction of the first adapter wire is parallel to the extension direction of the first conductive trace. The orthographic projection of the second adapter wire on the substrate intersects the orthographic projection of the first conductive trace on the substrate. The first connecting surface is located on the first adapter wire, and the second connecting surface is located on the second adapter wire.

3. The display panel according to claim 2, characterized in that, The surface of the first adapter cable facing the second electrode is exposed through the first via, and the second electrode is connected to the surface of the first adapter cable facing the second electrode through the first via.

4. The display panel according to any one of claims 1-3, characterized in that, Each opening corresponds to a sub-pixel region, the display panel includes multiple pixel regions, each pixel region includes multiple sub-pixel regions, and the orthogonal projection of the second electrode on the substrate includes at least one of the pixel regions.

5. The display panel according to claim 4, characterized in that, The conductive trace layer further includes multiple second conductive traces. The first conductive trace extends along a first direction, and the second conductive trace extends along a second direction. The multiple second conductive traces and the multiple first conductive traces intersect to form multiple windows, and each window is provided with at least one second electrode.

6. The display panel according to claim 4, characterized in that, The minimum distance between the orthographic projection boundary of the second electrode on the substrate and the boundary of the sub-pixel region located within the second electrode is greater than or equal to 30 μm.

7. The display panel according to claim 4, characterized in that, The minimum distance between the orthographic projection boundary of the conductive adapter line on the substrate and the boundary of the sub-pixel region is greater than or equal to 20 μm.

8. The display panel according to claim 4, characterized in that, The orthographic projection of the first via on the substrate is located within the orthographic projection of the second electrode on the substrate, and the minimum distance between the boundary of the orthographic projection of the second electrode on the substrate and the boundary of the orthographic projection of the first via on the substrate is greater than or equal to 30 μm; And / or, The distance between the orthographic projection boundary of the third via on the substrate and the orthographic projection boundary of the second electrode on the substrate is greater than or equal to 5 μm.

9. The display panel according to claim 1, characterized in that, A thin-film transistor is disposed in the substrate, and the conductive connection line is disposed in the same layer as the source electrode or drain electrode of the thin-film transistor; or... The conductive adapter wire is disposed in the same layer as the first electrode; or... The substrate includes a substrate, a thin-film transistor located on one side of the substrate, and a second insulating layer located on the side of the thin-film transistor opposite to the substrate. The conductive connection line is located on the side of the second insulating layer opposite to the substrate. The substrate also includes a third insulating layer located on the side of the conductive connection line opposite to the substrate. The first electrode is located on the side of the third insulating layer opposite to the substrate.

10. The display panel according to claim 1, characterized in that, The substrate further includes a third conductive trace, and the conductive adapter line is also connected to the third conductive trace, which is connected to the first power line.

11. The display panel according to claim 10, characterized in that, The third conductive trace is disposed on the same layer as the conductive adapter, and the extension direction of the third conductive trace is parallel to the extension direction of the first conductive trace.

12. The display panel according to claim 2, characterized in that, The substrate is provided with a thin-film transistor, and the conductive transition line is disposed on the same layer as the source electrode or drain electrode in the thin-film transistor. The substrate also includes a gate line, and the extension direction of the first transition line is parallel to the extension direction of the gate line.

13. A display device, characterized in that, The display panel includes any one of claims 1-12.

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