Host device and memory system

Abstract

During the period when the memory card is in the second operation mode, the host controller monitors the reset signal for the second operation mode, and detects the occurrence of an error in the second operation mode on the condition that the period in which both the card presence detection signal and the reset signal for the second operation mode are asserted lasts for more than the first period. The host controller generates a first interrupt signal for activating the first driver based on the detection of the occurrence of the error. If the first driver is activated due to the generation of the first interrupt signal, the operation mode of the memory card is changed from the second operation mode to the first operation mode by controlling the host controller.

Description

Technical Field

[0001] Embodiments of the present invention relate to a host device and a memory system for controlling a memory card. Background Art

[0002] In recent years, various memory cards have become widely used and are used in various host devices such as personal computers, mobile communication devices, game consoles, cameras, and vehicle-mounted equipment.

[0003] As an example of a memory card, an SD (registered trademark) card is known. Recently, a new memory card supporting two operation modes has been developed in the industry.

[0004] Background Art Literature

[0005] Patent Literature

[0006] Patent Document 1: U.S. Patent Application Publication No. 2020 / 0090020

[0007] Patent Document 2: International Publication No. 2018 / 186457 Summary of the invention

[0008] [Problems to be solved by the invention]

[0009] The problem to be solved by the present invention is to provide a host device and a memory system that are useful for controlling a memory card that supports two operation modes.

[0010] [Technical means to solve the problem]

[0011] According to an embodiment, a host device can control a memory card. The memory card supports: a first operation mode for communicating with the host device via a first interface, and a second operation mode for communicating with the host device via a second interface different from the first interface. The host device comprises: a host controller, a power supply circuit, and a communication control circuit. The host controller controls the memory card via the first interface under the control of a first driver, which is a program executed by a processor in the host device. The power supply circuit can supply the memory card with a first power supply voltage required for both the first operation mode and the second operation mode, and a second power supply voltage required only for the second operation mode and lower than the first power supply voltage. The communication control circuit starts communicating with the memory card via the second interface according to the assertion of a card presence detection signal under the control of a second driver, which is a program executed by the processor. When the memory card supports the second operation mode, the host controller turns on the second power supply voltage while the first power supply voltage is turned on, and asserts the card presence detection signal to the communication control circuit in such a manner that the operation mode of the memory card is changed from the first operation mode to the second operation mode. The host controller monitors the reset signal for the second operation mode output from the communication control circuit while the memory card is in the second operation mode. When the period in which both the card presence detection signal and the reset signal for the second operation mode are asserted lasts for more than the first period, the host controller detects that an error has occurred in the second operation mode, and generates a first interrupt signal for starting the first driver based on the detection of the error. When the first driver is started by the processor due to the first interrupt signal, the operation mode of the memory card is changed from the second operation mode to the first operation mode by controlling the host controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a block diagram showing a configuration example of a memory system including a host device according to an embodiment.

[0013] Figure 2 It is a block diagram showing the connection relationship between the SD host controller and the PCIe interface controller included in the host device according to the embodiment.

[0014] Figure 3 This is a diagram for explaining the timer count of the PCIe error detection process executed in the host device according to the embodiment.

[0015] Figure 4 This is a flowchart showing the procedure of an interruption cause identification process executed in the host device according to the embodiment.

[0016] Figure 5 This is a flowchart showing the procedure of PCIe error interrupt processing executed in the host device according to the embodiment.

[0017] Figure 6 This is a flowchart showing the steps of the operation mode switching process executed in the host device of the embodiment. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments will be described with reference to the drawings.

[0019] Figure 1 1 is a block diagram showing a configuration example of a memory system 1 including a host device 2 according to an embodiment.

[0020] The memory system 1 includes a host device 2 and a memory card 3. The memory card 3 is a removable storage device that can be inserted into a connector in the host device 2. The memory card 3 includes, for example, a nonvolatile memory and a controller that controls the nonvolatile memory. The memory card 3 is configured to write data to the nonvolatile memory in the memory card 3 and read data from the nonvolatile memory.

[0021] The memory card 3 supports two operation modes: a first operation mode for communicating with the host device 2 via a first interface and a second operation mode for communicating with the host device 2 via a second interface different from the first interface. That is, the memory card 3 is configured to operate in the first operation mode and the second operation mode.

[0022] The first interface is, for example, a conventional interface for a memory card, and the second interface is, for example, a general-purpose interface such as PCI Express (PCIe) (registered trademark).

[0023] The memory card 3 is not limited thereto, and may be implemented as, for example, an SD Express card (registered trademark). When the memory card 3 is implemented as an SD Express card, an SD interface, which is an existing interface for SD cards, is used as the first interface, and a PCIe interface is used as the second interface.

[0024] The SD Express card supports two operation modes: SD mode and PCIe / NVMe mode. The SD mode is an operation mode for communicating with the host device 2 via the SD interface. The PCIe / NVMe mode is an operation mode for communicating with the host device 2 via the PCIe interface.

[0025] The host device 2 includes both the first interface and the second interface. The host device 2 can control the memory card 3 using the first operation mode, and can also control the memory card 3 using the second operation mode.

[0026] Hereinafter, the configuration of the host device 2 will be described using the example of a case where the memory card 3 is an SD Express card.

[0027] The host device 2 is an information processing device that can be connected to the memory card 3. Examples of the host device 2 are personal computers, server computers, mobile terminals, vehicle-mounted devices, etc. The host device 2 includes a CPU 21, a system memory 22, a system controller 23, an SD host controller 24, a power supply circuit 25, and a switch circuit 26.

[0028] The CPU 21 is a processor configured to control a system controller 23 and an SD host controller 24. The CPU 21 accesses the system memory 22 via the system controller 23. In addition, the CPU 21 controls the SD host controller 24 via the system controller 23. Although the interface between the system controller 23 and the SD host controller 24 is not particularly limited, the SD host controller 24 is connected to the system controller 23 via, for example, a PCIe interface. The system controller 23 includes a PCIe interface controller 231, an interrupt controller 232, and the like.

[0029] The CPU 21 is a processor configured to execute control programs (operating system (OS), host driver, PCIe / NVM Express (NVMe) (registered trademark) driver, etc.) stored in the system memory 22. The host driver is a program (software driver) executed by the CPU 21. The CPU 21 controls the operation of the SD host controller 24 by executing the host driver. The PCIe / NVMe driver is a program (software driver) executed by the CPU 21. The CPU 21 controls the operation of the PCIe interface controller 231 by executing the PCIe / NVMe driver.

[0030] Hereinafter, the actions performed by the CPU 21 by executing the host driver and the PCIe / NVMe driver will be described as actions performed by the host driver and the PCIe / NVMe driver.

[0031] The system memory 22 is a main memory provided in the host device 2. The system memory 22 is implemented by, for example, a dynamic RAM (DRAM).

[0032] The power circuit 25 supplies two power supply voltages, namely, VDD1 (3.3V) as a first power supply voltage and VDD2 (1.8V) as a second power supply voltage, to the memory card 3 inserted into the connector of the host device 2 under the control of the SD host controller 24. VDD1 (3.3V) is a power supply voltage required for the memory card 3 to operate in the SD mode. On the other hand, in order to operate the memory card 3 in the PCIe / NVMe mode, both VDD1 (3.3V) and VDD2 (1.8V) must be supplied to the memory card 3.

[0033] The power circuit 25 controls the on / off of the power voltage VDD1 according to the first power voltage control signal VDD1-ON from the SD host controller 24. In addition, the power circuit 25 controls the on / off of the power voltage VDD2 according to the second power voltage control signal VDD2-ON from the SD host controller 24.

[0034] In more detail, the power circuit 25 turns on the first power supply voltage VDD1 when the first power supply control signal VDD1-ON is at a high level, and turns off the first power supply voltage VDD1 when the first power supply control signal VDD1-ON is at a low level. In addition, the power circuit 25 turns on the second power supply voltage VDD2 when the second power supply control signal VDD2-ON is at a high level, and turns off the second power supply voltage VDD2 when the second power supply control signal VDD2-ON is at a low level.

[0035] In the memory card 3, the power supply voltage VDD1 is supplied to a VDD1 terminal which is a power supply terminal of the memory card 3. The power supply voltage VDD2 is supplied to a VDD2 terminal which is another power supply terminal of the memory card 3.

[0036] The SD host controller 24 is a host controller configured to control the memory card 3 via the first interface (here, the SD interface) under the control of the host driver. The SD interface includes a clock signal SD CLK, an SD command SD CMD, and a 4-bit data signal DAT[3:0]. In this embodiment, in addition to communicating with the memory card 3 via the SD interface, the SD host controller 24 also performs, under the control of the host driver: a process for changing the operation mode of the memory card 3 from the SD mode to the PCIe / NVMe mode, and a process for returning the operation mode of the memory card 3 from the PCIe / NVMe mode to the SD mode.

[0037] Specifically, under the control of the host driver, the SD host controller 24 supplies the power circuit 25 with a first power control signal VDD1-ON for controlling on / off of the first power voltage VDD1 and a second power control signal VDD2-ON for controlling on / off of the second power voltage VDD2.

[0038] The SD host controller 24 first turns on the first power supply voltage VDD1 and supplies the clock signal SD CLK to the memory card 3, thereby temporarily operating the memory card 3 in the SD mode. The clock signal SD CLK is used to synchronize the operation timing of the SD interface circuit (not shown) in the memory card 3 with the operation timing of the SD host controller 24. The clock signal SD CLK is supplied to the clock CLK terminal of the memory card 3.

[0039] In addition, the SD host controller 24 sends an SD command SD CMD to the memory card 3. The SD command SD CMD includes various commands for controlling the memory card 3 using the SD mode. For example, the SD command SD CMD includes, in addition to I / O commands such as read / write commands, CMD0, a reset command for the SD mode, and CMD8, a command for checking functions supported by the memory card 3. The SD command SD CMD is supplied to the command CMD terminal of the memory card 3.

[0040] In addition, the SD host controller 24 performs a process of transmitting a 4-bit data signal DAT[3:0] to the memory card 3 via the switch circuit 26 , and a process of receiving a 4-bit data signal DAT[3:0] from the memory card 3 via the switch circuit 26 .

[0041] In addition, the SD host controller 24 receives a card detection signal Card Detection from a connector (not shown) into which the memory card 3 can be inserted. The card detection signal Card Detection is a signal indicating that the memory card 3 has been inserted into the connector, and that the memory card 3 has been removed from the connector (hereinafter referred to as removal). When the memory card 3 is inserted into the connector, the connector outputs a card detection signal Card Detection having a specific voltage level indicating that the memory card 3 has been inserted into the connector. In addition, when the memory card 3 is removed from the connector, the connector outputs a card detection signal Card Detection having another specific voltage level indicating that the memory card 3 has been removed from the connector. The SD host controller 24 can detect the insertion / removal of the memory card 3 based on the change in the voltage level of the card detection signal Card Detection. The signal voltage level of the card detection signal Card Detection varies depending on the detection method of the memory card 3. For example, in the case of using a pull-up method of pulling up the card detection signal Card Detection line, when the memory card 3 is inserted into the connector, the connector outputs a low-level card detection signal Card Detection indicating that the memory card 3 has been inserted into the connector. Furthermore, when the memory card 3 is removed from the connector, the connector outputs a high-level card detection signal Card Detection indicating that the memory card 3 has been removed from the connector.

[0042] In addition, when the memory card 3 is inserted into the connector and CMD8 detects that the memory card 3 supports the PCIe / NVMe mode, the SD host controller 24 turns on the second power supply voltage VDD2 while the first power supply voltage VDD1 is turned on, and asserts the card presence detection signal PRSNT# to the PCIe interface controller 231 in such a way that the operation mode of the memory card 3 is changed from the SD mode to the PCIe / NVMe mode. The card presence detection signal PRSNT# is a signal indicating that a memory card 3 supporting the PCIe / NVMe mode is connected to the host device 2, that is, a PCIe / NVMe device is connected to the PCIe interface controller 231. In addition, asserting a signal means setting the voltage level of the signal to a valid level. In addition, deasserting a signal means setting the voltage level of the signal to an invalid level.

[0043] Since the card presence detection signal PRSNT# is a low active signal, if the card presence detection signal PRSNT# is asserted to the PCIe interface controller 231, the voltage of the card presence detection signal PRSNT# is set to a low level. The PCIe interface controller 231 is configured to start communicating with the memory card 3 via the PCIe interface using the PCIe / NVMe driver based on the assertion of the card presence detection signal PRSNT#. In this way, the operation mode of the memory card 3 is changed to the PCIe mode.

[0044] During the period when the operation mode of the memory card 3 is the PCIe / NVMe mode, the SD host controller 24 monitors the reset signal PERST#, which is one of the sideband signals for the PCIe interface output from the PCIe interface controller 231 to the switch circuit 26. That is, the SD host controller 24 has an input terminal for inputting the reset signal PERST# output from the PCIe interface controller 231 to the switch circuit 26. The input terminal is connected to the reset signal PERST# line between the PCIe interface controller 231 and the switch circuit 26. The reset signal PERST# is a reset signal for the PCIe / NVMe mode. The reset signal PERST# is supplied from the PCIe interface controller 231 to the memory card 3 via the switch circuit 26. If the reset signal PERST# is asserted, the PCIe interface circuit (not shown) included in the memory card 3 is reset to the initial state (reset state). In addition, when the reset signal PERST# is deasserted by the PCIe interface controller 231, the reset state of the PCIe interface circuit included in the memory card 3 is released, whereby the PCIe interface circuit included in the memory card 3 starts to operate.

[0045] The system controller 23 is connected to the CPU 21, the system memory 22, and the SD host controller 24. The system controller 23 also includes the PCIe interface controller 231 and the interrupt controller 232 described above.

[0046] The PCIe interface controller 231 is a communication control circuit that communicates with the memory card 3 via a PCIe interface under the control of a PCIe / NVMe driver.

[0047] When the card presence detection signal PRSNT# is asserted by the SD host controller 24, the PCIe interface controller 231 starts communicating with the memory card 3 via the PCIe interface. In more detail, if the card presence detection signal PRSNT# is asserted, the PCIe / NVMe driver is started, and under the control of the PCIe / NVMe driver, the PCIe interface controller 231 starts the initialization process of the PCIe interface. If the initialization process of the PCIe interface is completed, under the control of the PCIe / NVMe driver, the PCIe interface controller 231 starts the read / write access to the memory card 3 via the PCIe interface.

[0048] The PCIe interface includes a signal group, namely, two sideband signals (reset signal PERST#, clock request signal CLKREQ#), differential reference clock signals REFCLK-P, REFCLK-N, differential transmission signals Tx-P, Tx-N, and differential reception signals Rx-P, Rx-N. The sign # after the signal name indicates that the signal is a low-active signal.

[0049] The reset signal PERST# is a reset signal for the PCIe / NVMe mode as described above. The clock request signal CLKREQ# is a signal for requesting the PCIe interface controller 231 to send a differential reference clock signal. The clock request signal CLKREQ# is supplied from the memory card 3 to the PCIe interface controller 231 via the switch circuit 26. The differential reference clock signals REFCLK-P and REFCLK-N do not require a clock oscillator in the memory card 3, and the structure of the clock circuit in the memory card 3 can be simplified.

[0050] Two sideband signal lines (a reset signal PERST# line and a clock request signal CLKREQ# line) and two reference clock signal lines REFCLK-P and REFCLK-N are connected to the DAT[3:0] terminal of the memory card 3 via a switch circuit 26 .

[0051] The differential transmission signals Tx-P and Tx-N are used to transmit commands, data, etc. from the PCIe interface controller 231 to the memory card 3. The differential reception signals Rx-P and Rx-N are used to transmit responses, data, etc. from the memory card 3 to the PCIe interface controller 231.

[0052] It is possible that, during the period when the operation mode of the memory card 3 is the PCIe / NVMe mode, the respective operations of the memory card 3 and the PCIe interface controller 231 are controlled by the PCIe / NVMe driver. In order to be able to control the PCIe interface controller 231 based on the latest PCIe / NVMe specifications, a standard PCIe / NVMe driver is preferentially used as the PCIe / NVMe driver. If a customized PCIe / NVMe driver is used, the PCIe / NVMe driver must be re-customized whenever the standard PCIe / NVMe driver is updated.

[0053] The standard PCIe / NVMe driver is a software driver independent of the host driver, so it does not have a special function for communicating with the host driver. In addition, during the period when the memory card 3 is in the PCIe / NVMe mode, the host driver is set to a dormant state to avoid consuming the resources of the CPU 21.

[0054] Therefore, in an environment using a standard PCIe / NVMe drive, if certain errors occur during the PCIe initialization process or during memory access operations in PCIe / NVMe mode, memory card 3 will freeze in PCIe / NVMe mode, making it impossible to use memory card 3.

[0055] In this case, in order to return the operation mode of the memory card 3 from the PCIe / NVMe mode to the SD mode, the user must temporarily remove the memory card 3 and insert the connector again, or restart the OS. In addition, information indicating that an error occurred in the PCIe / NVMe mode must be saved somewhere in advance, and the memory card 3 must be started in the SD mode.

[0056] In this embodiment, in order to cope with errors generated in the PCIe / NVMe mode even in an environment using a standard PCIe / NVMe driver, the SD host controller 24 detects that an error has occurred in the PCIe / NVMe mode. Then, based on the detection of an error in the PCIe / NVMe mode, the SD host controller 24 generates an interrupt signal for starting the host driver. If the host driver is started by the CPU 21 due to the interrupt signal, the host driver controls the SD host controller 24 to execute a process for changing the operation mode of the memory card 3 from the PCIe / NVMe mode to the SD mode.

[0057] Thereby, the operation mode of the memory card 3 can be automatically returned to the SD mode without adding a special function for communicating with the host driver to the PCIe / NVMe driver. Therefore, even if the user does not temporarily remove the memory card 3 and reinsert it, the memory card 3 can be operated in the D mode.

[0058] If some errors occur during the initialization process of the PCIe interface or during memory access in the PCIe / NVMe mode (for example, errors in the PCIe interface circuit in the memory card 3, etc.), the state of the reset signal PERST# is generally asserted for a long time. The SD host controller 24 detects that an error has occurred in the PCIe / NVMe mode by using the phenomenon that the state of the reset signal PERST# is asserted for a long time. In the initialization process of the PCIe interface or during memory access in the PCIe / NVMe mode, the PCIe / NVMe driver controls the PCIe interface controller 231 to assert the reset signal PERST# in order to retry a failed process. For the purpose of retrying, the period during which the reset signal PERST# is maintained in the asserted state is short. In the present embodiment, the SD host controller 24 is configured not to detect a shorter reset used for such a retry as an error.

[0059] More specifically, the SD host controller 24 also detects an error in the PCIe / NVMe mode when the period during which both the presence detection signal PRSNT# and the reset signal PERST# are asserted lasts for more than a first period. The error is also referred to as a PCIe Error below.

[0060] Errors (PCIe errors) generated in the PCIe / NVMe mode include recoverable errors and unrecoverable errors. A recoverable error means an error in which, even if an error related to a certain process occurs, the process succeeds through retries within a certain number of times. An unrecoverable error means an error in which the process continues to fail even after a certain number of retries. In the PCIe specification, unrecoverable errors are also referred to as fatal errors. Errors that should be detected by the SD host controller 24 are unrecoverable errors in the PCIe / NVMe mode. Recoverable errors are excluded from the detection targets of the SD host controller 24.

[0061] The switch circuit 26 selects any one of the four data signal DAT[3:0] lines and the four PCIe signal lines (reset signal PERST# line, clock request signal CLKREQ# line, differential reference clock signal REFCLK-P, REFCLK-N lines), and connects the selected signal line to the DAT[3:0] terminal of the memory card 3.

[0062] When the operation mode of the memory card 3 is the SD mode, that is, when the second power supply voltage control signal VDD2-ON is low, the switch circuit 26 selects four data signal DAT[3:0] lines, and respectively connects the four data signal DAT[3:0] lines to the DAT[3:0] terminals of the memory card 3. When the operation mode of the memory card 3 is the PCIe / NVMe mode, that is, when the second power supply voltage control signal VDD2-ON is high, the switch circuit 26 selects four PCIe signal lines (reset signal PERST# line, clock request signal CLKREQ# line, differential reference clock signal REFCLK-P, REFCLK-N lines), and connects the four PCIe signal lines to the DAT[3:0] terminals of the memory card 3.

[0063] Next, the interrupt signal generated by the SD host controller 24 will be described.

[0064] The reasons why the SD host controller 24 generates an interrupt signal include "card insertion", "card removal", and "PCIe error".

[0065] When “card insertion”, “card removal”, or “PCIe error” is detected, the SD host controller 24 generates an interrupt signal to the CPU 21 . The interrupt signal is supplied to the CPU 21 via the interrupt controller 232 .

[0066] The interrupt signal caused by the detection of "card insertion", "card removal", or "PCIe error" is used to drive the host driver. When the host driver is activated by the interrupt signal, the host driver performs interrupt processing corresponding to the cause of the interrupt signal ("card insertion", "card removal", or "PCIe error"). If the interrupt processing is completed, the host driver can be set to a sleep state to avoid using the CPU 21 before entering the next interrupt, which causes waste.

[0067] When the host driver is activated by an interrupt signal caused by a "PCIe error", the host driver executes a process for changing the operation mode of the memory card 3 from the PCIe / NVMe mode to the SD mode.

[0068] Thus, in this embodiment, when the SD host controller 24 detects the occurrence of a "PCIe error", the SD host controller 24 generates an interrupt signal, thereby restarting the host driver. Therefore, in an environment using a standard PCIe / NVMe driver, the operation mode of the memory card 3 can also be returned to the SD mode.

[0069] Figure 21 is a block diagram illustrating a connection relationship between the SD host controller 24 and the PCIe interface controller 231 included in the host device 2 according to the embodiment.

[0070] The SD host controller 24 detects that the voltage level of the card detection signal Card Detection sent from the connector of the host device 2 changes from, for example, a high level to a low level, and detects that the memory card 3 has been inserted into the connector. Based on the detection of the insertion of the memory card 3, the SD host controller 24 generates an interrupt signal ("card insertion" interrupt) for starting the host driver. The interrupt signal is input to the CPU 21 via the interrupt controller 232.

[0071] The host driver starts the inserted memory card 3 in SD mode and confirms whether the memory card 3 supports the PCIe / NVMe mode. If the PCIe / NVMe mode is supported, the host driver controls the SD host controller 24 and asserts the card presence detection signal PRSNT#. If the card presence detection signal PRSNT# is asserted, the PCIe driver controls the PCIe interface controller 231 and starts communicating with the memory card 3 via the PCIe interface.

[0072] In addition, the SD host controller 24 detects that the voltage level of the card detection signal Card Detection sent from the connector changes from, for example, a low level to a high level, and detects that the memory card 3 has been removed from the host device 2. Based on the detection of the removal of the memory card 3, the SD host controller 24 generates an interrupt signal ("card removal" interrupt) for starting the host driver. The host driver performs processing such as shutting down the card power supply (two power supply voltages VDD1, VDD2).

[0073] When an error occurs in the PCIe / NVMe mode, the PCIe interface controller 231 asserts the reset signal PERST# for the PCIe / NVMe mode. The SD host controller 24 monitors the reset signal PERST# for the PCIe / NVMe mode output from the PCIe interface controller 231. When the period during which the card presence detection signal PRSNT# and the reset signal PERST# are simultaneously asserted continues for more than a certain period, the SD host controller 24 determines that a PCIe error has occurred and generates an interrupt signal ("PCIe error" interrupt) for starting the host driver.

[0074] As described above, there are three reasons why the SD host controller 24 generates an interrupt signal: "card insertion", "card removal", and "PCIe error".

[0075] An interrupt status indicating the interrupt cause is stored in a status register (not shown) in the SD host controller 24. The host driver can specify whether the interrupt cause is "card insertion", "card removal" or "PCIe error" by reading the interrupt status from the status register in the SD host controller 24.

[0076] Next, the components of the SD host controller 24 will be described. The SD host controller 24 includes a reset timer (Res timer) 241 .

[0077] The reset timer (Res timer) 241 measures a period during which both the card presence detection signal PRSNT# and the reset signal PERST# are asserted.

[0078] When the PCIe driver performs a retry, it controls the PCIe interface controller 231 to temporarily assert the reset signal PERST# for the PCIe / NVMe mode. In this case, the period during which the reset signal PERST# is maintained in the asserted state (valid state = low level) is shorter (shorter reset). The period during which the reset signal PERST# is maintained in the asserted state for retry is, for example, up to 1 second. The reset timer (Res timer) 241 is used to exclude the shorter reset for retry from the detection object.

[0079] The reset timer (Res timer) 241 starts counting from an initial value (e.g., zero) when the reset signal PERST# for the PCIe / NVMe mode is asserted while the card presence detection signal PRSNT# to the PCIe interface controller 231 is asserted. When the reset signal PERST# is deasserted while the card presence detection signal PRSNT# is asserted, the counting operation performed by the reset timer (Res timer) 241 ends. When the deasserted reset signal PERST# is asserted again, the reset timer (Res timer) 241 starts counting from an initial value (e.g., zero) again.

[0080] The SD host controller 24 compares the count value of the reset timer (Res timer) 241 with the timeout value stored in the timeout value register 242 of the SD host controller 24. The SD host controller 24 detects the occurrence of a PCIe error (unrecoverable error) in the PCIe / NVMe mode, on the condition that the count value of the reset timer (Res timer) 241 is greater than the timeout value. Based on the detection of the occurrence of the PCIe error, the SD host controller 24 starts the host driver by generating an interrupt signal.

[0081] In the processing of the interruption caused by the occurrence of a PCIe error (PCIe error interruption processing), the host driver controls the SD host controller 24 to deassert the card presence detection signal PRSNT# and shut down the power supply voltage VDD2, thereby returning the operation mode of the memory card 3 to the SD mode. This prevents the memory card 3 from freezing in the PCIe / NVMe mode, and allows the memory card 3 to be used continuously. The host driver may also perform processing (warning) to notify the user of the occurrence of a PCIe error in the PCIe / NVMe mode via the OS.

[0082] The host driver can specify a timeout value for the SD host controller 24 by writing the timeout value into the timeout value register 242 in the SD host controller 24. Alternatively, the timeout value may be a predetermined fixed value.

[0083] In addition, the SD host controller 24 stores a flag (PCIeFerr: PCIe Fatel error) indicating that a PCIe error has occurred in the PCIe / NVMe mode. The flag (PCIeFerr) is stored in, for example, a flag register 243 in the SD host controller 24.

[0084] Flag (PCIeFerr) = 0 indicates that no PCIe error has occurred (default value). Flag (PCIeFerr) = 1 indicates that a PCIe error has been detected. When a "card insertion" event occurs, the flag (PCIeFerr) is cleared and set to the default value. In addition, although the flag (PCIeFerr) is saved while power is supplied to the host controller 24, if power is stopped to the host controller 24, the flag (PCIeFerr) is not saved. That is, the host controller 24 saves the flag (PCIeFerr) indicating that a PCIe error has been detected (= 1) while power is supplied to the host controller 24. The register group in the host controller 24 is volatile. Therefore, if power is stopped to the host controller 24, the content (= 1) of the flag (PCIeFerr) stored in the flag register 243 is lost. The flag (PCIeFerr) is set to the default value (= 0) indicating that no PCIe error has occurred when the host controller 24 is started next time. In addition, the flag (PCIeFerr) can be cleared and set to the default value not only when a "card insertion" event occurs, but also when a "card removal" event occurs.

[0085] When the OS is restarted by the user, the host driver reads the flag (PCIeFerr) from the flag register 243 of the SD host controller 24 .

[0086] When the memory card 3 inserted into the connector supports the PCIe / NVMe mode and the flag (PCIeFerr) is not set to "1", the host driver controls the SD host controller 24 in such a way that the operation mode of the memory card 3 is changed from the SD mode to the PCIe / NVMe mode.

[0087] On the other hand, when the flag (PCIeFerr) is set to "1", the host driver controls the SD host controller 24 in such a way that the memory card 3 operates in SD mode, regardless of whether the memory card 3 inserted into the connector supports the PCIe / NVMe mode. That is, even if the memory card 3 supports the PCIe / NVMe mode, the host driver uses the SD mode to control the memory card 3. This prevents the memory card 3 from being used again in the PCIe / NVMe mode, thereby preventing the PCIe error from occurring again. In addition, if the power supply to the host controller 24 is stopped, the content (=1) of the flag (PCIeFerr) stored in the flag register 243 is lost. Then, the flag (PCIeFerr) is set to a default value (=0) indicating that no PCIe error has occurred when the host controller 24 is started next time. Therefore, when the memory card 3 is replaced with a new memory card supporting the PCIe / NVMe mode while power supply to the host controller 24 is stopped, the host driver can control the SD host controller 24 by changing the operation mode of the new memory card from the SD mode to the PCIe / NVMe mode.

[0088] Figure 3 This is a diagram for explaining the timer count of the PCIe error detection executed in the host device 2 according to the embodiment.

[0089] exist Figure 3 In FIG. 1 , the horizontal axis represents time, the upper section represents the card presence detection signal PRSNT#, and the lower section represents the reset signal PERST#. The solid line represents the voltage level of each signal (card presence detection signal PRSNT#, reset signal PERST#) at a certain time.

[0090] The dashed line of the card presence detection signal PRSNT# indicates the voltage level (high level) when the card presence detection signal PRSNT# is in the deasserted state. Figure 3 In the example, it is assumed that the memory card 3 is in PCIe / NVMe mode. Therefore, the card presence detection signal PRSNT# is maintained in the asserted state (low level).

[0091] Similarly, the reset signal PERST# is asserted when the voltage is lower than the deasserted state. That is, the reset signal PERST# changes from the deasserted state to the asserted state at timings (a) and (c).

[0092] If the reset signal PERST# changes from the deasserted state to the asserted state at each of the timings (a) and (c), the Res timer 241 starts counting the elapsed time from an initial value (e.g., 0). Through the counting operation, the length of time for asserting the card presence detection signal PRSNT# and the reset signal PERST# is measured. When the count value of the elapsed time of the Res timer 241 reaches the timeout value of the timeout value register 242, a timeout event occurs.

[0093] Timing (b) indicates the point in time when the elapsed time from timing (a) reaches the timeout value. Figure 3 As shown, for example, when a shorter reset for retry is generated at timing (a), the reset signal PERST# is changed from the asserted state to the deasserted state before timing (b). In this case, no timeout event occurs. Therefore, the shorter reset for retry can be prevented from being detected as a PCIe error (unrecoverable error) in PCIe / NVMe mode.

[0094] Timing (d) indicates the point in time when the elapsed time from timing (c) reaches the timeout value. Figure 3 As shown in the figure, when a PCIe error (unrecoverable error) occurs in the PCIe / NVMe mode, the reset signal PERST# asserted at timing (c) remains in the asserted state during a period longer than the timeout value. Therefore, a timeout event occurs at timing (d). Under the condition that the timeout event occurs, the SD host controller 24 detects that a PCIe error (unrecoverable error) occurs in the PCIe / NVMe mode.

[0095] Next, the interruption cause identification process executed in the host device 2 will be described. Figure 4 This is a flowchart showing the procedure of the interruption cause identification process executed in the host device 2 according to the embodiment.

[0096] When an interrupt signal generated by the SD host controller 24 is input to the CPU 21 via the interrupt controller 232 , the host driver is activated by the CPU 21 .

[0097] The host driver first reads the interrupt status of the status register stored in the SD host controller 24 (step S11), and based on the read interrupt status, identifies whether the cause of the generated interrupt signal is "card insertion", "card removal", or "PCIe error" (step S12).

[0098] When the cause of the interrupt signal generated is "card insertion", the host driver performs card insertion interrupt processing (step S13). In the insertion interrupt processing of memory card 3, the host driver temporarily sets the operation mode of memory card 3 to SD mode, uses CMD8 to confirm whether memory card 3 supports PCIe / NVMe mode, and reads the flag (PCIeFerr) to confirm whether a PCIe error occurs. Based on the confirmation result, the host driver performs SD mode initialization processing or changes the operation mode of memory card 3 to PCIe / NVMe mode. The details of the card insertion interrupt processing are described in Figure 6 It will be described later in the text.

[0099] When the cause of the generated interrupt signal is "card removal", the host driver executes a card removal interrupt process. In the card removal interrupt process, for example, a process of deasserting the card presence detection signal PRSNT# or a process of shutting down VDD1 and VDD2 is executed.

[0100] When the cause of the generated interrupt signal is a "PCIe error", the host driver executes a PCIe error interrupt process. In the PCIe error interrupt process, a process of changing the operation mode of the memory card 3 from the PCIe / NVMe mode to the SD mode is executed.

[0101] Figure 5 This is a flowchart showing the procedure of PCIe error interrupt processing executed in the host device 2 according to the embodiment.

[0102] When the host driver is activated by the CPU 21 due to an interrupt signal caused by a "PCIe error", the host driver first controls the SD host controller 24 to change the card presence detection signal PRSNT# to a deasserted state (step S21). By changing the card presence detection signal PRSNT# from an asserted state to a deasserted state, the connection between the PCIe interface controller 231 and the memory card 3 is released.

[0103] Next, the host driver controls the SD host controller 24 to turn off the second power supply voltage VDD2 (step S22). Next, the host driver controls the SD host controller 24 to start supplying the SD clock (SD CLK) to the memory card 3 (step S23). After starting to supply the SD clock, the host driver starts the initialization process of the SD mode (step S24).

[0104] Through the above-described actions, if an error occurs when operating in PCIe / NVMe mode and a PCIe error determination has been performed, a transition from PCIe / NVMe mode to SD mode can be performed by sending an interrupt signal caused by the PCIe error from the SD host controller 24 to the system controller 231.

[0105] Figure 6 This is a flowchart showing the procedure of the operation mode switching process executed in the host device 2 according to the embodiment.

[0106] First, a card insertion interrupt process executed when an interrupt signal is generated due to “card insertion” and the host driver is activated by the CPU 21 will be described.

[0107] First, the host driver controls the SD host controller 24 to clear the flag (PCIeFerr) stored in the flag register 243, and reset the flag (PCIeFerr) to a default value (=0) indicating that no PCIe error has occurred (step S31). The flag (PCIeFerr) is reset to a default value (initial value) so as not to prohibit the use of the PCIe / NVMe mode when a new memory card is inserted into the connector.

[0108] Next, the host driver controls the SD host controller 24 to turn on the first power supply voltage VDD1 (step S32). Specifically, the SD host controller 24 supplies the first power supply voltage control signal VDD1-ON for turning on VDD1 to the power supply circuit 25. Then, the host driver controls the SD host controller 24 to supply the SD clock to the memory card 3 (step S33). Thereby, the memory card 3 starts to operate in the SD mode.

[0109] Then, the host driver controls the SD host controller 24 to send the SD command "CMD8" in which the bit "PCIe validity" for checking whether the memory card 3 supports the PCIe / NVMe mode is set to 1 to the memory card 3. The SD command "CMD8" is a command for inquiring the memory card 3 about the capability of the memory card 3. When receiving the SD command "CMD8", the memory card 3 returns a response "R7" including a bit "PCIe response" indicating whether the PCIe / NVMe mode is supported to the SD host controller 24.

[0110] PCIe response = 1 indicates that the memory card 3 supports the PCIe / NVMe mode. PCIe response = 0 indicates that the memory card 3 does not support the PCIe / NVMe mode.

[0111] When the reception of the response "R7" from the memory card 3 fails (error retry of step S35), the host driver reissues the SD command "CMD8" with the bit "PCIe validity" set to 1 to the memory card 3. The upper limit of the number of times the SD command "CMD8" can be retried is determined by the installation of the host driver.

[0112] The host driver reads the bit “PCIe Response” included in the response “R7” from the SD host controller 24 , and reads the flag (PCIeFerr) from the SD host controller 24 .

[0113] The host driver determines the operation mode to be used to control the memory card 3 based on the read bit "PCIe Response" and the read flag (PCIeFerr) (step S35).

[0114] When the bit memory card 3 does not support the PCIe / NVMe mode (PCIe response = 0) or the bit PCIeFerr = 1, the host driver executes the SD mode initialization process (step S36). Thus, the memory card 3 is maintained in the SD mode.

[0115] On the other hand, when the memory card 3 supports the PCIe / NVMe mode (PCIe response=1) and PCIeFerr=0, the host driver controls the SD host controller 24 to execute switching to the PCIe / NVMe mode (step S37).

[0116] In step S37, the host driver controls the SD host controller 24 to stop supplying the SD clock to the memory card 3. In addition, the host driver controls the SD host controller 24 to enable the generation of interrupt signals due to the "card insertion" event, the generation of interrupt signals due to the "card removal" event, and the generation of interrupt signals due to the "PCIe error" event. In addition, the host driver controls the SD host controller 24 to turn on VDD2, and then controls the SD host controller 24 to assert the card presence detection signal PRSNT#. By asserting the card presence detection signal PRSNT#, the PCIe interface controller 231 starts to operate. Thereby, the operation mode of the memory card 3 is changed to the PCIe / NVMe mode. Then, the host driver changes to the sleep state (step S38).

[0117] When the host driver is started by the CPU 21 due to the restart of the OS, the host driver first determines whether the memory card 3 is inserted into the connector by checking the value of a specific register in the SD host controller 24 indicating whether the memory card 3 is inserted into the connector (step S41). When the power is continuously supplied to the host controller 24 during the restart of the OS, the value of each register in the host controller 24 is saved. When the power supply to the host controller 24 is stopped during the restart of the OS, the value of each register is set to an initial value. When the memory card 3 is inserted into the connector, the value of the specific register indicating whether the memory card 3 is inserted into the connector is temporarily set to a value indicating that the memory card 3 is not inserted into the connector when the power supply to the host controller 24 is stopped during the restart of the OS, but is set again to a value indicating that the memory card 3 is inserted into the connector when the power supply to the host controller 24 is stopped during the restart of the OS. Since the flag (PCIeFerr) is stored in the flag register 243 in the host controller 24, when the power is continuously supplied to the host controller 24 during the restart of the OS, the host controller 24 continuously stores the flag (PCIeFerr) indicating that a PCIe error has been detected (=1). On the other hand, if the power supply to the host controller 24 is stopped during the restart of the OS, the flag (PCIeFerr) is set to a default value (initial value = 0) indicating that no PCIe error has occurred. In this way, the flag (PCIeFerr) is set to the initial value (=0) because the memory card 3 may be replaced with another memory card during the period when the power supply to the host controller 24 is stopped.

[0118] In addition, in order to effectively use the content (=1) of the flag (PCIeFerr) when restarting the OS, the host device 2 can be configured to continuously supply power to at least the host controller 24 during the restart of the OS. In this case, the content (=1) of the flag (PCIeFerr) is not lost. In addition, the card detection function of the host controller 24 effectively functions while power is supplied to the host controller 24. Therefore, when the memory card 3 is replaced with a new memory card during the restart of the OS, the host controller 24 can detect the insertion of the new memory card, and then the flag (PCIeFerr) can be set to a default value (initial value = 0) indicating that no PCIe error has occurred.

[0119] After the PCIe error of the memory card 3 is detected, the OS is restarted without replacing the memory card 3 and power is supplied to the host controller 24 during the restart of the OS. The operation mode of the memory card 3 is changed from the SD mode to the PCIe / NVMe mode again, and the PCIe error is detected again. However, since the host driver can identify the PCIe error, the operation mode of the memory card 3 can be returned to the SD mode. Furthermore, the host driver can also notify the user of the error in the PCIe / NVMe mode.

[0120] return Figure 6 When the host driver determines that the memory card 3 is inserted into the connector (Yes in step S41), the process proceeds to step S32.

[0121] The host driver controls the SD host controller 24 to turn on the first power supply voltage VDD1 (step S32). Specifically, the SD host controller 24 supplies the first power supply voltage control signal VDD1-ON for turning on VDD1 to the power supply circuit 25. Then, the host driver controls the SD host controller 24 to supply the SD clock to the memory card 3 (step S33). Thereby, the memory card 3 starts to operate in the SD mode.

[0122] Then, the host driver controls the SD host controller 24 to send the SD command "CMD8" with the bit "PCIe validity" set to 1 to the memory card 3. When receiving the SD command "CMD8", the memory card 3 returns a response "R7" including the bit "PCIe response" indicating whether the PCIe / NVMe mode is supported to the SD host controller 24.

[0123] The host driver reads the bit “PCIe Response” included in the response “R7” from the SD host controller 24 , and reads the flag (PCIeFerr) from the SD host controller 24 .

[0124] The host driver determines the operation mode to be used to control the memory card 3 based on the read bit "PCIe Response" and the read flag (PCIeFerr) (step S35).

[0125] When the memory card 3 does not support the PCIe / NVMe mode (PCIe Response = 0) or PCIeFerr = 1, the host driver executes the SD mode initialization process (step S36). Thus, the memory card 3 is maintained in the SD mode.

[0126] That is, when PCIeFerr=1, regardless of whether the memory card 3 supports the PCIe / NVMe mode, the host driver controls the SD host controller 24 in such a way that the memory card 3 operates in the SD mode. That is, even if the memory card 3 supports the PCIe / NVMe mode, the host driver uses the SD mode to control the memory card 3. As a result, the PCIe error can be prevented from occurring again.

[0127] On the other hand, if the memory card 3 supports the PCIe / NVMe mode (PCIe response = 1) and PCIeFerr = 0, the host driver controls the SD host controller 24 to switch to the PCIe / NVMe mode (step S37). Then, the host driver changes to the sleep state (step S38).

[0128] On the other hand, when the memory card 3 is not inserted into the connector (No in step S41), the host driver immediately changes to the sleep state (step S38).

[0129] In addition, when CMD0 is issued by the host driver (step S51), the processing from step S34 is also executed.

[0130] As described above, according to the present embodiment, in the memory system 1 including the memory card 3 and the host device 2 that can operate in the PCIe / NVMe mode and the SD mode, the SD host controller 24, when the memory card 3 supports the PCIe / NVMe mode, changes the operation mode of the memory card 3 from the SD mode to the PCIe / NVMe mode, turns on VDD2 while VDD1 is turned on, and asserts the card presence detection signal PRSNT#. During the period when the memory card 3 is in the PCIe / NVMe mode, the SD host controller 24 monitors the reset signal PERST#. When the period in which both the card presence detection signal PRSNT# and the reset signal PERST# are asserted continues for more than the first period, the SD host controller 24 detects that an error (unrecoverable error) has occurred in the PCIe / NVMe mode, and generates an interrupt signal for starting the host driver. The host driver is started by the interrupt signal. Therefore, in an environment using a standard PCIe / NVMe driver, the operation mode of the memory card 3 can also be returned to the SD mode.

[0131] In addition, although in the present embodiment, it is envisioned that the memory card 3 is implemented as an SD Express card, the configuration of the host device 2 of the present embodiment can be applied to various memory cards that support the following modes, namely: a first action mode for communicating with the host device 2 via a first interface, and a second action mode for communicating with the host device 2 via a second interface different from the first interface.

[0132] Although the embodiments of the present invention have been described, the embodiments are presented as examples and are not intended to limit the scope of the invention. The novel embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the invention. The embodiments or their variations are included in the scope or purpose of the invention, and are included in the inventions recorded in the claims and their equivalents.

[0133] Explanation of symbols

[0134] 1…memory system, 2…host device, 3…memory card, 21…CPU, 22…system memory, 23…system controller, 24…SD host controller, 25…power supply circuit, 26…switch circuit, 231…PCIe interface controller, 232…interrupt controller, 241…Res timer, 242…timeout value register, 243…flag register.

Claims

1. A host device capable of controlling a memory card supporting the following modes: a first operation mode of communicating with the host device via a first interface and a second operation mode of communicating with the host device via a second interface different from the first interface, and comprising: a host controller that controls the memory card via the first interface under the control of a first driver that is a program executed by a processor in the host device; a power supply circuit capable of supplying to the memory card a first power supply voltage required for both the first operation mode and the second operation mode, and a second power supply voltage required only for the second operation mode and lower than the first power supply voltage; as well as a communication control circuit, under the control of a program executed by the processor, i.e., a second driver, starting communication with the memory card via the second interface in response to assertion of a card presence detection signal; and The host controller is composed of: When the memory card supports the second operation mode, the operation mode of the memory card is changed from the first operation mode to the second operation mode, the second power supply voltage is turned on while the first power supply voltage is turned on, and the card presence detection signal is asserted to the communication control circuit. monitoring a reset signal for the second operation mode outputted from the communication control circuit while the operation mode of the memory card is the second operation mode, When the period during which both the card presence detection signal and the reset signal for the second operation mode are asserted continues for more than the first period, it is detected that an error occurs in the second operation mode, generating a first interrupt signal for starting the first driver according to the detection of the error; The first driver is configured to change the operation mode of the memory card from the second operation mode to the first operation mode by controlling the host controller when activated by the processor in response to the first interrupt signal.

2. A host device according to claim 1, wherein the host controller includes a timer for measuring the period during which both the card presence detection signal and the reset signal are asserted, and is configured to detect the occurrence of the error in the second action mode when the period measured by the timer reaches the first period.

3. The host device according to claim 1, wherein the first driver is configured as follows: According to the first interrupt signal, by controlling the host controller to deassert the card presence detection signal, By controlling the host controller, the second power supply voltage is turned off, The initialization process of the first operation mode is executed by controlling the host controller.

4. The host device according to claim 1, wherein the host controller maintains a flag set to a first value while the host controller is powered, the first value indicating that the error has occurred in the second operation mode, and when the power supply to the host controller is stopped, the flag is set to an initial value indicating that there is no error; and The first driver is configured as follows: In case of restarting the operating system of the host device, reading the flag from the host controller, When the memory card supports the second operation mode and the flag is not set to the first value, controlling the host controller so that the operation mode of the memory card is changed from the first operation mode to the second operation mode, When the flag is set to the first value, the host controller is controlled so that the memory card operates in the first operation mode regardless of whether the memory card supports the second operation mode.

5. The host device according to claim 4, wherein the host controller generates a second interrupt signal for activating the first driver according to a card detection signal indicating that a memory card has been inserted into a connector of the host device; and The first driver is configured as follows: If the processor is activated by the second interrupt signal, the flag is reset to an initial value indicating no error.

6. A memory system comprising a host device and a memory card; and The memory card is configured to operate in the following modes: a first operation mode for communicating with the host device via a first interface, and a second operation mode for communicating with the host device via a second interface different from the first interface; The host device comprises: a host controller that controls the memory card via the first interface under the control of a first driver that is a program executed by a processor in the host device; a power supply circuit capable of supplying to the memory card a first power supply voltage required for both the first operation mode and the second operation mode, and a second power supply voltage required only for the second operation mode and lower than the first power supply voltage; as well as a communication control circuit, under the control of a program executed by the processor, i.e., a second driver, starting communication with the memory card via the second interface in response to assertion of a card presence detection signal; and The host controller is composed of: When the memory card supports the second operation mode, the operation mode of the memory card is changed from the first operation mode to the second operation mode, the second power supply voltage is turned on while the first power supply voltage is turned on, and the card presence detection signal is asserted to the communication control circuit. monitoring a reset signal for the second operation mode outputted from the communication control circuit while the memory card is in the second operation mode, When the period during which both the card presence detection signal and the reset signal for the second operation mode are asserted continues for more than the first period, it is detected that an error occurs in the second operation mode, generating a first interrupt signal for starting the first driver according to the detection of the error; The first driver is configured to change the operation mode of the memory card from the second operation mode to the first operation mode by controlling the host controller when activated by the processor in response to the first interrupt signal.

7. A memory system according to claim 6, wherein the host controller includes a timer for measuring the period during which both the card presence detection signal and the reset signal are asserted, and is configured to detect that the error has occurred in the second action mode when the period measured by the timer reaches the first period.

8. The memory system according to claim 6, wherein the first driver is configured as follows: According to the first interrupt signal, by controlling the host controller to deassert the card presence detection signal, By controlling the host controller, the second power supply voltage is turned off, The initialization process of the first operation mode is executed by controlling the host controller.

9. The memory system according to claim 7, wherein the host controller maintains a flag set to a first value while the host controller is powered, the first value indicating that the error has occurred in the second operation mode, and when the power supply to the host controller is stopped, the flag is set to an initial value indicating that there is no error; and The first driver is configured as follows: In case of restarting the operating system of the host device, reading the flag from the host controller, When the memory card supports the second operation mode and the flag is not set to the first value, controlling the host controller so that the operation mode of the memory card is changed from the first operation mode to the second operation mode, When the flag is set to the first value, the host controller is controlled so that the memory card operates in the first operation mode regardless of whether the memory card supports the second operation mode.

10. The memory system according to claim 9, wherein the host controller generates a second interrupt signal for activating the first driver according to a card detection signal indicating that a memory card has been inserted into a connector of the host device; and The first driver is configured as follows: If the processor is activated by the second interrupt signal, the flag is reset to an initial value indicating no error.

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