Display device and driving method thereof

Abstract

A display device according to an embodiment of the present application includes a display panel including a plurality of pixels, a timing controller configured to receive a compensation instruction signal in a vertical blank period in which no image data is written into the pixels, and a sensing circuit configured to sense a driving characteristic of the pixels in at least one sensing period corresponding to the compensation instruction signal, wherein a length of the vertical blank period is different from each other in a first frame and a second frame, and a number of each sensing period having a predetermined length is changed according to the length of the vertical blank period.

Description

Technical Field

[0001] This disclosure relates to an electroluminescent display device. Background Technology

[0002] Based on the material of the light-emitting layer, electroluminescent display devices are divided into inorganic light-emitting display devices or organic light-emitting display devices. Each pixel of an electroluminescent display device includes a self-emissive light-emitting element, and the amount of light emitted from the light-emitting element is controlled by a data voltage based on the grayscale of the image data to adjust the brightness of the light-emitting element.

[0003] Electroluminescent display devices employ external compensation technology to improve image quality. External compensation technology is a technique that senses pixel voltage or current based on the electrical characteristics of pixels and modulates input image data based on the sensing results to compensate for electrical characteristic deviations between pixels.

[0004] However, in conventional external compensation techniques, when the frame rate changes abruptly, the pixel compensation period changes, leading to image speckles or afterimages due to compensation delay. Furthermore, sudden fluctuations in brightness at the compensation update point can be observed as flicker. Summary of the Invention

[0005] Technical issues

[0006] The purpose of this disclosure is to provide a display device and a driving method thereof, the display device being configured such that when an external compensation scheme is used to compensate for variations in electrical characteristics between pixels, compensation period delay and image defects are minimized even if the frame rate changes according to the input image.

[0007] Technical solution

[0008] A display device according to an embodiment of this application includes: a display panel comprising a plurality of pixels; a timing controller configured to receive a compensation instruction signal during a vertical blank period in which no image data is written to the pixels; and a sensing circuit configured to sense driving characteristics of the pixels during at least one sensing period corresponding to the compensation instruction signal, wherein the length of the vertical blank period is different from that of a first frame and a second frame, and the number of each sensing period having a predetermined length varies according to the length of the vertical blank period.

[0009] Beneficial effects

[0010] In this embodiment, when using an external compensation scheme to compensate for changes in electrical characteristics between pixels, even if the frame frequency changes according to the input image, the number of sensing times increases proportionally to the length of the vertical blank period (i.e., multiple sensing), thereby minimizing compensation cycle delay and image defects.

[0011] In this embodiment, when there are multiple compensation command signals in a vertical blank period for multiple sensing, the time interval between the last compensation command signal and the start time of the subsequent effective period is fixed as a sensing period according to the change of frame frequency, regardless of the length of the vertical blank period. This makes it easy to apply SLC technology and minimize cognitive errors caused by sensing.

[0012] The effects of this implementation are not limited to those described above, and include many other different effects in this application. Attached Figure Description

[0013] Figure 1 This is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure;

[0014] Figure 2 It is shown Figure 1 An illustration of a pixel array included in an electroluminescent display device;

[0015] Figure 3 yes Figure 2 The equivalent circuit diagram of a pixel included in the pixel array;

[0016] Figure 4 This is a diagram illustrating the structure used to change the frame rate in a host system;

[0017] Figure 5 and Figure 6 It is a diagram illustrating memory control operations related to data rendering on the host system;

[0018] Figure 7 This is a diagram illustrating the transmission and reception of signals based on a variable frame frequency between the host system and the timing controller;

[0019] Figure 8 and Figure 9 This is a diagram illustrating VRR technology, which uses an input image to change the frame rate.

[0020] Figure 10 This is a diagram illustrating an example in which at least one sensing period is set in a vertical blank period to correspond to a compensation command signal;

[0021] Figure 11 It is shown in Figure 10 A diagram illustrating the sensing operations performed during a sensing period;

[0022] Figure 12 This is a diagram illustrating how the number of compensation command signals changes according to the length of the vertical blank period in a variable frame rate environment.

[0023] Figure 13 This is a diagram illustrating an example in which the compensation command signal takes the form of an integrated control signal integrated with other signals;

[0024] Figure 14 This is a diagram illustrating a brightness recovery technique used to compensate for brightness loss caused by sensing.

[0025] Figure 15a and Figure 15b This is a diagram illustrating an example of a brightness compensation gain setting based on brightness recovery time;

[0026] Figure 16 and Figure 17 This is a diagram illustrating the signal delay operation of a host system used to equalize the time interval between the last compensation command signal in a vertical blank period and the start time of the vertical active period of the subsequent frame; and

[0027] Figure 18 This is a flowchart illustrating the control sequence related to the signal delay operation of the host system. Detailed Implementation

[0028] The advantages and features of this disclosure, as well as the methods for implementing these advantages and features, will become clearer from the embodiments described below with reference to the accompanying drawings. However, this disclosure is not limited to the following embodiments and can be implemented in various different forms. The embodiments are provided merely to complete the disclosure and to fully inform those skilled in the art of its scope. This disclosure is limited only by the scope of the claims.

[0029] In the accompanying drawings illustrating exemplary embodiments of this disclosure, for example, the shapes, dimensions, ratios, angles, and quantities shown are given by way of example and therefore do not limit the scope of this disclosure. Throughout the application, the same reference numerals denote the same constituent elements. Unless used with the term "only," the terms "comprising," "including," and / or "having" as used in this application do not exclude the presence or addition of other elements. Unless the context clearly indicates otherwise, the singular forms are intended to include the plural forms as well.

[0030] In interpreting the constituent elements included in the various embodiments of this disclosure, even if not explicitly described, the constituent elements are to be interpreted as including a range of error.

[0031] When describing positional relationships, for example, when using terms such as "above," "over," "below," "side," etc. to describe the positional relationship between two components, one or more other components may be placed between the two components unless the terms "directly" or "closely" are used with them.

[0032] In the description of various embodiments of this disclosure, although terms such as "first" and "second" may be used to describe various elements, these terms are only used to distinguish the same or similar elements from one another. Therefore, in this application, unless otherwise stated, within the technical scope of this disclosure, an element modified by "first" may be the same as an element modified by "second".

[0033] Throughout the application, the same reference numerals denote the same constituent elements.

[0034] In this disclosure, the pixel circuitry and gate driver on the substrate of the display panel can be implemented using a thin-film transistor (TFT) having an n-type metal-oxide-semiconductor field-effect transistor (MOSFET). However, this disclosure is not limited thereto. The pixel circuitry and gate driver can also be implemented using a TFT having a p-type MOSFET. A TFT is a three-electrode device comprising a gate, a source, and a drain. The source is the electrode that provides carriers to the transistor. In a TFT, carriers begin to flow out from the source. The drain is the electrode from which carriers are released to the outside of the TFT. That is, in a MOSFET, carriers flow from the source to the drain. For an n-type TFT (NMOS), the carriers are electrons, therefore the source voltage is lower than the drain voltage, allowing electrons to flow from the source to the drain. In an n-type TFT, because electrons flow from the source to the drain, current flows from the drain to the source. Conversely, for a p-type TFT (PMOS), the charge carriers are holes, so the source voltage is higher than the drain voltage, allowing holes to flow from the source to the drain. In a p-type TFT, since holes flow from the source to the drain, current flows from the source to the drain. It should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET can change depending on the applied voltage. Therefore, in the description of embodiments of this disclosure, one of the source and drain will be referred to as the first electrode, and the other will be referred to as the second electrode.

[0035] In the following description, detailed descriptions of known functions and configurations incorporated herein will be omitted where such omissions would obscure the subject matter of this disclosure. Hereinafter, embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 This is a diagram illustrating an electroluminescent display device according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1An illustration of the pixel array included in an electroluminescent display device. Figure 3 yes Figure 2 The equivalent circuit diagram of a pixel included in the pixel array. Figure 4 This is a diagram illustrating the structure used to change the frame rate in a host system. Figure 5 and Figure 6 It is a diagram illustrating the memory control operations related to data rendering on the host system.

[0037] Reference Figures 1 to 3 The display device according to embodiments of this disclosure may include: a display panel 10, a timing controller 11, panel driving circuits 121 and 13, and a sensing circuit 122. Panel driving circuits 121 and 13 include: a digital-to-analog converter (hereinafter referred to as DAC) 121 connected to a data line 15 of the display panel 10, and a gate driver 13 connected to a gate line 17 of the display panel 10. Panel driving circuits 121 and 13, and sensing circuit 122 may be mounted in a data integrated circuit 12.

[0038] The display panel 10 may be provided with multiple data lines 15, readout lines 16, and multiple gate lines 17. Pixels PXL may be located in the intersection area of ​​the data lines 15, readout lines 16, and multiple gate lines 17. For example... Figure 2 As shown, a pixel array can be formed in the display area AA of the display panel 10 by setting the pixels PXL into a matrix.

[0039] In a pixel array, pixels PXL can be divided into pixel groups in one direction. Each of the pixel groups Line 1 to Line 4 includes multiple pixels PXL adjacent to each other in the extension direction (or horizontal direction) of gate line 17. A pixel group is not a physical signal line, but refers to a group of pixels PXL arranged adjacent to each other in a horizontal direction. Therefore, pixels PXL constituting the same pixel group can be connected to the same gate line 17. Pixels PX constituting the same pixel group can be connected to different data lines 15; however, this disclosure is not limited thereto. Pixels PX constituting the same pixel group can be connected to different readout lines 16; however, this disclosure is not limited thereto. Multiple pixels PXL implementing different colors can share a single readout line 16.

[0040] In the pixel array, each pixel PXL can be connected to the DAC 121 via data line 15 and to the sensing circuit 122 via readout line 16. The sensing circuit 122 may be mounted together with the DAC 121 in the data integrated circuit 12; however, this disclosure is not limited thereto. The sensing circuit 122 may be mounted on a control printed circuit board (not shown) external to the data integrated circuit 12.

[0041] In the pixel array, each pixel PXL can be connected to the high-potential pixel power supply EVDD via the high-potential power supply line 18. In addition, each pixel PXL can be connected to the gate driver 13 via a corresponding one of the gate lines 17(1) to 17(4).

[0042] In the pixel array, pixel PXL may include pixels configured to implement a first color, pixels configured to implement a second color, and pixels configured to implement a third color, and may also include pixels configured to implement a fourth color. Each of the first to fourth colors can be any one of red, green, blue, and white.

[0043] Each pixel can be like Figure 3 The implementation shown is as illustrated; however, this disclosure is not limited thereto. A pixel PXL disposed in the kth (k is an integer) pixel group row may include a light-emitting element EL, a driving thin-film transistor (TFT) DT, a storage capacitor Cst, a first switch TFT ST1, and a second switch TFT ST2. The first switch TFT ST1 and the second switch TFT ST2 may be connected to the same gate line 17(k).

[0044] The light-emitting element (EL) emits light according to the pixel current. The EL includes an anode connected to the source node Ns, a cathode connected to the low-potential pixel power supply EVSS, and an organic or inorganic compound layer located between the anode and cathode. The organic or inorganic compound layer includes a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The EL turns on when the voltage applied to the anode becomes equal to or higher than the operating point voltage compared to the low-potential pixel power supply EVSS applied to the cathode. When the EL turns on, holes passing through the hole transport layer (HTL) and electrons passing through the electron transport layer (ETL) move to the emission layer (EML) to form excitons. As a result, the emission layer (EML) produces light.

[0045] The driving TFT DT is a driving element. Based on the voltage difference between the gate node Ng and the source node Ns, the driving TFT DT generates a pixel current flowing in the light-emitting element EL. The driving TFT DT includes a gate electrode connected to the gate node Ng, a first electrode connected to the high-potential pixel power supply EVDD, and a second electrode connected to the source node Ns. A storage capacitor Cst is connected between the gate node Ng and the source node Ns to store the voltage between the gate and source of the driving TFT DT.

[0046] The first switch TFT ST1 conducts current flow between data line 15 and gate node Ng according to the scan signal SCAN(k), so as to apply the data voltage charged in data line 15 to gate node Ng. The first switch TFT ST1 includes a gate electrode connected to gate line 17(k), a first electrode connected to data line 15, and a second electrode connected to gate node Ng. The second switch TFT ST2 conducts current flow between readout line 16 and source node Ns according to the scan signal SCAN(k), so as to transfer the voltage of source node Ns according to pixel current to readout line 16. The second switch TFT ST2 includes a gate electrode connected to gate line 17(k), a first electrode connected to source node Ns, and a second electrode connected to readout line 16.

[0047] The pixel structures described above are merely illustrative. It should be noted that the technical concept of this invention is not limited to pixel structures and can be applied to various pixel structures capable of sensing the electrical characteristics (threshold voltage or electron mobility) of the driving TFT DT.

[0048] The host system 14 is connected to the timing controller 11 via various interface circuits and sends the various signals DATA, DE, and CCMD required by the drive panel to the timing controller 11. For example... Figure 4 As shown, the host system 14 includes a graphics processing unit (GPU) and memory (DDR), and can process input image sources to suit a predetermined application, and can send the processed image sources to the timing controller 11. Since the image sources are input in a streaming form, they need to be temporarily stored in the memory (DDR) for data processing. Typically, the image sources are processed in units of one frame to reduce the cost and complexity incurred during data processing.

[0049] The Graphics Processing Unit (GPU) performs data rendering operations by processing image data frame by frame and storing the processed frame data in DDR memory using draw commands. DDR memory can be divided into two regions, A and B, allowing data rendering and transmission operations to be performed simultaneously in different regions, such as... Figure 5 and Figure 6 As shown in the diagram, while rendering the Nth frame of image data is being performed in region A, the (N-1)th frame of image data can be sent in region B in synchronization with the data enable signal DE. Then, when the rendering of the Nth frame of image data is complete, the graphics processing unit (GPU) sends the Nth frame of image data from region A to the timing controller 11 in synchronization with the data enable signal DE. At this time, the GPU performs image processing on the (N+1)th frame of image data and performs rendering operations on the (N+1)th frame of image data for region B.

[0050] The complexity of the input image can change in real time. The rendering process for complex images takes longer than for simple images. Therefore, the time spent sending data in the first region of the memory DDR and the time spent rendering data in the second region may not be consistent. For example, if the image data in frame (N+1) is more complex than that in frame N, even if the sending of frame N is completed in region A, the graphics processing unit (GPU) can still perform the rendering operation of frame (N+1) in region B. In this case, the GPU can extend the vertical blank period while reducing the frame rate until the rendering operation of frame (N+1) is completed. This prevents the sending of frame (N+1) from being in a state where it is not fully rendered. During the vertical blank period, image data is not sent because the data enable signal DE is only sent in a logic low state without transitioning. In this disclosure, the vertical active period can be defined as the period in each frame during which image data is written to the display panel 10 in a state matching the transition of the data enable signal DE. The vertical blank period can be defined as the period in which the data enable signal DE remains in a logic low state without transition between two adjacent vertical active periods and no image data is written to the display panel 10.

[0051] As described above, the graphics processing unit (GPU) can ensure data rendering time by varying the length of the vertical blank period according to the complexity of the image. When the length of the vertical blank period in a frame changes, the frame rate is variable; this is known as Variable Refresh Rate (VRR) technology. VRR technology changes the frame rate according to the input image to suppress image tearing and provide a smoother screen. The vertical blank period is shortest at the highest frame rate within a predetermined variable frame rate range and increases as the frame rate decreases. Furthermore, in a variable frame rate environment, the length of the vertical blank period changes according to the frame rate, but the length of the vertical active period remains fixed and independent. During the vertical active period, image data DATA is written to the pixel array of the display panel 10. Therefore, when the length of the vertical active period is fixed in a variable frame rate environment, the operation of the control panel drive circuits 121 and 13 can be more easily controlled.

[0052] When data rendering is completed in the first or second region, the graphics processing unit (GPU) generates at least one compensation instruction signal (CCMD) during a vertical blank period before sending the rendered image data, and sends the generated compensation instruction signal to the timing controller 11. In a variable frame rate environment where the length of the vertical blank period changes according to the frame rate, the GPU can adjust the number of compensation instruction signals (CCMD) proportionally to the length of the vertical blank period. When multiple compensation instruction signals (CCMD) are generated within a single vertical blank period, the time interval between adjacent compensation instruction signals (CCMD) can correspond to a sensing period. Preferably, the time interval between compensation instruction signals (CCMD), i.e., a sensing period, is designed to have a predetermined length to improve the reliability and accuracy of sensing.

[0053] Within the same vertical blank period, the number of sensing periods can be designed to correspond to the number of compensation command signals (CCMDs). Since the number of CCMDs is designed to be proportional to the length of the vertical blank period, the number of sensing periods can be increased proportionally to the length of the vertical blank period. For example, assuming the frequency of the second frame is lower than the frequency of the first frame, the length of the second vertical blank period belonging to the second frame is longer than the length of the first vertical blank period belonging to the first frame. In this case, the number of sensing periods located in the second vertical blank period is greater than the number of sensing periods located in the first vertical blank period. During one sensing period, a predetermined number of pixels are sensed and compensated. By increasing the number of sensing periods proportionally to the length of the vertical blank period, problems caused by compensation period delays in variable frame frequency environments (e.g., image speckles or afterimages, flicker, etc.) can be resolved.

[0054] After sending the compensation instruction signal CCMMD corresponding to the sensing period to the timing controller 11, the graphics processing unit (GPU) sends the data enable signal DE for the subsequent frame and the image data synchronized therewith to the timing controller 11.

[0055] Furthermore, to prevent the time interval between the compensation instruction signal (CCMD) located in a vertical blank period and the vertical active period of subsequent frames from changing according to the frame rate, the graphics processing unit (GPU) can delay the start time of the vertical active period of subsequent frames as needed, thereby uniformly fixing the time interval (i.e., fixing the time interval to a sensing period) regardless of the length of the vertical blank period. In this case, the reliability and accuracy of sensing and compensation are further improved.

[0056] The host system 14 may be implemented by an application processor, a personal computer, or a set-top box; however, this disclosure is not limited thereto. The host system 14 may be mounted on a system board; however, this disclosure is not limited thereto. The host system 14 may also include an input unit configured to receive user commands / data and a main power supply configured to generate primary power.

[0057] The timing controller 11 receives from the host system 14 a data enable signal DE synchronized with the variable frame frequency, input image data IDATA, and compensation command signal CCMD.

[0058] The timing controller 11 can control the operation timing of the control circuits 121 and 13 and the sensing circuit 122 based on the data enable signal DE and the compensation instruction signal CCMD, so that the display driver, the sensing driver and the brightness recovery driver are separated from each other in time.

[0059] The display driver is a driver in which a first data voltage (hereinafter referred to as the display data voltage) is written into a pixel group row during a vertical active period in a frame to reproduce an input image on the display panel 10. The sensing driver is a driver in which a second data voltage (hereinafter referred to as the sensing data voltage) is written into pixels PXL disposed in a specific pixel group row (hereinafter referred to as the sensing pixel group row) during a vertical blank period in a frame to sense and compensate for the electrical characteristics of the corresponding pixel PXL. The brightness recovery driver is a driver in which a third data voltage (hereinafter referred to as the brightness recovery data voltage) having a brightness compensation gain applied is written into pixels PXL in the sensing pixel group row where the sensing operation has been completed to compensate for brightness loss caused by the sensing operation. Since the third data voltage is a voltage obtained by applying a brightness compensation gain to the first data voltage, the third data voltage may be different from the first data voltage. The brightness recovery driver is executed until the data voltage for displaying subsequent frames is written into the pixels PXL disposed in the sensing pixel group row.

[0060] The timing controller 11 can generate a first data / gate control signal DDC / GDC for the operation timing of the control panel drive circuits 121 and 13 based on timing signals such as the data enable signal DE during display driving. The timing controller 11 can also generate a second data / gate control signal DDC / GDC for the operation timing of the control panel drive circuits 121 and 13 based on timing signals such as the data enable signal DE during sensing driving. Furthermore, the timing controller 11 can generate a third data / gate control signal DDC / GDC for the operation timing of the control panel drive circuits 121 and 13 based on timing signals such as the data enable signal DE during brightness recovery driving.

[0061] The timing controller 11 can independently control the display driving timing, sensing driving timing, and brightness recovery driving timing of the pixel group rows of the display panel 10 based on the data / gate control signals DDC / GDC, so that the electrical characteristics of the pixel PXL can be sensed and compensated in real time on a pixel group row basis during image display.

[0062] The timing controller 11 can control the operation of the control circuits 121 and 13 to enable display driving during the vertically active period in a frame, and can also control the operation of the control circuits 121 and 13 and the sensing circuit 122 to enable sensing driving during the vertically blank period before the vertically active period in a frame. Furthermore, the timing controller 11 can control the operation of the control circuits 121 and 13 to enable brightness recovery driving between the time point when sensing driving is completed and the time point when display driving begins.

[0063] The vertical active period corresponds to the transition period of the data enable signal DE, during which the data voltage for display is written to pixels PXL in all pixel group rows. The vertical blank period corresponds to the non-transition period of the data enable signal DE, during which the writing of the data voltage for display is interrupted. The vertical blank period includes the sensing period and may partially include the brightness recovery period. During the sensing period, the data voltage for sensing can be written to pixels PXL located in the sensing pixel group row, and during the brightness recovery period following the sensing period, the data voltage for brightness recovery can be written to pixels PXL located in the sensing pixel group row.

[0064] The gate driver 13 can generate a scan signal for display scanning, a scan signal for sensing, and a scan signal for brightness recovery under the control of the timing controller 11.

[0065] In order to achieve display driving, the gate driver 13 can generate a scan signal for display according to the first gate control signal GDC during the vertical active period, and can sequentially provide the generated scan signal for display to the gate line 17 connected to the pixel group row.

[0066] To achieve sensing drive, gate driver 13 can generate a scan signal for sensing according to a second gate control signal GDC during a vertical blank period, and can provide the generated scan signal for sensing to gate line 17 connected to the row of sensing pixels. Subsequently, to achieve brightness recovery drive, gate driver 13 can generate a scan signal for brightness recovery according to a third gate control signal GDC, and can also provide the generated scan signal for brightness recovery to gate line 17 connected to the row of sensing pixels.

[0067] The number of pixel groups to be sensed can be set based on the length of the vertical blank period. The positions of the sensed pixel groups can be randomly distributed. When the positions of the sensed pixel groups are randomly distributed, their positions are less likely to be recognized by the user due to the overall visual effect.

[0068] The gate driver 13 can be formed in the non-display area NA of the display panel 10 as a gate-driver in panel (GIP) scheme.

[0069] DAC 121 is connected to data line 15. Under the control of timing controller 11, DAC 121 can generate data voltages for display, data voltages for sensing, and data voltages for brightness recovery.

[0070] In order to achieve display driving, DAC 121 can convert image data DATA into data voltage for display according to the first data control signal DDC during the vertical effective period, and can provide the data voltage for display to data line 15 in a state synchronized with the scan signal for display.

[0071] In order to achieve sensing drive, DAC 121 can generate a predetermined level of data voltage for sensing according to the second data control signal DDC during the vertical blank period, and can provide the data voltage for sensing to the data line 15 in a state synchronized with the scan signal for sensing.

[0072] To achieve brightness recovery drive, DAC 121 can convert image data DATA, which further reflects the brightness compensation gain, into a data voltage for brightness recovery according to the third data control signal DDC, and can provide the data voltage for brightness recovery to data line 15 in a state synchronized with the scan signal for brightness recovery.

[0073] During sensing, the sensing circuit 122 is connected to the target pixel PXL in the row of sensing pixels via the readout line 16. The sensing circuit 122 senses the electrical characteristics of the driving TFT DT included in the target pixel PX during at least one sensing period in the vertical blank period via the readout line 16.

[0074] The sensing circuit 122 can be implemented as a voltage sensing circuit or a current sensing circuit.

[0075] The voltage-sensing sensing circuit 122 may include a sampling circuit and an analog-to-digital converter. The sampling circuit directly samples the specific node voltage of the target pixel PXL stored in the parasitic capacitor of the readout line 16. The analog-to-digital converter converts the analog voltage sampled by the sampling circuit into a digital sensed value and sends the digital sensed value to the timing controller 11.

[0076] The current-sensing circuit 122 may include a current integrator, a sampling circuit, and an analog-to-digital converter. The current integrator integrates the pixel current flowing in the target pixel PXL and outputs a sensed voltage. The sampling circuit samples the sensed voltage output from the current integrator. The analog-to-digital converter converts the analog voltage sampled by the sampling circuit into a digital sensed value and sends the digital sensed value to the timing controller 11.

[0077] The compensation circuit included in the timing controller 11 can correct image data based on digital sensing values ​​to compensate for deviations in electrical characteristics between pixels. The corrected image data is converted into data voltages for display by the DAC 121 and written into the pixels (display driver).

[0078] Additionally, the compensation circuit included in the timing controller 11 can further apply the brightness compensation gain to the corrected image data to minimize cognitive errors caused by the length deviation of the brightness recovery period based on the position of the sensing pixel group row. The image data to which the brightness compensation gain has been further applied is converted into a data voltage for brightness recovery by the DAC 121 and written into the pixels (brightness recovery drive).

[0079] Figure 7 This is a diagram illustrating the transmission and reception of signals based on a variable frame frequency between the host system and the timing controller. Figure 8 and Figure 9 This is a diagram illustrating VRR technology, which uses an input image to change the frame rate.

[0080] Reference Figure 7Considering the data rendering time of the input image, the host system 14 changes the frame rate by altering the length of the vertical blank period (i.e., the length of the non-conversion period of the data enable signal). This resolves problems caused by sudden image changes due to frame rate variations, such as screen cutting, screen flicker, and input latency. The host system 14 can adjust the frame rate within a frequency range of 40Hz to 240Hz depending on the data rendering time of the input image, or within a frequency range of 1Hz to 10Hz for still images; however, this disclosure is not limited thereto. The variable frame rate range may vary depending on the model and specifications.

[0081] like Figure 8 As shown, the host system 14 can change the frame rate by fixing the length of the vertical active period Vactive and adjusting the length of the vertical blank period Vblank according to the data rendering time of the input image. For example, as Figure 9 As shown, host system 14 may include a first vertical blank period Vblank1 to achieve a 144Hz mode. Host system 14 may include a second vertical blank period Vblank2 that is "X" longer than the first vertical blank period Vblank1 to achieve a 100Hz mode. Host system 14 may include a third vertical blank period Vblank3 that is "Y" longer than the first vertical blank period Vblank1 to achieve an 80Hz mode. Host system 14 may include a fourth vertical blank period Vblank4 that is "Z" longer than the first vertical blank period Vblank1 to achieve a 60Hz mode.

[0082] The host system 14 can control the number of compensation command signals, such that the number of sensing operations increases proportionally to the length of the vertical blank period in a variable frame frequency environment. For example, as Figure 9 As shown, the host system 14 can generate A compensation command signals (A being a natural number including 0) at predetermined intervals (e.g., a sensing time interval) during a first vertical blank period Vblank1 in 144Hz mode, causing A sensing operations to be performed, and can generate B compensation command signals (B being a natural number greater than A) at predetermined intervals during a second vertical blank period Vblank2 in 100Hz mode, causing B sensing operations to be performed. Similarly, as... Figure 9As shown, the host system 14 can generate C compensation command signals (C is a natural number greater than B) at predetermined intervals during the third vertical blank period Vblank2 in 80Hz mode, causing C sensing operations to be performed, and can generate D compensation command signals (D is a natural number greater than C) at predetermined intervals during the fourth vertical blank period Vblank4 in 60Hz mode, causing D sensing operations to be performed. As described above, by setting the number of sensing operations differently according to the length of the vertical blank period, compensation cycle delay can be prevented and image defects can be minimized.

[0083] Figure 10 This is a diagram illustrating an example in which at least one sensing period is set in a vertical blank period to correspond to a compensation command signal. Figure 11 It is shown in Figure 10 A diagram illustrating the sensing operations performed during a sensing period.

[0084] Reference Figure 10 Multiple sensing periods TCMP can be set within a single vertical blank period Vblank to correspond to multiple compensation command signals CCMD1 to CCMDn.

[0085] In response to each of the multiple sensing periods, panel driving circuits 121 and 13 (see Figure 1 The scanning signal used for sensing and the data voltage synchronized therewith for sensing are written to the target pixel PXL, and the sensing circuit 122 (see...) Figure 1 The electrical characteristics (voltage or current) of the target pixel PXL are sensed. Therefore, the panel driving circuits 121 and 13 (see [reference]) can be configured according to the number of sensing time periods TCMP set within a vertical blank time period Vblank. Figure 1 The number of signal writes performed by the sensing circuit 122 (see...) Figure 1 The number of times sensing is performed. In other words, it can be achieved through panel driving circuits 121 and 13 (see [reference]) that are executed during the vertical blank period Vblank. Figure 1 The number of signal writes and sensing circuit 122 (see) Figure 1 The number of sensing times is used to identify the number of sensing periods (TCMPs) set within the same vertical blank period (Vblank).

[0086] The vertical blank period Vblank is located between the falling edge FE of the last data enable signal DE belonging to the first frame and the rising edge RE of the first data enable signal DE belonging to the second frame after the first frame.

[0087] The first time interval ITV1 between one of the compensation command signals CCMD1 to CCMDn (i.e., the last compensation command signal CCMDn) and the rising edge RE of the first data enable signal DE is uniform and independent of the length of the vertical blank period. When the first time interval ITV1 varies according to the frame rate, the length of the brightness recovery period deviates for the same group of sensing pixels. As a result, it cannot be applied... Figures 14 to 15b The Sensing Pixel Group Line Compensation (SLC) technique shown herein allows the sensing pixel group lines to be visible as either bright or dark lines. Preferably, the first time interval ITV1 is fixed to a sensing period TCMP, independent of the length of the vertical blank period, in order to prevent this side effect from occurring.

[0088] Furthermore, preferably, the second time interval ITV2 between the first compensation command signal CCMD1 (from CCMD1 to CCMDn) and the falling edge FE of the last data enable signal DE is also uniformly set, regardless of the length of the vertical blank period. Here, the second time interval ITV2 can be defined as "the vertical blank period at the highest frame frequency - one sensing period". Since "the vertical blank period at the highest frame frequency" and "one sensing period" are predetermined constant values, the second time interval ITV2 is also a constant value. Therefore, the second time interval ITV2 can be fixed to the same length, that is, shorter than the length of one sensing period TCMP, regardless of the length of the vertical blank period. In each vertical blank period with a variable length, the first compensation command signal CCMD1 and the first sensing period TCMP synchronized with it are located after the second time interval ITV2. The second time interval ITV2 provides uniform reference information about the start time of the sensing period TCMP in each vertical blank period with a variable length, thereby improving the accuracy of sensing.

[0089] like Figure 11 As shown, a sensing period TCMP can be defined as the time during which at least some of the pixels included in the same sensing pixel group line Line K (K is a natural number) are sensed simultaneously. R pixels, G pixels, B pixels, and W pixels with different driving characteristics and luminous efficiencies are included in the same sensing pixel group line. Therefore, to improve sensing accuracy, it is more advantageous to sense R pixels, G pixels, B pixels, and W pixels separately. With this in mind, it is more preferable to define a sensing period TCMP as the time during which pixels achieving the same color are sensed simultaneously among the pixels included in the same sensing pixel group line Line K.

[0090] Figure 12This is a diagram illustrating how the number of compensation command signals changes according to the length of the vertical blank period in a variable frame rate environment.

[0091] Reference Figure 12 The compensation command signal (CCMD) can be a separate control signal independent of other signals. In a third vertical blank period (Vblank3) that is longer than the first vertical blank period (Vblank1), there can be a greater number of compensation command signals (CCMD) than in the first vertical blank period (Vblank1). For example, the number of compensation command signals (CCMD) in the first vertical blank period (Vblank1) can be 3, while the number of compensation command signals (CCMD) in the third vertical blank period (Vblank3) can be 5. Here, each of the first vertical blank period (Vblank1) and the third vertical blank period (Vblank3) is longer than a sensing period (TCMP). As a result, three sensing operations can be performed in the first vertical blank period (Vblank1), and five sensing operations can be performed in the third vertical blank period (Vblank3).

[0092] Additionally, due to the delay in the effective time period, the length A of a specific vertical blank time period can be shorter than the length B of a sensing time period TCMP, which will be referenced. Figure 16 and Figure 17 Describe it. As an example, during a specific vertical blank period is Figure 12 In the case of the second vertical blank period Vblank2, the host system can perform control such that no compensation command signal CCMD is present in the second vertical blank period Vblank2. In other words, the host system can skip generating the compensation command signal CCMD in response to a vertical blank period shorter than a sensing period TCMP, thereby preventing a reduction in sensing accuracy due to insufficient sensing time.

[0093] Figure 13 This is a diagram illustrating an example in which the compensation command signal takes the form of an integrated control signal integrated with other signals.

[0094] Reference Figure 13The compensation command signal (CCMD) may take the form of an integrated control signal integrated with other signals. The integrated control signal may include a compensation command signal (CCMD) having a first mode and a vertical synchronization signal (Vsync) having a second mode different from the first mode. The number of transitions in the first mode may be greater than the number of transitions in the second mode; however, this disclosure is not limited thereto. During a vertical blank period, a sensing period (TCMP) may be set to correspond to the compensation command signal (CCMD) having the first mode, and may also be set to correspond to the vertical synchronization signal (Vsync) having the second mode. The vertical synchronization signal (Vsync) can be used not only to define a frame period, but also to define the last sensing period (TCMP) in the vertical blank period. Furthermore, if the length of the vertical blank period is short, the compensation command signal (CCMD) having the first mode may be omitted, and only the vertical synchronization signal (Vsync) having the second mode may be present in the vertical blank period. In this case, during the vertical blank period, a sensing period (TCMP) may be set to correspond to the vertical synchronization signal (Vsync) having the second mode, or it may be set to be shorter than a sensing period (TCMP) and shorter than... Figure 10 The "ITV2" program has a long airtime. This will be referenced below. Figure 16 and Figure 17 Describe it.

[0095] Figure 14 This is a diagram illustrating a brightness recovery technique used to compensate for brightness loss caused by sensing. Figure 15a and Figure 15b This is a diagram illustrating an example of a brightness compensation gain setting based on brightness recovery time.

[0096] Figures 14 to 15b An SLC technique for compensating for length deviations in the brightness recovery period based on the position of the sensing pixel group row is shown.

[0097] When an image is displayed on a screen with all pixels having the same brightness, such as Figure 14 As shown, the sensing pixel PXL-B does not emit light during the sensing period in the vertical blank period Vblank, and therefore can exhibit a brightness that is "ΔL" lower than that of the non-sensing pixel PXL-A.

[0098] To compensate for brightness loss caused by sensing, a brightness recovery drive is performed on the sensing pixel PXL-B. The brightness recovery drive is executed immediately after the sensing drive, based on the brightness compensation gain. Because the sensing pixel to which the brightness compensation gain is applied exhibits higher brightness than other pixels during the brightness recovery period, all pixels on a screen can exhibit essentially the same brightness. The brightness recovery period continues until the data voltage used for display is written to the corresponding sensing pixel in a subsequent frame.

[0099] The magnitude of the brightness compensation gain can be inversely proportional to the length of the brightness recovery period. Regardless of the relative positions of the sensing pixels, all sensing pixels experience the same brightness loss. However, since the brightness recovery periods of different lengths are matched to each other based on the position of the sensing pixel rows, brightness compensation gains capable of compensating for brightness loss can be applied differently to the sensing pixel rows.

[0100] The correction of image data caused by the brightness compensation gain can be performed by the timing controller. The timing controller's compensation circuit may also include SLC compensation logic, which is used to further apply the brightness compensation gain to the image data to be written into the rows of sensing pixels.

[0101] like Figure 15a As shown, the magnitude of the luminance compensation gain can be matched differently for each luminance recovery block time period grouped by a predetermined time size. In this case, the SLC compensation logic in the compensation circuit is simplified, and the compensation processing speed is high.

[0102] like Figure 15b As shown, the brightness compensation gain can be set differently for each individual brightness recovery period that changes in each row of sensing pixels. In this case, the accuracy of compensation is improved.

[0103] Figure 16 and Figure 17 This is a diagram illustrating the signal delay operation of a host system used to equalize the time interval between the last compensation command signal in a vertical blank period and the start time of the vertical active period of the subsequent frame.

[0104] Reference Figure 16Due to changes in frame rate, the time point when the rendering of the input image completes and the time point when the final compensation command signal for the vertical blanking period is generated may not be consistent. In this case, the time interval between the completion time of the input image rendering and the start time point t01 of the vertical valid period is shorter than one sensing period TCMP. In this situation, the host system can delay the start time point of the vertical valid period of the output rendering data from "t01" by XY to "t02", making the time interval between the completion time of the input image rendering and the start time point of the vertical valid period equal to one sensing period TCMP. That is, the host system can delay the start time point of the vertical valid period by "XY" to further ensure one sensing period TCMP. Through this delay, the start time point of the new vertical valid period is reset to "t02". The host system also delays the vertical synchronization signal Vsync by "XY" to further ensure one sensing period TCMP, and further allocates one sensing period TCMP based on the delayed vertical synchronization signal Vsync. The delay time "XY" is shorter than one sensing period TCMP.

[0105] Reference Figure 17 Due to the change in frame rate, the time when the rendering process of the input image is completed and the time when the final compensation instruction signal for the vertical blank period is generated may coincide or may not coincide.

[0106] For example, when the rendering process is completed at the same time as the last compensation instruction signal that generates the vertical blank period, such as in the first vertical blank period Vblank1, the host system does not delay the start time of the vertical valid period.

[0107] Conversely, when the rendering process is completed at a time that is not the same as the time when the final compensation command signal for the vertical blank period is generated, such as in the second vertical blank period Vblank2, the host system delays the start time of the vertical valid period and extends the second vertical blank period Vblank2 to a second vertical blank period 'Vblank2'. Furthermore, a compensation command signal is generated again in the second vertical blank period 'Vblank2', and a further sensing period TCMP is allocated.

[0108] Furthermore, if the completion time of the next frame's rendering process occurs during the current frame's vertical effective time period due to a delay in the start time of the vertical effective time period caused by the delay in the start time of the vertical effective time period, then the first vertical blank period 'Vblank1' immediately following the completion of the current frame can be shorter than one sensing time period TCMP. However, in this case, where the frequency of the next frame is close to the maximum frame frequency, the extended second vertical blank period 'Vblank2' in the current frame, compared to the second vertical blank period Vblank2, does not exceed one sensing time period TCMP. Therefore, the vertical blank period Vblank of the next frame maintains the second time interval ITV2 (see...). Figure 10 The second time interval ITV2 is the time by which a sensing period TCMP is removed or more compared to the original first vertical blank period 'Vblank1'. In this case, the host system skips the generation of the compensation command signal and does not allocate a sensing period in the first vertical blank period 'Vblank1'. Therefore, it is not necessary to maintain the relationship between the vertical synchronization signal Vsync and the active DE (the defined vertical active period) for a sensing period TCMP, so the interval between the vertical synchronization signal Vsync and the active DE can be shortened to the second time interval ITV2 (see...). Figure 10 ).

[0109] In addition, Figure 17 In this context, the minimum blank (min-blank) represents... Figure 10 The second time interval ITV2.

[0110] Figure 18 This is a flowchart illustrating the control sequence related to the signal delay operation of the host system.

[0111] Reference Figure 18 The host system monitors whether a vertical blank period has begun and whether a delay has been inserted in the previous frame based on the data enable signal. The host system handles the minimum blank period (which refers to...). Figure 17 The minimum blank period ends and the rendering process is monitored to ensure completion. The host system processes the minimum blank period (which refers to...) even outside of the valid period, based on the output data enable signal. Figure 17 The minimum blank period ends, and the rendering process is monitored to see if it is completed within the period between the valid period and the end of the minimum blank period.

[0112] The host system generates a first compensation command signal CCMD after the minimum blank period ends, with a sensing period TCMP (see Figure 17 The system generates subsequent compensation instruction signals at intervals of ) and monitors whether the rendering process is complete.

[0113] If the completion time of the rendering process is not synchronized with the time of the last compensation command signal that generates the vertical blank period, the host system delays the start time of the vertical active period and outputs image data and a data enable signal in a state that matches the delayed vertical active period. By further generating compensation command signals and allocating a sensing period during the extended vertical blank period due to the delay, the host system generates compensation command signals at predetermined intervals (i.e., one sensing period interval) until the subsequent vertical active period, regardless of the length of the vertical blank period.

[0114] Additionally, when a rendering completion signal is generated at the end of the output vertical effective period and the minimum blank period, the host system skips the generation of the compensation instruction signal.

[0115] As described above, in this embodiment, when using an external compensation scheme to compensate for changes in electrical characteristics between pixels, even if the frame frequency changes according to the input image, the number of sensing times increases proportionally to the length of the vertical blank period (i.e., multiple sensing), thereby minimizing compensation cycle delay and image defects.

[0116] Invention Model

[0117] Various implementations have been described in the best mode for carrying out the contents of this disclosure.

[0118] Industrial applicability

[0119] In this embodiment, when using an external compensation scheme to compensate for changes in electrical characteristics between pixels, even if the frame frequency changes according to the input image, the number of sensing times increases proportionally to the length of the vertical blank period (i.e., multiple sensing), thereby minimizing compensation cycle delay and image defects.

[0120] In this embodiment, when there are multiple compensation command signals in a vertical blank period for multiple sensing, the time interval between the last compensation command signal and the start time of the subsequent effective period is fixed as a sensing period according to the change of frame frequency, regardless of the length of the vertical blank period. This makes it easy to apply SLC technology and minimize cognitive errors caused by sensing.

[0121] Therefore, this disclosure has industrial applicability.

Claims

1. A display device comprising: a display panel including a plurality of pixels; a timing controller configured to receive a compensation instruction signal in a vertical blanking period in which no image data is written into the pixels; and a sensing circuit configured to sense a driving characteristic of the pixels in at least one sensing period corresponding to the compensation instruction signal, wherein a length of the vertical blanking period is different from each other in a first frame and a second frame, and a number of sensing periods each having a predetermined length is changed according to the length of the vertical blanking period, wherein the vertical blanking period is located between a falling edge of a last data enable signal in the first frame and a rising edge of a first data enable signal in the second frame after the first frame, and a first time interval between a last compensation instruction signal among the compensation instruction signals and the rising edge of the first data enable signal is uniform regardless of the length of the vertical blanking period.

2. The display device according to claim 1, wherein the number of sensing periods is increased according to the length of the vertical blanking period.

3. The display device according to claim 1, wherein the number of sensing periods during at least one vertical blanking period corresponds to the number of compensation instruction signals during the at least one vertical blanking period.

4. The display device according to claim 1, wherein the first time interval is fixed to one sensing period regardless of the length of the vertical blanking period.

5. The display device according to claim 1, wherein a second time interval between a first compensation instruction signal among the compensation instruction signals and the falling edge of the last data enable signal is uniform regardless of the length of the vertical blanking period.

6. The display device according to claim 5, wherein the second time interval is shorter than one sensing period regardless of the length of the vertical blanking period.

7. The display device according to claim 1, wherein the vertical blanking period includes: a first vertical blanking period longer than one sensing period; and a second vertical blanking period shorter than one sensing period, and at least one compensation instruction signal is located in the first vertical blanking period.

8. The display device according to claim 7, wherein the compensation instruction signal is not located in the second vertical blanking period.

9. The display device according to claim 1, wherein the compensation instruction signal has a form of an integrated control signal integrated with other signals or a form of a separate control signal independent of other signals.

10. The display device according to claim 9, wherein the integrated control signal includes a compensation instruction signal having a first pattern and a vertical synchronization signal having a second pattern different from the first pattern, and the vertical synchronization signal defines one frame period.

11. The display device according to claim 9, wherein the integrated control signal is implemented by a vertical synchronization signal for defining one frame period. ​ 12. The display device according to claim 1, wherein the sensing period is a period in which at least some of the plurality of pixels are sensed at the same time.

13. The display device according to claim 1, further comprising: a host system configured to generate the compensation instruction signal and output the compensation instruction signal to the timing controller, wherein the host system is configured to control a length of the vertical blanking period in accordance with a complexity of an input image.

14. The display device according to claim 13, wherein whether the compensation instruction signal is generated and a number of the compensation instruction signal are varied in accordance with the length of the vertical blanking period and a predetermined length of one sensing period.

15. The display device according to claim 14, wherein generation of the compensation instruction signal is skipped when the length of the vertical blanking period is shorter than the predetermined length of the one sensing period.

16. The display device according to claim 13, wherein a length of a vertical active period after the vertical blanking period is fixed regardless of a complexity of an input image.

17. The display device of claim 16, wherein, the host system delays a time point at which the vertical active period starts in a case where a time interval between a time point at which a rendering process of the input image is completed and the time point at which the vertical active period starts is shorter than the one sensing period due to a change in a frame frequency.

18. The display device according to claim 17, wherein any one of the compensation instruction signals corresponds to the one sensing period secured by the delay.

19. A method of driving a display device, the method comprising: receiving a compensation instruction signal in a vertical blanking period in which no image data is written into a plurality of pixels; and sensing a driving characteristic of the plurality of pixels in at least one sensing period corresponding to the compensation instruction signal, wherein a length of the vertical blanking period is different from each other in a first frame and a second frame, and a number of sensing periods each having a predetermined length corresponds to the length of the vertical blanking period, wherein the vertical blanking period is located between a falling edge of a last data enable signal in the first frame and a rising edge of a first data enable signal in the second frame after the first frame, and a first time interval between a last compensation instruction signal among the compensation instruction signals and the rising edge of the first data enable signal is uniform regardless of the length of the vertical blanking period.

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