A reconfigurable multi-range detection endoscope system

Abstract

The application provides a reconfigurable multi-range detection endoscope system, comprising a plurality of shooting modules for shooting first image data at multiple angles; an FPGA module, wherein the FPGA module has a plurality of LVDS interfaces respectively for receiving a plurality of first image data; a data exchange module for splicing processing of the plurality of first image data; and an output interface for outputting second image data after splicing processing; wherein the data exchange module comprises a front-end FIFO module for writing and buffering the first image data transmitted by the LVDS interface; a DDR memory for controlling the DDR to write, process and read out the image data; and a back-end FIFO module for writing and buffering the second image data read out from the DDR memory. The endoscope system has the advantage of being easy to reconfigure.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of medical devices, in particular to a reconfigurable multi-range detection endoscope system. BACKGROUND

[0002] Medical endoscopes are important medical devices for minimally invasive surgery. With the development of minimally invasive surgery in recent years, endoscopes have been constantly updated.

[0003] Existing endoscopes usually use CIS chips as the image acquisition core. Since different CIS chips have different interfaces, such as MIPI, SPI, IIC, and DVP, if a special image processing embedded board available on the market is used as the main control board, several problems will exist. Most existing special image data processing boards cannot have multiple camera interfaces at the same time, so these boards cannot meet the requirement of simultaneously connecting multiple CIS data to the main control core board. Moreover, all interfaces are fixed, and if the CIS chip needs to be replaced or the number of channels needs to be increased or decreased, the main control board needs to be replaced, which is a great waste for the reform and replacement of the entire endoscope system.

[0004] Therefore, it is particularly important to provide a reconfigurable multi-range detection endoscope system. SUMMARY

[0005] To solve the above technical problems, the present application provides a reconfigurable multi-range detection endoscope system.

[0006] The present application provides a reconfigurable multi-range detection endoscope system, which comprises:

[0007] A plurality of shooting modules for shooting first image data at multiple angles;

[0008] An FPGA module having:

[0009] A plurality of LVDS interfaces for receiving a plurality of first image data respectively;

[0010] A data exchange module for stitching processing a plurality of first image data;

[0011] An output interface for outputting second image data after stitching processing;

[0012] The data exchange module comprises:

[0013] A front-end FIFO module for writing and buffering first image data transmitted by the LVDS interface;

[0014] A DDR memory for controlling DDR to write, process, and read out the image data.

[0015] a back-end FIFO module for buffering the second image data read out from the DDR memory.

[0016] Preferably, the data exchange module further comprises a data gating module, wherein:

[0017] the front-end FIFO module comprises a plurality of input FIFOs respectively arranged in channels where the plurality of LVDS interfaces are located, and the data gating module is configured to gate the DDR memory and one of the plurality of input FIFOs;

[0018] the output interface comprises an HDMI interface and a USB interface, the back-end FIFO module comprises two output FIFOs respectively arranged in channels where the two output interfaces are located, and the data gating module is configured to gate the DDR memory and one of the two output FIFOs;

[0019] Preferably, the plurality of photographing modules and the two output interfaces are arranged to work asynchronously.

[0020] Preferably, the data gating module is configured to arrange a counter on each channel of the input FIFO, and the counter is configured to count the number of data read out from the DDR memory to the input FIFO, when all data of an image are read out, the input FIFO and the corresponding counter stop working and are in a reset state.

[0021] Preferably, the data gating module is configured to assign a judgment bit to each of the two asynchronous output FIFOs, when the data written from the DDR memory to the output FIFO is the last data of an image, the output FIFO stops writing data, and the corresponding judgment bit is in a reset state.

[0022] Preferably, the DDR memory selects the input FIFO which is not in a reset state and has the smallest remaining storage space to read data each time when writing data.

[0023] Preferably, the DDR memory selects the output FIFO which is not in a reset state and has the largest remaining storage space to input data each time when reading data.

[0024] Preferably, the writing data rate of the DDR memory is greater than the incoming data rate of the plurality of photographing modules, the reading data rate of the DDR memory is greater than the output data rate of the two output interfaces, and the data read-write time ratio of the DDR memory is 1:1.

[0025] Preferably, the input order of the first image data and the output order of the second image data are both from top to bottom and from left to right.

[0026] The input FIFO is provided with a first register configured to record a position corresponding to reading of the first image data in the input FIFO by the DDR memory;

[0027] The output FIFO is provided with a second register configured to record a position corresponding to reading of the second image data in the DDR memory by the output FIFO.

[0028] Preferably, the photographing module comprises a CIS chip and a light source, and the FPGA module further has:

[0029] an IIC communication interface for setting parameters of the CIS chip;

[0030] an IO interface for adjusting brightness of the light source.

[0031] Preferably, a bridge chip is arranged between the CIS chip and the LVDS interface, and the bridge chip is configured to read parallel signals output by the CIS chip and convert the parallel signals into parallel data signals input to the LVDS interface.

[0032] Preferably, the photographing module comprises a first photographing module and a second photographing module, the first photographing module is used to photograph the first image data in front, and the second photographing module is used to photograph the first image data around.

[0033] The present application provides a reconfigurable multi-range detection endoscope system, based on the programmable hardware characteristics of FPGA, adopts FPGA as the main control core board of multi-channel image data acquisition and forwarding, can process image sensor data of multiple channels at high speed and can forward at high speed without blocking, has great flexibility for adding channels or replacing data interfaces, does not need to replace the main control board and does not need to change the hardware circuit on a large scale. Moreover, FPGA has very good real-time advantage for medical image processing, makes the processing speed much faster than CPU in the case of sacrificing a certain area, and the concurrency of FPGA can be between different logic functions, instead of being limited to executing the same function. In summary, the endoscope system has the advantages of convenient reconfiguration and very fast processing speed for medical images. BRIEF DESCRIPTION OF DRAWINGS

[0034] The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain principles of the present application. Other embodiments and many of the intended advantages of the present application will be readily appreciated as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

[0035] Figure 1 is a reconfigurable multi-range detection endoscope system architecture diagram according to one embodiment of the present application;

[0036] Figure 2 is a side and front structural schematic diagram of an endoscope head module product according to one embodiment of the present application;

[0037] Figure 3 is an image data splicing schematic diagram according to one embodiment of the present application;

[0038] Figure 4 is an architecture diagram of a data exchange module according to one embodiment of the present application;

[0039] Figure 5 is an image data storage sequence diagram according to one embodiment of the present application. DETAILED DESCRIPTION

[0040] The features and exemplary embodiments of various aspects of the present application will be described in detail below with reference to the drawings. The following detailed description is merely intended to provide a better understanding of the present application, and is not intended to limit the present application. The present application can be practiced without some of these specific details. The following description of the embodiments is merely provided to provide a better understanding of the present application by showing examples of the present application.

[0041] It is to be understood that the terminology used herein such as first and second, and the like, is merely intended to differentiate one entity or operation from another entity or operation, without necessarily requiring or implying any actual such relationship or order between such entities or operations. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0042] The present application provides a reconfigurable multi-range detection endoscope system. Figure 1 The reconfigurable multi-range detection endoscope system architecture diagram according to one embodiment of the present application is shown as Figure 1 The system comprises a plurality of shooting modules and an FPGA module. The plurality of shooting modules are used for shooting first image data of a plurality of angles; the FPGA module has a plurality of LVDS interfaces, a data exchange module and an output interface. The plurality of LVDS interfaces are respectively used for receiving the plurality of first image data. The data exchange module is used for stitching processing the plurality of first image data. The output interface is used for outputting second image data after the stitching processing. The endoscope system of the present application will be introduced in detail from the selection of each module and the functional principle.

[0043] The FPGA has three advantages, i.e. a high-speed communication interface can be designed, digital signal processing and parallel processing information, it can process image sensor data of a plurality of channels at high speed and can forward at high speed without blocking. And because of the programmable hardware characteristics of the FPGA, it has great flexibility for adding channels or replacing data interfaces, without replacing the main control board and without large-scale changing of the hardware circuit. In addition, the FPGA has very good real-time advantage for medical image processing, and in the case of sacrificing a certain area, the processing speed is very fast, much faster than the CPU. The concurrency of the FPGA can be between different logic functions, rather than being limited to performing the same function. Based on the above advantages, the main control board of the endoscope system of the present application adopts the FPGA module, and the model of the FPGA board used is XC7K7325T.

[0044] Because the FPGA board size is only 83.8mm*64.8mm, the area is very small and convenient for developing small portable endoscope instrument. And has 288 IO interfaces, which can be set to 1.8V / 2.5V / 3.3V three different levels, supports CMOS and LVDS input, and can be compatible with multiple MIPI, DVP, SPI and IIC interfaces in terms of quantity and pin characteristics. And embedded with four DDR memory of MT41K256M16TW type (refer to the following description), the total capacity reaches 2G, which can store multiple high-definition image data, and the internal DDR processing frequency can reach 800M, which is enough to meet the high-speed storage of multiple images without blocking. And the board working clock frequency is 200M, which can meet the efficient operation of various image data processing.

[0045] The FPGA board has multiple LVDS interfaces, a data exchange module, two output interfaces, an IIC communication interface and an IO interface. The multiple LVDS interfaces are respectively used for receiving multiple first image data; the data exchange module is used for splicing processing of the multiple first image data; the two output interfaces are respectively an HDMI interface and a USB interface, and are used for outputting second image data after splicing processing.

[0046] The multiple shooting modules include a first shooting module and a second shooting module, wherein the first shooting module is used for shooting first image data in front, and the second shooting module is used for shooting second image data around. Specifically, each shooting module includes a CIS chip and a light source. For the CIS chip, the selected chip model is OV9734, and the light source is an adjustable voltage LED. The camera shooting image size of this CIS chip can reach 1280*720, and the maximum image data refresh rate can reach 30fps. The initial size of the chip is only 2532um*1722um, which is very suitable for making endoscope series lenses. The chip interface is MIPI, which can ensure that long-distance image data transmission will not be wrong. The pins connected by the FPGA board are configured as an IIC communication interface and an IO interface, the IIC communication interface is used for setting the CIS chip data in the endoscope lens (such as the parameters of the CIS chip internal register), and the IO interface is used for adjusting the voltage of the LED, thereby adjusting the brightness of the LED. In the final lens module product, the entire camera can collect wide-angle view image, and the adjustable voltage LED is used for lighting in front of the lens.

[0047] Figure 2 The side and front structure schematic diagram of the endoscope lens module product according to one specific embodiment of the application is shown in FIG. 1. Figure 2As shown, the photographing module in the embodiment is provided with 4, and the camera composed of A, B, C, D 4 CIS chips is used to form the camera of the endoscope, that is, the A camera is mainly used to observe the front part of the detection tube, the fields of view of the B, C, D three cameras are connected into a ring shape, and are used to observe the part around the detection tube, and the 130-degree wide angle ensures the ring detection, so that the front data and the part around can be detected in the detection process. In the embodiment, the image size of each camera is set to 1280*720 through the FPGA board, and the output image format is YUV.

[0048] Since the FPGA cannot be directly compatible with the MIPI interface, a bridge chip with a model of MC20901 is added between the 4 LVDS interfaces of the FPGA board and the CIS chip, and the main use of the MC20901 is to convert the MIPI interface of the OV9734 into an LVDS interface signal compatible with the FPGA.

[0049] Figure 3 As shown in the image data splicing schematic diagram according to one specific embodiment of the application, Figure 3 As shown, the first image data photographed by the A, B, C, D 4 cameras is spliced into a second image data of 2560*1440 after being processed by the data exchange module in the FPGA board, and is output by the USB interface together with the HDMI interface.

[0050] Figure 4 As shown in the architecture diagram of the data exchange module according to one specific embodiment of the application, Figure 4 As shown, the data exchange module includes a front-end FIFO module, a data gating module, a DDR memory and a back-end FIFO module. The model of the DDR memory selected is MT41K256M16TW, and the DDR memory is provided with 4 and is embedded in the FPGA; the front-end FIFO module includes 4 input FIFOs arranged in the channels of the 4 LVDS interfaces respectively, the data gating module is used to gate the DDR memory and one of the multiple input FIFOs; the back-end FIFO module includes two output FIFOs arranged in the channels of the HDMI interface and the USB interface respectively, and the data gating module is used to gate the DDR memory and one of the two output FIFOs.

[0051] Because the speed of DDR memory reading and writing is not synchronized with the rate of data input or output, in order to ensure that data is not lost, a FIFO is set on each exchange channel as a data intermediate cache. Because the internal DDR reading and writing interface of the FPGA is only one and the same, in order to ensure smooth data reading and writing, it is necessary to ensure that: the DDR writing data rate ≥ (camera A incoming data speed + camera B incoming data speed + camera C incoming data speed + camera D incoming data speed); the DDR reading data rate ≥ (HDMI interface output data rate + USB interface output data rate).

[0052] The calculation data rate formula is:

[0053] Data rate = number of bits of effective data transmitted in T time ÷ T

[0054] T is usually the period length required for storing a complete image or outputting a complete image, so that the data stored in the DDR memory and the output image data can be real-time. If the DDR interface speed is not large enough, the formula is not satisfied, then the camera image frame rate is reduced and the FIFO width is lengthened.

[0055] In the embodiment, the four cameras (CIS chips) and the two output interfaces (HDMI interface and USB interface) are set to work asynchronously, or the four input FIFOs and the two output FIFOs are set to work asynchronously, which is one of the important application points of the application, and the application point is described below through a detailed introduction of the working process of the data exchange module.

[0056] The specific process of the data exchange module is as follows:

[0057] The four cameras and the two output interfaces are set to work asynchronously, the data gating module sets a counter (not shown in the drawing) for each camera, the function of the counter is to count the number of data in the input FIFO of the corresponding camera read by the DDR memory, when all the data of a complete image (first image data) are read, the corresponding input FIFO and the corresponding counter are in a reset state, until the next image transmission start signal from the camera is received, the input FIFO and the counter start working again. The data gating module also gives the output FIFO of the HDMI interface and the USB interface each a judgment bit, when the data (second image data) written from the DDR memory to the output FIFO is the last data of a complete image, the output FIFO stops writing data, the corresponding judgment bit is in a reset state, until the HDMI interface and the USB interface read the output FIFO, the corresponding output FIFO is reset and the corresponding judgment bit is reset.

[0058] Figure 5Figure 1 shows an image data storage sequence diagram according to one embodiment of the present application, as shown in Figure 5 As shown, an image is composed of one pixel after another, and the image data contains color information of the pixels, and the image data expression sequence is from the first pixel in the first row to the last pixel in the first row, then to the first pixel in the second row, and finally to the last pixel in the last row, i.e., the input sequence of the first image data is row first and column second. The output sequence of the second image data is also row first and column second, and the DDR supports fast address jump writing inside the FPGA, so a separate first register (not shown in the figure) is used to record the position in the DDR memory to which the current input FIFO writes data, to ensure that the storage sequence of all cameras is row first and column second. For the HDMI interface and the USB interface, a complete second image data is expected to be output, so the output channel reads the DDR directly according to the address of the first bit of data stored in the DDR, and then reads the last bit of data stored in the DDR, so a separate second register (not shown in the figure) is used to record the position in the image data address to which the current output FIFO reads data. The advantage of this is that the reading and writing are separated, and the DDR memory has only one interface, but it reads and writes data as much as it can, and as long as the processing rate is greater than the required rate, there will be no delayed image data output.

[0059] The specific DDR read-write process is as follows:

[0060] Because the embedded DDR rate and interface size inside the FPGA are different, the number of data operated by different FPGAs in a fixed time is different. In this embodiment, the transmissible interface size of the DDR is 512 bits. Because the interface size is too large, for each camera, the first image data of multiple cameras needs to be packaged together and then cached to the DDR memory. For the HDMI and USB outputs, the data output by the DDR memory at a time can be processed and output by the interface multiple times, so during the gap period of packaging the first image data of each camera or processing the 512-bit second image data output by the DDR memory at a time, the DDR memory can read the first image data of the input FIFO of another camera or output the second image data to another output FIFO, so that each channel can operate smoothly, and the entire image transmission speed depends on whether the read-write speed of the DDR memory interface can keep up with the rate requirement of each external device.

[0061] DDR memory how to choose which channel priority processing, also need to follow certain rules. In this embodiment, a total of 4 camera channels, 2 output interface channels, a total of 6 channels need to be processed, that is, the operation of 6 FIFO. First, in order to make the overall power consumption as small as possible, so the FIFO can not be too long, in this embodiment, all the FIFOs are the same length, are read-write asynchronous FIFO, the length is 512, the width is 512bit. For input FIFO, DDR memory preferentially selects the input FIFO that is not in the reset state and has the smallest remaining storage space to read data. For output FIFO, DDR memory preferentially selects the output FIFO that is not in the reset state and has the largest remaining storage space to input data. Moreover, for the time ratio of read and write operations of DDR memory, there is no mandatory ratio, because read and write have been separated. The same camera can write several first image data of pictures to DDR memory, but the output interface can only output one complete second image data in this time, or the output interface can output several complete second image data, but these cameras can only write one or two first image data. In practice, it is also not required that a camera cannot output or a complete second image data cannot be output by the output interface before one first image data is completely written into DDR memory or these cameras cannot write new pictures into DDR memory. Therefore, it is possible that the output interface outputs one complete second image data that may contain several periods of first image data, new and old mixed together, and it may also cause the output interface to output a complete second image data before the first image data in DDR memory is updated. And because the data processing rate is very fast, in actual application, the human eye cannot see this difference, even if a complete second image data may contain several periods of first image data, that is, the true sense of read-write separation, but the observer still feels that it is continuous real-time detection. Therefore, in practice, the read-write time should be set to 1:1, because even if the writing is faster or the reading is slower, the image flow rate will not change. Therefore, for the formula:

[0062] DDR write data rate ≥ (camera A incoming data speed + camera B incoming data speed + camera C incoming data speed + camera D incoming data speed); DDR read data rate ≥ (HDMI interface output data rate + USB interface output data rate); data rate = T time transmission of valid data bit number ÷ T.

[0063] Because the DDR memory read-write time is the same length, the DDR write data rate = DDR read data rate, unified 100M*512bit, for other image input or HDMI output, etc. Data rate calculation T should be the basic unit of the complete processing cycle, and the number of bits of valid data transmitted in T time only represents the valid image data, that is, it does not include data generated in the reset state and various start and end control signals, etc. When all operations meet the above formula, it can be ensured that all channels of data are mixed transmission in time, but it can also ensure that multiple images are real-time captured and spliced output.

[0064] Such a form can satisfy that the DDR memory can switch the read-write state at any time, and the read-write channel can be switched at any time, but it does not affect the final image integration output, and will not cause delay and blockage. The DDR memory tries to make all input FIFOs not full, and the output FIFO has something to output. Reading and writing are separated, and it is not required to read or write first, or to read and write a complete image data, each channel does not affect each other to operate on the address recorded by itself, and the DDR memory decides to process the data in the FIFO according to the state of each FIFO, which maximizes the transmission efficiency.

[0065] In the test of the endoscope system of the embodiment, the maximum read-write rate of the DDR memory interface in the FPGA can reach 1866Mb / s, that is, if the read-write time is 1:1, the read rate and the write rate can reach 933Mb / s respectively. Each camera transmits 30 frames of 1280*720 images per second, that is, 55.296Mb / s. The maximum output rate of the HDMI interface and the USB interface in the FPGA can reach 55Mb / s and 1.5Mb / s, but actually T also includes reset time and transmission time of other signals, so the output rate of the HDMI interface and the USB interface is less than the theoretical maximum value, so the above requirements are met.

[0066] The application provides a reconfigurable multi-range detection endoscope system, which is based on the programmable hardware characteristics of FPGA, uses FPGA as a main control core board for multi-channel image data acquisition and forwarding, can process image sensor data of multiple channels at high speed and can forward at high speed without blocking, has great flexibility for adding channels or replacing data interfaces, does not need to replace the main control board and does not need to make large-scale changes to the hardware circuit. Moreover, FPGA has very good real-time advantage for medical image processing, and in the case of sacrificing a certain area, the processing speed is much faster than CPU, and the concurrency of FPGA can be between different logic functions, instead of being limited to executing the same function. The endoscope system has the advantages of convenient reconfiguration and fast medical image processing speed.

[0067] In the embodiments of the present application, it should be understood that the disclosed technology can be implemented in other manners. The described embodiments of the apparatus / system / method are merely illustrative, for example, the division of the units can be a logical function division, and there can be another division manner in actual implementation, for example, a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed coupling or direct coupling or communication connection between the units can be indirect coupling or communication connection through some interfaces, and can be electrical or other forms.

[0068] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place or can be distributed on a plurality of units. Some or all of the units can be selected according to actual needs to achieve the purposes of the embodiments of the present application.

[0069] In addition, each functional unit in the embodiments of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit. The integrated unit can be implemented in the form of hardware or in the form of a software functional unit.

[0070] When the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium. Based on such an understanding, the technical solutions of the present application essentially or substantially, or all or part of the technical solutions, can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in the embodiments of the present application. The foregoing storage medium includes: a U disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a mobile hard disk, a magnetic disk or an optical disk, and various other media that can store program codes.

[0071] It is clear that many modifications and changes can be made to the embodiments of the application without departing from the spirit and scope of the application. In that manner, the application also intends to cover what falls within the scope of the following claims and their equivalents. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The mere fact that different claims depend on a common parent claim does not indicate that combinations of measures of the different dependent claims cannot be used in advantage. Any reference signs in the claims should not be construed as limiting the scope.

Claims

1. A reconfigurable multi-range detection endoscope system, characterized in that, include: Multiple shooting modules are used to capture first image data from multiple angles; FPGA module, the FPGA module having: Multiple LVDS interfaces are used to receive multiple sets of the first image data; The data exchange module is used to stitch together multiple sets of the first image data. The output interface is used to output the stitched second image data. The data exchange module includes: The front-end FIFO module is used to write the first image data transmitted from the LVDS interface for caching; DDR memory, used to control the DDR to realize the writing, processing and reading of the image data; The back-end FIFO module is used to write the second image data read from the DDR memory for caching; The data exchange module further includes a data gating module, wherein: the front-end FIFO module includes multiple input FIFOs respectively disposed in the channels where the multiple LVDS interfaces are located, and the data gating module is configured to select the DDR memory and one of the multiple input FIFOs; the output interface includes an HDMI interface and a USB interface, and the back-end FIFO module includes two output FIFOs respectively disposed in the channels where the two output interfaces are located, and the data gating module is configured to select the DDR memory and one of the two output FIFOs; wherein, the multiple shooting modules and the two output interfaces are all set to work asynchronously; The data gating module selects a counter on each channel of the input FIFO. This counter is configured to count the number of times data is read from the input FIFO by the DDR memory. When all data for an image has been read, the input FIFO and the corresponding counter stop working and are in a reset state. The data gating module is configured to assign a judgment bit to each of the two output FIFOs. When the data written to the output FIFO from the DDR memory is the last data of an image, the output FIFO stops writing data, and the corresponding judgment bit is in a reset state. Each time data is written, the DDR memory selects the input FIFO that is not in a reset state and has the smallest remaining storage space to read data. Each time data is read, the DDR memory selects the output FIFO that is not in a reset state and has the largest remaining storage space to input data.

2. The reconfigurable multi-range detection endoscope system according to claim 1, characterized in that, The write data rate of the DDR memory is greater than or equal to the input data rate of the multiple shooting modules, the read data rate of the DDR memory is greater than or equal to the output data rate of the two output interfaces, and the data read / write time ratio of the DDR memory is 1:

1.

3. The reconfigurable multi-range detection endoscope system according to claim 1, characterized in that, The input order of the first image data and the output order of the second image data are both row-first, column-second. The input FIFO is provided with a first register, which is configured to record the position where the DDR memory reads the first image data corresponding to the input FIFO; The output FIFO is equipped with a second register, which is configured to record the position where the output FIFO reads the second image data from the DDR memory.

4. The reconfigurable multi-range detection endoscope system according to claim 1, characterized in that, The imaging module includes a CIS chip and a light source, and the FPGA module also has: The IIC communication interface is used to set the parameters of the CIS chip; An I / O interface is used to adjust the brightness of the light source.

5. The reconfigurable multi-range detection endoscope system according to claim 4, characterized in that, A bridge chip is provided between the CIS chip and the LVDS interface. The bridge chip is configured to read the parallel signal output by the CIS chip and convert it into a parallel data signal input to the LVDS interface.

6. The reconfigurable multi-range detection endoscope system according to claim 1, characterized in that, The shooting module includes a first shooting module and a second shooting module. The first shooting module is used to capture the first image data in front, and the second shooting module is used to capture the first image data around.

Images