Data transmission apparatus and data transmission method

Abstract

The disclosure provides a data transmission device and a data transmission method, and relates to the technical field of communication, in particular to the field of chips. The specific implementation scheme is: a master device, comprising a first chip selection interface, the master device is configured to generate a chip selection analog signal value; a plurality of analog-to-digital conversion circuits, the input end of each analog-to-digital conversion circuit is electrically connected with the first chip selection interface respectively, and each analog-to-digital conversion circuit is configured to convert the chip selection analog signal value into a chip selection digital signal value; a plurality of slave devices, each slave device comprises a second chip selection interface, each second chip selection interface is electrically connected with the output end of the analog-to-digital conversion circuit corresponding to the slave device, and each slave device is configured to establish a communication connection with the master device in the case that the chip selection digital signal value received by the second chip selection interface is a valid chip selection digital signal value.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and more particularly to the field of chips. Specifically, it relates to a data transmission device and a data transmission method. Background Technology

[0002] Data transmission between multiple devices can be achieved based on communication protocols. Before data transmission can occur, a communication connection needs to be established between each pair of devices. Communication protocols can include the Serial Peripheral Interface (SPI) protocol or the Inter-Integrated Circuit (IIC) protocol. For example, multiple devices may include a master device and multiple slave devices; data transmission between the master device and the multiple slave devices can be achieved based on the SPI protocol. Summary of the Invention

[0003] This disclosure provides a data transmission device and a data transmission method.

[0004] According to one aspect of this disclosure, a data transmission apparatus is provided, comprising: a master device including a first chip select interface, the master device being configured to generate a chip select analog signal value; a plurality of analog-to-digital conversion circuits, each of the analog-to-digital conversion circuits having an input terminal electrically connected to the first chip select interface, each of the analog-to-digital conversion circuits being configured to convert the chip select analog signal value into a chip select digital signal value; and a plurality of slave devices, each of the slave devices including a second chip select interface, each of the second chip select interfaces being electrically connected to an output terminal of an analog-to-digital conversion circuit corresponding to the slave device, each of the slave devices being configured to establish a communication connection with the master device when the chip select digital signal value received by the second chip select interface is a valid chip select digital signal value.

[0005] According to another aspect of this disclosure, a data transmission method for the data transmission apparatus described above is provided, comprising: a master device generating a chip select analog signal value; each of a plurality of analog-to-digital conversion circuits converting the chip select analog signal value into a chip select digital signal value; and each of a plurality of slave devices establishing a communication connection with the master device when the received chip select digital signal value is a valid chip select digital signal value.

[0006] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0007] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0008] Figure 1 A schematic diagram of the structure of a data transmission device is shown.

[0009] Figure 2A This schematic diagram illustrates the structure of a data transmission apparatus according to an embodiment of the present disclosure;

[0010] Figure 2B A schematic diagram of the structure of a window comparison sub-circuit according to an embodiment of the present disclosure is shown.

[0011] Figure 2C The schematic diagram illustrates the structure of a data transmission apparatus according to an embodiment of the present disclosure when N=5;

[0012] Figure 2D A schematic diagram of the structure of a window comparison sub-circuit according to an embodiment of the present disclosure is shown; and

[0013] Figure 3 A flowchart illustrating a data transmission method according to an embodiment of the present disclosure is shown schematically. Detailed Implementation

[0014] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0015] Multiple devices include a master device and multiple slave devices. Data transmission between the master device and the multiple slave devices can be achieved based on a Serial Peripheral Interface (SPEI) protocol. The SPEI is a high-speed, full-duplex, and synchronous communication bus. Before data transmission between the master device and the multiple slave devices, a communication connection needs to be established between the master device and the slave devices that need to transmit data. In a data transmission device based on the SPEI protocol, the master device and slave devices may include a serial clock (SCK) interface, a master input / slave output (MISO) interface, a master output / slave input (MOSI) interface, and a chip select (NSS) interface. The master device and slave devices can establish a communication connection based on the chip select interfaces of the master device and the slave devices. The chip select interface included in the master device can be referred to as the first chip select interface. The chip select interface included in the slave device can be referred to as the second chip select interface.

[0016] In a data transmission device based on an external network device interface protocol, there may be a master device and multiple slave devices. The following section combines... Figure 1 Taking a master device and three slave devices as an example, the process of establishing a communication connection between the master device and the slave devices is explained.

[0017] Figure 1 A schematic diagram of a data transmission device is shown.

[0018] like Figure 1 As shown, the data transmission device 100 may include a master device 110 and three slave devices. The three slave devices include slave device 1201, slave device 1202, and slave device 1203. The master device 110 includes a first chip select interface 1111, a first chip select interface 1112, and a first chip select interface 1113. Slave device 1201 includes a second chip select interface 1211. Slave device 1202 includes a second chip select interface 1212. Slave device 1203 includes a second chip select interface 1213.

[0019] The first chip select interface 1111 is electrically connected to the second chip select interface 1211. The first chip select interface 1112 is electrically connected to the second chip select interface 1212. The first chip select interface 1113 is electrically connected to the second chip select interface 1213.

[0020] If a communication connection needs to be established between the master device 110 and the slave device 1201, the master device 110 can generate a valid chip select digital signal value. The master device sends the valid chip select digital signal value to the first slave device 1201 through the first chip select interface 1111 and the second chip select interface 1211. Upon receiving the valid chip select digital signal value, the first slave device 1201 establishes a communication connection with the master device 110.

[0021] If the master device 110 needs to establish a communication connection with other slave devices, the same method described above can be used, which will not be repeated here.

[0022] In the aforementioned data transmission device, the number of first chip select interfaces included in the master device can be determined based on the number of slave devices requiring data transmission. That is, the master device needs to have the same number of first chip select interfaces as the number of slave devices to establish communication connections and enable data transmission. This method consumes a significant amount of the master device's interface resources. For master devices with a limited number of interfaces, each interface has limited resources, necessitating the replacement with a master device that has a larger number of interfaces, thus increasing hardware costs.

[0023] To this end, embodiments of this disclosure provide a data transmission apparatus, including a master device, a plurality of analog-to-digital converters (ADCs), and a plurality of slave devices. The master device includes a first chip select interface and is configured to generate a chip select analog signal value. The input terminal of each of the plurality of ADCs is electrically connected to the first chip select interface, and each ADC is configured to convert the chip select analog signal value into a chip select digital signal value. Each of the plurality of slave devices includes a second chip select interface, and each second chip select interface is electrically connected to the output terminal of the ADC corresponding to the slave device. Each slave device is configured to establish a communication connection with the master device when the chip select digital signal value received at the second chip select interface is a valid chip select digital signal value.

[0024] Each analog-to-digital converter (ADC) circuit has its input terminal electrically connected to the first chip select interface of the master device, and its output terminal electrically connected to the second chip select interface of its corresponding slave device. The master device generates a chip select analog signal value and sends it to each ADC circuit through the first chip select interface. Each ADC circuit converts the chip select analog signal value into a chip select digital signal value. If each slave device determines that the received chip select digital signal value is a valid chip select digital signal value that can be enabled, it establishes a communication connection with the master device. This allows all slave devices to establish a communication connection with the master device by sharing a single first chip select interface, thereby reducing hardware costs.

[0025] Figure 2A A schematic diagram of the structure of a data transmission apparatus according to an embodiment of the present disclosure is shown.

[0026] like Figure 2A As shown, the data transmission device 200 may include a master device 210, multiple analog-to-digital conversion circuits 220 and multiple slave devices 230.

[0027] The master device 210 may include a first chip select interface 211.

[0028] The multiple analog-to-digital converter circuits 220 may include N analog-to-digital converter circuits, namely, analog-to-digital converter circuit 2201, analog-to-digital converter circuit 2202, ..., analog-to-digital converter circuit 220. i ...... Analog-to-digital converter circuit 220 N-1 and analog-to-digital converter circuit 220 N The input terminal of analog-to-digital converter 2201 can be 2211, the input terminal of analog-to-digital converter 2202 can be 2212, ..., and the input terminal of analog-to-digital converter 220... i The input terminal can be 221 i , ..., Analog-to-digital converter circuit 220 N-1 The input terminal can be 221 N-1Analog-to-digital converter circuit 220 N The input terminal can be 221 N-1 N is an integer greater than or equal to 2. i∈{1,2,......,N-1,N}.

[0029] Multiple slave devices 230 may include N slave devices, namely, slave device 2301, slave device 2302, ..., slave device 230i, ..., slave device 230 N-1 and from device 230 N Slave device 2301 may include a second chip select interface 2311, slave device 2302 may include a second chip select interface 2312, ..., slave device 230 i It may include a second chip select interface 231 i ..., from device 230 N-1 It may include a second chip select interface 231 N-1 and from device 230 N It may include a second chip select interface 231 N .

[0030] The master device 210 can be configured to generate chip select analog signal values.

[0031] Analog-to-digital converter circuit 220 i Input terminal 221 i Electrically connected to the first chip select interface 211. Analog-to-digital converter circuit 220 i It is configured to convert the chip select analog signal value to the chip select digital signal value.

[0032] From equipment 230 i Second chip select interface 231 i and from equipment 230 i The corresponding analog-to-digital converter circuit 220 i The output terminal is electrically connected. From device 230. i Configured to use the second chip select interface 231 i If the received chip select digital signal value is a valid chip select digital signal value, establish a connection with the master device 220. i Communication connections between them.

[0033] According to embodiments of this disclosure, each slave device has an analog-to-digital conversion circuit corresponding to that slave device. For example, slave device 230 i With analog-to-digital converter circuit 220 i Correspondingly, the first chip select interface 211 can be used as an enable slave device 230. i The interface.

[0034] According to embodiments of this disclosure, during each communication connection establishment process between a slave device and a master device 210, one slave device can establish a communication connection with the master device 210, while none of the slave devices 230 other than the one already connected to the master device 210 can establish a communication connection with the master device 210. Based on whether a slave device can establish a communication connection with the master device 210 during each communication connection process, the multiple slave devices 230 can be divided into a target slave device and at least one other slave device. The target slave device can refer to the slave device 230 that is currently able to establish a communication connection with the master device 210. Other slave devices can refer to the slave devices 230 that are currently unable to establish a communication connection with the master device 210. The slave device establishing a communication connection with the master device 210 each time can be different; therefore, the target slave device determined each time can be different. That is, each slave device can be a target slave device.

[0035] According to embodiments of this disclosure, the master device 210 can generate a chip select analog signal value for selecting a target slave device from a plurality of slave devices 230 based on a preset chip select rule. The master device 210 may include means capable of generating the chip select analog signal value. For example, the master device 210 may include a digital-to-analog converter (DAC). That is, the DAC generates the chip select analog signal value based on a preset digital signal value according to the preset chip select rule. For example, the master device 210 may include a pulse width modulation (PWM) unit and a filtering unit. The PWM unit generates a pulse width modulation (PWM) signal value based on the preset chip select rule. The filtering unit converts the PWM signal value into a chip select analog signal value.

[0036] According to embodiments of this disclosure, during each communication connection establishment process between the master device 110 and a target slave device among the plurality of slave devices 130, the master device 201 generates a chip select analog signal value according to a preset chip select rule, which ensures that the number of target slave devices determined from the plurality of slave devices 230 is one. The chip select analog signal value may refer to the amplitude value of the chip select analog signal. The chip select analog signal value may include a chip select analog voltage signal value. The preset chip select rule can be used as a rule for the master device 210 to select which slave device among the plurality of slave devices 230 as the target slave device for data transmission with the target slave device.

[0037] According to embodiments of this disclosure, the preset chip select rule can be determined as follows: N chip select analog signal values ​​are determined. A one-to-one mapping relationship is established between the chip select signal values ​​and the slave devices. For example, the N chip select analog signal values ​​may include chip select analog signal value C1, chip select analog signal value C2, ..., chip select analog signal value C... i ..., Chip select analog signal value C N-1 And the chip select analog signal value CN The chip select analog signal value corresponds one-to-one with the slave device, that is, slave device 230. i It has the corresponding chip select analog signal value C i .

[0038] According to embodiments of this disclosure, the preset chip select rule can also be determined by determining N analog signal value ranges. A one-to-one mapping relationship is established between the analog signal value ranges and the slave devices. For example, the N analog signal value ranges may include analog signal value range Cr1, analog signal value range C... r2 The range of analog signal values ​​C ri The range of analog signal values ​​C rN-1 and analog signal value range Cr N The analog signal value range corresponds one-to-one with the slave device, that is, slave device 230. i It has the corresponding analog signal value range C ri If the chip select analog signal value belongs to the corresponding analog signal value range, then a mapping relationship can be established between the chip select analog signal value and the slave device corresponding to the analog signal value range C. ri Chip select analog signal value C i With device 230 i The mapping relationship between them.

[0039] According to embodiments of this disclosure, analog-to-digital conversion circuit 220 i This can refer to the ability to realize the chip select analog signal value C i An analog-to-digital converter circuit that converts the chip select digital signal value. Analog-to-digital converter circuit 220 i The circuit can be based on the window comparator principle, or it can be based on other principles; no limitation is made here. The chip select digital signal value can include a valid chip select digital signal value and a invalid chip select digital signal value. A valid chip select digital signal value can refer to a chip select digital signal value that enables the slave device. An invalid chip select digital signal value can refer to a chip select digital signal value that does not enable the slave device. The analog-to-digital converter (ADC) circuit that can convert the chip select analog signal value into a valid chip select digital signal value can be called the target ADC circuit. Any ADC circuit other than the target ADC circuit among the multiple ADC circuits 120 can be called the other ADC circuit. During each communication connection establishment process between the master device 110 and the target slave device among the multiple slave devices 130, the master device 110 generates a chip select analog signal value according to a preset chip select rule, so that the ADC circuit corresponding to the target slave device can convert the chip select analog signal value into a valid chip select digital signal value, while the ADC circuit corresponding to any other slave device can convert the chip select analog signal value into an invalid chip select digital signal value.

[0040] According to embodiments of this disclosure, the master device 210 needs to transmit data with the i=jth slave device, i.e., with the slave device 230. j Data transmission is performed. From device 230 j This refers to the target slave device. Prior to this, the master device 210 needs to establish a connection with the slave device 230. j The communication connection between them. The master device 210 can generate a chip select analog signal value C according to a preset chip select rule. j Analog-to-digital converter circuits 2201 to 220 N Each analog-to-digital converter circuit in the circuit receives the chip select analog signal value C through the first chip select interface 211. j Next, the chip select analog signal value C j Convert to the corresponding chip select digital signal value. (This is related to the slave device 230.) j The corresponding analog-to-analog converter circuit 220 j The chip select analog signal value C j Converted to a valid chip select digital signal value, except for the analog-to-analog converter 220. j Any other analog-to-digital converter circuit 220 i The chip select analog signal value C j Converted to a non-active chip select digital signal value. Analog-to-analog converter circuit 220 j This is the target analog-to-digital conversion circuit. From device 2301 to slave device 230... N After each slave device receives the chip select digital signal value through the second chip select interface corresponding to the slave device, slave device 230 j The received chip select digital signal value is a valid chip select digital signal value, except for the slave device 230. j Any chip select digital signal value received from the device other than the specified value is a invalid chip select digital signal value. Therefore, the chip select digital signal value received from the device 230 is invalid. j A communication connection can be established with the master device 210, except for the slave device 230. j No other slave device has established a communication connection with master device 210.

[0041] According to embodiments of this disclosure, the input terminal of each analog-to-digital converter (ADC) is electrically connected to the first chip select interface of the master device, and the output terminal of each ADC is electrically connected to the second chip select interface of its corresponding slave device. The master device generates a chip select analog signal value and sends the chip select analog signal value to each ADC through the first chip select interface. Each ADC converts the chip select analog signal value into a chip select digital signal value. If each slave device determines that the received chip select digital signal value is a valid chip select digital signal value that can be enabled, it establishes a communication connection with the master device. This enables all slave devices to establish a communication connection with the master device by sharing a single first chip select interface, thereby reducing hardware costs.

[0042] The following is for reference. Figures 2B to 2D The data transmission apparatus described in accordance with the embodiments of this disclosure will be further described.

[0043] Figure 2B A schematic diagram of the structure of a window comparison sub-circuit according to an embodiment of the present disclosure is shown.

[0044] like Figure 2B As shown, analog-to-digital converter circuit 220 i It may include window comparator sub-circuit 222 i Window comparator circuit 222 i It can include input terminal 2220 i and output terminal 2221 i Input terminal 2220 i Electrically connected to the first chip select interface 211 of the main device 210. Output terminal 2221 i With device 230 i Second chip select interface 231 i Electrical connection. Input terminal 2220 i The number can include two.

[0045] Window comparator circuit 222 i It can be configured to: in window comparator subcircuit 222 i Input terminal 2220 i The received chip select analog signal value is greater than that of the window comparator circuit 222 i When the corresponding first reference analog signal value is less than the second reference analog signal value, a valid chip select digital signal value is generated. The valid chip select digital signal value is used to characterize the chip select digital signal value of the first level.

[0046] In window comparison subcircuit 222 i Input terminal 2220 iIf the received chip select analog signal value is less than or equal to the first reference analog signal value or greater than or equal to the second reference analog signal value, an invalid chip select digital signal is generated. The invalid chip select digital signal value is used to characterize the second level chip select digital signal value.

[0047] According to embodiments of this disclosure, each of the plurality of analog-to-digital converter (ADC) circuits 220 may include a window comparison sub-circuit. Each window comparison sub-circuit operates on the same principle. Each window comparison sub-circuit has a first reference analog signal value and a second reference analog signal value corresponding to that window comparison sub-circuit. Each slave device has an ADC circuit corresponding to it. Therefore, each slave device has a first reference analog signal value and a second reference analog signal value corresponding to that slave device. The first reference analog signal value may be less than the second reference analog signal value. The first and second reference analog signal values ​​can be used as the basis for the window comparison sub-circuit to convert the received chip select analog signal value into a valid chip select digital signal value or an invalid chip select digital signal value.

[0048] According to embodiments of this disclosure, the level form of the first level and the second level can be determined based on the level required to enable the slave device. For example, if the slave device's enable signal is high, the first level can be high and the second level can be low. If the slave device's enable signal is low, the first level can be low and the second level can be high. A valid chip select digital signal value represents a chip select digital signal value that enables the slave device; that is, a valid chip select digital signal value represents a chip select digital signal value with a level of the first level. A invalid digital signal value represents a chip select digital signal value that does not enable the slave device; that is, a invalid chip select digital signal value represents a chip select digital signal value with a level of the second level.

[0049] According to embodiments of this disclosure, for each of the plurality of window comparison sub-circuits, if the chip select analog signal value received at the input terminal of the window comparison sub-circuit is greater than a first reference analog signal value and less than a second reference analog signal value, then the window comparison sub-circuit can generate a valid chip select digital signal value. If the chip select analog signal value is less than or equal to the first reference analog signal value or greater than or equal to the second reference analog signal value, then the window comparison sub-circuit can generate an invalid chip select digital signal value. The first reference analog signal value and the second reference analog signal value can form a range of analog signal values. The ranges of analog signal values ​​of different window comparison sub-circuits are different from each other. Therefore, during each process of establishing a communication connection between a slave device and the master device 210, it can be guaranteed that the chip select digital signal value corresponding to one slave device is a valid chip select digital signal value, while the chip select digital signal value corresponding to any other slave device is an invalid chip select digital signal value. Thus, it is possible to realize that a slave device establishes a communication connection with the master device 210. The slave device that establishes a communication connection with the master device 210 mentioned here is the target slave device described above.

[0050] Figure 2C The schematic diagram illustrates the structure of a data transmission apparatus according to an embodiment of the present disclosure when N=5.

[0051] like Figure 2C As shown, it includes a master device 210, five window comparison sub-circuits, and five slave devices. The five window comparison sub-circuits include window comparison sub-circuit 2221, window comparison sub-circuit 2222, window comparison sub-circuit 2223, window comparison sub-circuit 2224, and window comparison sub-circuit 2225. The five slave devices include slave device 2301, slave device 2302, slave device 2303, slave device 2304, and slave device 2305.

[0052] Window comparator subcircuit 2221 includes input terminal 22201 and output terminal 22211. Window comparator subcircuit 2222 includes input terminal 22202 and output terminal 22212. Window comparator subcircuit 2223 includes input terminal 22203 and output terminal 22213. Window comparator subcircuit 2224 includes input terminal 22204 and output terminal 22214. Window comparator subcircuit 2225 includes input terminal 22205 and output terminal 22215.

[0053] Slave device 2301 includes a second chip select interface 2311. Slave device 2302 includes a second chip select interface 2312. Slave device 2303 includes a second chip select interface 2313. Slave device 2304 includes a second chip select interface 2314. Slave device 2305 includes a second chip select interface 2315.

[0054] The first chip select interface 211 is electrically connected to input terminals 22201, 22202, 22203, 22204, and 22205, respectively. Output terminal 22211 is electrically connected to the second chip select interface 2311. Output terminal 22212 is electrically connected to the second chip select interface 2312. Output terminal 22213 is electrically connected to the second chip select interface 2313. Output terminal 22214 is electrically connected to the second chip select interface 2314. Output terminal 22215 is electrically connected to the second chip select interface 2315.

[0055] The first reference analog signal value corresponding to slave device 2301 and window comparator subcircuit 2221 can be 0V, the second reference analog signal value can be 1V, and the chip select analog signal value can be 0.5V. The first reference analog signal value corresponding to slave device 2302 and window comparator subcircuit 2222 can be 1V, the second reference analog signal value can be 2V, and the chip select analog signal value can be 1.5V. The first reference analog signal value corresponding to slave device 2303 and window comparator subcircuit 2223 can be 2V, the second reference analog signal value can be 3V, and the chip select analog signal value can be 2.5V. The first reference analog signal value corresponding to slave device 2304 and window comparator subcircuit 2224 can be 3V, the second reference analog signal value can be 4V, and the chip select analog signal value can be 3.5V. The first reference analog signal value corresponding to slave device 2305 and window comparator subcircuit 2225 can be 4V, the second reference analog signal value can be 5V, and the chip select analog signal value can be 4.5V.

[0056] For example, master device 210 needs to transmit data with slave device 2301. Before this, master device 210 needs to establish a communication connection with slave device 2301. Master device 210 can generate a chip select analog signal value of 0.5V.

[0057] For the window comparator circuit 2221, the chip select analog signal value 0.5V received at the input terminal 22201 of the window comparator circuit 2221 is greater than the first reference analog signal value 0V corresponding to the window comparator circuit and less than the second reference analog signal value 1V. Therefore, the window comparator circuit 2221 generates a valid chip select digital signal value.

[0058] For the window comparator circuit 2222, the chip select analog signal value of 0.5V received at the input terminal 22202 of the window comparator circuit 2222 is less than the first reference analog signal value of 1V corresponding to the window comparator circuit 2222. Therefore, the window comparator circuit 2222 generates an invalid chip select digital signal value.

[0059] Based on the same method described above, it can be obtained that window comparator circuits 2223, 2224, and 2225 all generate invalid chip select digital signal values, which will not be elaborated here.

[0060] Figure 2D A schematic diagram of the structure of a window comparison sub-circuit according to an embodiment of the present disclosure is shown.

[0061] like Figure 2D As shown, the window comparator sub-circuit 222 i It may include a first comparator 2222 i Second comparator 2223 i and voltage limiting unit 2224 i .

[0062] First comparator 2222 i It may include the first non-inverting input terminal 2222 i+ First inverting input terminal 2222 i- and output terminal 2222 io First inverting input 2222 i- Electrically connected to the first chip select interface 211. First non-inverting input terminal 2222 i+ Used to input the first reference analog signal value corresponding to the window comparator sub-circuit 222i.

[0063] Second comparator 2223 i It may include a second non-inverting input 2223 i+ Second inverting input terminal 2223 i- and output terminal 2223 io The second non-inverting input terminal 2223 i+ Electrically connected to the first chip select interface 211. Second inverting input terminal 2223. i- Used to input the second reference analog signal value corresponding to the window comparator sub-circuit.

[0064] Voltage limiting unit 2224 i It may include the first input terminal 2224 i1 Second input terminal 2224 i2 and output terminal 2224 io First input terminal 2224 i1 With the output terminal 2222 of the first comparator io Electrical connection. Second input terminal 2224 i2 With the second comparator 2223 io The output terminal is electrically connected. Output terminal 2224 io Interface 231 with the second chip select i Electrical connection.

[0065] Voltage limiting unit 2224 i Configured according to the first comparator 2222 i The output value and the second comparator 2223 i The output value generates a valid chip select digital signal value or a invalid chip select digital signal value.

[0066] According to embodiments of this disclosure, voltage limiting unit 2224 i It may include at least one of transistors, switching elements, and logic gate elements. Voltage limiting unit 2224 i It can be used to implement the first comparator 2222 i The output value and the second comparator 2223 i The output value generates a valid chip select digital signal value or a invalid chip select digital signal value.

[0067] According to embodiments of this disclosure, if the chip select analog signal value is greater than the first reference analog signal value and less than the second reference analog signal value, then the first comparator 2222 i The output value of the second comparator 2223 is low. i The output value is low. When the first level is low, the voltage limiting unit 2224... i It needs to be able to implement the first comparator 2222 i The low level of the output and the second comparator 2223 i The output low level generates a low level. When the first level is high, the voltage limiting unit 2224... i It needs to be able to implement the first comparator 2222 i The low level of the output and the second comparator 2223 i A low output level generates a high level.

[0068] According to embodiments of this disclosure, the first inverting input terminal 2222 can also be used. i+ Electrically connected to the first chip select interface 211. First inverting input terminal 2222 i- Subcircuit 222 for input and window comparison i The corresponding first reference analog signal value. Second inverting input terminal 2223 i- Electrically connected to the first chip select interface 211. Second non-inverting input terminal 2223. i+ This is used to input the second reference analog signal value corresponding to the window comparator sub-circuit. Ensure that the input terminal electrically connected to the first chip select interface 211 is a common input terminal and an inverting input terminal.

[0069] According to embodiments of this disclosure, voltage limiting unit 2224 i It may include a first switching element, a second switching element, and a transistor.

[0070] One end of the first switching element is connected to the first comparator 2222 i The output terminal is electrically connected.

[0071] One end of the second switching element is connected to the second comparator 2223 i The output terminal is electrically connected.

[0072] The transistor is configured to output a valid chip select digital signal value when the transistor is in the off state, and to output a invalid chip select digital signal value when the transistor is in the saturation state.

[0073] According to embodiments of this disclosure, the switching element can be a component capable of performing a switching function. The switching element may include a diode. The first switching element may be a first diode. The second switching element may be a second diode. The transistor may include a bipolar transistor or a field-effect transistor. The bipolar transistor may include a PNP type transistor or an NPN type transistor. The field-effect transistor may include an enhancement-mode field-effect transistor or a depletion-mode field-effect transistor.

[0074] According to embodiments of this disclosure, the first switching element may be a first diode, and one end of the first switching element may be either a positive terminal or a negative terminal. The second switching element may be a second diode, and one end of the second switching element may be either a positive terminal or a negative terminal.

[0075] For example, the first switching element can be a first diode. The second switching element can be a second diode. The transistor can be an NPN transistor. Voltage limiting unit 2224 i It may also include a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, a third diode, a fourth diode, a fifth diode, and a sixth diode.

[0076] The positive terminal of the first diode is connected to the first comparator 2222. i The output terminal is electrically connected. The negative terminal of the first diode is electrically connected to one end of the first resistor.

[0077] The positive terminal of the second diode is connected to the second comparator 2223. i The output terminal of the first diode is electrically connected. The negative terminal of the second diode is electrically connected to one end of the first resistor.

[0078] The other end of the first resistor is electrically connected to one end of the second resistor and the base of the NPN transistor. The other end of the second resistor is connected to the emitter and collector of the NPN transistor. The collector of the NPN transistor is connected to the second chip select interface 231. i One end of the third resistor is electrically connected to the power supply. The other end of the third resistor is electrically connected to the power source.

[0079] One end of the fourth resistor is connected to the first non-inverting input terminal 2222. i+ The positive terminal of the third diode and the reverse terminal of the fourth diode are electrically connected. The other end of the fourth resistor is used to input the first reference analog signal value.

[0080] The negative terminal of the third diode is connected to the first inverting input terminal 2222. i- The positive terminal of the fourth diode is electrically connected to one end of the fifth resistor. The other end of the fifth resistor is electrically connected to the first chip select interface 211 and the other end of the sixth resistor. The other end of the sixth resistor is electrically connected to the second non-inverting input terminal 2223. i+ The positive terminal of the fifth diode and the negative terminal of the sixth diode are electrically connected.

[0081] One end of the seventh resistor is connected to the second inverting input terminal 2223. i- The negative terminal of the fifth diode and the positive terminal of the sixth diode are electrically connected. The other end of the seventh resistor is used to input the second reference analog signal value.

[0082] For example, if the chip select analog signal value is greater than the first reference analog signal value and less than the second reference analog signal value, then the first comparator 2222 i The output value of the second comparator 2223 is low. i The output value is low, so both the first and second diodes are reverse-biased and cut off. The NPN transistor is in the cut-off state and outputs a valid chip select digital signal value.

[0083] If the chip select analog signal value is less than or equal to the first reference analog signal value, then the first comparator 2222 i The output value of the second comparator 2223 is high. i The output value is low. Therefore, the first diode is forward-biased, the second diode is reverse-biased, the NPN transistor is in saturation, and the output is a non-valid chip select digital signal value.

[0084] If the chip select analog signal value is greater than or equal to the second reference analog signal value, then the first comparator 2222 i The output value of the second comparator 2223 is low. i The output value is high. Therefore, the first diode is reverse-biased and the second diode is forward-biased, the NPN transistor is in saturation, and the output is a non-valid chip select digital signal value.

[0085] For example, the first switching element could be a seventh diode. The second switching element could be an eighth diode. Voltage limiting unit 2224 i It may also include an eighth resistor, a ninth resistor, and a ninth diode. The ninth diode can be a Zener diode.

[0086] The positive terminal of the seventh diode is connected to the first comparator 2222 i The output terminal of the seventh diode is electrically connected. The negative terminal of the seventh diode is electrically connected to one end of the eighth resistor.

[0087] The positive terminal of the eighth diode is connected to the second comparator 2223 i The output terminal of the eighth diode is electrically connected. The negative terminal of the eighth diode is electrically connected to one end of the eighth resistor.

[0088] The other end of the eighth resistor is connected to the second chip select interface 231. i One end of the ninth resistor is electrically connected to the negative terminal of the ninth diode. The other end of the ninth resistor is electrically connected to the positive terminal of the ninth diode.

[0089] According to embodiments of this disclosure, voltage limiting unit 2224 i It can include logic gate circuits.

[0090] For example, if the chip select analog signal value is greater than the first reference analog signal value and less than the second reference analog signal value, then the first comparator 2222 i The output value of the second comparator 2223 is low. i The output value is low, therefore, both the first heptode and the eighth diode are reverse-biased and the output is a valid chip select digital signal value.

[0091] If the chip select analog signal value is less than or equal to the first reference analog signal value, then the first comparator 2222 i The output value of the second comparator 2223 is high. i The output value is low. Therefore, the seventh diode is forward-biased, the eighth diode is reverse-biased, and the output is a non-valid chip select digital signal value.

[0092] If the chip select analog signal value is greater than or equal to the second reference analog signal value, then the first comparator 2222 i The output value of the second comparator 2223 is low. i The output value is high. Therefore, the seventh diode is reverse-biased and the eighth diode is forward-biased, resulting in an invalid chip select digital signal value.

[0093] The first input of the logic gate element and the first comparator 2222 i The output terminal is electrically connected, and the second input terminal of the logic gate element is connected to the second comparator 2223. i The output terminal is electrically connected.

[0094] According to embodiments of this disclosure, logic gate elements may include OR gate elements or NOR gate elements.

[0095] For example, the first switching element 2224i3 It could be the ninth diode. The second switching element is 2224. i4 It can be the tenth diode. If the chip select analog signal value is greater than the first reference analog signal value and less than the second reference analog signal value, then the first comparator 2222... i The output value of the second comparator 2223 is low. i The output value is low. If the chip select analog signal value is less than or equal to the first reference analog signal value, then the first comparator 2222... i The output value of the second comparator 2223 is high. i The output value is low. If the chip select analog signal value is greater than or equal to the second reference analog signal value, then the first comparator 2222... i The output value of the second comparator 2223 is low. i The output value is high. When the first level is low, the logic gate element can be an OR gate element. When the first level is high, the logic gate element can be a NOR gate element.

[0096] According to embodiments of this disclosure, the main device 210 may include a digital-to-analog converter.

[0097] The digital-to-analog converter is configured to generate a chip select analog signal value based on a preset chip select rule and a preset digital signal value.

[0098] According to embodiments of this disclosure, a preset chip select rule can be used as a rule for the master device 210 to select which of a plurality of slave devices 230 is the target slave device for data transmission with the target slave device. The digital-to-analog converter can convert a preset digital signal value into a chip select analog signal value based on the preset chip select rule.

[0099] According to embodiments of this disclosure, the main device 210 may include a pulse width modulation unit and a filtering unit.

[0100] The pulse width modulation unit is configured to generate a pulse width modulation signal value based on a preset chip select rule. The filtering unit is configured to convert the pulse width modulation signal value into a chip select analog signal value.

[0101] According to embodiments of this disclosure, a pulse width modulation (PWM) unit can generate a PWM signal value corresponding to a chip select analog signal value based on a preset chip select rule, and then use a filtering unit to convert the PWM signal value into a chip select analog signal value. The filtering unit may include an RC filtering unit.

[0102] Figure 3 A flowchart illustrating a data transmission method according to an embodiment of the present disclosure is shown schematically.

[0103] like Figure 3As shown, the method 300 includes operations S310 to S330.

[0104] Operate S310 to generate a chip select analog signal value.

[0105] By operating the S320, each of the multiple analog-to-digital converters converts the chip select analog signal value into a chip select digital signal value.

[0106] In operation S330, each of the multiple slave devices establishes a communication connection with the master device if the received chip select digital signal value is a valid chip select digital signal value.

[0107] According to embodiments of this disclosure, the methods described in these embodiments can be applied to the data transmission apparatus described in these embodiments.

[0108] According to embodiments of this disclosure, each analog-to-digital converter circuit includes a window comparator sub-circuit.

[0109] According to embodiments of this disclosure, operation S320 may include the following operations.

[0110] Each of the multiple window comparator subcircuits generates a valid chip select digital signal value when the received chip select analog signal value is greater than the first reference analog signal value corresponding to the window comparator subcircuit and less than the second reference analog signal value. The valid chip select digital signal value represents the first level of the chip select digital signal value. If the received chip select analog signal value is less than or equal to the first reference analog signal value or greater than or equal to the second reference analog signal value, an invalid chip select digital signal value is generated. The invalid chip select digital signal value represents the second level of the chip select digital signal value.

[0111] According to embodiments of this disclosure, the main device may include a digital-to-analog conversion unit.

[0112] According to embodiments of this disclosure, operation S310 may include the following operations.

[0113] The digital-to-analog converter generates a chip select analog signal value based on a preset chip select rule and a preset digital signal value.

[0114] According to embodiments of this disclosure, the main device may include a pulse width modulation unit and a filtering unit.

[0115] According to embodiments of this disclosure, operation S310 may include the following operations.

[0116] The pulse width modulation unit generates a pulse width modulation signal value based on a preset chip select rule. The filtering unit converts the pulse width modulation signal value into a chip select analog signal value.

[0117] The above are merely exemplary embodiments, but are not limited thereto. Other data transmission methods known in the art may also be included, as long as they enable all slave devices to share a single first chip select interface to achieve communication connections with the master device.

[0118] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0119] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A data transmission device, comprising: A master device, including a first chip select interface, is configured to generate a chip select analog signal value; Multiple analog-to-digital converter circuits, each of which has its input terminal electrically connected to the first chip select interface, and each of which is configured to convert the chip select analog signal value into a chip select digital signal value; as well as Multiple slave devices, each slave device including a second chip select interface, each second chip select interface being electrically connected to the output terminal of an analog-to-digital converter circuit corresponding to the slave device, each slave device being configured to establish a communication connection with the master device when the chip select digital signal value received by the second chip select interface is a valid chip select digital signal value; Each analog-to-digital converter circuit includes: A window comparator circuit is configured to generate a valid chip select digital signal value when the chip select analog signal value received at the input of the window comparator circuit is greater than a first reference analog signal value corresponding to the window comparator circuit and less than a second reference analog signal value. The valid chip select digital signal value is used to characterize a first level chip select digital signal value. The window comparison sub-circuit includes: The first comparator includes a first non-inverting input and a first inverting input. The first inverting input is electrically connected to the first chip select interface. The first non-inverting input is used to input a first reference analog signal value corresponding to the window comparator sub-circuit. The second comparator includes a second non-inverting input and a second inverting input. The second non-inverting input is electrically connected to the first chip select interface, and the second inverting input is used to input a second reference analog signal value corresponding to the window comparator sub-circuit. A voltage limiting unit is provided, wherein a first input terminal of the voltage limiting unit is electrically connected to the output terminal of the first comparator, a second input terminal of the voltage limiting unit is electrically connected to the output terminal of the second comparator, and the output terminal of the voltage limiting unit is electrically connected to the second chip select interface of the slave device. The voltage limiting unit is configured to generate the valid chip select digital signal value based on the output value of the first comparator and the output value of the second comparator.

2. The apparatus according to claim 1, wherein, The window comparator subcircuit is further configured to generate an invalid chip select digital signal value when the chip select analog signal value received at the input of the window comparator subcircuit is less than or equal to the first reference analog signal value or greater than or equal to the second reference analog signal value, wherein the invalid chip select digital signal value is used to characterize the chip select digital signal value of the second level.

3. The apparatus according to claim 2, wherein, The voltage limiting unit is further configured to generate the invalid chip select digital signal value based on the output value of the first comparator and the output value of the second comparator.

4. The apparatus according to claim 3, wherein, The voltage limiting unit includes: A first switching element, one end of which is electrically connected to the output terminal of the first comparator; A second switching element, one end of which is electrically connected to the output terminal of the second comparator; and A transistor configured to output the valid chip select digital signal value when the transistor is in a cutoff state, and to output the invalid chip select digital signal value when the transistor is in a saturated state.

5. The apparatus according to claim 3, wherein, The voltage limiting unit includes: A logic gate element, wherein the first input terminal of the logic gate element is electrically connected to the output terminal of the first comparator, and the second input terminal of the logic gate element is electrically connected to the output terminal of the second comparator.

6. The apparatus according to any one of claims 1 to 5, wherein, The main device includes: A digital-to-analog converter is configured to generate the chip select analog signal value based on a preset digital signal value according to a preset chip select rule.

7. The apparatus according to any one of claims 1 to 5, wherein, The main device includes: A pulse width modulation unit, configured to generate a pulse width modulation signal value based on a preset chip select rule; and A filtering unit configured to convert the pulse width modulation signal value into the chip select analog signal value.

8. A data transmission method for use in any one of the data transmission apparatuses of claims 1 to 7, comprising: The master device generates the chip select analog signal value; Each of the plurality of analog-to-digital converter circuits converts the chip select analog signal value into a chip select digital signal value; as well as Each of the multiple slave devices establishes a communication connection with the master device when the received chip select digital signal value is a valid chip select digital signal value.

9. The method according to claim 8, wherein, Each of the aforementioned analog-to-digital conversion circuits includes a window comparator sub-circuit; Each of the plurality of analog-to-digital conversion circuits converts the chip select analog signal value into a chip select digital signal value, including: Each of the plurality of window comparator subcircuits generates the valid chip select digital signal value when the received chip select analog signal value is greater than a first reference analog signal value corresponding to the window comparator subcircuit and less than a second reference analog signal value, wherein the valid chip select digital signal value is used to characterize a first level chip select digital signal value; and If the received chip select analog signal value is less than or equal to the first reference analog signal value or greater than or equal to the second reference analog signal value, an invalid chip select digital signal value is generated, wherein the invalid chip select digital signal value is used to characterize the chip select digital signal value of the second level.

10. The method according to claim 8 or 9, wherein, The main equipment includes a digital-to-analog conversion unit; The master device generates a chip select analog signal value, including: The digital-to-analog conversion unit generates the chip select analog signal value based on a preset chip select rule and a preset digital signal value.

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