High-speed SPI bus interface for portability across electrical domains

Abstract

A high-speed SPI bus interface with portability across electrical domains is provided in the disclosed embodiments, belonging to the field of circuit electronics. The universal SPI bus interface across electrical domains has two additional signals, SCSN and SCLK, compared to a typical four-wire SPI bus interface. After communication occurs, the SPI slave device generates SCLK while completing the MISO shift output based on MCLK. MISO and SCLK are simultaneously input to the SPI master device through an isolation chip. The SPI master device then completes the shift acquisition of MISO based on the rising edge of SCLK, effectively eliminating the impact of the transmission delay of the isolator chip, improving the transmission rate between master and slave SPI devices, enabling cross-platform porting, and significantly improving the universality of the SPI bus.

Description

Technical Field

[0001] The present invention relates to the field of circuit electronic technology, and in particular to a high-speed SPI bus interface with portability across electrical domains. Background Art

[0002] The SPI bus is a commonly used standard serial bus interface with the characteristics of simple structure, small pin and logic resource occupation, and high flexibility. It is often used in CCDL scenarios between processors across electrical domains. Currently, the traditional SPI bus interface across electrical domains has two main problems:

[0003] (1) The transmission delay of the isolator results in a low SPI bus interface rate across electrical domains, which seriously affects the bandwidth of the CCDL between processors;

[0004] (2) Isolators vary in type, and transmission delays range from tens of nanoseconds to dozens of nanoseconds, resulting in poor portability of SPI bus control logic across platforms.

[0005] Therefore, in order to solve the problems of low speed and poor portability of SPI bus interface across electrical domains, it is of great significance to design a high-speed SPI bus interface that is portable across electrical domains and improve the communication speed and versatility of the SPI bus interface. Summary of the Invention

[0006] In view of this, the present invention provides a high-speed SPI bus interface that is portable across electrical domains, which at least partially solves the problems of low communication rate and versatility of the SPI bus interface in the prior art during data interaction.

[0007] A high-speed SPI bus interface with portability across electrical domains, suitable for data exchange between SPI master devices and SPI slave devices, including the MCSN, MCLK, MOSI, and MISO signals of the four-wire SPI bus and the SCSN and SCLK signals, among which:

[0008] After the SPI bus transmission starts, the SPI master device sets the chip select signal MCSN to low, and the SPI master device outputs the SPI bus clock signal MCLK. The SPI master device shifts and outputs the SPI serial data signal MOSI at the falling edge of MCLK. The SPI slave device shifts and collects the SPI serial data signal MOSI at the rising edge of MCLK. The SPI slave device generates and outputs SCLK based on MCLK, and shifts and outputs the SPI serial data signal MISO at the falling edge of SCLK.

[0009] After the SPI slave device finishes outputting the SPI bus, it sets SCSN to high. The SPI master device shifts and collects the SPI serial data signal MISO at the rising edge of SCLK. After collecting the rising edge of SCSN, the SPI master device sets MCSN to high, and the SPI bus transmission ends.

[0010] Beneficial effects:

[0011] The universal SPI bus interface across electrical domains has two more signals, SCSN and SCLK, than the typical four-wire SPI bus interface. After communication occurs, the SPI slave device generates the SCLK signal based on the MCLK signal, and shifts the output MISO signal at the same time. The SPI master device shifts and collects the MISO signal at the rising edge of the SCLK signal, effectively eliminating the influence of the transmission delay of the isolator chip, improving the transmission rate between the master and slave SPI devices, and realizing cross-platform transplantation, which significantly improves the universality of the SPI bus and can be widely used in the industrial field. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0013] Figure 1 This is a typical four-wire SPI bus interface architecture diagram;

[0014] Figure 2 The diagram shows the architecture of a high-speed SPI bus interface that is portable across electrical domains. DETAILED DESCRIPTION

[0015] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0016] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0017] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on this disclosure, it should be understood by those skilled in the art that an aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement an apparatus and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein can be used to implement this apparatus and / or practice this method.

[0018] like Figure 2 The high-speed SPI bus interface with cross-electrical domain portability shown in the figure is suitable for data exchange between SPI master devices and SPI slave devices. It includes the MCSN, MCLK, MOSI, and MISO signals of the four-wire SPI bus and the SCSN and SCLK signals. That is, the SCSN and SCLK signals are additionally provided in a typical four-wire SPI bus interface, where:

[0019] After the SPI bus transmission starts, the SPI master sets the chip select signal MCSN to low, and the SPI master outputs the SPI bus clock signal MCLK. The SPI master shifts and outputs the SPI serial data signal MOSI at the falling edge of MCLK. The SPI slave shifts and collects the SPI serial data signal MOSI at the rising edge of MCLK. The SPI slave generates and outputs SCLK based on MCLK, and shifts and outputs the SPI serial data signal MISO at the falling edge of SCLK.

[0020] After the SPI slave device finishes outputting the SPI bus, it sets SCSN to high. The SPI master device shifts and collects the SPI serial data signal MISO at the rising edge of SCLK. After collecting the rising edge of SCSN, the SPI master device sets MCSN to high, and the SPI bus transmission ends.

[0021] The method of the present invention is more suitable for situations where there is an isolator, such as Figure 2 As shown in FIG, the SCSN signal and the SCLK signal are generated and output by the SPI slave device and input to the SPI master device after passing through the isolator.

[0022] As a specific implementation provided in this case, at the beginning of an SPI bus transmission, the SPI master sets the MCSN signal low. Upon detecting the rising edge of the SCSN signal, the SPI master sets the MCSN signal high. Upon detecting the falling edge of the MCSN signal, the SPI slave sets the SCSN signal low. After the MISO shift output is complete, the SPI slave sets the SCSN signal high.

[0023] As a specific implementation provided in this case, the SPI slave device outputs the SCLK signal based on the MCLK signal. When the SPI slave device detects the rising edge of the MCLK signal, the SCLK signal is set to high, and when the SPI slave device detects the falling edge of the MCLK signal, the SCLK signal is set to low.

[0024] As a specific implementation method provided in this case, the SPI slave device shifts and outputs the MISO signal at the falling edge of the SCLK signal, and the SPI master device shifts and collects the MISO signal at the rising edge of the SCLK signal.

[0025] The invention is applicable to CCDL scenarios between FPGAs across electrical domains. Compared to the typical four-wire SPI bus interface, the universal SPI bus interface across electrical domains has two additional signals: SCSN and SCLK. After communication occurs, the SPI slave device generates the SCLK signal based on the MCLK signal and simultaneously shifts the output MISO signal. The SPI master device shifts and collects the MISO signal at the rising edge of the SCLK signal, effectively eliminating the impact of the isolator chip's transmission delay, increasing the transmission rate between master and slave SPI devices, and enabling cross-platform porting. This significantly improves the universality of the SPI bus and can be widely used in industrial fields.

[0026] First, combine Figure 1 This article describes the issues that exist in a typical four-wire SPI bus interface in cross-electrical domain scenarios. When SPI bus communication begins, the SPI master sets the chip select signal MCSN low, generates the serial clock signal MCLK, and shifts and outputs the serial data signal MOSI at the falling edge of MCLK. MCSN, MCLK, and MOSI are simultaneously input to the SPI slave device through an isolator. When MCSN is low and detects the rising edge of MCLK, the SPI slave shifts and samples MOSI. When MCSN is low and detects the falling edge of MCLK, the SPI slave shifts and outputs the serial data signal MISO. The SPI master shifts and samples MISO at the rising edge of MCLK. After the sample is complete, the SPI master sets MCSN high, ending the SPI communication.

[0027] On the one hand, the SPI master generates the serial clock signal MCLK, which is input to the SPI slave device through an isolator. This transmission delay is Δt. The delay between the SPI slave detecting the falling edge of MCLK and the time when the SPI master generates MCLK is also Δt. On the other hand, the SPI slave device shifts and outputs MISO upon detecting the falling edge of MCLK. MISO is input to the SPI master device through an isolator, with a transmission delay of Δt. The SPI master shifts and captures MISO at the rising edge of MCLK. The delay between MISO and the time when the SPI master generates MCLK is 2 × Δt. The SPI master can correctly capture MISO only if the MCLK period is greater than 4 × Δt. Δt is typically in the tens of nanoseconds, making it difficult to achieve 10 Mbps across SPI bus communication across electrical domains. Furthermore, there are many different types of electrical isolation chips, and their transmission delays vary. This makes SPI bus control logic difficult to port between different platforms, resulting in low interoperability.

[0028] In view of the problem that the typical four-wire SPI bus interface has low transmission rate and poor portability in the above-mentioned cross-electrical domain scenario, the present invention designs a high-speed SPI bus interface that is portable across electrical domains. Figure 2The high-speed SPI bus interface that is portable across electrical domains described in the present invention includes MCSN, SCSN, MCLK, MOSI, SCLK, and MISO, which has two more signals, SCSN and SCLK, than the typical four-wire SPI bus interface. The SPI master device sets the chip select signal MCSN to low after the SPI bus transmission starts; the SPI master device outputs the SPI bus clock signal MCLK, and the SPI master device shifts and outputs the SPI serial data signal MOSI at the falling edge of MCLK; the SPI slave device shifts and collects the SPI serial data signal MOSI at the rising edge of MCLK, and the SPI slave device generates and outputs SCLK based on MCLK, and shifts and outputs the SPI serial data signal MISO at the falling edge of SCLK. The SPI slave device sets SCSN to high after the SPI bus output ends; the SPI master device shifts and collects the SPI serial data signal MISO at the rising edge of SCLK, and the SPI master device sets MCSN to high after collecting the rising edge of SCSN, and the SPI bus transmission ends. The SCSN and SCLK signals are generated and output by the SPI slave device and then input to the SPI master device after passing through an isolator. At the start of SPI bus transmission, the SPI master device sets the MCSN signal low. Upon detecting the rising edge of the SCSN signal, the SPI master device sets the MCSN signal high. Upon detecting the falling edge of the MCSN signal, the SPI slave device sets the SCSN signal low. After the MISO shift output is complete, the SPI slave device sets the SCSN signal high. The SPI slave device outputs the SCLK signal based on the MCLK signal, setting the SCLK signal high upon detecting the rising edge of the MCLK signal and setting the SCLK signal low upon detecting the falling edge of the MCLK signal. The SPI slave device shifts and outputs the MISO signal at the falling edge of the SCLK signal. The SPI master device shifts and collects the MISO signal at the rising edge of the SCLK signal.

[0029] After communication occurs, the SPI slave device generates SCLK while completing the MISO shift output based on MCLK. MISO and SCLK are simultaneously input to the SPI master device through the isolation chip. The SPI master device then completes the shift acquisition of MISO based on the rising edge of SCLK. At this time, the delay of SCLK relative to MISO can be ignored, effectively eliminating the influence of the transmission delay of the isolator chip, improving the transmission rate between the master and slave SPI devices, realizing cross-platform transplantation, and significantly improving the universality of the SPI bus.

[0030] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A high-speed SPI bus interface with portability across electrical domains, suitable for data interaction between an SPI master device and an SPI slave device, characterized in that: Contains the MCSN, MCLK, MOSI, and MISO signals of the four-wire SPI bus and the SCSN and SCLK signals, among which: After the SPI bus transmission starts, the SPI master device sets the chip select signal MCSN to low, and the SPI master device outputs the SPI bus clock signal MCLK. The SPI master device shifts and outputs the SPI serial data signal MOSI at the falling edge of MCLK. The SPI slave device shifts and collects the SPI serial data signal MOSI at the rising edge of MCLK. The SPI slave device generates and outputs SCLK based on MCLK, and shifts and outputs the SPI serial data signal MISO at the falling edge of SCLK. After the SPI slave device finishes outputting the SPI bus, it sets SCSN to high. The SPI master device shifts and collects the SPI serial data signal MISO at the rising edge of SCLK. After collecting the rising edge of SCSN, the SPI master device sets MCSN to high, and the SPI bus transmission ends. The SCSN signal and the SCLK signal are generated and output by the SPI slave device, and are input to the SPI master device after passing through the isolator. When the SPI bus transmission starts, the SPI master device sets the MCSN signal to low; the SPI master device sets the MCSN signal to high when detecting the rising edge of the SCSN signal; The SPI slave device sets the SCSN signal to low when detecting the falling edge of the MCSN signal; the SPI slave device sets the SCSN signal to high after the MISO shift output is completed, and the SPI slave device outputs the SCLK signal according to the MCLK signal. When the SPI slave device detects the rising edge of the MCLK signal, the SCLK signal is set to high, and when the SPI slave device detects the falling edge of the MCLK signal, the SCLK signal is set to low; The SPI slave device shifts and outputs the MISO signal at the falling edge of the SCLK signal, and the SPI master device shifts and collects the MISO signal at the rising edge of the SCLK signal.

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