Method for inter-pHY interference cancellation in tiled screen

Abstract

The present application relates to the technical field of splicing screen, in particular to a method for eliminating interference between PHYs in a splicing screen, comprising the following steps: S1: packaging two PHYs in one ASIC in the splicing screen; S2: synchronizing the clocks of the two PHYs in the same ASIC; S3: transmitting information between the two PHYs as a reference for adaptive filters of each other to realize crosstalk elimination. The present application realizes crosstalk elimination by packaging two PHYs in one ASIC in the splicing screen, synchronizing the clocks of the two PHYs in the same ASIC and transmitting information between the two PHYs as a reference for adaptive filters of each other. The present application solves the technical problem that two PHYs will share a transformer and an RJ45 connector, so there will be mutual interference when receiving and transmitting data, which can be called PHY near-end crosstalk.

Description

Technical Field

[0001] This invention relates to the field of video wall technology, specifically to a method for eliminating interference between PHYs in a video wall. Background Technology

[0002] Video wall displays can be used individually as monitors or combined to form ultra-large screens. Depending on the usage needs, the graphics processor enables the screen to be enlarged or reduced in size. It supports single-screen multi-view display, single-screen single-view display, arbitrary combination display of video walls, image splicing, and full-screen splicing. Image borders can be compensated or covered. It supports digital signal roaming, scaling and stretching, cross-screen display, setting and running of various display presets, and real-time processing of full HD signals.

[0003] When a video stream needs to be transmitted between different display screens, the signal is sent from the video source to the splicing screen (a display cluster composed of multiple display modules). The signal is transmitted between different display modules. For each display module, the signal is input and output once, using two PHYs. In order to reduce costs, it is considered to integrate the two PHYs into one ASIC. In this way, the two PHYs can share some modules, thereby minimizing costs.

[0004] However, since the two PHYs share the transformer and RJ45 connector, they will interfere with each other when transmitting and receiving data. This is known as near-end crosstalk between PHYs. There is no existing technology that proposes a method to reduce or eliminate near-end crosstalk between two PHYs within the same ASIC. Summary of the Invention

[0005] When video streams need to be transmitted between different display screens, two PHYs are required for each screen, one for input and one for output. To reduce costs, it is considered to integrate the two PHYs together (as an ASIC). This way, the two PHYs can share some modules, thereby minimizing costs. However, since the two PHYs share transformers and RJ45 connectors, there will be mutual interference when transmitting and receiving data, which can be called near-end crosstalk between PHYs. This paper proposes a method to reduce or eliminate near-end crosstalk between two PHYs within the same ASIC.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A method for eliminating inter-PHY interference in a video wall includes the following steps:

[0008] S1: In a video wall, two PHYs are packaged within a single ASIC;

[0009] S2: Synchronize the clocks of two PHYs within the same ASIC;

[0010] S3: The transmitted information is passed between the two PHYs as a reference for each other's adaptive filters, thereby achieving crosstalk cancellation.

[0011] As a preferred real-time solution of the present invention, S2 specifically includes:

[0012] S21: The two PHYs in the same ASIC adopt a fixed configuration. The configuration of Master and Slave does not change with link_partner. Master will synchronize the clock with Slave.

[0013] S22: Two adjacent display modules are connected in a paired manner, with the Master of this module connected to the Slave of the adjacent module, or the Slave of this module connected to the Master of the adjacent module.

[0014] As a preferred real-time solution of the present invention, the synchronization of the clock between the Master and the Slave in S21 includes: the clocks of the two PHYs (PHY1 and PHY2) in the same ASIC originate from the same crystal oscillator; the phase synthesizer takes the sine output of the crystal oscillator as input and the frequency control word as a reference to adjust the frequency and phase of its own output clock signal to provide the working clock for the two PHYs; wherein the frequency control word of the phase synthesizer 1 always comes from PHY1 (Slave); the frequency control word of the phase synthesizer 2 comes from PHY2 (Master) during the link establishment process, and its frequency control word comes from PHY1 (Slave) after the link is established.

[0015] As a preferred real-time solution of the present invention, S3 specifically further includes:

[0016] S31: The transmitted information is passed between the two PHYs (PHY1 and PHY2) as a reference for each other's adaptive filters;

[0017] S32: Use a cyclic search strategy to determine the interference magnitude of each differential transmission line of PHY1 (PHY2) to each differential transmission line of PHY2 (PHY1) in turn;

[0018] S33: Automatically determines the tracking and elimination of interference on the corresponding differential transmission lines in PHY1 (PHY2) based on the size of the filter coefficients.

[0019] As a preferred real-time solution of the present invention, the adaptive filter update process is as follows:

[0020] Let x(n)…x(nL) be the data transmitted by a differential transmission line of PHY1 (PHY2) and also be the input signal, and d(n) be the crosstalk at different times;

[0021] Where e(n) is the error signal, and y(n) is the output signal generated after the input signal x(n) passes through the adaptive filter;

[0022] Theoretically, the adaptive filter coefficients w l An analytical solution can be obtained based on the minimum mean square error optimization criterion, namely:

[0023] w l =argmin(E(e(n)) 2 ), where E(e(n) 2 Let w be the objective function of the optimization problem. l (n) Taking the partial derivative and setting it to 0, we get:

[0024]

[0025] From the above formula, we can obtain: w l (n)E(x 2 (nl))=E(d(n)x(nl))

[0026] then:

[0027] However, in practice, the expected value in the above formula cannot be obtained. The gradient descent method is usually used to iteratively obtain the coefficients of the adaptive filter, i.e.: w l (n)=w l (n-1)-αE(e(n)x(nl)).

[0028] As a preferred real-time solution of the present invention, step S33 automatically determines the tracking and elimination of interference on the corresponding differential transmission lines in PHY1 (PHY2) based on the magnitude of the filter coefficients, which includes:

[0029] Based on the obtained w0(n)...w L (n) represents the impulse response coefficient for approximating crosstalk. By sending data to different differential transmission lines of PHY1 (PHY2), the crosstalk situation of each differential transmission line in PHY1 (PHY2) to one differential transmission line of PHY2 (PHY1) is obtained. Each time, w0(n)…w L Take the absolute value of (n) and then sum them up to find the differential transmission line with the largest sum of coefficients in PHY1 (PHY2), and then track and eliminate its crosstalk.

[0030] The present invention provides a display device comprising multiple sets of display modules, each set of display modules comprising two sets of PHYs.

[0031] The present invention provides a computer device including a memory, a processor, and a computer program stored in the memory, wherein the computer program, when executed by the processor, performs instructions according to the method described herein.

[0032] The present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor of a computer device, performs instructions according to the method described herein.

[0033] One or more technical solutions provided in this application have at least the following technical effects or advantages:

[0034] This application embodiment achieves crosstalk cancellation by encapsulating two PHYs within one ASIC in the splicing screen. The clock synchronization and information transmission between the two PHYs within the same ASIC are used as references for each other's adaptive filters. This solves the technical problem of near-end crosstalk between PHYs, which currently occurs when two PHYs share transformers and RJ45 connectors and therefore interfere with each other when transmitting and receiving data.

[0035] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a flowchart illustrating a method for eliminating inter-PHY interference in a video wall, as provided in an embodiment of this application.

[0038] Figure 2 This is a flowchart illustrating a clock synchronization method for two PHYs provided in an embodiment of this application.

[0039] Figure 3 This is a flowchart illustrating the crosstalk cancellation method implemented by two PHYs using an adaptive filter, as provided in an embodiment of this application.

[0040] Figure 4This is a schematic diagram of the series structure of the display module provided in an embodiment of this application.

[0041] Figure 5 This is a schematic diagram of the structure for synchronizing the Master and Slave clocks according to an embodiment of this application.

[0042] Figure 6 This is a schematic diagram of crosstalk between PHYs provided in an embodiment of this application.

[0043] Figure 7 This is a schematic diagram illustrating the principle of the adaptive filter provided in an embodiment of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0045] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0046] like Figure 1 As shown, this invention provides a method for eliminating inter-PHY interference in a video wall. By encapsulating two PHYs within a single ASIC in the video wall, the clock synchronization and information transmission between the two PHYs within the same ASIC are used as references for their adaptive filters, thus achieving crosstalk elimination. This solves the technical problem of near-end crosstalk between PHYs, where two PHYs share a transformer and RJ45 connector, leading to mutual interference during data transmission and reception. Specifically, this includes:

[0047] like Figure 1 As shown, the present invention provides a method for eliminating inter-PHY interference in a video wall, comprising the following steps:

[0048] S1: In a video wall, two PHYs are packaged within a single ASIC;

[0049] S2: Synchronize the clocks of two PHYs within the same ASIC;

[0050] S3: The transmitted information is passed between the two PHYs as a reference for each other's adaptive filters, thereby achieving crosstalk cancellation.

[0051] In this embodiment, step S2 specifically includes:

[0052] S21: The two PHYs in the same ASIC adopt a fixed configuration. The configuration of Master and Slave does not change with link_partner. Master will synchronize the clock with Slave.

[0053] S22: Two adjacent display modules are connected in a paired manner, with the Master of this module connected to the Slave of the adjacent module, or the Slave of this module connected to the Master of the adjacent module.

[0054] like Figure 2 As shown, specifically, after two adjacent display modules are connected in a paired manner, all display modules can be configured as follows: Figure 2 The “serialized” structure shown above, when using this strategy, ensures that the clocks of all PHYs in the above application scenarios will eventually be synchronized to the same clock.

[0055] like Figure 3 As shown, in this embodiment, the Master synchronizing the clock with the Slave in S21 includes: the clocks of the two PHYs (PHY1 and PHY2) in the same ASIC originate from the same crystal oscillator; the phase synthesizer takes the sine output of the crystal oscillator as input and the frequency control word as a reference to adjust the frequency and phase of its own output clock signal to provide the working clock for the two PHYs; the frequency control word of the phase synthesizer 1 always comes from PHY1 (Slave); the frequency control word of the phase synthesizer 2 comes from PHY2 (Master) during the link establishment process, and its frequency control word comes from PHY1 (Slave) after the link is established.

[0056] In this embodiment, as Figure 6 As shown, S3 specifically includes:

[0057] S31: The transmitted information is passed between the two PHYs (PHY1 and PHY2) as a reference for each other's adaptive filters;

[0058] S32: Use a cyclic search strategy to determine the interference magnitude of each differential transmission line of PHY1 (PHY2) to each differential transmission line of PHY2 (PHY1) in turn;

[0059] S33: Automatically determines the tracking and elimination of interference on the corresponding differential transmission lines in PHY1 (PHY2) based on the size of the filter coefficients.

[0060] like Figure 4As shown, since each PHY has 4 pairs of differential transmission lines, taking PHY1's Ch1 as an example, it will be affected by interference from the four pairs of lines from PHY2. Therefore, theoretically, each PHY needs to add 4*4=16 adaptive filter modules, which will obviously consume a lot of resources. In reality, the interference amplitude from the four pairs of lines from PHY2 to PHY1's Ch1 is not the same, and the difference can be quite large. We only need to equip Ch1 with 1 to 2 adaptive filter modules to eliminate most of the interference. However, we do not know which Ch of PHY2 has a greater impact on PHY1's Ch1. Therefore, we need to adopt a cyclic search strategy to determine the interference magnitude of each Ch of PHY2 to PHY1's Ch1, and then automatically determine which Ch of PHY2 to track and eliminate the interference based on the filter coefficients.

[0061] like Figure 5 and Figure 7 As shown, in this embodiment, the adaptive filter update process is as follows:

[0062] Let x(n)…x(nL) be the data transmitted by a differential transmission line of PHY1 (PHY2) and also be the input signal, and d(n) be the crosstalk at different times;

[0063] Where e(n) is the error signal, and y(n) is the output signal generated after the input signal x(n) passes through the adaptive filter;

[0064] Theoretically, the adaptive filter coefficients w l An analytical solution can be obtained based on the minimum mean square error optimization criterion, namely:

[0065] w l =argmin(E(e(n)) 2 ), where E(e(n) 2 Let w be the objective function of the optimization problem. l (n) Taking the partial derivative and setting it to 0, we get:

[0066]

[0067] From the above formula, we can obtain: w l (n)E(x 2 (nl))=E(d(n)x(nl))

[0068] then:

[0069] However, in practice, the expected value in the above formula cannot be obtained. The gradient descent method is usually used to iteratively obtain the coefficients of the adaptive filter, i.e.: w l (n)=w l(n-1)-αE(e(n)x(nl)).

[0070] In this embodiment, step S33, which automatically determines the tracking and cancellation of interference on the corresponding differential transmission lines in PHY1 (PHY2) based on the magnitude of the filter coefficients, includes:

[0071] Based on the obtained w0(n)...w L (n) represents the impulse response coefficient for approximating crosstalk. By sending data to different differential transmission lines of PHY1 (PHY2), the crosstalk situation of each differential transmission line in PHY1 (PHY2) to one differential transmission line of PHY2 (PHY1) is obtained. Each time, w0(n)…w L The absolute values ​​of (n) are taken and then summed to identify the differential transmission line with the largest sum of coefficients in PHY1 (PHY2), and then its crosstalk is tracked and eliminated. This invention provides a display device comprising multiple sets of display modules, each set of display modules including two sets of PHYs.

[0072] The present invention provides a computer device, including a memory, a processor, and a computer program stored in the memory, wherein the computer program, when executed by the processor, executes instructions according to the method described above.

[0073] The present invention provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor of a computer device, executes instructions according to the method described above.

[0074] Although this application has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made thereto without departing from the spirit and scope of this application. Accordingly, this specification and drawings are merely illustrative examples of this application and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of this application. Clearly, those skilled in the art can make various alterations and modifications to this application without departing from its scope. Thus, if such modifications and modifications fall within the scope of this application and its equivalents, this application intends to include such modifications and modifications.

Claims

1. A method for inter-PHY interference cancellation in a tiled screen, the method comprising: The method comprises the following steps: S1: two PHYs are packaged in one ASIC in the tiled screen; S2: the clocks of the two PHYs in the same ASIC are synchronized, comprising: S21: the two PHYs in the same ASIC adopt fixed configuration, the configuration of Master and Slave does not change with link_partner, and the Master synchronizes the clock with the Slave; wherein the Master synchronizes the clock with the Slave, comprising: the clocks of the two PHYs (PHY1 and PHY2) in the same ASIC are derived from the same crystal oscillator, the phase synthesizer takes the sine output of the crystal oscillator as input, takes the frequency control word as reference to adjust the frequency and phase of its own output clock signal, and provides working clock for the two PHYs, wherein the frequency control word of the phase synthesizer 1 always comes from the Slave PHY1, and the frequency control word of the phase synthesizer 2 comes from the Master PHY2 in the process of establishing link, and after the Slave PHY1 establishes link, the frequency control word comes from the Slave PHY1; S22: the two adjacent display modules adopt the pairing connection mode, the Master of the module is connected with the Slave of the adjacent module, or the Slave of the module is connected with the Master of the adjacent module; S3: the transmission information is transmitted between the two PHYs as the reference of adaptive filter of each other to realize crosstalk elimination, comprising: S31: the transmission information is transmitted between the two PHYs (PHY1 and PHY2) as the reference of adaptive filter of each other; S32: the interference size of each team of differential transmission line of PHY1 to each team of differential transmission line of PHY2 is determined in turn by adopting the cyclic search strategy, or the interference size of each team of differential transmission line of PHY2 to each team of differential transmission line of PHY1 is determined in turn by adopting the cyclic search strategy; S33: according to the coefficient size of the filter, it is automatically determined that the interference of which team of differential transmission line in PHY1 is tracked and eliminated, or according to the coefficient size of the filter, it is automatically determined that the interference of which team of differential transmission line in PHY2 is tracked and eliminated.

2. The method of claim 1, wherein, The adaptive filter updating process is as follows: Let x(n)…x(n-L) be the data sent out by a certain differential transmission line of PHY1 or PHY2 and also be the input signal, and d(n) be the crosstalk at different time; where e(n) is an error signal and y(n) is an output signal of the input signal x(n) through the adaptive filter. Theoretically adaptive filter coefficients w l An analytical solution can be found based on the minimum mean square error optimization criterion, i.e.: w l = argmin(E(e(n) 2 )) where E(e(n) 2 ) is the objective function of the optimization problem, taking the partial derivative with respect to the coefficients w l (n) and setting it to zero gives From the above equation, we have: l (n) = E(x(n) - x(n-l)) = E(d(n)x(n-l)) 2 (n-l)) = E(d(n)x(n-l)) Thus: But the expected value in the above formula cannot be obtained in practice, and the gradient descent method is usually used to iteratively calculate the coefficients of the adaptive filter, i.e. w l (n) = w l (n-1) - aE(e(n)x(n-1)).

3. The method of claim 2, wherein, The S33 further comprises: According to the obtained w0(n)…w L (n) is the impulse response coefficient of the crosstalk approximation, by sending data through different differential transmission lines of PHY1, the crosstalk of each differential transmission line of PHY1 to one differential transmission line of PHY2 is obtained, the absolute value of w0(n)…w L (n) obtained each time is summed up, the differential transmission line with the largest coefficient sum in PHY1 is counted, and then the crosstalk thereof is tracked and eliminated; or According to the obtained w0(n)…w L (n) is the impulse response coefficient of the crosstalk approximation. By sending data through different differential transmission lines of PHY2, the crosstalk of each differential transmission line of PHY2 to one differential transmission line of PHY1 is obtained, and the absolute values of w0(n)…w L (n) obtained each time are summed up to count the differential transmission line with the largest coefficient in PHY2, and then the crosstalk of the differential transmission line is tracked and eliminated.

4. A display device comprising a plurality of groups of display modules, characterized in that Each group of the display module comprises two groups of PHYs, and each group of the PHY runs to execute the instructions of the method according to any one of claims 1-3.

5. A computer device comprising a memory, a processor, and a computer program stored on the memory, wherein, The computer program is run by the processor to execute the instructions of the method according to any one of claims 1-3.

6. A computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program is run by the processor of the computer device to execute the instructions of the method according to any one of claims 1-3.

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