A semiconductor device structure and a method of fabricating the same

Abstract

The application provides a semiconductor device structure and a preparation method thereof, and the device structure comprises: a substrate layer, a device epitaxial layer, a field plate dielectric layer, a negative capacitance dielectric layer, a gate layer and a field plate electrode; the field plate dielectric layer is arranged on the device epitaxial layer, the negative capacitance dielectric layer is arranged on the field plate dielectric layer, the gate layer is arranged on a first side of the field plate dielectric layer and the negative capacitance dielectric layer, and the gate layer extends from the first side to a second side to cover at least part of the negative capacitance dielectric layer to form the field plate electrode. By arranging the negative capacitance dielectric layer between the field plate electrode and the field plate dielectric layer, a negative capacitance structure is introduced, so that less input energy is needed in the case of generating the same amount of charge, the additional capacitance generated by introducing the field plate electrode in the GaN-based HEMT device is balanced, the charging and discharging time is shortened while the high breakdown voltage and the long service life brought by the field plate electrode are maintained, the device switching speed is improved, and the switching characteristics and the frequency characteristics of the GaN-based HEMT device are optimized.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a semiconductor device structure and a preparation method thereof. BACKGROUND

[0002] GaN (gallium nitride) -based HEMT (High Electron Mobility Transistors) devices, as a representative of WBG (wide band gap) power semiconductor devices, have higher electron mobility, saturation electron velocity and breakdown field than devices with silicon and silicon carbide as substrates, and have great potential in high-frequency and power applications.

[0003] When the GaN-based HEMT device works under a larger drain bias, the channel electric field, especially on the side close to the drain of the gate, will generate a peak electric field, which is prone to cause device leakage and even breakdown, and cannot exert the advantages of gallium nitride devices.

[0004] As shown in FIG. 1, the GaN-based HEMT device in the prior art can effectively reduce the peak electric field at the edge of the gate by introducing a field plate electrode, so that the electric field distribution between the gate and the drain is more uniform, thereby improving the breakdown voltage of the device and increasing the service life of the device. However, since an additional capacitance is formed between the field plate electrode and the channel, the device needs a longer time to charge and discharge the additional capacitance when working, which degrades the switching characteristics and frequency characteristics, and the energy of the switching loss is also larger, so there is an urgent need for a solution that can reduce or eliminate the additional capacitance generated when the field plate electrode is introduced. Figure 1

[0005] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application, and for the convenience of understanding by those skilled in the art, and the above technical scheme cannot be considered as known to those skilled in the art only because it is described in the background section of the present application. SUMMARY

[0006] In view of the above shortcomings of the prior art, the purpose of the present application is to provide a semiconductor device structure and a preparation method thereof, which can solve the problem of degradation of switching characteristics and frequency characteristics caused by the introduction of a field plate electrode in the GaN-based HEMT device in the prior art.

[0007] To achieve the above purpose, the present application provides a semiconductor device structure, which comprises: a substrate layer, a device epitaxial layer, a field plate dielectric layer, a negative capacitance dielectric layer, a gate layer, and a field plate electrode.

[0008] ​The device epitaxial layer is disposed on the substrate layer, the field plate dielectric layer is disposed on the device epitaxial layer, the negative capacitance dielectric layer is disposed on the field plate dielectric layer, the gate layer is disposed on a first side of the field plate dielectric layer and the negative capacitance dielectric layer, and the gate layer extends from the first side toward a second side of the field plate dielectric layer and the negative capacitance dielectric layer to cover at least part of the negative capacitance dielectric layer to form a field plate electrode.

[0009] Optionally, the device structure further comprises a source layer and a drain layer, and the field plate dielectric layer separates the gate layer, the source layer and the drain layer.

[0010] Optionally, the second side is a side of the field plate dielectric layer and the negative capacitance dielectric layer close to the drain layer.

[0011] Optionally, a projection of the field plate electrode on a first plane completely covers a projection of the negative capacitance dielectric layer on the first plane, and the first plane is parallel to the device epitaxial layer.

[0012] Optionally, a projection of the field plate electrode on a first plane completely covers a projection of the negative capacitance dielectric layer on the first plane, and the first plane is parallel to the device epitaxial layer.

[0013] Optionally, a projection of the field plate electrode on a first plane completely covers a projection of the negative capacitance dielectric layer on the first plane, and the first plane is parallel to the device epitaxial layer.

[0014] Optionally, a material of the negative capacitance dielectric layer comprises one or more than one combination of hafnium-based oxide, epsilon-type potassium oxide, barium titanate, lithium niobate, lithium titanate or lead titanate.

[0015] Optionally, a preparation method of the negative capacitance dielectric layer comprises one or more than one arbitrary combination of metal organic chemical vapor deposition, molecular beam epitaxy, pulsed laser deposition, atomic layer deposition or sputtering.

[0016] Optionally, the device epitaxial layer comprises a channel layer and a barrier layer, the barrier layer is located on the channel layer, the barrier layer comprises one or more than one arbitrary combination of InAlN, InAlGaN and AlGaN, and the channel layer comprises GaN.

[0017] The application further provides a preparation method of the semiconductor device structure, which is used for preparing any one of the device structures, and comprises the following steps: providing a substrate layer; arranging the device epitaxial layer on the substrate layer; arranging the field plate dielectric layer on the device epitaxial layer; arranging the negative capacitance dielectric layer on the field plate dielectric layer; arranging the gate layer on the first side of the field plate dielectric layer and the negative capacitance dielectric layer; and arranging the field plate electrode on the gate layer, wherein the field plate electrode extends from the first side to the second side to cover at least part of the negative capacitance dielectric layer.

[0018] As described above, the semiconductor device structure and the preparation method thereof have the following beneficial effects:

[0019] The application introduces the negative capacitance structure by arranging the negative capacitance dielectric layer between the field plate electrode and the field plate dielectric layer, thereby needing less input energy in the case of generating the same amount of charge, balancing the additional capacitance generated by the field plate electrode of the GaN-based HEMT device, shortening the charging and discharging time while maintaining the high breakdown voltage and long service life brought by the field plate electrode, improving the switching speed of the device, and optimizing the switching characteristics and frequency characteristics of the GaN-based HEMT device. BRIEF DESCRIPTION OF DRAWINGS

[0020] Figure 1 A semiconductor device structure in which a field plate electrode is introduced in the prior art is shown.

[0021] Figure 2 A semiconductor device structure in an embodiment of the application is shown.

[0022] Figure 3 A schematic diagram showing the functional relationship between energy and charge of different capacitances in the prior art is shown.

[0023] ELEMENT NUMBER EXPLANATION

[0024] 10, substrate layer; 20, device epitaxial layer; 21, channel layer; 22, barrier layer; 30, field plate dielectric layer; 40, negative capacitance dielectric layer; 50, gate layer; 51, field plate electrode; 60, drain layer; 70, source layer; 81, positive capacitance curve; 82, negative capacitance curve; 83, positive and negative series capacitance curve; 84, negative capacitance region. DETAILED DESCRIPTION

[0025] The embodiments of the application are described below in detail through specific examples, and those skilled in the art can easily understand other advantages and effects of the application from the disclosure. The application can also be implemented or applied through other different embodiments, and the details in the specification can be modified or changed based on different viewpoints and applications without departing from the spirit of the application.

[0026] In the detailed description of embodiments of the present invention, for ease of explanation, the schematic diagrams illustrating the device structure may be partially enlarged without adhering to the general scale, and the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. Furthermore, in actual manufacturing, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0027] For ease of description, spatial relation terms for semiconductor device structures, such as "below," "below," "below," "under," "above," "upper," etc., may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the accompanying drawings for devices in use or operation.

[0028] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0029] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0030] Example 1:

[0031] like Figure 2 As shown, the present invention provides a semiconductor device structure, the device structure comprising: a substrate layer 10, a device epitaxial layer 20, a field plate dielectric layer 30, a negative capacitor dielectric layer 40, a gate layer 50, and a field plate electrode 51.

[0032] The device epitaxial layer 20 is disposed on the substrate layer 10, the field plate dielectric layer 30 is disposed on the device epitaxial layer 20, the negative capacitance dielectric layer 40 is disposed on the field plate dielectric layer 30, and the gate layer 50 is disposed on a first side of the field plate dielectric layer 30 and the negative capacitance dielectric layer 40, and the gate layer 50 extends from the first side toward a second side of the field plate dielectric layer 30 and the negative capacitance dielectric layer 40 to at least cover a portion of the negative capacitance dielectric layer 40 to form a field plate electrode 51.

[0033] In one embodiment, the substrate 10 is made of one or more of silicon carbide, sapphire, silicon, or diamond.

[0034] In one embodiment, the material of the negative capacitance dielectric layer 40 is a ferroelectric material.

[0035] Specifically, the ferroelectric material is a material having a spontaneous polarization within a certain temperature range, and the polarization direction can be changed by an applied electric field.

[0036] The conventional electronic device is subject to carrier injection mechanism, and the sub-threshold swing is greater than or equal to 60 mV / dec; the energy U and the charge Q of a general dielectric capacitor are in a parabolic relationship, as shown in a positive capacitance curve 81, the capacitor is a "positive" capacitor (the capacitor is defined as the second derivative of the energy U to the charge Q); and the energy U and the charge Q of the ferroelectric material are in an "even polynomial" relationship, as shown in a negative capacitance curve 82, the capacitor between the double wells is "negative", that is, a negative capacitance region 84; adding (in series) the ferroelectric material and the general dielectric capacitor will form a stable negative capacitance in the "double well region", as shown in a positive-negative series capacitance curve 83. Figure 3 Figure 3 Figure 3

[0037] Specifically, the device structure further includes a source layer 70 and a drain layer 60, and the field plate dielectric layer 30 separates the gate layer 50, the source layer 70 and the drain layer 60.

[0038] The present application completely covers the upper surface of the negative capacitance dielectric layer 40 by the field plate electrode 51, so that the negative capacitance dielectric layer 40 can be stacked in series with the field plate dielectric layer 30, thereby forming a stable negative capacitance structure; due to the existence of the negative capacitance, a lower energy is required to generate an equal amount of charge Q, which realizes the effect of equivalent voltage amplification, so that the device structure with the negative capacitance dielectric layer 40 can realize shorter charging and discharging time and faster switching speed, while retaining the effect of the breakdown voltage improvement of the field plate electrode 51 on the device structure, solving the problem that the high field degradation effect (the phenomenon of leakage or breakdown caused by the peak electric field generated on the side of the gate layer 50 close to the drain layer 60 when the semiconductor device structure works under a larger drain bias) and the switching frequency characteristics (charging and discharging speed, switching loss energy) cannot be optimized at the same time.

[0039] In one embodiment, the material of the gate layer 50 is preferably a nickel-gold alloy or a platinum-gold alloy, which has a high work function and can suppress the leakage current of the gate layer 50.

[0040] In one embodiment, the material of the source layer 70 and / or the drain layer 60 is preferably a titanium-aluminum alloy or a titanium-aluminum-titanium-gold alloy, which forms a smaller ohmic contact resistance through high-temperature annealing.

[0041] In one embodiment, the distance between the gate layer 50 and the drain layer 60 is often larger than the distance between the gate layer 50 and the source layer 70, in order to improve the breakdown characteristics.

[0042] ​​​As an example, the second side is a side of the field plate dielectric layer 30 and the negative capacitance dielectric layer 40 close to the drain layer 60.

[0043] The present application can better solve the problem of the peak electric field on the side of the drain layer 60 by arranging the field plate electrode 51 on the side close to the drain layer 60, and the peak electric field problem on the side of the gate layer 50 close to the drain layer 60 in the semiconductor device structure is more serious, arranging the field plate electrode 51 on the side close to the drain layer 60 can have a better weakening effect on the high field degradation effect, and improve the efficiency of the negative capacitance dielectric layer 40 in improving the performance of the device.

[0044] As an example, the projection of the field plate electrode 51 on the first plane completely covers the projection of the negative capacitance dielectric layer 40 on the first plane, and the first plane is parallel to the device epitaxial layer 20.

[0045] As an example, the projection of the field plate electrode 51 on the first plane completely coincides with the projection of the negative capacitance dielectric layer 40 on the first plane.

[0046] The present application can further ensure the weakening effect on the high field degradation effect in the device structure by arranging the field plate electrode 51 and the negative capacitance dielectric layer 40 on the first plane to completely coincide, so that the negative capacitance dielectric layer 40 exists between the field plate electrode 51 and the device epitaxial layer 20 to reduce the influence of the additional capacitance.

[0047] As an example, the projection of the field plate dielectric layer 30 on the first plane completely covers the projection of the negative capacitance dielectric layer 40 on the first plane, and the first plane is parallel to the device epitaxial layer 20.

[0048] The present application can further reduce the influence of parasitic capacitance by completely covering the negative capacitance dielectric layer 40 by the field plate dielectric layer 30 through insulation coverage.

[0049] In one embodiment, the material of the field plate dielectric layer 30 is one or a combination of more than one of silicon oxide, silicon nitride or aluminum oxide.

[0050] Specifically, the material of the field plate dielectric layer 30 can also be other suitable insulating materials, which are not limited here.

[0051] As an example, the material of the negative capacitance dielectric layer 40 includes one or a combination of more than one of hafnium-based oxide, epsilon-type potassium oxide, barium titanate, lithium niobate, lithium titanate or lead titanate.

[0052] As an example, the negative capacitance dielectric layer 40 is prepared by one or more than one of metal-organic chemical vapor deposition, molecular beam epitaxy, pulsed laser deposition, atomic layer deposition, or sputtering, in any combination.

[0053] As an example, the device epitaxial layer 20 includes a channel layer 21 and a barrier layer 22, the barrier layer 22 is on the channel layer 21, the barrier layer 22 includes one or more than one of InAlN, InAlGaN, and AlGaN, in any combination, and the channel layer 21 includes GaN.

[0054] In particular, GaN as the material of the channel layer 21 has high resistance, for forming a two-dimensional electron gas (2DEG) together with the barrier layer 22, and reducing the background carrier concentration to reduce the drain current collapse caused by buffer trap effect.

[0055] In one embodiment, the device epitaxial layer 20 further includes a spacer layer (not shown), the barrier layer 22 is on the spacer layer, and the spacer layer is an unintentionally doped AlN layer.

[0056] The present application separates the barrier layer 22 and the channel layer 21 by the spacer layer, to reduce the influence of ion scattering caused by doping on the 2DEG mobility and concentration in the channel layer 21.

[0057] In one embodiment, a cap layer (not shown) is provided on the barrier layer 22, the cap layer is GaN, to reduce the current collapse of the drain layer 60, maintain the 2DEG generated by the polarization property, while reducing the leakage current of the gate layer 50, enhance the ohmic contact and breakdown voltage of the source layer 70 and the drain layer 60.

[0058] In one embodiment, the device epitaxial layer 20 can further include a buffer layer (not shown), the buffer layer is between the channel layer 21 and the substrate layer 10. The present application provides the buffer layer to reduce the lattice mismatch between the substrate layer 10 and the channel layer 21, to reduce the current collapse caused by interface defects or trap effect, reduce the static current leakage and improve the radio frequency performance and radio frequency transmission.

[0059] In one embodiment, the buffer layer can include a III-V compound. The III-V compound can include, but is not limited to, aluminum, gallium, indium, nitrogen, or one or more than one of them in any combination. Therefore, the exemplary material of the buffer layer can also include, for example, but not limited to, GaN, AlN, AlGaN, InAlGaN, or one or more than one of them in any combination.

[0060] As an example, the semiconductor device structure is a HEMT device structure.

[0061] Specifically, the HEMT device structure can be N-type or P-type, which can be selected by the practitioner according to actual needs.

[0062] Embodiment two:

[0063] The present application provides a preparation method of a semiconductor device structure, which is used for preparing any one of the device structures in the above embodiment one, and the preparation method comprises:

[0064] Step 1: providing a substrate layer 10;

[0065] Step 2: providing a device epitaxial layer 20 on the substrate layer 10;

[0066] Step 3: providing a field plate dielectric layer 30 on the device epitaxial layer 20;

[0067] Step 4: providing a negative capacitance dielectric layer 40 on the field plate dielectric layer 30;

[0068] Step 5: providing a gate layer 50 on a first side of the field plate dielectric layer 30 and the negative capacitance dielectric layer 40;

[0069] Step 6: providing a field plate electrode 51 on the gate layer 50, the field plate electrode 51 extending from the first side to a second side of the field plate dielectric layer 30 and the negative capacitance dielectric layer 40 to cover at least part of the negative capacitance dielectric layer 40.

[0070] The preparation method of the semiconductor device structure of the present application will be described in detail below with reference to the accompanying drawings, and it should be noted that the above sequence does not strictly represent the preparation method sequence of the semiconductor device structure protected by the present application, and the skilled person can change the actual preparation steps.

[0071] First, step 1 is performed to provide a substrate layer 10.

[0072] In one embodiment, the substrate layer 10 material is one or a combination of more than one of silicon carbide, sapphire, silicon or diamond.

[0073] Next, step 2 is performed to provide a device epitaxial layer 20 on the substrate layer 10.

[0074] As an example, the device epitaxial layer 20 comprises a channel layer 21 and a barrier layer 22, the barrier layer 22 is located on the channel layer 21, the barrier layer 22 comprises one or a combination of more than one of InAlN, InAlGaN and AlGaN, and the channel layer 21 comprises GaN.

[0075] Specifically, GaN as the material of the channel layer 21 has high resistance, is used to form a two-dimensional electron gas (2DEG) together with the barrier layer 22, and reduces the background carrier concentration to reduce the drain current collapse caused by the buffer layer trap effect.

[0076] In one embodiment, the preparation method further comprises disposing a spacer layer (not shown in the figure) between the barrier layer 22 and the channel layer 21, wherein the spacer layer is an unintentionally doped AlN layer.

[0077] The present application separates the barrier layer 22 and the channel layer 21 by disposing the spacer layer, and reduces the influence of ion scattering caused by doping on the 2DEG mobility and concentration in the channel layer 21.

[0078] In one embodiment, a cap layer (not shown in the figure) is disposed on the barrier layer 22, wherein the cap layer is GaN, used to reduce the current collapse of the drain layer 60, maintain the 2DEG generated by the polarization characteristics, reduce the leakage current of the gate layer 50, and enhance the ohmic contact and breakdown voltage of the source layer 70 and the drain layer 60.

[0079] In one embodiment, the preparation method further comprises disposing a buffer layer (not shown in the figure) between the channel layer 21 and the substrate layer 10. The present application reduces the lattice mismatch between the substrate layer 10 and the channel layer 21 by disposing the buffer layer, to reduce the current collapse caused by the interface defects or trap effect, reduce the static current leakage and radio frequency conduction, and improve the radio frequency performance.

[0080] In one embodiment, the buffer layer can comprise a III-V compound. The III-V compound can comprise, but is not limited to, aluminum, gallium, indium, nitrogen, or any combination of one or more thereof. Therefore, the exemplary material of the buffer layer can further comprise, for example, but is not limited to, GaN, AlN, AlGaN, InAlGaN, or any combination of one or more thereof.

[0081] Then, step 3 is performed to dispose a field plate dielectric layer 30 on the device epitaxial layer 20.

[0082] Next, step 4 is performed to dispose a negative capacitance dielectric layer 40 on the field plate dielectric layer 30.

[0083] In one embodiment, the material of the negative capacitance dielectric layer 40 is a ferroelectric material. Specifically, the ferroelectric material is a material that has spontaneous polarization within a certain temperature range, and the polarization direction can be changed by an applied electric field.

[0084] Then, step 5 is performed to dispose a gate layer 50 on the first side of the field plate dielectric layer 30 and the negative capacitance dielectric layer 40.

[0085] Next, step 6 is performed to dispose a field plate electrode 51 on the gate layer 50, the field plate electrode 51 extending from the first side to the second side of the field plate dielectric layer 30 and the negative capacitance dielectric layer 40 to cover at least part of the negative capacitance dielectric layer 40.

[0086] Specifically, the device structure further comprises a source layer 70 and a drain layer 60, and the field plate dielectric layer 30 separates the gate layer 50, the source layer 70 and the drain layer 60.

[0087] The present application completely covers the upper surface of the negative capacitance dielectric layer 40 by the field plate electrode 51, so that the negative capacitance dielectric layer 40 can be stacked in series with the field plate dielectric layer 30 to form a stable negative capacitance structure. Due to the existence of negative capacitance, the same amount of charge Q requires lower energy, which realizes the effect of equivalent voltage amplification, so that the device structure with the negative capacitance dielectric layer 40 can realize shorter charging and discharging time and faster switching speed, while retaining the effect of the field plate electrode 51 on the breakdown voltage of the device structure, solving the problem that high field degradation effect (peak electric field is generated on the side of the gate layer 50 close to the drain layer 60 in a semiconductor device structure under a large drain bias, causing leakage or breakdown) and switching frequency characteristics (charging and discharging speed, switching loss energy) cannot be optimized at the same time.

[0088] As an example, the second side to which the field plate electrode 51 extends is the side of the field plate dielectric layer 30 and the negative capacitance dielectric layer 40 close to the drain layer 60.

[0089] The present application sets the field plate electrode 51 on the side close to the drain layer 60, so that the negative capacitance dielectric layer 40 can better solve the problem of peak electric field on the side of the drain layer 60. Since the problem of peak electric field generated on the side of the gate layer 50 close to the drain layer 60 in a semiconductor device structure is more serious, setting the field plate electrode 51 on the side close to the drain layer 60 can have a better weakening effect on high field degradation effect, improving the efficiency of the negative capacitance dielectric layer 40 in improving device performance.

[0090] In one embodiment, the field plate electrode 51 can be etched directly on the gate layer 50 to obtain the gate layer 50 with the field plate electrode 51, or the field plate electrode 51 can be obtained by growth and etching process on the gate layer 50.

[0091] In one embodiment, the field plate electrode 51 is obtained by dry etching.

[0092] In summary, the semiconductor device structure and the preparation method thereof can introduce a negative capacitance structure by arranging a negative capacitance dielectric layer between the field plate electrode and the field plate dielectric layer, thereby needing less input energy in the case of generating equal charges, balancing the additional capacitance generated by the field plate electrode of the GaN-based HEMT device, shortening the charging and discharging time while maintaining the high breakdown voltage and long service life brought by the field plate electrode, improving the switching speed of the device, and optimizing the switching characteristics and frequency characteristics of the GaN-based HEMT device.

[0093] Therefore, the present application effectively overcomes the shortcomings in the prior art and has high industrial utilization value.

[0094] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.

Claims

1. A semiconductor device structure, characterized by, The device structure comprises: a substrate layer, a device epitaxial layer, a field plate dielectric layer, a negative capacitance dielectric layer, a gate layer, and a field plate electrode. The device epitaxial layer is disposed on the substrate layer, the field plate dielectric layer is disposed on the device epitaxial layer, the negative capacitance dielectric layer is disposed on the field plate dielectric layer, the gate layer is disposed on a first side of the field plate dielectric layer and the negative capacitance dielectric layer, and the gate layer extends from the first side towards a second side of the field plate dielectric layer and the negative capacitance dielectric layer to cover at least part of the negative capacitance dielectric layer to form a field plate electrode. The device structure further comprises a source layer and a drain layer, and the field plate dielectric layer separates the gate layer, the source layer, and the drain layer; and the second side is a side of the field plate dielectric layer and the negative capacitance dielectric layer close to the drain layer.

2. The semiconductor device structure of claim 1, wherein, A projection of the field plate electrode on a first plane completely covers a projection of the negative capacitance dielectric layer on the first plane, and the first plane is parallel to the device epitaxial layer.

3. The semiconductor device structure of claim 2, wherein, The projection of the field plate electrode on a first plane completely coincides with the projection of the negative capacitance dielectric layer on the first plane.

4. The semiconductor device structure of claim 1, wherein, A projection of the field plate dielectric layer on a first plane completely covers a projection of the negative capacitance dielectric layer on the first plane, and the first plane is parallel to the device epitaxial layer.

5. The semiconductor device structure of claim 1, wherein, The material of the negative capacitance dielectric layer comprises one or more than one combination of hafnium-based oxide, epsilon-type potassium oxide, barium titanate, lithium niobate, lithium titanate, or lead titanate.

6. The semiconductor device structure of claim 1, wherein, The preparation method of the negative capacitance dielectric layer comprises one or more than one arbitrary combination of metal organic chemical vapor deposition, molecular beam epitaxy, pulsed laser deposition, atomic layer deposition, or sputtering.

7. The semiconductor device structure of claim 1, wherein, The device epitaxial layer comprises a channel layer and a barrier layer, the barrier layer is located on the channel layer, the barrier layer comprises one or more than one arbitrary combination of InAlN, InAlGaN, and AlGaN, and the channel layer comprises GaN.

8. A method of fabricating a semiconductor device structure, characterized by, The preparation method is used for preparing the device structure according to any one of claims 1-7, and the preparation method comprises: providing a substrate layer; disposing the device epitaxial layer on the substrate layer; disposing the field plate dielectric layer on the device epitaxial layer; disposing the negative capacitance dielectric layer on the field plate dielectric layer; disposing the gate layer on a first side of the field plate dielectric layer and the negative capacitance dielectric layer; disposing the field plate electrode on the gate layer, and the field plate electrode extends from the first side towards a second side of the field plate dielectric layer and the negative capacitance dielectric layer to cover at least part of the negative capacitance dielectric layer; the device structure further comprises a source layer and a drain layer, and the field plate dielectric layer separates the gate layer, the source layer, and the drain layer; and the second side is a side of the field plate dielectric layer and the negative capacitance dielectric layer close to the drain layer.

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