A vertical transistor and its manufacturing method

Abstract

This invention discloses a vertical transistor and its manufacturing method, relating to the field of transistor technology. It addresses the technical problem that the size of existing transistors cannot be further reduced, and integrated circuits cannot accommodate more transistors. The solution includes: a source, a gate, a drain, and a channel, with the source and drain spaced vertically apart; a sandwich structure is disposed between the source and drain; the sandwich structure includes a gate, a first insulating layer bonded to the lower surface of the gate, and a second insulating layer bonded to the upper surface of the gate, the gate being made of graphene; the channel includes a first end and a second end connected to the drain and source respectively, and a middle portion corresponding to the sidewalls of the sandwich structure; a gate dielectric layer is disposed between the middle portion of the channel and the sidewalls of the sandwich structure. This invention can reduce the size of transistors in both the vertical and horizontal directions, while enhancing transistor layout capabilities, allowing integrated circuits to accommodate more transistors.

Description

Technical Field

[0001] This invention relates to the field of transistor technology, and more particularly to a vertical transistor and its manufacturing method. Background Technology

[0002] In recent decades, as described by the famous Moore's Law (proposed by Gordon Moore in 1965, the core of which states that the number of transistors that can be placed on an integrated circuit roughly doubles every 18 months), transistor size has needed to be continuously reduced to meet the exponential growth in the number of transistors per unit area of ​​integrated circuits over a yearly timescale. However, when the size of traditional planar devices shrinks to a certain process node, problems such as short-channel effects and large leakage currents emerge. Although strained silicon technology, HKMG technology, and SOI technology were further introduced, the miniaturization of traditional planar transistors became unsustainable when transistor size shrank to the 22nm node. Upon reaching the 22nm node, FinFETs (Fin Field Test Devices) replaced planar transistors with their improved gate potential control. Nevertheless, the scaling of FinFETs was quickly limited by the width of the fins and the spacing between them.

[0003] Therefore, how to further reduce the size of transistors in order to accommodate more transistors on integrated circuits has become a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a vertical transistor and a manufacturing method thereof, in order to solve the problem that the size of transistors in existing structures cannot be further reduced and integrated circuits cannot accommodate more transistors.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] The present invention provides a vertical transistor, including a source, a gate, a drain, and a channel, wherein the source and the drain are spaced apart in a vertical direction; a sandwich structure is disposed between the source and the drain; the sandwich structure includes a gate, a first insulating layer attached to the lower surface of the gate, and a second insulating layer attached to the upper surface of the gate, wherein the gate is made of graphene material; the channel includes a first end and a second end respectively connected to the drain and the source, and a middle portion corresponding to the sidewall of the sandwich structure; a gate dielectric layer is disposed between the middle portion of the channel and the sidewall of the sandwich structure.

[0007] Optionally, the drain is located above the source; the source has a connection portion offset from the drain along the horizontal direction; the channel is stepped, with the first end of the channel located on the upper surface of the drain, the second end of the channel located on the upper surface of the connection portion, the middle part of the channel located on one side of the sandwich structure, and a gate dielectric layer located between the middle part of the channel and the sidewall of the sandwich structure.

[0008] Optionally, the drain is located above the source, the sandwich structure is provided with a vertically penetrating first through groove, the first through groove is provided with the channel, the channel is a solid columnar structure, and the gate dielectric layer is provided between the outer wall of the channel and the inner wall of the first through groove.

[0009] Optionally, the drain is located above the source, and the channel is provided with a vertically penetrating second through groove; the sandwich structure is provided in the second through groove, the sandwich structure is a solid columnar structure, and the gate dielectric layer is provided between the outer wall of the sandwich structure and the inner wall of the second through groove.

[0010] Optionally, the channel is made of IGZO.

[0011] Optionally, both the source and the drain are configured as a double-layer structure consisting of a titanium layer and a gold layer.

[0012] This vertical transistor offers the following advantages: Compared to existing planar transistors and finned transistors, this invention employs a structure where the source and drain are spaced vertically. The source, drain, gate, and channel share a portion of the planar space, resulting in a smaller planar dimension. Furthermore, graphene is used as the gate. Graphene possesses excellent optical, electrical, and mechanical properties, and its thinness (1 nm for a single layer) allows for a gate length reduction to 1 nm, thereby enabling a reduction in channel length and ultimately decreasing the transistor's vertical dimension. This allows for the integration of more transistors within a given planar area and height.

[0013] In another aspect, the present invention provides a method for manufacturing a vertical transistor, comprising: performing photolithography on a substrate, electron beam evaporation of a source material, and stripping to form a source;

[0014] A first insulating layer is atomically deposited on the source electrode;

[0015] Graphene is wet-transferred and patterned on the first insulating layer to form a gate;

[0016] A second insulating layer is deposited on the gate at an atomic layer to form a sandwich structure;

[0017] A drain, a channel, and a gate dielectric layer are formed on the basis of the sandwich structure; the source and the drain are spaced apart in a vertical direction; the channel includes a first end and a second end connected to the drain and the source respectively, and a middle portion corresponding to the sidewall of the sandwich structure; the gate dielectric layer is disposed between the middle portion of the channel and the sidewall of the sandwich structure.

[0018] Optionally, the channel is stepped, with the middle portion of the channel located on one side of the sandwich structure. The sandwich structure forms a drain, a channel, and a gate dielectric layer, specifically including:

[0019] Photolithography, electron beam evaporation of drain material, and stripping are performed on the second insulating layer to form the drain;

[0020] The sandwich structure is etched to form a connection between the source electrode and the drain electrode that is offset in the horizontal direction;

[0021] Atomic layer gate dielectric material is atomically deposited on the upper surface of the connection portion, the sandwich structure, and the side of the drain electrode, and etched to form the gate dielectric layer;

[0022] Channel material is grown and patterned on the upper surface of the connection, the side of the gate dielectric layer, and the upper surface of the drain to form the channel.

[0023] Optionally, the sandwich structure is provided with a vertically penetrating first through slot, and the channel is provided within the first through slot; the formation of a drain, a channel, and a gate dielectric layer on the basis of the sandwich structure specifically includes:

[0024] The first through groove is etched into the sandwich structure;

[0025] Inside the first through-slot, an atomic layer of gate dielectric material is deposited on the upper surface of the source electrode and etched to form the gate dielectric layer, which has a ring structure.

[0026] Inside the gate dielectric layer, a channel material is magnetron sputtered onto the upper surface of the source electrode to form the channel;

[0027] The drain electrode material is photolithographically etched and electron beam evaporated on the upper surface of the channel to form the drain electrode.

[0028] Optionally, the channel is provided with a vertically penetrating second through slot, and the sandwich structure is disposed within the second through slot; the formation of a drain, a channel, and a gate dielectric layer on the basis of the sandwich structure specifically includes:

[0029] The sandwich structure is etched to create a vacant region at the source electrode that extends horizontally toward the outer periphery of the sandwich structure.

[0030] A gate dielectric material is deposited on the outer atomic layer of the sandwich structure on the upper surface of the vacant area to form the gate dielectric layer;

[0031] A channel material is atomically laminated on the outer periphery of the gate dielectric layer on the upper surface of the vacant region to form the channel;

[0032] The drain electrode is formed by photolithography, electron beam evaporation of the drain material, and stripping on the upper surface of the channel.

[0033] The manufacturing method of the vertical transistor provided by the present invention has the following beneficial effects: it can reduce the size of the vertical transistor in both the vertical and horizontal directions, and at the same time, it can effectively protect the graphene during the manufacturing process, preventing the graphene from being damaged and affecting its performance. Attached Figure Description

[0034] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0035] Figure 1 This is a schematic diagram of the structure of a vertical transistor shown in Embodiment 1 of the present invention;

[0036] Figure 2 This is a schematic diagram of the structure of the vertical transistor shown in Embodiment 2 of the present invention;

[0037] Figure 3 This is a schematic diagram of the structure of the vertical transistor shown in Embodiment 3 of the present invention;

[0038] Figure 4 for Figure 3 The diagram shows the structure of two vertically stacked transistors.

[0039] Figure 5 This is a schematic diagram of the vertical transistor formation process shown in Embodiment 1;

[0040] Figure 6 This is a schematic diagram of the vertical transistor formation process shown in Embodiment 2;

[0041] Figure 7 This is a schematic diagram of the vertical transistor formation process shown in Embodiment 3;

[0042] Figure 8 This is a flowchart illustrating a method for manufacturing a vertical transistor according to the present invention;

[0043] Figure 9 This is a flowchart illustrating the formation of a drain, channel, and gate dielectric layer based on a sandwich structure, as described in Embodiment 1 of the present invention.

[0044] Figure 10 A flowchart illustrating the process of forming a drain, channel, and gate dielectric layer based on a sandwich structure in Embodiment 2 of the present invention;

[0045] Figure 11 The flowchart of Embodiment 3 of the present invention for forming a drain, channel, and gate dielectric layer based on a sandwich structure.

[0046] Figure label:

[0047] 1. Source; 2. Drain; 3. Gate; 4. Channel; 5. Gate dielectric layer; 6. First insulating layer; 7. Second insulating layer; 8. Protective layer; 9. First through-slot; 11. Connecting portion; 12. Empty area; 41. First end; 42. Second end; 43. Middle portion; 44. Second through-slot. Detailed Implementation

[0048] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0049] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0050] This invention provides a vertical transistor, with reference to... Figures 1-3 It includes a source 1, a gate 3, a drain 2, and a channel 4. The source 1 and the drain 2 are spaced apart in a vertical direction. A sandwich structure is provided between the source 1 and the drain 2. The sandwich structure includes a gate 3, a first insulating layer 6 bonded to the lower surface of the gate 3, and a second insulating layer 7 bonded to the upper surface of the gate 3. The gate 3 is made of graphene material. The channel 4 includes a first end 41 and a second end 42 respectively connected to the drain 2 and the source 1, and a middle portion 43 corresponding to the sidewall of the sandwich structure. A gate dielectric layer 5 is provided between the middle portion 43 of the channel 4 and the sidewall of the sandwich structure.

[0051] Among existing transistors, there are planar transistors and finned transistors. Their source and drain are spaced apart in the horizontal direction, and their horizontal dimensions are relatively large.

[0052] In this invention, the vertical transistor has its source and drain electrodes spaced vertically, with the gate electrode positioned between them. The source, drain, gate, and channel share a portion of the horizontal space, reducing the horizontal dimension and allowing for more transistors to be arranged within the same area. Furthermore, the gate electrode is fabricated using graphene material with a single-layer thickness of 1 nm, miniaturizing the gate length to 1 nm. This further reduces the channel length, making it possible to reduce the vertical dimension of the transistor (the channel length must be greater than or equal to the gate length). More transistors can be stacked at the same height. Because this invention uses a vertical structure, the gate thickness becomes the gate length, and fabricating a single layer of graphene as the gate electrode is easily achieved. Existing transistors, when reducing the gate length (the horizontal dimension is the gate length), are limited by the precision of instruments such as photolithography machines, making the process difficult. This invention also employs a sandwich structure: a first insulating layer and a second insulating layer are respectively disposed on the lower and upper surfaces of the graphene. These first and second insulating layers effectively support and electrically isolate the graphene. This makes it possible to place graphene as a gate between the source and drain.

[0053] Reference Figure 1 and Figure 5 Embodiment 1 of the present invention will be described. The drain 2 is located above the source 1 (the drain 2 and the source 1 are interchangeable; when one of them is the drain, the other is the source); the source 1 is provided with a connection portion 11 that is offset from the drain 2 in the horizontal direction; the channel 4 is arranged in a stepped shape, the first end 41 of the channel is provided on the upper surface of the drain 2, the second end 42 of the channel 4 is provided on the upper surface of the connection portion 11, the middle part 43 of the channel 4 is provided on one side of the sandwich structure (6,3,7), and a gate dielectric layer 5 is provided between the middle part 43 of the channel 4 and the sidewall of the sandwich structure.

[0054] In this structure, the left side of the sandwich structure and drain 2 is a vertical plane, the gate dielectric layer 5 is a vertical plate structure located on the left side of the sandwich structure and drain 2, and the middle part 43 of the channel 4 is a vertical plate structure. With this structure, the shapes of each layer are relatively simple, and the manufacturing process is also relatively simple; each layer can be stacked using the corresponding process.

[0055] It should be noted that in actual manufacturing, leads can be drawn from the corresponding gate, drain, and source terminals according to actual needs, and the lead configuration should be determined according to actual needs.

[0056] Reference Figure 2 and Figure 6Embodiment 2 of the present invention will be described. The drain electrode 2 is located above the source electrode 1. The sandwich structure is provided with a vertically penetrating first through groove 9. A channel 4 is provided in the first through groove 9. The channel 4 is a solid columnar structure. A gate dielectric layer 5 is provided between the outer side wall of the channel 4 and the inner side wall of the first through groove 9.

[0057] In this structure, the gate control area is the inner circumferential area of ​​the gate 3. Compared to Embodiment 1, the left side area of ​​the gate 3 is larger (in Embodiment 2, it is the circumferential side area, while in Embodiment 1, it is only the single-sided side area). The larger the gate control area of ​​the transistor, the stronger the gate control capability. This structure has strong gate control capability. The channel 4 is a solid columnar structure, and each cross-section is a solid plane (there are no holes inside each cross-section). First, the channel 4 can be generated by magnetron sputtering, which is a relatively simple method. Second, the solid columnar structure has good formability. After forming, the forming effect of each part of the channel 4 is good (the physical properties of the material are consistent in all parts), and the performance of the channel 4 is good.

[0058] One or more first through slots 9 can be provided, and each first through slot 9 has a channel 4 inside. This can indirectly increase the gate control area and improve the gate control capability.

[0059] In this embodiment, the upper surface of the channel 4 is connected to the lower surface of the drain 2 as the first end 41, the lower surface of the channel 4 is connected to the upper surface of the source 1 as the second end 42, and the portion between the upper and lower surfaces of the channel 4 is the middle portion 43.

[0060] Reference Figure 3 , Figure 4 and Figure 7 Example 3 will be described below. The drain 2 is located above the source 1, and the channel 4 is provided with a vertically penetrating second through-slot 44; a sandwich structure is provided inside the second through-slot 44, the sandwich structure is a solid columnar structure, and a gate dielectric layer 5 is provided between the outer wall of the sandwich structure and the inner wall of the second through-slot 44. A protective layer 8 may be provided on the outer periphery of the channel 4, and an Al2O3 passivation layer may be selected as the protective layer.

[0061] Multiple second through slots 44 can be provided, and each second through slot 44 contains a sandwich structure. A gate dielectric layer is provided between the inner sidewall of each second through slot 44 and the outer sidewall of the sandwich structure. This can indirectly increase the gate control area and improve the gate control capability.

[0062] This structure facilitates the stacking of vertical transistors in the vertical direction. When stacked, two adjacent transistors can share a single electrode, which can serve as the drain (2) of the lower vertical transistor and simultaneously as the source (1) of the upper vertical transistor. This effectively reduces the vertical dimension of the vertical transistors, allowing for the stacking of more vertical transistors.

[0063] exist Figure 3 In the middle, the upper surface of the channel 4 is connected to the lower surface of the drain electrode 2 as the first end 41, the lower surface of the channel 4 is connected to the upper surface of the source electrode 1 as the second end 42, and the part between the upper and lower surfaces of the channel 4 is the middle part 43.

[0064] exist Figure 4 In this configuration, two vertically stacked transistors are arranged. The portion of the inner surface of channel 4 that contacts the common electrode serves as the first end 41 of the lower vertical transistor and is connected to it, while the portion serves as the second end 42 of the upper vertical transistor and is connected to it. The lower surface of channel 4 serves as the second end 42 and is connected to the upper surface of the source of the lower vertical transistor, while the upper surface of channel 4 serves as the first end 41 and is connected to the lower surface of the drain of the upper vertical transistor.

[0065] Of course, multiple vertical transistors can also be stacked in the vertical direction as needed.

[0066] The channel 4 can be made of IGZO, and the first insulating layer 6, the second insulating layer 7 and the gate dielectric layer 5 can be made of Al2O3.

[0067] Both source 1 and drain 2 are configured as a double-layer structure consisting of a titanium layer and a gold layer.

[0068] The present invention also provides a method for manufacturing a vertical transistor, referring to... Figure 8 Explanation may include:

[0069] S1, photolithography is performed on the substrate, the source material is evaporated by electron beam and then stripped to form the source.

[0070] Photolithography is performed on substrates such as Si or SiO2, 10nm of titanium is evaporated by electron beam, 30nm of gold is evaporated by electron beam, and then the substrate is stripped to obtain the source electrode of the desired shape.

[0071] S2, deposits the first insulating layer on the source electrode in atomic layers.

[0072] Materials such as Al2O3 are atomically deposited on the source electrode as the first insulating layer.

[0073] S3, graphene is wet-transferred and patterned in the first insulating layer to form a gate.

[0074] Wet transfer of monolayer graphene is preferred to minimize gate thickness.

[0075] S4, deposit a second insulating layer on the gate atomic layer to form a sandwich structure.

[0076] Materials such as Al2O3 are atomically deposited on the source electrode as a second insulating layer.

[0077] S5, a drain, a channel, and a gate dielectric layer are formed on the basis of the sandwich structure; the source and drain are spaced apart in the vertical direction, the channel includes a first end and a second end connected to the gate and drain respectively, and a middle part corresponding to the sidewall of the sandwich structure; a gate dielectric layer is disposed between the middle part of the channel and the sidewall of the sandwich structure.

[0078] This manufacturing method first forms a sandwich structure on the source electrode, where the first and second insulating layers effectively support and electrically isolate the graphene. Then, other structures are fabricated based on this sandwich structure, effectively protecting the graphene during manufacturing and processing to prevent damage that could affect its performance.

[0079] Reference Figure 5 and Figure 9 The manufacturing method of Example 1 will be described as follows:

[0080] After the sandwich structure is formed.

[0081] S511, photolithography is performed on the second insulating layer, the drain material is evaporated by electron beam and then stripped to form the drain.

[0082] Photolithography is performed on the second insulating layer, 10nm of titanium is evaporated by electron beam, then 30nm of gold is evaporated by electron beam, and then the material is peeled off to obtain the drain of the desired shape.

[0083] S512, etch the sandwich structure to form a connection between the source and the drain that is offset in the horizontal direction;

[0084] S513, gate dielectric material is atomically deposited on the upper surface of the connector, the sandwich structure and the side of the drain and etched to form a gate dielectric layer;

[0085] S514, a channel material is grown and patterned on the upper surface of the connector, the side of the gate dielectric layer, and the upper surface of the drain to form a channel.

[0086] It should be noted that a vertical transistor naturally includes a protective layer and leads for each electrode. A protective layer can be grown on the upper surface of the channel as needed; an Al2O3 passivation layer can be selected as the protective layer. The lead fabrication process can be specifically configured as required; however, the details of lead fabrication are existing technology and will not be described in detail here. For example, when fabricating the gate lead, a via extending to the gate is etched into the portion of the upper surface of the second insulating layer 7 not covered by the drain, and a metal contact is grown there.

[0087] Reference Figure 6 and Figure 10 The manufacturing method of Example 2 will be described as follows:

[0088] After the sandwich structure is formed.

[0089] S521, the first through groove 9 is etched into the sandwich structure.

[0090] One or more first through grooves 9 can be etched as needed, and the first through grooves 9 penetrate the sandwich structure.

[0091] S522, the gate dielectric material is deposited in the atomic layer inside the first channel and on the upper surface of the source electrode and etched to form a gate dielectric layer, which has a ring structure.

[0092] S523 uses magnetron sputtering of channel material inside the gate dielectric layer and on the upper surface of the source to form a channel.

[0093] S524, the drain material is photolithographically etched and electron beam evaporated on the upper surface of the channel to form the drain.

[0094] When fabricating the gate leads, a via can be etched from the upper surface of the drain to the gate, and a metal contact can be grown inside the via. An insulating layer is added between the metal contact and the inner wall of the via on the drain to electrically isolate the gate leads from the drain.

[0095] Reference Figure 7 and Figure 11 The manufacturing method of Example 3 will be described as follows:

[0096] After the sandwich structure is formed.

[0097] S531, the sandwich structure is etched to form a vacant region 12 extending horizontally to the outer periphery of the sandwich structure.

[0098] After etching, the sandwich structure can be a single solid pillar or multiple spaced solid pillars. The portion of the source's upper surface not covered by the sandwich structure forms a void area.

[0099] S532, a gate dielectric material is deposited on the upper surface of the vacant area and the outer periphery of the sandwich structure to form a gate dielectric layer, and the gate dielectric layer is wrapped in a ring on the outer wall of the sandwich structure.

[0100] S533, channel material is atomically laminated on the upper surface of the vacant area and the outer periphery of the gate dielectric layer to form a channel. During the channel forming process, a second through groove is naturally formed. The second through groove runs through the channel (rather than a second through groove processed by etching or other processes). The inner sidewall of the second through groove wraps around the outer sidewall of the gate dielectric layer.

[0101] S534 involves photolithography, electron beam evaporation of metal, and stripping on the upper surface of the channel to form the drain.

[0102] A protective layer 8 can be grown on the upper surface of the source and the outer periphery of the channel. An Al2O3 passivation layer can be selected as the protective layer. When fabricating the gate leads, a via can be etched from the upper surface of the drain to the gate, and a metal contact can be grown in the via. An insulating layer is added between the metal contact and the inner sidewall of the via on the drain to electrically isolate the gate leads from the drain.

[0103] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art will understand and implement other variations of the disclosed embodiments by reviewing the accompanying drawings, the disclosure, and the appended claims in carrying out the claimed invention. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While different dependent claims may recite certain measures, this does not mean that these measures cannot be combined to produce good results.

[0104] Although the invention has been described in conjunction with specific features and embodiments, it is obvious that various modifications and combinations can be made therein without departing from the spirit and scope of the invention. Accordingly, this specification and drawings are merely exemplary descriptions of the invention as defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the invention. Clearly, those skilled in the art can make various alterations and modifications to the invention without departing from its spirit and scope. Thus, if such modifications and modifications of the invention fall within the scope of the claims and their equivalents, the invention is also intended to include such modifications and modifications.

Claims

1. A vertical transistor comprising a source, a gate, a drain and a channel, characterized in that, The source and the drain are arranged in a vertical direction; a sandwich structure is arranged between the source and the drain; the sandwich structure comprises a gate, a first insulating layer attached to the lower surface of the gate, and a second insulating layer attached to the upper surface of the gate, the gate is made of graphene material; the channel comprises a first end and a second end connected to the drain and the source respectively, and a middle part corresponding to the sidewall of the sandwich structure; a gate dielectric layer is arranged between the middle part of the channel and the sidewall of the sandwich structure. The drain is located above the source; the source is arranged in a horizontal direction and has a connecting part staggered with the drain; the channel is arranged in a stepped shape, the first end of the channel is arranged on the upper surface of the drain, the second end of the channel is arranged on the upper surface of the connecting part, the middle part of the channel is arranged on one side of the sandwich structure, and a gate dielectric layer is arranged between the middle part of the channel and the sidewall of the sandwich structure; the source, drain, gate and channel share a part of the horizontal space.

2. The vertical transistor of claim 1, wherein The channel is made of IGZO.

3. The vertical transistor of claim 1, wherein The source and the drain are both arranged as a double-layer structure composed of a titanium layer and a gold layer.

4. A method of manufacturing a vertical transistor, characterized by, Comprising: Performing photolithography, electron beam evaporation of source material and peeling on a substrate to form a source; Atomic layer deposition of a first insulating layer on the source; Wet transfer of graphene on the first insulating layer and patterning to form a gate; Atomic layer deposition of a second insulating layer on the gate to form a sandwich structure; Forming a drain, a channel and a gate dielectric layer on the basis of the sandwich structure; the source and the drain are arranged in a vertical direction, the channel comprises a first end and a second end connected to the drain and the source respectively, and a middle part corresponding to the sidewall of the sandwich structure; the gate dielectric layer is arranged between the middle part of the channel and the sidewall of the sandwich structure; The channel is arranged in a stepped shape, the middle part of the channel is arranged on one side of the sandwich structure, and the drain, the channel and the gate dielectric layer are formed on the basis of the sandwich structure, specifically comprising: Performing photolithography, electron beam evaporation of drain material and peeling on the second insulating layer to form the drain; Etching the sandwich structure to form a connecting part of the source staggered with the drain in a horizontal direction; atomic layer deposition of gate dielectric layer material on the upper surface of the connecting part, the sidewall of the sandwich structure and the edge of the drain and etching to form the gate dielectric layer; growing channel material on the upper surface of the connecting part, the edge of the gate dielectric layer and the upper surface of the drain and patterning to form the channel; the source, drain, gate and channel share a part of the horizontal space.

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