Signal receiving method, device, electronic device and storage medium

Abstract

The embodiments of the present invention provide a signal receiving method, device, electronic device and storage medium, which relate to the field of signal transmission. The signal receiving method includes: receiving a target differential signal; providing a local clock signal, wherein the local clock signal is a clock signal generated by the signal receiving device; synchronizing the target differential signal according to the local clock signal to obtain a destination signal; and controlling the signal receiving state of the signal receiving device according to the destination signal, wherein the signal receiving state includes a high-speed state and a low-speed state. The signal receiving method, device, electronic device and storage medium provided by the embodiments of the present invention have the advantage of being able to control the signal receiving device to reset autonomously when the signal receiving device enters a receiving error state.

Description

Technical Field

[0001] The present invention relates to the field of signal transmission, and in particular to a signal receiving method, device, electronic equipment and storage medium. Background Art

[0002] MIPI stands for Mobile Industry Processor Interface. It is an open standard and specification initiated by the MIPI Alliance for mobile application processors. The purpose of the MIPI Alliance is to standardize various interfaces such as cameras, display interfaces, RF / baseband interfaces, etc., so as to reduce the complexity of electronic device design and increase design flexibility. The MIPI Alliance has defined a series of mobile phone internal interface standards, such as camera interface (CMOSSerial Interface, CSI), display interface (Display Serial Interface, DSI), RF interface (DigitalRF, DigRF), microphone / speaker interface (Serial Low-power Inter-chip Media Bus, SLIMbus), etc. At present, the more mature and commonly used standards are DSI (Display Serial Interface, Display Serial Interface) and CSI (Camera Serial Interface, Camera Serial Interface). Among them, the physical layer of CSI and DSI follows the D-PHY (one of the MIPI protocols, D-PHY provides the definition of DSI and CSI at the physical layer) standard.

[0003] D-PHY supports two transmission modes: LP (Low Power) mode and HS (High Speed) mode. In LP mode, the data transmission rate is very low (usually no more than 20Mbps), and the corresponding power consumption is also very low. In HS mode, the transmission rate is very high (usually 80Mbps to 2.5Gbps), but the power consumption is relatively high.

[0004] During the signal transmission process, the signal receiving device can switch between LP mode and HS mode according to different needs. In the traditional solution, when the signal receiving device is ready to exit the HS mode, the signal sending end will send a control signal so that the signal receiving device can smoothly exit the HS mode and return to the LP mode. However, if the control signal sent by the signal sending end is incorrect or the control signal changes during the signal transmission process, causing the receiving device to receive an erroneous control signal, the state machine will enter the receiving error state. In this state, the signal receiving device cannot receive the clock signal sent by the signal sending end, causing the signal receiving device to hang. Unless the signal receiving device is asynchronously reset, the signal receiving device will never be able to recover. Summary of the invention

[0005] The object of the present invention is to provide a signal receiving method, device, electronic device and storage medium, which can control the signal receiving device to reset autonomously when the signal receiving device enters a receiving error state.

[0006] In the first aspect, an embodiment of the present invention provides a signal receiving method, which is applied to a signal receiving device, including: receiving a target differential signal; providing a local clock signal, wherein the local clock signal is a clock signal generated by the signal receiving device; synchronizing the target differential signal according to the local clock signal to obtain a destination signal; and controlling the signal receiving state of the signal receiving device according to the destination signal, wherein the signal receiving state includes a high-speed state and a low-speed state.

[0007] In some embodiments of the present invention, before the target differential signal is synchronously processed according to the local clock signal to obtain the target signal, the method further includes: extracting a recovery clock signal from the target differential signal; using the local clock signal to perform edge detection on the recovery clock signal to obtain a change pulse signal; performing AND logic processing on the change pulse signal and the target differential signal to obtain an AND logic processing signal; the target differential signal is synchronously processed according to the local clock signal to obtain the target signal, including: performing synchronization processing on the AND logic processing signal according to the local clock signal to obtain the target signal. Extracting a recovery clock signal from the target differential signal; and using the local clock signal to perform edge detection on the recovery clock signal to achieve phase synchronization between the local clock signal and the recovery clock signal, so that the local clock signal can be phase synchronized with the target differential signal when the target differential signal is subsequently processed.

[0008] In some embodiments of the present invention, performing AND logic processing on the changing pulse signal and the target differential signal includes: combining the target differential signal according to line combination logic to generate a combined signal; and performing AND logic processing on the combined signal and the changing pulse signal.

[0009] In some embodiments of the present invention, the target differential signal is synchronously processed according to the local clock signal to obtain the target signal, including: sampling the target differential signal according to the local clock signal to obtain a sampled signal; performing timing counting on the sampled signal to obtain a counting result; and generating the target signal according to the relationship between the counting result and a pre-designed value. Since the local clock signal is a signal generated by the signal receiving device itself, its frequency may not be affected by the data rate of the signal sent by the signal transmitting end, and the timing counting process is added. During the timing counting process, the pre-designed value can be adjusted according to actual needs, so there will be no problem that the THS-SETTLE duration exceeds the duration range defined in the MIPI protocol.

[0010] In some embodiments of the present invention, sampling the target differential signal according to the local clock signal includes: using a D-type flip-flop to sample the target differential signal according to the local clock signal.

[0011] In some embodiments of the present invention, before generating the received logic signal according to the magnitude relationship between the counting result and the pre-designed value, the method further includes: obtaining the data rate of the target differential signal; and obtaining the pre-designed value according to the data rate. Selecting the corresponding pre-designed value according to the data rate of the target differential signal can further avoid the problem that the THS-SETTLE duration exceeds the duration range defined in the MIPI protocol.

[0012] In some embodiments of the present invention, the local clock signal is an oscillating clock signal generated by an oscillator in the signal receiving device.

[0013] In some embodiments of the present invention, the frequency of the local clock signal is greater than 90 MHz and less than 110 MHz.

[0014] In the second aspect, an embodiment of the present invention provides a signal receiving device, comprising: a signal receiving module, the signal receiving module is used to receive a target differential signal; a clock signal generating module, the clock signal generating module is used to generate a local clock signal; a control module, the control module is used to synchronize the target differential signal according to the local clock signal to obtain a destination signal, and control the signal receiving state of the signal receiving device according to the destination signal, the signal receiving state including a high-speed state and a low-speed state.

[0015] In some embodiments of the present invention, the clock signal generating module is an oscillator.

[0016] In some embodiments of the present invention, the control module includes a sampling submodule, a counting submodule and a judgment submodule; the sampling submodule is used to sample the target differential signal according to the local clock signal to obtain a sampling signal; the counting submodule is used to perform time counting on the sampling signal to obtain a counting result; the judgment submodule is used to generate the destination signal according to the size relationship between the counting result and a pre-designed numerical value.

[0017] In a third aspect, an embodiment of the present invention provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the signal receiving method as described above.

[0018] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium storing a computer program, wherein the computer program is executed by a processor to implement the aforementioned signal receiving method.

[0019] Compared with the prior art, in the signal receiving method, device, electronic device and storage medium provided by the embodiments of the present invention, when receiving the target differential signal sent by other devices, the signal receiving device autonomously generates a constant clock signal as a local clock signal, uses the local clock signal to synchronize the target differential signal, parses the target signal contained in the target differential signal, and finally controls the signal receiving device to use a high-speed state or a low-speed state for signal reception according to the target signal; since the local clock signal is a clock signal generated by the signal receiving device itself and is not affected by the signal sending end, it can be ensured that even if the signal sending end sends an erroneous control signal, causing the signal receiving device to enter a receiving error state, the local clock signal can be used to continue subsequent signal processing, that is, the signal receiving device is controlled to reset autonomously when it enters a receiving error state. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A schematic diagram of a flow chart of a signal receiving method provided in Embodiment 1 of the present invention;

[0022] Figure 2 It is the waveform diagram of some differential signals;

[0023] Figure 3 A schematic diagram of a synchronous processing process for a target differential signal;

[0024] Figure 4 A schematic diagram of a flow chart of a signal receiving method provided in Embodiment 2 of the present invention;

[0025] Figure 5 A schematic diagram of a signal receiving method provided in Embodiment 1 of the present invention;

[0026] Figure 6 is a waveform diagram of a target differential signal and a recovered clock signal;

[0027] Figure 7 A schematic diagram of a signal receiving state switching process of a signal receiving device in the prior art;

[0028] Figure 8 A schematic diagram of a signal receiving state switching process of a signal receiving device according to an embodiment of the present invention;

[0029] Fig. 9 A schematic diagram of the structure of a signal receiving device provided in Embodiment 3 of the present invention;

[0030] Fig.10 A schematic diagram of the structure of a signal receiving device provided in Embodiment 4 of the present invention;

[0031] Fig.11 This is a schematic diagram of the structure of an electronic device provided in Embodiment 5 of the present invention. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0033] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0034] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0035] In the description of the present invention, it should be noted that if the terms "upper", "lower", "inside", "outside", etc. appear to indicate an orientation or position relationship, they are based on the orientation or position relationship shown in the accompanying drawings, or are the orientation or position relationship in which the product of the invention is usually placed when used. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0036] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0037] It should be noted that, in the absence of conflict, the features in the embodiments of the present invention may be combined with each other.

[0038] Embodiment 1 of the present invention provides a signal receiving method, which is applied to a signal receiving device, such as Figure 1 As shown, the specific steps include:

[0039] Step S101: receiving a target differential signal.

[0040] Specifically, the target differential signal is the differential signal from the signal transmitting end received by the signal receiving device. The differential signal is a signal form transmitted via differential transmission. Differential transmission is a signal transmission technology. Different from the traditional method of one signal line and one ground line, differential transmission transmits signals on both lines. The amplitudes of the two signals are the same. The signals transmitted on the two lines are differential signals. Figure 2 FIG. 2 is a waveform diagram of a partial differential signal, wherein Dp and Dn are waveforms of two of the differential signals respectively.

[0041] Step S102: providing a local clock signal.

[0042] Specifically, the local clock signal is a clock signal generated by the signal receiving device itself. Since the local clock signal is a clock signal generated by an electronic device arranged in the signal receiving device, the local clock signal is not affected by the signal sender, can maintain a constant clock frequency, a constant amplitude, and is not prone to interruption and other problems. In some embodiments of the present invention, an oscillator is arranged in the signal receiving device, and the local clock signal is an oscillating clock signal generated by the oscillator. It can be understood that the aforementioned local clock signal is an oscillating clock signal generated by the oscillator, which is only an example in some embodiments of the present invention and does not constitute a limitation. In some other embodiments of the present invention, electronic devices with other structures such as clock generators can also be arranged in the signal receiving device, and clock signals are generated by electronic devices with other structures such as clock generators as local clock signals. Specifically, it can be flexibly set according to actual needs, and it is only necessary to ensure that the local clock signal has the aforementioned constant clock frequency, constant amplitude, and is not prone to interruption and other characteristics.

[0043] Step S103: Synchronize the target differential signal according to the local clock signal to obtain a destination signal.

[0044] Specifically, the MIPI protocol defines some key timing conditions that must be met, including that when starting the high-speed transmission mode, the signal receiving device must switch from the low-power transmission mode to the high-speed transmission mode within the THS-SETTLE time range required by the protocol (generally by controlling the internal receiving logic signal HSRXEN, the default low-speed transmission HSRXEN = 0, after the THS-SETTLE time, HSRXEN = 1, at this time it has switched to the high-speed transmission mode, after the high-speed transmission ends, the receiving logic signal HSRXEN switches back to 0). The control digital logic of the receiving logic signal HSRXEN must be based on a clock signal. In the prior art, a clock signal defined by the signal transmitter is usually used, and this clock signal is easily affected by the signal transmission data rate. When the transmission data rate does not exceed 20Mbps, the frequency of this clock signal does not exceed 20MHz. When the transmission data rate reaches [80Mbps, 2.5Gbps], the frequency of this clock signal reaches [10MHz, 312.5MHz].

[0045] Assuming that the frequency of this clock signal is 10MHz, when the transmission data rate is 80Mbps, 1UI=1 / 80MHz=12.5ns (nanoseconds), the THS-SETTLE time range required by the protocol is [85ns+6*UI,145ns+10*UI], which is equal to [160ns,270ns]. At this time, the actual circuit THS-SETTLE time is [200ns,300ns], which exceeds the maximum THS-SETTLE time range.

[0046] Assuming the frequency of this clock signal is 20MHz, when the transmission data rate is 2.5Gbps, 1UI=1 / 2.5GHz=0.4ns (nanoseconds), then the THS-SETTLE range requirement for this rate is [87.4ns, 149ns]. The actual circuit THS-SETTLE is [53.2ns, 56.4ns], which violates the minimum THS-SETTLE range.

[0047] In some embodiments of the present invention, Figure 3 As shown, firstly, the local clock signal (OSC_CLK) is used to sample the target differential signal Dp and Dn (Dp and Dn together constitute the target differential signal LPRX) respectively to obtain the sampling signal. Then, the sampling signal is counted (Count) to obtain the timing counting result; finally, the destination signal is generated according to the size relationship between the counting result and the pre-designed value (SET_CNT), and the destination signal is used to control the internal receiving logic signal HSRXEN. Since the local clock signal is a signal generated by the signal receiving device itself, its frequency may not be affected by the data rate of the signal sent by the signal transmitting end, and the timing counting process is added. During the timing counting process, the pre-designed value can be adjusted according to actual needs, so there will be no problem that the THS-SETTLE duration exceeds the duration range defined in the MIPI protocol.

[0048] In some embodiments of the present invention, the frequency of the local clock signal may be set to be greater than 90 MHz and less than 110 MHz.

[0049] Furthermore, in some embodiments of the present invention, a D-type trigger (delay flip flop, DFF) may be used to sample the target differential signal. It is understood that the aforementioned use of a D-type trigger to sample the target differential signal is only a specific example in the embodiments of the present invention and does not constitute a limitation.

[0050] In some embodiments of the present invention, the pre-designed value may be obtained according to the data rate of the target differential signal. For example, a correspondence between a plurality of pre-designed values ​​and the data rate of the target differential signal is pre-set, and during the actual signal transmission process, the corresponding pre-designed value is selected according to the data rate of the target differential signal. By selecting the corresponding pre-designed value according to the data rate of the target differential signal, the problem of the THS-SETTLE duration exceeding the duration range defined in the MIPI protocol can be further avoided.

[0051] Step S104: controlling the signal receiving state of the signal receiving device according to the destination signal, the signal receiving state including a high speed state and a low speed state.

[0052] In some embodiments of the present invention, when the destination signal received by the signal receiving device is a preset state switching signal, the signal receiving state is switched. The preset state switching signal is a signal mode that has been preset by each signal receiving device, so when the destination signal received is the preset state switching signal, the signal receiving state is switched.

[0053] In some embodiments of the present invention, the low speed state is the LP (Low Power) mode in the D-PHY standard, and the high speed state is the HS (High Speed) mode in the D-PHY standard.

[0054] Compared with the prior art, in the signal receiving method provided in the first embodiment of the present invention, when receiving the target differential signal sent by other devices, the signal receiving device autonomously generates a constant clock signal as a local clock signal, uses the local clock signal to synchronize the target differential signal, parses the target signal contained in the target differential signal, and finally controls the signal receiving device to use a high-speed state or a low-speed state for signal reception according to the target signal; since the local clock signal is a clock signal generated by the signal receiving device itself and is not affected by the signal sending end, it can be ensured that even if the signal sending end sends an erroneous control signal, causing the signal receiving device to enter a receiving error state, the local clock signal can be used to continue subsequent signal processing, that is, the signal receiving device is controlled to reset autonomously when it enters a receiving error state.

[0055] Embodiment 2 of the present invention provides a signal receiving method, which is applied to a signal receiving device, such as Figure 4 and Figure 5 As shown, the specific steps include:

[0056] Step S201: Receive a target differential signal.

[0057] Step S202: Provide a local clock signal.

[0058] Step S203: extracting a recovered clock signal from the target differential signal.

[0059] Specifically, in some embodiments of the present invention, the target differential signal may be subjected to XOR logic processing to extract the recovered clock signal from the target differential signal. Figure 6 Shown are the target differential signals Dp and Dn, and the recovered clock signal obtained thereafter.

[0060] Step S204: Use the local clock signal to perform edge detection on the recovered clock signal to obtain a changing pulse signal.

[0061] Specifically, in some embodiments of the present invention, a local clock signal is used to perform edge detection (Edge Det) on a recovered clock signal, that is, the local clock signal is used as a reference clock to detect a rising edge or a falling edge of the recovered clock signal, thereby achieving phase synchronization between the local clock signal and the recovered clock signal.

[0062] Step S205: performing AND logic processing on the changing pulse signal and the target differential signal to obtain an AND logic processing signal.

[0063] In some embodiments of the present invention, it is first necessary to combine the target differential signals according to the line state combination logic to generate a combination signal; then the combination signal and the change pulse signal are ANDed. For example, the combination signal generated by the LPDP / LPDN line state combination logic combination can be LPRX11, LPRX00, LPRX01, LPRX10 (where LPRX01 represents LPDP=0, LPDN=1, and LP represents low speed mode).

[0064] Step S206: Synchronize the logic processing signal with the local clock signal to obtain the destination signal.

[0065] It can be understood that steps S201, S202, and S206 in the signal receiving method provided in the second embodiment of the present invention are substantially the same as steps S101 to S103 in the first embodiment, and the details may refer to the specific description in the aforementioned embodiment, which will not be repeated here.

[0066] Compared with the prior art, in the signal receiving method provided in the second embodiment of the present invention, a recovered clock signal is extracted from the target differential signal; and the local clock signal is used to perform edge detection on the recovered clock signal to achieve phase synchronization between the local clock signal and the recovered clock signal, so that the local clock signal can be phase synchronized with the target differential signal when processing the target differential signal subsequently.

[0067] Specifically, Figure 7The figure shows a schematic diagram of the signal receiving state switching process of the signal receiving device in the prior art. In the conventional solution, when the signal receiving device is ready to exit the LPD_RX_HS state, i.e., the high-speed transmission state, the process specified by the protocol is that the signal receiving device receives the control signal of LPRX01->LPRX11, so that the signal receiving device can pass through the LPD_RX_HS_END (i.e., the intermediate process of state conversion) state and smoothly return to the LPD_RX_IDLE, i.e., the idle state. However, if the protocol of the transmitting end is sent incorrectly, resulting in the receiving end receiving the state of LPRX10->LPRX11, the state machine will enter the LPD_RX_ERROR, i.e., the receiving error state. In this state, the signal receiving device cannot receive the clock signal sent by the signal transmitting end, causing the signal receiving device to hang up. In the conventional solution, when the signal receiving device is ready to enter the LPD_RX_HS state, the process specified by the protocol is that the signal receiving device receives the control signal of LPRX01->LPRX00, so that the signal receiving device can pass through the LPD_RX_LP01 (i.e., the intermediate process of state conversion) state and smoothly enter the LPD_RX_HS state.

[0068] And in Figure 8 As shown in some embodiments of the present invention, during the switching process of the signal receiving state, if the sending end sends the protocol incorrectly, although it will also cause the receiving end to enter the LPD_RX_ERROR error state, due to the existence of the local clock signal OSC_CLK, based on the prior art, the signal received by the signal receiving device will be ANDed (AND, and logical processing) Lprx_pu signal, so the signal receiving device can use the local clock signal to continue the subsequent signal processing, and the system will automatically enter the LPD_RX_IDLE idle state, so that the system can recover without additional reset operations when it knows that an error has occurred. When the signal receiving device is ready to enter the LPD_RX_HS state, the process specified by the protocol is that the signal receiving device receives the control signal of LPRX01->LPRX00, so that the signal receiving device can pass through the LPD_RX_LP01 (i.e., the intermediate process of state conversion) state and smoothly enter the LPD_RX_HS state.

[0069] Embodiment 3 of the present invention provides a signal receiving device, such as Fig. 9 As shown, it includes: a signal receiving module 701, the signal receiving module 701 is used to receive a target differential signal; a clock signal generating module 702, the clock signal generating module 702 is used to generate a local clock signal; a control module 703, the control module 703 is used to synchronize the target differential signal according to the local clock signal to obtain a target signal, and control the signal receiving state of the signal receiving device according to the target signal, and the signal receiving state includes a high-speed state and a low-speed state.

[0070] Compared with the prior art, in the signal receiving device provided in the third embodiment of the present invention, when the signal receiving module 701 receives the target differential signal sent by other devices, the clock signal generating module 702 autonomously generates a constant clock signal as a local clock signal, and the control module 703 uses the local clock signal to synchronize the target differential signal, parses out the destination signal contained in the target differential signal, and finally controls the signal receiving device to use a high-speed state or a low-speed state for signal reception according to the destination signal; since the local clock signal is a clock signal generated by the clock signal generating module 702 itself and is not affected by the signal sending end, it can be ensured that even if the signal sending end sends an erroneous control signal, causing the signal receiving device to enter a receiving error state, the local clock signal can be used to continue subsequent signal processing, that is, the signal receiving device is controlled to reset autonomously when it enters a receiving error state.

[0071] Furthermore, in some embodiments of the present invention, the control module 703 includes a sampling submodule 704, a counting submodule 705 and a judgment submodule 706; the sampling submodule 704 is used to sample the target differential signal according to the local clock signal to obtain the sampling signal; the counting submodule 705 is used to perform time counting on the sampling signal to obtain the counting result; the judgment submodule 706 is used to generate the target signal according to the size relationship between the counting result and the pre-designed numerical value.

[0072] It is not difficult to find that embodiment three of the present invention is an embodiment of the device corresponding to embodiment one of the present invention. Therefore, all technical details in embodiment three of the present invention can also be applied to embodiment one of the present invention, and have the same technical effects as embodiment three; similarly, all technical details in embodiment one of the present invention can also be applied to embodiment three of the present invention, and have the same technical effects as embodiment one, which will not be repeated here.

[0073] Embodiment 4 of the present invention provides a signal receiving device, such as Fig.10 As shown, it includes: a signal receiving module 701, a clock signal generating module 702, a control module 703, a clock signal recovery module 707, an edge detection module 708, an AND logic processing module 709, and a signal combining module 710. Among them, the clock signal recovery module 707 is used to extract the recovered clock signal from the target differential signal; the edge detection module 708 is used to use the local clock signal to perform edge detection on the recovered clock signal to obtain a change pulse signal; the signal combining module 710 is used to combine the target differential signal according to the line state combination logic to generate a combined signal; and the AND logic processing module 709 is used to perform AND logic processing on the combined signal and the change pulse signal.

[0074] Compared with the prior art, in the signal receiving device provided in the fourth embodiment of the present invention, a clock signal recovery module 707 is used to extract a recovered clock signal from the target differential signal; the edge detection module 708 uses a local clock signal to perform edge detection on the recovered clock signal to achieve phase synchronization between the local clock signal and the recovered clock signal, so that the local clock signal can be phase synchronized with the target differential signal when processing the target differential signal subsequently.

[0075] It is not difficult to find that the fourth embodiment of the present invention is an embodiment of the device corresponding to the second embodiment of the present invention. Therefore, all the technical details in the fourth embodiment of the present invention can also be applied to the second embodiment of the present invention, and have the same technical effects as the fourth embodiment; similarly, all the technical details in the second embodiment of the present invention can also be applied to the fourth embodiment of the present invention, and have the same technical effects as the second embodiment, which will not be repeated here.

[0076] A fifth embodiment of the present invention relates to an electronic device, such as Fig.11 As shown, it includes: at least one processor 901; and a memory 902 that is communicatively connected to the at least one processor 901; wherein the memory 902 stores instructions that can be executed by the at least one processor 901, and the instructions are executed by the at least one processor 901 so that the at least one processor 901 can execute the signal receiving method in the above-mentioned embodiments.

[0077] Among them, the memory and the processor are connected in a bus manner, and the bus may include any number of interconnected buses and bridges, and the bus connects various circuits of one or more processors and memories together. The bus can also connect various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be one element or multiple elements, such as multiple receivers and transmitters, providing a unit for communicating with various other devices on a transmission medium. The data processed by the processor is transmitted on a wireless medium via an antenna, and further, the antenna also receives data and transmits the data to the processor.

[0078] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0079] Embodiment 6 of the present invention relates to a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the above method embodiment is implemented.

[0080] That is, those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk and other media that can store program codes.

[0081] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A signal receiving method, characterized in that: Applicable to signal receiving devices, including: receiving a target differential signal; Providing a local clock signal, wherein the local clock signal is a clock signal generated by the signal receiving device; extracting a recovered clock signal from the target differential signal; Use the local clock signal to perform edge detection on the recovered clock signal to obtain a changing pulse signal; Performing AND logic processing on the change pulse signal and the target differential signal to obtain an AND logic processing signal; Synchronously processing the AND logic processing signal according to the local clock signal to obtain a destination signal; The signal receiving state of the signal receiving device is controlled according to the destination signal, and the signal receiving state includes a high-speed state and a low-speed state.

2. The method according to claim 1, characterized in that The step of performing AND logic processing on the change pulse signal and the target differential signal comprises: Combining the target differential signals according to line state combination logic to generate a combined signal; The combined signal and the changing pulse signal are subjected to AND logic processing.

3. The method according to claim 1, characterized in that The step of synchronously processing the target differential signal according to the local clock signal to obtain the destination signal includes: Sampling the target differential signal according to the local clock signal to obtain a sampled signal; Performing time series counting on the sampling signal to obtain a counting result; The target signal is generated according to the magnitude relationship between the counting result and the pre-designed value.

4. The method according to claim 3, characterized in that The sampling of the target differential signal according to the local clock signal comprises: The target differential signal is sampled using a D-type flip-flop according to the local clock signal.

5. The method according to claim 3, characterized in that: Before generating the target signal according to the magnitude relationship between the counting result and the pre-designed value, the method further includes: Acquiring a data rate of the target differential signal; The pre-designed value is obtained according to the data rate.

6. The method according to claim 1, characterized in that The local clock signal is an oscillating clock signal generated by an oscillator in the signal receiving device.

7. The method according to claim 1, characterized in that The frequency of the local clock signal is greater than 90 MHz and less than 110 MHz.

8. A signal receiving device, characterized in that: include: A signal receiving module, wherein the signal receiving module is used to receive a target differential signal; A clock signal generating module, wherein the clock signal generating module is used to generate a local clock signal; A clock signal recovery module, the clock signal recovery module is used to extract a recovery clock signal from a target differential signal; An edge detection module, the edge detection module is used to use the local clock signal to perform edge detection on the recovered clock signal to obtain a change pulse signal; An AND logic processing module is used to perform AND logic processing on the combined signal and the changing pulse signal to obtain an AND logic processing signal; A control module, the control module is used to synchronize the AND logic processing signal according to the local clock signal to obtain a destination signal, and control the signal receiving state of the signal receiving device according to the destination signal, the signal receiving state including a high-speed state and a low-speed state.

9. The device according to claim 8, characterized in that The clock signal generating module is an oscillator.

10. The device according to claim 8, characterized in that The control module includes a sampling submodule, a counting submodule and a judging submodule; The sampling submodule is used to sample the target differential signal according to the local clock signal to obtain a sampled signal; The counting submodule is used to perform time-series counting on the sampling signal to obtain a counting result; The judgment submodule is used to generate the target signal according to the magnitude relationship between the counting result and the pre-designed value.

11. An electronic device, characterized in that: include: at least one processor; and, a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the signal receiving method as described in any one of claims 1 to 7.

12. A computer-readable storage medium storing a computer program, characterized in that: The computer program is executed by a processor to implement the signal receiving method according to any one of claims 1 to 7.

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