Shared Balance Operator Circular Array Mapping Method Based on Reconfigurable Cryptographic Algorithm

Abstract

The present invention analyzes and designs data communications within a loop body and between multiple loop bodies, and provides a shared balancing operator loop array mapping method based on a reconfigurable cryptographic algorithm. The present invention optimizes the mapping graph using a balancing node operator method, so that it has the smallest iteration interval and the largest pipeline performance, which solves the problem of poor pipeline performance due to manual configuration, saves a lot of human and mental labor, and does not require manual calculation to add balancing operator nodes. The present invention uses a shared balancing node operator solution to process multi-fan-out operator balancing nodes, minimizing computing resources and maximizing performance. The storage data unit SREG is used for data transmission communication, which solves the problem of data communication between loop bodies occupying more transmission operator resources, saves a lot of hardware resources, and further improves pipeline performance.

Description

Technical Field

[0001] The invention relates to a shared balance operator cyclic array mapping method based on a reconfigurable cryptographic algorithm, and belongs to the technical field of information security. Background Art

[0002] With the development and innovation of information technology, the demand for data processing capabilities in the information explosion era is constantly increasing. There are two main traditional computing methods: one is the application-specific integrated circuit (ASIC). Due to its specialization and production characteristics, once it is put into production, the hardware circuit cannot be changed. With the continuous increase in the complexity of silicon manufacturing process, the one-time investment cost becomes extremely expensive. Therefore, when the ASIC production does not reach a certain scale, the fully customized ASIC acceleration unit can only be adopted by a few computing logics with a large number of applications; the other is the general-purpose processor (GPP), which performs specific computing tasks through instruction sets and completes different functional computing tasks by modifying the instruction set sequence, without modifying the hardware circuit, so GPP has good flexibility. However, in order to complete a computing task, GPP needs to read instructions and data from the memory, decode and execute them, and each execution of the instruction requires a large performance overhead, so the performance of GPP is generally far behind ASIC.

[0003] Reconfigurable computing can essentially be seen as "a compromise between the high flexibility of GPP and the high performance of ASIC, a combination of time computing and space computing." At the same time, reconfigurable computing is also a compromise between flexibility and area / power consumption, with better flexibility than ASIC. Reconfigurable architecture is a type of programmable logic device in which the processing unit is a large logic array similar to ALU, and the interconnection structure is based on a bus. This is in sharp contrast to the field programmable array FPGA. Reconfigurable processors have flexibility and programmability, while having a smaller area and requiring fewer configuration bits. For some occasions that require both programmability and flexibility, the reconfigurable architecture is the most suitable choice. Many businesses and academia have proposed some supporting compilers to apply reconfigurable systems.

[0004] The computational characteristics of cryptographic algorithms will directly affect the structural design of the target reconfigurable processor. Cryptographic algorithms are roughly divided into block cipher algorithms, stream cipher algorithms, and digest algorithms. The ciphertext length of digest algorithms is fixed and irreversible, and they are mainly used in consistency verification, digital signatures, and security authentication. Block cipher algorithms and stream cipher algorithms are both reversible cryptographic algorithms and can be used in all encryption and decryption scenarios. Block cipher algorithms are the most widely used cryptographic algorithm type. Cryptographic algorithms are used to encrypt or decrypt a large amount of data in the same form. Therefore, unlike ordinary program fragments, a single mapping of a cryptographic algorithm on a computing array is usually used by multiple groups of data. Among the various encryption modes of block cipher algorithms, the ECB mode is one of the most commonly used modes. In this mode, the encryption of the latter group of data does not depend on the encryption result of the previous group of data, so multiple groups of data can be pipelined. It can be seen that the performance of pipeline computing has a huge impact on the performance of cryptographic algorithms. Therefore, the target array structure must support the function of pipeline computing.

[0005] In comparison, automatic mapping is fast and effective, avoiding the shortcomings of manual mapping, and thus becomes an indispensable part of reconfigurable systems. Traditional mature compilation technology cannot be directly used in reconfigurable mapping problems, making automatic mapping technology a research hotspot in the current reconfigurable field.

[0006] At present, the research on reconfigurable processor structures for special fields is a hot topic, and the wide application scenarios of cryptographic algorithms make reconfigurable processors for cryptographic algorithms a typical representative. In order to achieve general functions, ordinary calculations are often simple and clear. As algorithms in the security field, cryptographic algorithms must try to decouple ciphertext and plaintext to improve the security of ciphertext. Therefore, a large amount of complex data calculations are usually performed. It can be seen that compared with ordinary calculations, manual mapping of cryptographic algorithms has more disadvantages in terms of requirements for mapping personnel, mapping time and mapping effect. Not only are the requirements for mapping personnel high, the time cycle is long, and the cycle communication is poor, but the mapping effect is not good and the mapping pipeline performance is poor. At this stage, the research on the reconfigurable technology of cryptographic algorithms is more inclined to the research on its array structure. Others also have the research on manual mapping schemes for specific cryptographic algorithms. However, for cryptographic algorithms, the research on the loop body and the loop body is the most important part. Therefore, the research on the loop calculation operator mapping technology of reconfigurable processors for cryptographic algorithms is still very urgent, and its importance is self-evident. Based on the above background, the mapping design of compiler backend for information security-oriented reconfigurable cryptographic chips has become a hot research topic, but there is no satisfactory solution yet. Summary of the invention

[0007] In view of the fact that the existing mapping technology is not mature enough, has high requirements for mapping personnel, long time period, poor loop communication, poor mapping effect and poor mapping pipeline performance, the present invention analyzes and designs the data communication within a loop and between multiple loops, and proposes a shared balanced operator loop array mapping method based on a reconfigurable cryptographic algorithm.

[0008] In order to achieve the above object, the present invention provides the following technical solutions:

[0009] A shared balance operator cyclic array mapping method based on a reconfigurable cryptographic algorithm comprises the following steps:

[0010] Step 1: Calculate the path length of all paths in the current operation, and obtain the MII of each path based on the path length difference between the current path and the maximum path;

[0011] Step 2: Determine whether the currently processed operator is a multi-fan-out operator. If so, proceed to step 3; if not, use a balancing node operator to reduce the MII of the path guided by the operator.

[0012] Step 3: For a multi-fan-out operator, calculate the minimum value of the MII of all paths guided by the operator, and use the balancing node operator as a shared balancing node operator to reduce the minimum value of the MII;

[0013] Step 4: After subtracting the shortest path from the path guided by the multi-fan-out operator, determine whether the current shared balancing node operator is a multi-fan-out operator, and repeat steps 2 and 3 until the MII of the path guided by the multi-fan-out operator is reduced to the minimum;

[0014] Step 5: Traverse all paths of the current operation and repeat steps 2 to 4 until the MII of all paths drops to the minimum and the operation ends.

[0015] Furthermore, in step 4 and step 5, MII is eliminated to 0.

[0016] Furthermore, the method of using a balancing node operator includes: adding a balancing node operator to transfer data.

[0017] Furthermore, the balance node operator adopts a linear basic logic unit BFU.

[0018] Furthermore, when the balanced node operator optimization is used for the entire mapping graph, the two longest input paths in the data path are optimized first; when the two longest paths are balanced, the second longest input path is selected for optimization analysis until the input operator paths of the entire graph are balanced or the MII is minimized.

[0019] Furthermore, the shared balancing node operator in the multiple fan-out operator paths is shared in multiple paths.

[0020] Furthermore, in multiple cycles, data communication is performed through the storage data unit SREG, so that the input data received by each input operator of the second cycle is independent, and the second cycle retains the performance indicators of the first cycle.

[0021] Furthermore, when it is determined that there is a data dependency within the loop round, SREG is used instead of MEM as the intermediate memory.

[0022] Furthermore, after the data transfer of this round is completed, SREG is released and an idle flag is given.

[0023] Furthermore, the priority of using SREG is: the data dependency priority of the inner loop of the cryptographic algorithm is the highest, the data dependency priority between cryptographic algorithms is the second, and the feature shift function priority of SREG is the lowest.

[0024] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0025] 1. The present invention optimizes the mapping graph by using a balancing node operator so that it has the smallest iteration interval and the largest flow performance, thereby solving the problem of poor flow performance due to manual configuration, saving a lot of human and mental labor, and eliminating the need for manual calculation of adding balancing operator nodes.

[0026] 2. The present invention adopts a solution of sharing balancing node operators to process multi-fan-out operator balancing nodes, solving the problem of mapping failure of multi-fan-out operator units under resource constraints, thereby minimizing computing resources and maximizing performance.

[0027] 3. The storage data unit SREG is used for data transmission communication, which solves the problem that data communication between loop bodies occupies more transmission operator resources, saves a lot of hardware resources, and further improves pipeline performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is the input directed data flow graph DFG of the mapping process of the present invention.

[0029] Figure 2 The transfer balance operator is inserted into the present invention to extend the input path.

[0030] Figure 3 This is an example of the MII optimization process of the mapping diagram of the present invention.

[0031] Figure 4 A shared example of the operator is passed for the present invention.

[0032] Figure 5 An example of a reconfigurable high-performance compiler for optimization.

[0033] Figure 6 This is a schematic diagram of the SREG module unit of the present invention. DETAILED DESCRIPTION

[0034] The technical solution provided by the present invention will be described in detail below in conjunction with specific embodiments. It should be understood that the following specific implementation methods are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0035] The design of a reconfigurable system-on-chip compiler for information security includes three important processes: the primitive input of the front end, the optimization of the intermediate files, and the mapping of the back end. Among them, in the back end mapping process, there are different mapping schemes for different hardware architectures. The indicator that affects the compiler effect is mainly the performance of the compiler, and the key technical indicator that affects the performance is the parallel computing performance of the mapping graph. The input of the back end mapping of the reconfigurable processor is to map the directed data flow graph (DFG) to the hardware architecture. Figure 1 It is a graph of data dependencies represented by the intermediate process generated by the compiler front end. It is a directed data flow graph that represents the direction of the data and the computational logic functions performed by the data. The cryptographic algorithm can obtain the final encryption result by executing it in sequence according to the given data flow graph. In the figure, the arrows represent the data flow direction, and the circles represent executable logical operations. The achievable logic operations include addition, basic arithmetic and logical operations, shift operations, and multiplication operations. Each operator has three inputs and two outputs. Figure 1 In the figure, AU, SU, and MU are the addition unit, shift unit, and multiplication unit, respectively. The parallel computing performance of the mapping graph refers to the ability of multiple independent computing units to calculate simultaneously in reconfigurable computing. Such computing power reflects the parallel degree of the mapping scheme to a certain extent, which is called parallel computing power. Since cryptographic algorithms are computationally intensive algorithms, and the size of the computing array and the hardware resources are limited, each reconstruction of the hardware usually consists of 8 linear basic logic computing units, 4 lookup table units, and 1 position permutation unit. A complete data flow graph of a cryptographic algorithm often requires multiple reconstructions to be implemented. Therefore, the data flow graph can be divided into the initial calculation round, the loop iteration round, and the output pre-processing round according to the characteristics of the cryptographic algorithm. Due to the complexity of the cryptographic algorithm, the loop iteration round will take a lot of time, so the loop iteration round is the design core of the entire mapping scheme. Since each round of loops is similar or identical, the general practice is to use a round of loops as a subgraph to explore the mapping scheme, and finally implement the mapping iteration of the entire data flow graph through iterative replication. The present invention designs a mapping scheme of parallel water bubbles oriented to information security based on a parallel mapping scheme of a single cycle and data iteration between multiple cycles.

[0036] A given mapping graph carries the dependencies between cryptographic algorithm data and the operations performed. The mapping graph can be further optimized by adjusting the routing and other parameters in the array. In previous studies, there were insufficient optimization or even mapping failures in the face of special constraints. The present invention analyzes and designs data communication within a loop and between multiple loops, and proposes a loop mapping scheme that shares a balancing operator node. Figure 2 It is a fixed mapping diagram, A->B->D and C->D are two data calculation transmission paths. The short data stream input path length is extended by inserting the balancing node operator. It can be seen from the figure that if each node calculation in the figure takes 1 time cycle, the arrival time is different because the path lengths passed by the node 125D are different. In the pipeline reconfigurable calculation, the calculation unit array of each cycle is not the same. Therefore, as long as the current calculation does not affect the data of the previous iteration process, the next iteration calculation can be started in advance, thereby improving the pipeline performance. The period between two iterative calculations is called the iteration interval (IterationInterval, II), where the smaller the II, the higher the pipeline performance. Therefore, the method of improving the pipeline performance of the present invention becomes to find the minimum iteration interval (MinIterationInterval, MII). When MII is 0, it means that the next iteration will be started immediately after the previous iteration is started. At this time, it has the smallest iteration interval and the maximum pipeline performance.

[0037] Figure 2 A->B->D requires 3 cycles, and C->D requires 2 cycles. At this time, MII should be 1. If the next iterative calculation starts in the next cycle after the previous calculation is started, that is, MII=0, then the data of C is changed at the same time as B arrives, which causes calculation errors in the data of D. Therefore, a balancing node operator needs to be added to transfer data so that multiple calculation paths of the input data are equal. At this time, MII is 0, and the mapping diagram will have the smallest iteration interval and the largest flow performance.

[0038] The balance node operator uniformly uses BFU (Linear Basic Logic Computing Unit), which can play the role of single-cycle data transmission when used. For the two operators SBOX (Lookup Table Unit) and BENES (Position Exchange Unit), specified resource configuration support is required when performing data processing. Using these two operators for data transmission has the risk of resource conflicts and performance degradation. There are 8 BFUs in total. During compilation optimization, idle BFUs are randomly selected as balance node operators. When using BFU as a balance node operator, a BFU can eliminate 1 MII in a single cycle. In an RCA (Reconstruction Computing Unit) cycle, idle BFUs can eliminate MII in series, but a BFU cannot be reused. Therefore, a maximum of 8 MII values ​​can be eliminated in one RCA cycle.

[0039] Through analysis, we can know that the minimum iteration interval MII is the difference between the input path length of the operator with the latest trigger cycle and the input path length of the operator with the earliest trigger cycle. When MII is 0, it means that the path lengths of the triggering operators are consistent. At this time, there is a balanced operator path input, which can achieve the maximum pipeline performance. Figure 3 As shown, an example of inserting a balancing node operator for a given entire mapping graph is described. For the entire mapping graph, a scheme for balancing the operator path input by inserting a transfer node operator first optimizes the two longest input paths in the data path. After the two longest paths are balanced, the second longest input path is selected for optimization analysis until the input operator path of the entire graph is balanced. However, for computationally intensive algorithms such as cryptographic algorithms, it is common for a node in its data flow graph to be used by multiple paths. 150 This type of node operator is referred to as a multi-fan-out node. The scheme of inserting an operator node balancing operator to improve performance is very effective for single fan-out operator outputs, but for multi-fan-out operator nodes, it may cause unnecessary resource performance overhead, and may even cause algorithm mapping failure when resources are limited. Therefore, the present invention proposes a scheme of sharing a balancing node operator to deal with this multi-fan-out operator balancing node problem. The implementation steps of the shared balancing node operator are as follows:

[0040] 155Step 1: Calculate the path length of all paths in the current operation, based on the difference in path length between the current path and the maximum path.

[0041] Get the MII for each path.

[0042] Step 2: Determine whether the currently processed operator is a multi-fan-out operator. If so, proceed to step 3; if not, use the balancing node operator to eliminate the MII of the path guided by the operator.

[0043] Step 3: For a multi-fan-out operator, calculate the minimum value of the MII of all paths guided by the operator, and use the balancing node 160 operator to eliminate the minimum value of the MII. At this time, the balancing node operator is called a shared balancing node operator.

[0044] Step 4: After subtracting the shortest path from the path guided by the multi-fan-out operator, determine whether the current shared balancing node operator is a multi-fan-out operator, and repeat steps 2 and 3 until the MII of the path guided by the multi-fan-out operator is eliminated to 0.

[0045] Step 5: Traverse all paths of the current operation and repeat steps 2 to 4 until the MII of all paths is eliminated to 0 and the operation is completed.

[0046] 165 It should be noted that the "MII = 0" condition is an ideal goal, but it may not be met through compilation optimization. However, as long as the MII is optimized as small as possible, it will be beneficial to improve performance.

[0047] The following are examples: Figure 4 (a) shows a given data flow graph with multiple fan-out operators, where node D is a multi-fan-out node. For this type of operator, the traditional approach is to analyze the operator according to each different path.

[0048] like Figure 4 (b) Directly inserting a balancing node operator on each path can reduce MII and improve pipeline performance. However, 170 will bring a series of performance problems when some resources are scarce. For reconfigurable computing units, the input source of operators in each row can be the output of the previous row, the output of this row, and the storage unit. Therefore, for node D, the role of the balancing node operator inserted on multiple paths is the same. Therefore, the transfer operator of the multi-fan-out operator path is shared by multiple paths, such as Figure 4 (c) as shown, thereby minimizing computing resources and maximizing performance.

[0049] Compared with ordinary balancing node operators, shared balancing node operators are optimized in terms of operator resources. The more multi-fan-out operators there are, the greater the optimization effort. In computationally intensive algorithms such as encryption algorithms, the advantages of shared balancing node solutions are very significant. In the present invention, shared balancing node operators are used to optimize reconfigurable high-performance compilers for cryptographic algorithms, such as Figure 5As shown in the figure, 8 BFUs (basic operation units), 4 SBOXs (nonlinear permutation tables) and 1 BENES (bit permutation) are used as basic operators to form an RCA (reconstruction operation unit). BFU implements most of the basic operations in the cryptographic algorithm, such as SU supports logical shift and arithmetic shift functions; LU supports basic XOR function; AU supports addition and subtraction operations; MU supports multiplication operations. These operations do not require additional resource configuration information, and three inputs can get two output results under different reconstruction configurations. SBOX implements the function of the lookup table, which facilitates nonlinear operations in the cryptographic algorithm. BENES supports the big-endian and small-endian conversion function to ensure the correctness of data on different processors. Among these operators, SBOX and BENES require additional resource configuration, and the resource configuration needs to be loaded before each RCA runs, which takes a certain amount of time. The actual operation of RCA is configured by the compiler, and the performance and resource overhead are also determined by the optimization strength of the compiler. In terms of hardware, the cryptographic reconfigurable operation module is mounted in the hardware system as a peripheral, and the compiled configuration code can be written through the PCIe bus or the system AXI bus. In the actual encryption process, the resource optimization and performance optimization brought about by the reconstruction configuration generated by the compiler by the shared balance node operator have been greatly improved.

[0050] When exploring the mapping scheme of a cryptographic algorithm, although the first exploration object is one of the cycles, the entire mapping process is an overall mapping of multiple cycles and multiple cycles outside the loop body. Therefore, the impact of the communication of multiple cycles on the algorithm performance should also be considered. Due to the characteristics of hardware logic, the operator input of each row can only come from the output of the operator in the previous row and the operator in this row and the storage unit. Therefore, there may be a problem of data communication failure between loop bodies. If a restriction is added that the output of a loop body must be in the last row and the input must be in the starting row, the mapping may fail because of such harsh restrictions and the mapping cannot find the best mapping scheme. The present invention transmits data communication through the storage data unit SREG, thereby ensuring that the input data received by each input operator in the second cycle is independent, thereby ensuring that the second cycle still retains the performance indicators of the first cycle, such as Figure 6As shown in the figure, it is the schematic diagram of SREG. It has three working modes, namely 1*16 independent read and write modules, 4*4 modules with shift function and 1*16 modules with shift function. It has 16 independent storage units, each row has four write ports, and includes storage and shift functions. It is of great significance for algorithms with vector shifts such as hash algorithms. Compared with MEM storage units, SREG can read the correct data by writing the next row in this row, so it will not cause data delay, reduce the connection of data communication and increase the use of additional operators, and ensure the correct transmission and communication of data. During the compilation and generation process of SREG:

[0051] First, determine whether there is a data dependency in the cycle of the encryption algorithm. If so, consider using SREG instead of MEM as the intermediate memory.

[0052] Secondly, consider the release of SREG. As a fast memory, the resource consumption of SREG with the same capacity must be greater than that of MEM. Considering the reuse characteristics of SREG, SREG needs to be released after the current round of data transfer is completed, and an idle flag is given.

[0053] Finally, considering the priority of SREG usage, the data dependency within the inner loop of the cryptographic algorithm has the highest priority, followed by the data dependency between cryptographic algorithms, and the feature shift and other functions of SREG have the lowest priority.

[0054] The SREG designed by the above design rules plays a good role in 210 data transmission in the actual general cryptographic algorithm reconstruction compilation process. When compiling the cryptographic algorithm of this design, the ciphertext of each round of encryption in the AES-CBC encryption mode is used as the initial data of the second round of encryption. In order to ensure the consistency between loops, the traditional compiler needs to use memory for data storage while judging the ciphertext as the result output, resulting in the initial data of the next round cannot be obtained immediately. In order to ensure the correctness of the algorithm, the compiler adopts the method of adding an empty round operation, which reduces the operation efficiency. After adding the SREG structure, this problem is well solved through the fast access characteristics of SREG.

[0055] 215 The technical means disclosed in the scheme of the present invention are not limited to the technical means disclosed in the above-mentioned implementation mode, but also include technical schemes composed of any combination of the above-mentioned technical features. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention, and these improvements and modifications are also regarded as the protection scope of the present invention.

Claims

1. A shared balance operator cyclic array mapping method based on a reconfigurable cryptographic algorithm, characterized in that: The steps include: Step 1: Calculate the path length of all paths in the current operation, and obtain the MII of each path based on the path length difference between the current path and the maximum path; Step 2: Determine whether the currently processed operator is a multi-fan-out operator. If so, proceed to step 3; if not, use a balancing node operator to reduce the MII of the path guided by the operator. Step 3: For a multi-fan-out operator, calculate the minimum value of the MII of all paths guided by the operator, and use the balancing node operator as a shared balancing node operator to reduce the minimum value of the MII; Step 4: After subtracting the shortest path from the path guided by the multi-fan-out operator, determine whether the current shared balancing node operator is a multi-fan-out operator, and repeat steps 2 and 3 until the MII of the path guided by the multi-fan-out operator is reduced to the minimum; Step 5: Traverse all paths of the current operation and repeat steps 2 to 4 until the MII of all paths drops to the minimum and the operation ends.

2. The shared balance operator cyclic array mapping method based on the reconfigurable cryptographic algorithm according to claim 1 is characterized in that: In the steps 4 and 5, MII is eliminated to 0.

3. The shared balance operator cyclic array mapping method based on the reconfigurable cryptographic algorithm according to claim 1 is characterized in that: The method of using a balancing node operator includes: adding a balancing node operator to transfer data.

4. The shared balance operator cyclic array mapping method based on a reconfigurable cryptographic algorithm according to claim 1 is characterized in that: The balance node operator adopts a linear basic logic unit BFU.

5. The shared balance operator cyclic array mapping method based on the reconfigurable cryptographic algorithm according to claim 1 is characterized in that: When using balanced node operator optimization for the entire mapping graph, the two longest input paths in the data path are optimized first; when the two longest paths are balanced, the second longest input path is selected for optimization analysis until the input operator paths of the entire graph are balanced or the MII is minimized.

6. The shared balance operator cyclic array mapping method based on the reconfigurable cryptographic algorithm according to claim 1 is characterized in that: Shared balancing node operators in multiple fan-out operator paths are shared in multiple paths.

7. The shared balance operator cyclic array mapping method based on a reconfigurable cryptographic algorithm according to claim 1 is characterized in that: In multiple cycles, data communication is performed through the storage data unit SREG, so that the input data received by each input operator of the second cycle is independent, and the second cycle retains the performance indicators of the first cycle.

8. The shared balance operator circular array mapping method based on the reconfigurable cryptographic algorithm according to claim 7 is characterized in that: When it is determined that there is a data dependency within the loop round, SREG is used instead of MEM as the intermediate memory.

9. The shared balance operator cyclic array mapping method based on the reconfigurable cryptographic algorithm according to claim 7 is characterized in that: After the data transfer of this round is completed, SREG is released and an idle flag is given.

10. The shared balance operator cyclic array mapping method based on the reconfigurable cryptographic algorithm according to claim 7, characterized in that: The priority of SREG usage is: the data dependency within the inner loop of the cryptographic algorithm has the highest priority, the data dependency between cryptographic algorithms has the second highest priority, and the feature shift function of SREG has the lowest priority.

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