Capacitor array structure and method of forming the same

Abstract

A capacitor array structure includes a substrate, a plurality of first pedestal container stacked capacitor structures, a plurality of second pedestal container stacked capacitor structures, and a plurality of third pedestal container stacked capacitor structures. The first pedestal container stacked capacitor structures extend upward above the substrate and are arranged in a first column. The second pedestal container stacked capacitor structures extend upward above the substrate and are arranged in a second column. The second column is adjacent to the first column. The third pedestal container stacked capacitor structures extend upward above the substrate and are arranged in a third column. The third column is adjacent to the second column. The first column is a first distance from the second column. The second column is a second distance from the third column. The first distance is less than the second distance.

Description

Technical Field

[0001] This disclosure relates to a capacitor array structure, and more particularly to a method for forming a capacitor array structure. Background Technology

[0002] As the cell density of dynamic random-access memory (DRAM) continues to increase, maintaining sufficiently high storage capacitance within the shrinking cell area presents a challenge. Furthermore, the cell area is continuously decreasing. The primary method for increasing cell capacitance is through cell structure technology, which involves forming three-dimensional cell capacitors, such as trench or stacked capacitors. Moreover, capacitor structures can be categorized into cylindrical capacitor structures or basic cylindrical capacitor structures. Summary of the Invention

[0003] This disclosure provides a capacitor array structure.

[0004] In some embodiments, the capacitor array structure includes a substrate, a plurality of first pillar capacitor stacked structures, a plurality of second pillar capacitor stacked structures, and a plurality of third pillar capacitor stacked structures. The first pillar capacitor stacked structures extend upward above the substrate and are arranged in a first column. The second pillar capacitor stacked structures extend upward above the substrate and are arranged in a second column. The second column is adjacent to the first column. The third pillar capacitor stacked structures extend upward above the substrate and are arranged in a third column. The third column is adjacent to the second column. The first column and the second column are separated by a first distance. The second column and the third column are separated by a second distance. The first distance is less than the second distance.

[0005] In some embodiments, the capacitor array structure further includes a plurality of fourth pillar capacitor stacked structures extending upward above the substrate and arranged in a fourth column. The fourth column is adjacent to the third column. The third column and the fourth column are separated by a third distance. The third distance is less than a second distance.

[0006] In some implementations, the first distance is less than half of the second distance.

[0007] In some embodiments, the first pillar container stacked capacitor structures are arranged at equal intervals in the first column.

[0008] In some embodiments, the second pillar container stacked capacitor structures are arranged at equal intervals in the second column.

[0009] In some embodiments, each second-pillar container stacked capacitor structure includes a bottom electrode layer, a capacitor dielectric layer, and a top electrode layer. The bottom electrode layer has a U-shaped cross-section. The capacitor dielectric layer is located above the bottom electrode layer. The top electrode layer is located above the capacitor dielectric layer.

[0010] In some embodiments, the capacitor array structure further includes a first dielectric layer. The first dielectric layer laterally surrounds the first pillar capacitor stacked capacitor structure, the second pillar capacitor stacked capacitor structure, and the third pillar capacitor stacked capacitor structure.

[0011] In some embodiments, the bottom electrode layer of one of the second pillar container stacked capacitor structures has a portion that extends through the first dielectric layer and is located between the first column and the second column.

[0012] In some embodiments, the top surface of the first dielectric layer is flush with the top surface of the bottom electrode layer of one of the second pillar container stacked capacitor structures.

[0013] In some embodiments, the capacitor array structure further includes a second dielectric layer. The second dielectric layer laterally surrounds the first pillar capacitor stacked capacitor structure, the second pillar capacitor stacked capacitor structure, and the third pillar capacitor stacked capacitor structure, and is separated from the first dielectric layer.

[0014] In some embodiments, a method for forming a capacitor array structure includes: sequentially depositing a first nitride layer, a first oxide layer, and a second nitride layer over a first contact and a second contact, the first contact and the second contact being located on a substrate; etching the first nitride layer, the first oxide layer, and the second nitride layer to form a first opening and a second opening exposing the first contact and the second contact; conformally depositing a bottom metal layer over the first nitride layer, the first oxide layer, the second nitride layer, the first contact, and the second contact; forming a shielding layer on a first portion of the bottom metal layer, the first portion being located above the first contact and the second contact, while simultaneously exposing a second portion of the bottom metal layer, the second portion being located between the first contact and the second contact; etching the second nitride layer and the first oxide layer through the shielding layer to form a third opening, the third opening having a bottom position higher than the top surface of the first nitride layer; removing the shielding layer from the bottom metal layer after etching the second nitride layer and the first oxide layer; removing the first oxide layer through the third opening after removing the shielding layer; forming a capacitor dielectric layer over a bottom electrode layer; and forming a top electrode layer over the capacitor dielectric layer.

[0015] In some embodiments, the second nitride layer and the first oxide layer are etched by a dry etching process.

[0016] In some implementations, the first oxide layer is removed by a wet etching process.

[0017] In some embodiments, the wet etching process etches the first oxide layer at a rate greater than the rate at which the first nitride layer and the second nitride layer are etched.

[0018] In some implementations, the third opening does not cover the first contact and the second contact.

[0019] In some embodiments, the third opening in the cross-sectional view has a larger size than the first opening.

[0020] In some implementations, the shielding layer is removed via a planarization process.

[0021] In some embodiments, a capacitor dielectric layer is formed above the bottom electrode layer such that the capacitor dielectric layer is further formed on the sidewall of the third opening.

[0022] In some embodiments, the method of forming the capacitor array structure further includes depositing a second oxide layer over the first contact and the second contact before depositing the first nitride layer, the first oxide layer and the second nitride layer.

[0023] In some embodiments, the method of forming the capacitor array structure further includes depositing an etch stop layer over the first contact and the second contact before depositing the first nitride layer, the first oxide layer and the second nitride layer. Attached Figure Description

[0024] The state of this disclosure is in relation to the accompanying documents. Figure 1 The best way to understand this text is by referring to the following detailed description. It should be noted that, according to industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features can be arbitrarily increased or decreased for clarity of explanation.

[0025] Figure 1 A method M for manufacturing a capacitor array structure according to some embodiments of the present disclosure is illustrated.

[0026] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A as well as Figure 9A A top view of a capacitor array structure according to some embodiments of this disclosure is shown.

[0027] Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B as well as Figure 9B Draw along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A as well as Figure 9A A sectional view of the midline segment A-A'. Detailed Implementation

[0028] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0029] Furthermore, for the convenience of describing the relationship between one element or feature as illustrated in the figures and another element(s) or feature(s), spatial relative terms such as "below," "under," "lower," "above," "upper," and the like are used herein. Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. The device may be oriented in other ways (rotated 180 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0030] As used herein, “approximately,” “about,” “roughly,” or “generally” should generally refer to within 20%, 10%, or 5% of a given value or range. The quantities given herein are approximate values, thus implying that the terms “approximately,” “about,” “roughly,” or “generally” can be inferred unless explicitly stated otherwise.

[0031] This disclosure provides a capacitor array structure with a pillar-capacitor stacked capacitor structure in several embodiments. The method for forming the pillar-capacitor stacked capacitor structure includes, prior to forming the pillar-capacitor stacked capacitor structure, forming a dielectric stack structure having at least two dielectric layers above a plurality of capacitor contacts; and forming a bottom electrode layer of the pillar-capacitor stacked capacitor structure through the dielectric stack structure to land on the capacitor contacts. To increase the capacitance value of the cell, a sacrificial layer located in the dielectric stack structure is removed through an opening in the top dielectric layer of the dielectric stack structure, which covers the capacitor contacts. This allows the space freed up by removing the sacrificial layer to be further filled with the top metal material of the pillar-capacitor stacked capacitor structure to increase the capacitance value. However, when etching the top dielectric layer to form the opening for the removable sacrificial layer, the bottom electrode layer formed above the capacitor contacts may be damaged by the etching process, resulting in a decrease in capacitance.

[0032] Therefore, various embodiments disclosed herein provide capacitor array structures having dense and sparse regions of capacitor patterns. Openings for removing the sacrificial layer in the dielectric stack structure are formed in the sparse regions of the capacitor pattern to prevent these openings from forming above the capacitor contacts. Therefore, during the etching of the top dielectric layer to form the aforementioned openings, the bottom electrode layer formed above the capacitor contacts is not damaged by the etching process, thereby improving the capacitance value of the pillar-capacitor stacked capacitor structure.

[0033] Please refer to Figure 1 . Figure 1 A flowchart illustrating a manufacturing method M for fabricating a capacitor array structure A1 according to some embodiments of this disclosure is shown. Method M includes relevant parts of the overall manufacturing process. It should be understood that the fabrication process can be carried out by... Figure 1 Additional operations are provided before, during, and after the operations shown, and for additional embodiments of method M, some operations described below may be replaced or eliminated. The order of operations / processes is interchangeable. Method M includes the fabrication of a capacitor array structure A1. However, the fabrication of the capacitor array structure A1 is merely used to describe examples of fabrication processes according to some embodiments of this disclosure.

[0034] Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A as well as Figure 9A A top view of a capacitor array structure A1 according to some embodiments of the present disclosure is shown. Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B as well as Figure 9B Draw along Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A as well as Figure 9A A sectional view of the midline segment A-A'.

[0035] Method M begins with step S101, where capacitive contacts are formed above the substrate. Please refer to... Figure 2A as well as Figure 2B In some embodiments of step S101, a capacitive contact 102 is formed above the substrate 100. The substrate 100 may be formed with a metal-oxide-semiconductor (MOS) transistor (not shown) having a memory cell belonging to a dynamic random-access memory (DRAM) element located below the capacitive contact 102. In some embodiments, the capacitive contact 102 may comprise a conductive material. For example, the capacitive contact 102 may comprise copper (Cu), tungsten (W), cobalt (Co), or other suitable materials.

[0036] A dielectric material 103 is formed and laterally surrounds the capacitor contact 102. In some embodiments, the dielectric material 103 may be formed of a dielectric material. For example, the dielectric material 103 may comprise silicon nitride, silicon oxide, silicon oxynitride, or other similar materials. In some embodiments, the method of forming the dielectric material 103 may include chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0037] A metal layer 101 is formed above the capacitor contact 102 and has a material different from that of the capacitor contact 102. In some embodiments, the metal layer 101 may comprise a conductive material. For example, the metal layer 101 may comprise copper (Cu), tungsten (W), cobalt (Co), or other suitable materials. In some embodiments, the method for forming the metal layer 101 may include chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0038] Please refer to the reply. Figure 1 Method M then proceeds to step S102, where a dielectric structure is formed above the capacitor contact. Please refer to... Figure 2A as well as Figure 2B In some embodiments of step S102, the dielectric structure 105 may include a stacked structure, which is sequentially formed having an etch stop layer 104, a first dielectric layer 106, a second dielectric layer 107, a sacrificial layer 108, and a third dielectric layer 110. Next, a first patterned hard shielding layer 112 having a capacitor opening pattern 120 may be formed over the dielectric structure 105. Figure 2A As shown, capacitor opening patterns 120 are arranged in columns r1, r2, r4, and r5, wherein columns r1, r2, r4, and r5 are parallel to each other. The capacitor opening pattern 120 has a circular top view pattern. In some embodiments, the capacitor opening pattern 120 may have a square top view pattern, a rectangular top view pattern, or an elliptical top view pattern.

[0039] In some embodiments, the etch stop layer 104 may be formed of a dielectric material. For example, the etch stop layer 104 may comprise silicon nitride, silicon oxide, silicon oxynitride, or other similar materials. In some embodiments, the method for forming the etch stop layer 104 may include chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, the etch stop layer 104 may have approximately The thickness.

[0040] In some embodiments, the first dielectric layer 106 may be made of a material different from that of the etch stop layer 104. The etch stop layer 104 may be formed of a dielectric material. For example, the first dielectric layer 106 may comprise silicon nitride, silicon oxide, silicon oxynitride, or other similar materials. The material of the first dielectric layer 106 may be selected from materials that have high selectivity during etching compared to the etch stop layer 104. For example, but not limiting the scope of this disclosure, the material of the first dielectric layer 106 may comprise silicon oxide, while the material of the etch stop layer 104 may comprise silicon nitride. In some embodiments, the method for forming the first dielectric layer 106 may include chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0041] In some embodiments, the second dielectric layer 107 and / or the third dielectric layer 110 may be made of a material different from the first dielectric layer 106 and the sacrificial layer 108. In some embodiments, the second dielectric layer 107 and / or the third dielectric layer 110 may be formed of a dielectric material. For example, the second dielectric layer 107 and / or the third dielectric layer 110 may comprise silicon nitride, silicon oxide, silicon oxynitride, or other similar materials. For example, but not limiting the scope of this disclosure, the second dielectric layer 107 and / or the third dielectric layer 110 may comprise silicon nitride, and the sacrificial layer 108 may comprise silicon oxide. In some embodiments, the second dielectric layer 107 and / or the third dielectric layer 110 may have a thickness less than that of the first dielectric layer 106 and the sacrificial layer 108. In some embodiments, the third dielectric layer 110 may have a thickness greater than that of the second dielectric layer 107. In some embodiments, the method for forming the second dielectric layer 107 and / or the third dielectric layer 110 may include chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0042] In some etchants used for wet etching, the sacrificial layer 108 may have a higher etch rate than the second dielectric layer 107 and the third dielectric layer 110. The etch selectivity of the sacrificial layer 108 relative to the second dielectric layer 107 and the third dielectric layer 110 may be in the range of about 1.5 to about 5.0. In some embodiments, the sacrificial layer 108 may comprise doped polysilicon, while the second dielectric layer 107 and the third dielectric layer 110 may comprise undoped polysilicon. For example, but not limiting this disclosure, using ammonia (NH4OH) solution or tetramethyl ammonium hydroxide (TMAH) solution as the wet etchant, the etch selectivity of the doped polysilicon relative to the undoped polysilicon may be in the range of about 1.5 to about 5.0. The choice between ammonia (NH4OH) solution and tetramethyl ammonium hydroxide (TMAH) solution for wet etching can be based on the type of dopant. For example, argon (Ar), silicon (Si), arsenic (As), and phosphorus (P) have higher etching rates, while boron (B) has a lower etching rate.

[0043] In some embodiments, the sacrificial layer 108 may be formed of a dielectric material. For example, the sacrificial layer 108 may comprise silicon nitride, silicon oxide, silicon oxynitride, or other similar materials. The material of the sacrificial layer 108 may be selected from materials that have high selectivity with respect to the second dielectric layer 107 and the third dielectric layer 110 during etching. In some embodiments, the method of forming the sacrificial layer 108 may include chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0044] In some embodiments, the first patterned hard shielding layer 112 may comprise tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The formation of the first patterned hard shielding layer 112 may include a series of processes, including deposition, photolithography patterning, and etching. The photolithography patterning process may include photoresist coating (e.g., selective coating), soft baking, shield alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (e.g., hard baking), and / or other suitable processes. The etching process may include dry etching, wet etching, and / or other suitable etching processes (e.g., reactive ion etching).

[0045] Please refer to the reply. Figure 1 Method M then proceeds to step S103, where one or more etching processes are performed on the dielectric structure to form a plurality of first openings exposing capacitor contacts. Please refer to... Figure 3A as well as Figure 3B In some embodiments of step S103, the dielectric structure 105 is anisotropically etched and patterned by using a first patterned hard shielding layer 112 as an etching shield to form a first opening O1 thereon, wherein when the aforementioned patterning is completed, the first patterned hard shielding layer 112 is partially consumed, and the first patterned hard shielding layer 112 is removed after the etching is completed.

[0046] like Figure 3AAs shown, first openings O1 are arranged in columns r1, r2, r4, and r5. There is a distance D1 between columns r1 and r2, and a distance D2 between columns r2 and r4, where distance D1 is less than distance D2. There is a distance D3 between columns r4 and r5, where distance D3 is less than distance D2. In some embodiments, distance D1 may be less than half the distance D2. Distance D3 may be less than half the distance D2. In some embodiments, the first openings O1 in column r1 may be evenly spaced. The first openings O1 in column r2 may be evenly spaced. The first openings O1 in column r4 may be evenly spaced. The first openings O1 in column r5 may be evenly spaced. The first openings O1 have a circular top view pattern. In some embodiments, the first openings O1 may have a square top view pattern, a rectangular top view pattern, or an elliptical top view pattern. Figure 3B As shown in the cross-sectional view, the bottom of the first opening O1 has a width W1, the capacitor contact 102 has a width W2, and the width W1 is smaller than the width W2.

[0047] Please refer to the reply. Figure 1 Method M then proceeds to step S104, wherein the bottom metal layer of the pillar-capacitor stacked capacitor structure is conformally formed above the dielectric structure and in the first opening. Please refer to... Figure 4A as well as Figure 4B In some embodiments of step S104, the bottom electrode layer 130 is conformally formed over the dielectric structure 105 and the capacitor contact 102. For example... Figure 4B As shown, the bottom electrode layer 130 is liner-shaped on the sidewall of the first opening O1 and the top surface of the capacitive contact 102. In some embodiments, the bottom electrode layer 130 may be made of copper, platinum (Pt), ruthenium (Ru), aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), or other suitable materials. In some embodiments, the bottom electrode layer 130 may be formed using chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, the bottom electrode layer 130 may also be referred to as a surface substrate in this disclosure.

[0048] Please refer to the reply. Figure 1 Method M then proceeds to step S105, wherein a patterned hard shielding layer is formed above the bottom metal layer, wherein at least one perforation in the patterned hard shielding layer is laterally located between two adjacent first openings and does not cover the first openings. Please refer to... Figure 5A as well as Figure 5B In some embodiments of step S105, a second patterned hard shielding layer 114 is formed above the bottom electrode layer 130 belonging to the pillar-capacitor stacked capacitor structure C1. The second patterned hard shielding layer 114 has a through-hole E1. The through-hole E1 is laterally located between two adjacent first openings O1 in columns r2 and r4, and does not cover the first openings O1. In subsequent processes, the through-hole E1 can be used to remove the bottom electrode layer 130, the third dielectric layer 110, and the sacrificial layer 108 located beneath it. Figure 5A As shown, perforations E1 are arranged in column r3. Perforations E1 have a circular top view pattern. In some embodiments, perforations E1 may have a square top view pattern, a rectangular top view pattern, or an elliptical top view pattern.

[0049] In some embodiments, the second patterned hard shielding layer 114 may comprise tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The formation of the second patterned hard shielding layer 114 may include a series of processes, including deposition, photolithography patterning, and etching. The photolithography patterning process may include photoresist coating (e.g., selective coating), soft baking, shield alignment, exposure, post-exposure baking, photoresist development, cleaning, drying (e.g., hard baking), and / or other suitable processes. The etching process may include dry etching, wet etching, and / or other suitable etching processes (e.g., reactive ion etching).

[0050] Please refer to the reply. Figure 1 Method M then proceeds to step S106, wherein one or more etching processes are performed on the top dielectric layer in the dielectric structure by patterning a hard shielding layer to form at least one second opening. Please refer to... Figure 6A as well as Figure 6BIn some embodiments of step S106, one or more etching processes P1 are performed through the second patterned hard shielding layer 114 on the bottom electrode layer 130, the third dielectric layer 110, and the sacrificial layer 108 to form the second opening O2. In some embodiments, the etching process P1 may be performed to etch through the third dielectric layer 110 and further etch the sacrificial layer 108, and the etching may be stopped before the etching reaches the second dielectric layer 107. In some embodiments, the etching process P1 may be performed to etch through the third dielectric layer 110 and further etch the sacrificial layer 108 until the second dielectric layer 107 is exposed.

[0051] like Figure 6A as well as Figure 6B As shown, the second opening O2 is laterally located between two adjacent first openings O1 and does not cover the first openings O1 or the capacitor contact 102. Specifically, the capacitor array structure A1 has a dense capacitor pattern region T1 and a sparse capacitor pattern region T2. ​​The second opening O2, used to remove the sacrificial layer 108 in a subsequent process, is formed in the sparse capacitor pattern region T2 to prevent the second opening O2 from forming above the capacitor contact 102. Therefore, during the etching of the third dielectric layer 110 to form the second opening O2, the bottom electrode layer 130 formed above the capacitor contact 102 is not damaged by the etching process P1, thereby improving the capacitance value of the pillar-capacitor stacked capacitor structure C1.

[0052] like Figure 6B As shown, the second opening O2 has a width W3. In the cross-sectional view, the width W3 is greater than the width W1 of the bottom of the first opening O1 and greater than the width W4 of the top of the first opening O1. Figure 6B As shown, the second opening O2 is arranged in column r3. Column r3 is parallel to columns r2 and r4, and is located between columns r2 and r4. Figure 5A As shown, the perforations E1 are arranged in column r3. The second opening O2 has a circular top view pattern. In some embodiments, the second opening O2 may have a square top view pattern, a rectangular top view pattern, or an elliptical top view pattern.

[0053] In some embodiments, the etching process P1 may include a dry etching process, a wet etching process, and / or other suitable etching processes (e.g., reactive ion etching). In some embodiments, the bottom metal layer 130, the sacrificial layer 108, and the third dielectric layer 110 are anisotropically etched and patterned using a second patterned hard shielding layer 114 as an etching shield to form a second opening O2 therein. When the aforementioned patterning is completed, the second patterned hard shielding layer 114 is partially consumed, and the second patterned hard shielding layer 114 is removed after etching is completed. In some embodiments, the etching process P1 may be an anisotropic dry etching process (e.g., reactive-ion etching process (RIE) or atomic layer etching (ALE). For example, but not limited to this disclosure, the dry etching process may include oxygen-containing gas, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBR3), iodine-containing gas or other suitable gas and / or plasma, or any combination thereof.

[0054] Please refer to the reply. Figure 1 Method M then proceeds to step S107, where a planarization process is performed on the patterned hard shielding layer and the bottom electrode layer until the dielectric structure is exposed. Please refer to... Figure 7A as well as Figure 7B In some embodiments of step S107, a planarization process P2 is performed to remove the second patterned hard shielding layer 114 and the excess bottom electrode layer 130 above the dielectric structure 105 until the third dielectric layer 110 is exposed. For example, the planarization process P2 may be a chemical mechanical planarization (CMP) process.

[0055] In the aforementioned embodiments, during the planarization process, the third dielectric layer 110 can serve as a stop layer for chemical mechanical planarization. Specifically, the polishing slurry used in the chemical mechanical planarization process has a faster removal rate for the bottom electrode layer 130 than for the third dielectric layer 110 (e.g., silicon nitride). After planarization process P2 is completed, the bottom electrode layer 130 may have a U-shaped profile, and the third dielectric layer 110 may have a top surface 110t flush with the top surface 130t of the bottom electrode layer 130.

[0056] Please refer to the reply. Figure 1Method M then proceeds to step S108, where the sacrificial layer laterally surrounding the first opening in the dielectric structure is removed through the second opening. Please refer to... Figure 8A as well as Figure 8B In some embodiments of step S108, the remaining sacrificial layer 108 in the dielectric structure 105 is removed to form a space S1 between the second dielectric layer 107 and the third dielectric layer 110, such that the top surface 107s of the second dielectric layer 107 and the bottom surface 110b of the third dielectric layer 110 are exposed from the space S1.

[0057] In some embodiments, the sacrificial layer 108 is removed by etching process P3. In some embodiments, the second dielectric layer 107 and the third dielectric layer 110 have greater etch resistance than the sacrificial layer 108. In other words, etching process P3 is a selective etching process, allowing for a faster etching rate to etch the sacrificial layer 108 compared to the second dielectric layer 107 and the third dielectric layer 110. In some embodiments, the sacrificial layer 108 can be removed using a wet etching process. In some embodiments, the sacrificial layer 108 can be removed using an etching process containing diluted hydrogen fluoride (HF), SiCoNi (containing hydrogen fluoride (HF) and ammonia (NH3)), or other similar etchants. For example, if the material of the sacrificial layer 108 contains silicon nitride, the sacrificial layer 108 can be removed by diluted hydrogen fluoride.

[0058] Please refer to the reply. Figure 1 Method M then proceeds to step S109, where a capacitor dielectric layer is formed above the bottom electrode layer. Please refer to... Figure 9A as well as Figure 9BIn some embodiments of step S109, the capacitor dielectric layer 132 is conformally formed above the bottom electrode layer 130. The capacitor dielectric layer 132 may comprise a high dielectric constant dielectric material. For example, the capacitor dielectric layer 132 may comprise aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium oxynitride (ZrON), zirconium silicate (ZrSiO2), yttrium oxide (Y2O3), lanthanum oxide (La2O3), cerium oxide (CeO2), titanium oxide (TiO2), tantalum oxide (Ta2O5), or any combination thereof. In some embodiments, the method for forming the capacitor dielectric layer 132 may include chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD).

[0059] Please refer to the reply. Figure 1 Method M then proceeds to step S110, where the top electrode layer is formed above the capacitor dielectric layer. Please refer to... Figure 9A as well as Figure 9B In some embodiments of step S110, the top electrode layer 134 is formed above the capacitor dielectric layer 132 and is located in the space S1 between the second dielectric layer 107 and the third dielectric layer 110, thereby laterally surrounding the base column container stacked capacitor structure C1.

[0060] like Figure 9BAs shown, the top electrode layer 134 has a portion 134p extending through the third dielectric layer 110. Viewed from the top view, portion 134p has a larger dimension than the top electrode layer 134 located directly above the capacitor contact 102. In some embodiments, the size of portion 134p, viewed from the top view, may be in the range of approximately 1.5 to approximately 10 times the size of the top electrode layer 134 located directly above the capacitor contact 102 (e.g., approximately 1.5, 2, 3, 4, 5, 6, 7, 8, 9, or 10 times). In some embodiments, the distance between two adjacent portions 134p in the same column may be greater than the distance between two adjacent base-pillar container stacked capacitor structures C1 in the same column. In some embodiments, the distance between portion 134p and its adjacent base-pillar container stacked capacitor structure C1 may be less than the distance between two adjacent base-pillar container stacked capacitor structures C1 in the same column.

[0061] like Figure 9A As shown, portions 134p of the top electrode layer 134 are arranged in column r3, where column r3 is located between and parallel to columns r2 and r4. The portions 134p of the top electrode layer 134 have a circular top view pattern. In some embodiments, the portions 134p may have a square, rectangular, or elliptical top view pattern.

[0062] Therefore, a column-mounted capacitor stack C1 is formed and extends upward above the substrate 100, and is arranged in columns r1, r2, r4, and r5. In some embodiments, there are no other column-mounted capacitor stack C1 structures between columns r1 and r2, between columns r2 and r4, and between columns r4 and r5. In some embodiments, the column-mounted capacitor stack C1 structures in column r1 may be evenly spaced (see...). Figure 9B The stacked capacitor structure C1 in column r2 can be arranged at equal intervals, the stacked capacitor structure C1 in column r4 can be arranged at equal intervals, and the stacked capacitor structure C1 in column r5 can be arranged at equal intervals.

[0063] In some embodiments, the top electrode layer 134 may be made of copper, platinum (Pt), ruthenium (Ru), aluminum, tantalum, tungsten, tantalum nitride (TaN), titanium, titanium nitride (TiN), or other suitable materials. In some embodiments, the top electrode layer 134 may be made of a metallic material. In some embodiments, the top electrode layer 134 may be made of a doped polycrystalline silicon layer. In some embodiments, the top electrode layer 134 may be formed using chemical vapor deposition (CVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). In some embodiments, the bottom electrode layer 130 may also be referred to as the surface top plate in this disclosure.

[0064] Based on the foregoing discussion, it is evident that this disclosure offers advantages. However, it should be understood that other embodiments may offer additional advantages, and not all advantages need to be disclosed herein, nor is any particular advantage required for all embodiments. This disclosure provides a capacitor array structure with a pillar-capacitor stacked capacitor structure in several embodiments. The method of forming the pillar-capacitor stacked capacitor structure includes, prior to forming the pillar-capacitor stacked capacitor structure, forming a dielectric stack structure having at least two dielectric layers over a plurality of capacitor contacts; and forming a bottom electrode layer of the pillar-capacitor stacked capacitor structure through the dielectric stack structure to land on the capacitor contacts. To increase the capacitance value of the cell, a sacrificial layer located in the dielectric stack structure is removed through an opening in the top dielectric layer of the dielectric stack structure, the aforementioned opening covering the capacitor contacts. This allows the additional space created by removing the sacrificial layer to be further filled with the top metal material of the pillar-capacitor stacked capacitor structure to increase the capacitance value. However, when etching the top dielectric layer to form the opening for the removable sacrificial layer, the bottom electrode layer formed above the capacitor contacts may be damaged by the etching process, resulting in a decrease in capacitance.

[0065] Therefore, various embodiments disclosed herein provide capacitor array structures having dense and sparse regions of capacitor patterns. Openings for removing the sacrificial layer in the dielectric stack structure are formed in the sparse regions of the capacitor pattern to prevent these openings from forming above the capacitor contacts. Therefore, during the etching of the top dielectric layer to form the aforementioned openings, the bottom electrode layer formed above the capacitor contacts is not damaged by the etching process, thereby improving the capacitance value of the pillar-capacitor stacked capacitor structure.

[0066] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same objectives and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

[0067] [Symbol Explanation]

[0068] 100: Substrate

[0069] 101: Metal layer

[0070] 102: Capacitor Contact

[0071] 103: Dielectric Materials

[0072] 104: Etching Stop Layer

[0073] 105: Dielectric Structure

[0074] 106: First dielectric layer

[0075] 107: Second dielectric layer

[0076] 107s: Top surface

[0077] 108: Sacrifice Layer

[0078] 110: Third dielectric layer

[0079] 110b: Bottom surface

[0080] 110t: Top surface

[0081] 112: First patterned hard shielding layer

[0082] 114: Second patterned hard shielding layer

[0083] 120: Capacitor opening pattern

[0084] 130: Bottom electrode layer

[0085] 130t: Top surface

[0086] 132: Capacitor dielectric layer

[0087] 134: Top electrode layer

[0088] 134p: Location

[0089] A1: Capacitor array structure

[0090] A-A': Line segment

[0091] C1: Pillar-type stacked capacitor structure

[0092] D1: Distance

[0093] D2: Distance

[0094] D3: Distance

[0095] E1: Perforation

[0096] M: Method

[0097] O1: First opening

[0098] O2: Second opening

[0099] P1: Etching process

[0100] P2: Planarization process

[0101] P3: Etching Process

[0102] r1: column

[0103] r2: column

[0104] r3: column

[0105] r4: column

[0106] r5: column

[0107] S1: Space

[0108] S101: Steps

[0109] S102: Steps

[0110] S103: Steps

[0111] S104: Steps

[0112] S105: Steps

[0113] S106: Steps

[0114] S107: Steps

[0115] S108: Steps

[0116] S109: Steps

[0117] S110: Steps

[0118] T1: Dense area of ​​capacitor pattern

[0119] T2: Sparse area of ​​capacitor pattern

[0120] W1: Width

[0121] W2: Width

[0122] W3: Width.

Claims

1. A capacitor array structure, characterized in that, include: Substrate; A plurality of first-base-pillar stacked capacitor structures extend upward above the substrate and are arranged in a first column; A plurality of second-base-pillar stacked capacitor structures extend upward above the substrate and are arranged in a second column, the second column being adjacent to the first column; A plurality of third-pillar capacitor stacked structures extend upward above the substrate and are arranged in a third column, the third column being adjacent to the second column. The first column is separated from the second column by a first distance, and the second column is separated from the third column by a second distance, wherein the first distance is less than the second distance. Each of the first, second, and third-pillar capacitor stacked structures includes a bottom electrode layer with a U-shaped cross-section, a capacitor dielectric layer located above the bottom electrode layer, and a top electrode layer located above the capacitor dielectric layer; and The first dielectric layer laterally surrounds the plurality of top positions of the first, second, and third pillar-type stacked capacitor structures. In one of the second pillar container stacked capacitor structures, the top electrode layer extends downward through the first dielectric layer to the space below the first dielectric layer to laterally surround the second pillar container stacked capacitor structure, and the portion of the top electrode layer of the second pillar container stacked capacitor structure is located in the first dielectric layer, and in the top view, the portion has a circular top view pattern and is adjacent to the second pillar container stacked capacitor structure.

2. The capacitor array structure according to claim 1, characterized in that, Further includes: A plurality of fourth-base-pillar stacked capacitor structures extend upward above the substrate and are arranged in a fourth column, the fourth column being adjacent to the third column, the third column being a third distance from the fourth column, and the third distance being less than the second distance.

3. The capacitor array structure according to claim 2, characterized in that, The first distance is less than half of the second distance.

4. The capacitor array structure according to claim 1, characterized in that, These first-pillar container stacked capacitor structures are arranged at equal intervals in the first column.

5. The capacitor array structure according to claim 1, characterized in that, These second-pillar container stacked capacitor structures are arranged at equal intervals in the second column.

6. The capacitor array structure according to claim 1, characterized in that, It further includes a capacitive contact located between the second pillar container stacked capacitor structure and the substrate, wherein the width of the capacitive contact is greater than the width of the bottommost surface of the bottom electrode layer of the second pillar container stacked capacitor structure.

7. The capacitor array structure of claim 6, wherein the portion of the top electrode layer of the second pillar capacitor stacked structure does not cover the capacitor contact.

8. The capacitor array structure according to claim 1, characterized in that, The portion of the top electrode layer of the second pillar container stacked capacitor structure is further located between the second column and the third column.

9. The capacitor array structure according to claim 1, characterized in that, The top surface of the first dielectric layer is flush with the top surface of the bottom electrode layer of the second pillar container stacked capacitor structure.

10. The capacitor array structure according to claim 1, characterized in that, Further includes: The second dielectric layer laterally surrounds a plurality of bottom positions of the first pillar container stacked capacitor structures, the second pillar container stacked capacitor structures, and the third pillar container stacked capacitor structures, and is separated from the first dielectric layer.

11. A method for forming a capacitor array structure, characterized in that, include: A first nitride layer, a first oxide layer, and a second nitride layer are sequentially deposited over a first contact and a second contact, the first contact and the second contact being located on a substrate; The first nitride layer, the first oxide layer, and the second nitride layer are etched to form a first opening and a second opening that expose the first contact and the second contact; A bottom metal layer is conformally deposited on the first nitride layer, the first oxide layer, the second nitride layer, the first contact, and the second contact; A shielding layer is formed on a first portion of the bottom metal layer, the first portion being located above the first contact and the second contact, while exposing a second portion of the bottom metal layer, the second portion being located between the first contact and the second contact; The shielding layer is etched to form the second nitride layer and the first oxide layer to form a third opening, the third opening having a bottom position higher than the top surface of the first nitride layer; After etching the second nitride layer and the first oxide layer, the shielding layer is removed from the bottom metal layer; After the shielding layer is removed, the first oxide layer is removed through the third opening; A capacitor dielectric layer is formed above the bottom metal layer; as well as A top electrode layer is formed above the capacitor dielectric layer.

12. The method according to claim 11, characterized in that, The second nitride layer and the first oxide layer are etched by a dry etching process.

13. The method according to claim 11, characterized in that, The first oxide layer was removed by a wet etching process.

14. The method according to claim 13, characterized in that, The rate at which the wet etching process etches the first oxide layer is greater than the rate at which it etches the first nitride layer and the second nitride layer.

15. The method according to claim 11, characterized in that, The third opening does not cover the first contact or the second contact.

16. The method according to claim 11, characterized in that, In a cross-sectional view, the third opening has a larger size than the first opening.

17. The method according to claim 11, characterized in that, The shielding layer was removed through a planarization process.

18. The method according to claim 11, characterized in that, The capacitor dielectric layer is formed above the bottom metal layer, so that the capacitor dielectric layer is further formed on the sidewall of the third opening.

19. The method according to claim 11, characterized in that, Further includes: Before depositing the first nitride layer, the first oxide layer, and the second nitride layer, a second oxide layer is deposited over the first contact and the second contact.

20. The method according to claim 11, characterized in that, Further includes: Before depositing the first nitride layer, the first oxide layer, and the second nitride layer, an etch stop layer is deposited over the first contact and the second contact.

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