An ultrasonic control circuit and a driving method thereof, and an ultrasonic monitoring device

Abstract

The application provides an ultrasonic control circuit and a driving method thereof and an ultrasonic monitoring device, relates to the technical field of ultrasonic waves, and can effectively reduce or even eliminate background noise and improve the signal-to-noise ratio. The ultrasonic control circuit comprises an ultrasonic sensor, a first node, a first reset sub-circuit, a first reset signal line, a first control signal line and the first node. The ultrasonic sensor is electrically connected to the first node and is configured to receive a return signal of an object and write the return signal into the first node. The first reset sub-circuit is electrically connected to the first reset signal line, the first control signal line and the first node, is configured to reset the first node under the control of a first reset signal of the first reset signal line in a first state, and does not work in a second state.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of ultrasonic waves, and in particular to an ultrasonic control circuit, a driving method thereof, and an ultrasonic monitoring device. BACKGROUND

[0002] With the development of science and technology, ultrasonic sensors have been more and more widely applied, for example, can be applied to medical diagnosis, medical treatment, etc., and a large-area integrated flexible ultrasonic sensor is one of them.

[0003] In the current large-area integrated flexible ultrasonic sensor, the control circuit often has the problems of thermal noise, flicker noise, shot noise, and other background noise (background noise), which may cause ultrasonic signal distortion, etc., and thus cannot guarantee the effectiveness of the image, resulting in poor user experience. SUMMARY

[0004] Embodiments of the present application provide an ultrasonic control circuit, a driving method thereof, and an ultrasonic monitoring device, which can effectively reduce or even eliminate background noise and improve the signal-to-noise ratio.

[0005] To achieve the above-mentioned purpose, embodiments of the present application adopt the following technical solutions:

[0006] In one aspect, an ultrasonic control circuit is provided, which includes:

[0007] An ultrasonic sensor is electrically connected to a first node and is configured to be capable of receiving a return signal of an object and writing the return signal to the first node;

[0008] A first reset sub-circuit is electrically connected to a first reset signal line, a first control signal line, and the first node, and is configured to, in a first state, reset the first node under the control of a first reset signal of the first reset signal line, and in a second state, not to work;

[0009] A second reset sub-circuit is electrically connected to a second reset signal line, a ground terminal, and a second node, and is configured to reset the second node under the control of a second reset signal of the second reset signal line;

[0010] A signal transmission sub-circuit is electrically connected to a second control signal line, a third node, and the first node, and is configured to write a signal of the first node to the third node under the control of a second control signal of the second control signal line;

[0011] an output sub-circuit electrically connected with the gate signal line, the third node, the voltage signal line and the second node, configured to write a voltage signal of the voltage signal line and the signal of the third node into the second node under control of a gate signal of the gate signal line and the signal of the third node;

[0012] a storage sub-circuit electrically connected with the second node, a third control signal line and a processing sub-circuit, configured to write the signal of the second node into the processing sub-circuit under control of a third control signal of the third control signal line;

[0013] the processing sub-circuit configured to receive and process the signal of the second node.

[0014] Optionally, the ultrasonic control circuit further comprises an adjusting sub-circuit electrically connected with the third node, an adjusting signal line and the ground terminal, configured to control the electrical signal of the third node under control of an adjusting signal of the adjusting signal line.

[0015] Optionally, the first reset sub-circuit comprises a first transistor.

[0016] a control electrode of the first transistor is electrically connected with the first reset signal line, a first electrode is electrically connected with the first control signal line, and a second electrode is electrically connected with the first node.

[0017] Optionally, the first reset sub-circuit comprises a first transistor.

[0018] a control electrode of the first transistor is electrically connected with the first reset signal line, a first electrode is electrically connected with the voltage signal line, and a second electrode is electrically connected with the first node.

[0019] Optionally, the second reset sub-circuit comprises a fifth transistor.

[0020] a control electrode of the fifth transistor is electrically connected with the second reset signal line, a first electrode is electrically connected with the ground terminal, and a second electrode is electrically connected with the second node.

[0021] Optionally, the signal transmission sub-circuit comprises a second transistor.

[0022] a control electrode of the second transistor is electrically connected with the second control signal line, a first electrode is electrically connected with the first node, and a second electrode is electrically connected with the third node.

[0023] Optionally, the output sub-circuit comprises a third transistor, a fourth transistor and a first capacitor.

[0024] a control electrode of the third transistor is electrically connected with the third node, a first electrode is electrically connected with the voltage signal line, and a second electrode is electrically connected with the second node.

[0025] a control electrode of the fourth transistor is electrically connected with the gate signal line, a first electrode is electrically connected with the second node, and a second electrode is electrically connected with the third node;

[0026] a first end of the first capacitor is electrically connected with the third node, and a second end is electrically connected with the ground terminal.

[0027] Optionally, the storage sub-circuit at least includes a sixth transistor and a second capacitor;

[0028] a control electrode of the sixth transistor is electrically connected with a first third control signal line, a first electrode is electrically connected with the second node, and a second electrode is electrically connected with a first end of the second capacitor;

[0029] the first end of the second capacitor is also electrically connected with the processing sub-circuit, and a second end is electrically connected with the ground terminal.

[0030] Optionally, the storage sub-circuit includes the sixth transistor, the second capacitor, a seventh transistor and a third capacitor;

[0031] a control electrode of the seventh transistor is electrically connected with a second third control signal line, a first electrode is electrically connected with the second node, and a second electrode is electrically connected with a first end of the third capacitor;

[0032] the first end of the third capacitor is also electrically connected with the processing sub-circuit, and a second end is electrically connected with the ground terminal.

[0033] Optionally, the processing sub-circuit at least includes an amplifier;

[0034] a first end of the amplifier is electrically connected with the storage sub-circuit.

[0035] Optionally, the adjustment sub-circuit includes at least one switching transistor and an adjustment capacitor;

[0036] a control electrode of the switching transistor is electrically connected with the adjustment signal line, a first electrode is electrically connected with the adjustment capacitor, and a second electrode is electrically connected with the third node;

[0037] a second end of the adjustment capacitor is electrically connected with the ground terminal.

[0038] In another aspect, an ultrasonic monitoring device is provided, which includes at least one of the above ultrasonic control circuits.

[0039] In still another aspect, a driving method is provided for driving the above ultrasonic control circuit;

[0040] The method includes:

[0041] in the first state stage, a first reset signal is written to a first reset signal line;

[0042] In the second state stage, the first reset signal line is not written with the first reset signal.

[0043] Embodiments of the present application provide an ultrasonic control circuit, comprising: an ultrasonic sensor, electrically connected to a first node, configured to receive a return signal of an object and write the return signal to the first node; a first reset sub-circuit, electrically connected to a first reset signal line, a first control signal line and the first node, configured to reset the first node under control of a first reset signal of the first reset signal line in a first state, and not work in a second state; a second reset sub-circuit, electrically connected to a second reset signal line, a ground terminal and a second node, configured to reset the second node under control of a second reset signal of the second reset signal line; a signal transmission sub-circuit, electrically connected to a second control signal line, a third node and the first node, configured to write a signal of the first node to the third node under control of a second control signal of the second control signal line; an output sub-circuit, electrically connected to a gate signal line, the third node, a voltage signal line and the second node, configured to write a voltage signal of the voltage signal line and a signal of the third node to the second node under control of a gate signal of the gate signal line and the signal of the third node; a storage sub-circuit, electrically connected to the second node, a third control signal line and a processing sub-circuit, configured to write a signal of the second node to the processing sub-circuit under control of a third control signal of the third control signal line; and the processing sub-circuit, configured to receive and process the signal of the second node.

[0044] In this way, when the ultrasonic control circuit is in the first state, since the first reset sub-circuit is configured to reset the first node under control of the first reset signal of the first reset signal line, whether the ultrasonic sensor transmits the return signal or not, the return signal will not affect the potential of the third node, and the third node can maintain the first reset signal of the first reset signal line, at this time, the ultrasonic control circuit can obtain a first electric signal with a background noise. When the ultrasonic control circuit is in the second state, since the first reset sub-circuit does not work, if the ultrasonic sensor transmits the return signal, the return signal will affect the potential of the third node, and the potential of the third node changes, at this time, the ultrasonic control circuit can obtain a second electric signal with a background noise and an effective signal. Thus, the second electric signal is subtracted from the first electric signal, and an effective signal of the ultrasonic control circuit is obtained, and then the effective signal can be better analyzed. Therefore, the present application effectively reduces or even eliminates the background noise of the ultrasonic control circuit, improves the signal-to-noise ratio, and thus obtains a low-noise ultrasonic control circuit, and the user experience is good.

[0045] The above description is only a summary of the technical solutions of the present application. In order to make the technical means of the present application more clear and understandable, and to make the above and other purposes, characteristics and advantages of the present application more obvious and easy to understand, the following will describe the specific embodiments of the present application in detail. BRIEF DESCRIPTION OF DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without any creative labor.

[0047] Figure 1 A schematic diagram of the principle of the ultrasonic sensor emitting sound waves is provided for the embodiments of the present application;

[0048] Figure 2 A schematic diagram of the principle of the ultrasonic sensor receiving sound waves is provided for the embodiments of the present application;

[0049] Figure 3 Another schematic diagram of the principle of the ultrasonic sensor receiving sound waves is provided for the embodiments of the present application;

[0050] Figure 4 An actual application diagram of the ultrasonic sensor is provided for the embodiments of the present application;

[0051] Figure 5 A schematic diagram of the ultrasonic control circuit is provided for the embodiments of the present application;

[0052] Figure 6 A driving timing diagram of the ultrasonic control circuit is provided for the embodiments of the present application;

[0053] Figure 7 Another schematic diagram of the ultrasonic control circuit is provided for the embodiments of the present application;

[0054] Figure 8 Another driving timing diagram of the ultrasonic control circuit is provided for the embodiments of the present application;

[0055] Figure 9 A schematic diagram of the ultrasonic control circuit is provided for the embodiments of the present application;

[0056] Figure 10 A schematic diagram of the electrical connection of two ultrasonic control circuits is provided for the embodiments of the present application;

[0057] Figures 11-16 The ultrasonic control circuit is used for Figure 9 the ultrasonic control circuit in Figure 6A driving principle schematic diagram under the driving timing of the driving circuit. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0059] In the embodiments of the present application, the same items or similar items with basically the same functions and effects are distinguished by using "first", "second", "third", "fourth", "fifth", "sixth", "seventh", "eighth", "ninth", "8+n", "4+n", etc. only for clearly describing the technical solutions of the embodiments of the present application, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features.

[0060] In the embodiments of the present application, the meaning of "at least one" is one or more than one, unless otherwise explicitly and specifically limited.

[0061] In the embodiments of the present application, the gate of a transistor is referred to as a control electrode, one of the source and the drain is referred to as a first electrode, and the other is referred to as a second electrode. In the embodiments of the present application, the first electrode of all transistors is referred to as a drain, and the second electrode is referred to as a source as an example.

[0062] In the embodiments of the present application, the term "electrically connected" can mean that two components are directly electrically connected, or that two components are electrically connected via one or more other components; "electrically connected" can mean electrically connected by a wire, or can mean electrically connected by a wireless electrical signal.

[0063] With the development of science and technology, ultrasonic waves have been more and more widely used, for example, can be applied to nondestructive testing, distance measurement, thickness measurement in industry, breeding, seedling raising, and production promotion in agriculture, diagnosis and treatment in biology and medicine, fingerprint recognition in consumer electronic products, and other fields, so that ultrasonic sensors using ultrasonic waves are also being more and more widely studied.

[0064] The generation principle and the receiving principle of ultrasonic waves in the ultrasonic sensor will be described below. Figure 1 The generation principle and the receiving principle of ultrasonic waves in the ultrasonic sensor will be described below. Figure 2 The generation principle and the receiving principle of ultrasonic waves in the ultrasonic sensor will be described below. Figure 1 The generation principle and the receiving principle of ultrasonic waves in the ultrasonic sensor will be described below. Figure 2As shown, the ultrasonic sensor includes a top electrode, a piezoelectric material layer and a bottom electrode, and the piezoelectric material layer is arranged between the top electrode and the bottom electrode. Among them, the top electrode and the bottom electrode are both arranged in layers.

[0065] Referring to Figure 1 As shown, a voltage with a phase difference can be input between the top electrode and the bottom electrode, for example, the top electrode can be grounded and the bottom electrode can input an AC (Alternating Current) voltage, at this time, the piezoelectric material layer can be deformed to generate a sound wave, and the sound wave here is an ultrasonic wave.

[0066] Referring to Figure 2 As shown, the object reflects the sound wave, and when the sound wave is reflected to the piezoelectric material layer, it can be converted into an AC voltage, at this time, if the top electrode is grounded, the bottom electrode can output the AC voltage as a receiving end.

[0067] It should be noted that the material of the piezoelectric material layer can include a high polymer piezoelectric material, for example: PVDF (Polyvinylidene Fluoride), PVDF-TrFE (Poly(Vinylidene Fluoride-Co-Trifluoroethylene)), etc.; or the material of the piezoelectric material layer can include inorganic materials, for example: AlN (aluminum nitride), PZT (lead zirconate titanate piezoelectric ceramic), ZnO (zinc oxide), etc.

[0068] The principle of the ultrasonic wave in the ultrasonic sensor will be introduced below. Figure 3 Referring to Figure 3 As shown, the ultrasonic sensor includes a bottom electrode (Ag), a piezoelectric material layer (PVDF), a top electrode, a driving circuit (TFT (Thin Film Transistor)) and a substrate (Glass) arranged in sequence. Among them, the bottom electrode is arranged in layers, and the top electrode includes a plurality of discrete and spaced sub-electrodes (RX).

[0069] Referring to Figure 3 As shown, the PZT emits a sound wave to the object, the sound wave reflected by the object is shot to the ultrasonic sensor, the ultrasonic sensor receives the sound wave reflected by the object and converts it into an electrical signal, and then transmits it to the TFT driving circuit through the RX electrode. At this time, the PZT emits an excitation signal, and the emission energy of the PZT sound source is large.

[0070] It should be noted that, Figure 3The sound wave is generated by the PZT, and the ultrasonic sensor only receives the sound wave. Of course, the ultrasonic sensor itself can generate and receive the sound wave, which is not specifically limited here.

[0071] Traditional medical ultrasonic imaging often uses an ultrasonic focusing beam to detect human tissue. However, due to the narrowness of the focusing beam, each time of focusing imaging is in the form of a line, and a two-dimensional image is obtained by splicing multiple scanning focused images, and then the probe is moved to scan a three-dimensional image. This technology has the defects of slow imaging rate, complex device structure, and a frame rate of generally only 30 frames per second. In order to solve this problem, Figure 4 A large-area integrated flexible ultrasonic sensor is provided, as shown in Figure 4 The ultrasonic sensor can be entirely covered on the surface of human tissue, such as the back, belly, arm, thigh, and other large tissue surfaces of the human body, to realize high-precision, large-area, multi-dimensional real-time imaging, and other advantages.

[0072] However, in the current large-area integrated flexible ultrasonic sensor, the ultrasonic control circuit often has problems such as thermal noise, flicker noise, shot noise, and other noise floors. The noise floor of the ultrasonic control circuit in the ultrasonic sensor can cause ultrasonic signal distortion, and thus cannot guarantee the effectiveness of the image, resulting in poor user experience.

[0073] To solve the above problems, an ultrasonic control circuit is provided, as shown in Figure 5 and Figure 7 The ultrasonic control circuit includes:

[0074] An ultrasonic sensor 1 is electrically connected to a first node P and is configured to be capable of receiving a return signal of an object and writing the return signal to the first node P.

[0075] A first reset sub-circuit 2 is electrically connected to a first reset signal line Reset1, a first control signal line Drst, and the first node P, and is configured to reset the first node P under the control of a first reset signal of the first reset signal line Reset1 in a first state, and not to work in a second state.

[0076] A second reset sub-circuit 5 is electrically connected to a second reset signal line Reset2, a ground terminal GND, and a second node Q, and is configured to reset the second node Q under the control of a second reset signal of the second reset signal line Reset2.

[0077] A signal transmission sub-circuit 3 is electrically connected to a second control signal line Vclose, a third node W, and the first node P, and is configured to write a signal of the first node P to the third node W under the control of a second control signal of the second control signal line Vclose.

[0078] The output sub-circuit 4, electrically connected with the gate signal line Gate, the third node W, the voltage signal line VDD and the second node Q, is configured to write the voltage signal of the voltage signal line VDD and the signal of the third node W into the second node Q under the control of the gate signal of the gate signal line Gate and the signal of the third node W.

[0079] The storage sub-circuit 6, electrically connected with the second node Q, the third control signal line Vg and the processing sub-circuit 7, is configured to write the signal of the second node Q into the processing sub-circuit 7 under the control of the third control signal of the third control signal line Vg.

[0080] The processing sub-circuit 7 is configured to receive and process the signal of the second node Q.

[0081] Here, the echo is not specifically limited, and may include a sound wave reflected by an object, a sound wave scattered by an object, etc.

[0082] The first state may be a state in which the ultrasonic sensor does not transmit a signal, or a state in which the ultrasonic sensor transmits a signal, but the signal does not affect the potential of the third node. At this time, the ultrasonic control circuit outputs an electrical signal with the background noise (noise floor) of the ultrasonic control circuit.

[0083] The second state may be a state in which the ultrasonic sensor transmits a signal, and the signal affects the potential of the third node. At this time, the ultrasonic control circuit outputs an electrical signal with the background noise (noise floor) of the ultrasonic control circuit and an effective signal, wherein the effective signal refers to an echo signal of an object.

[0084] The specific circuit structures of the first reset sub-circuit, the second reset sub-circuit, the signal transmission sub-circuit, the output sub-circuit, the output sub-circuit and the processing sub-circuit are not limited, as long as the corresponding functions are met.

[0085] The first node, the second node and the third node are only defined for the convenience of describing the circuit structure, and are not actual circuit units.

[0086] An embodiment of this application provides an ultrasonic control circuit, comprising: an ultrasonic sensor electrically connected to a first node, configured to receive echo signals from an object and write the echo signals into the first node; a first reset sub-circuit electrically connected to a first reset signal line, a first control signal line, and the first node, configured to reset the first node under the control of a first reset signal on the first reset signal line in a first state, and to not operate in a second state; a second reset sub-circuit electrically connected to a second reset signal line, a ground terminal, and a second node, configured to reset the second node under the control of a second reset signal on the second reset signal line; and a signal transmission sub-circuit electrically connected to a ground terminal and a second node; and a signal transmission sub-circuit electrically connected to a first reset signal line, a first control signal line, and the first node; and a signal transmission sub-circuit electrically connected to a first reset signal line, a first reset signal line, a first reset signal line, a first reset signal line, a first reset signal line, a first reset signal line, a first reset signal line, a first reset signal line, a first reset signal line, a first reset signal line, a first reset signal line, a second ... A sub-circuit is configured to connect a second control signal line, a third node, and a first node, and to write the signal of the first node to the third node under the control of a second control signal on the second control signal line; an output sub-circuit is electrically connected to a gate signal line, a third node, a voltage signal line, and a second node, and is configured to write the voltage signal of the voltage signal line and the signal of the third node to the second node under the control of the gate signal on the gate signal line and the signal of the third node; a storage sub-circuit is electrically connected to the second node, a third control signal line, and a processing sub-circuit, and is configured to write the signal of the second node to the processing sub-circuit under the control of a third control signal on the third control signal line; and a processing sub-circuit is configured to receive and process the signal of the second node.

[0087] Thus, when the ultrasonic control circuit is in the first state, since the first reset sub-circuit is configured to reset the first node under the control of the first reset signal of the first reset signal line, the echo signal will not affect the potential of the third node regardless of whether the ultrasonic sensor transmits an echo signal. The third node can maintain the first reset signal of the first reset signal line, and the ultrasonic control circuit can obtain a first electrical signal with background noise. When the ultrasonic control circuit is in the second state, since the first reset sub-circuit is not working, if the ultrasonic sensor transmits an echo signal, the echo signal will affect the potential of the third node, and the potential of the third node will change. At this time, the ultrasonic control circuit can obtain a second electrical signal with background noise and an effective signal. Therefore, subtracting the first electrical signal from the second electrical signal yields the effective signal of the ultrasonic control circuit, which can then be used for better analysis. Therefore, this application effectively reduces or even eliminates the background noise of the ultrasonic control circuit, improves the signal-to-noise ratio, and thus obtains a low-noise ultrasonic control circuit with a better user experience.

[0088] Optional, see reference Figure 9 As shown, the ultrasonic control circuit also includes an adjustment sub-circuit 8, which is electrically connected to the third node W, the adjustment signal line Vgc, and the ground terminal GND. It is configured to control the electrical signal of the third node W under the control of the adjustment signal of the adjustment signal line Vgc.

[0089] The ultrasonic control circuit provided by the embodiment of the present application can output different electrical signals by adjusting the potential of the third node when the adjusting sub-circuit is in the working state and when the adjusting sub-circuit is in the non-working state, thereby improving the collection range of the ultrasonic echo signal, so that the ultrasonic control circuit has a piezoelectric signal with a high dynamic range and low noise, and the ultrasonic control circuit can be applied more widely.

[0090] Optionally, as shown in Figure 5 The first reset sub-circuit 2 includes a first transistor M1; the control electrode of the first transistor M1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor M1 is electrically connected to the first control signal line Drst, and the second electrode of the first transistor M1 is electrically connected to the first node P.

[0091] Optionally, as shown in Figure 7 The first reset sub-circuit 2 includes a first transistor M1; the control electrode of the first transistor M1 is electrically connected to the first reset signal line Reset1, the first electrode of the first transistor M1 is electrically connected to the first control signal line Drst, and the second electrode of the first transistor M1 is electrically connected to the first node P. Figure 5 Compared with Figure 7 In the embodiment, the first electrode of the first transistor M1 is electrically connected to the voltage signal line VDD instead of the first control signal line Drst, so that one power supply design can be saved.

[0092] Optionally, as shown in Figure 5 and Figure 7 The second reset sub-circuit 5 includes a fifth transistor M5; the control electrode of the fifth transistor M5 is electrically connected to the second reset signal line Reset2, the first electrode of the fifth transistor M5 is electrically connected to the ground terminal GND, and the second electrode of the fifth transistor M5 is electrically connected to the second node Q.

[0093] Optionally, as shown in Figure 5 and Figure 7 The signal transmission sub-circuit 3 includes a second transistor M2; the control electrode of the second transistor M2 is electrically connected to the second control signal line Vclose, the first electrode of the second transistor M2 is electrically connected to the first node P, and the second electrode of the second transistor M2 is electrically connected to the third node W.

[0094] Optionally, as shown in Figure 5 and Figure 7 The output sub-circuit 4 includes a third transistor M3, a fourth transistor M4, and a first capacitor Cg; the control electrode of the third transistor M3 is electrically connected to the third node W, the first electrode of the third transistor M3 is electrically connected to the voltage signal line VDD, and the second electrode of the third transistor M3 is electrically connected to the second node Q; the control electrode of the fourth transistor M4 is electrically connected to the gate signal line Gate, the first electrode of the fourth transistor M4 is electrically connected to the second node Q, and the second electrode of the fourth transistor M4 is electrically connected to the third node W; the first end of the first capacitor Cg is electrically connected to the third node W, and the second end of the first capacitor Cg is electrically connected to the ground terminal GND.

[0095] Optionally, as shown in Figure 5As shown in the figure, the storage sub-circuit 6 at least includes the sixth transistor M6 and the second capacitor Cp1; the control electrode of the sixth transistor M6 is electrically connected with the first third control signal line Vg6, the first electrode is electrically connected with the second node Q, and the second electrode is electrically connected with the first end of the second capacitor Cp1; the first end of the second capacitor Cp1 is also electrically connected with the processing sub-circuit 7, and the second end is electrically connected with the ground terminal GND.

[0096] The storage sub-circuit at least including the sixth transistor and the second capacitor refers to that the storage sub-circuit only includes the sixth transistor and the second capacitor; or, the storage sub-circuit can include other transistors and other capacitors in addition to the sixth transistor and the second capacitor.

[0097] It should be noted that when the storage sub-circuit only includes the sixth transistor and the second capacitor, the second capacitor needs to store the electrical signal of the ultrasonic control circuit in the first state and the electrical signal of the ultrasonic control circuit in the second state, and then the sixth transistor needs to be reset and the like before the second capacitor is used to store the electrical signal of the ultrasonic control circuit in another state.

[0098] Optionally, referring to Figure 5 As shown in the figure, the storage sub-circuit 6 includes the sixth transistor M6, the second capacitor Cp1, the seventh transistor M7 and the third capacitor Cp2; the control electrode of the seventh transistor M7 is electrically connected with the second third control signal line Vg7, the first electrode is electrically connected with the second node Q, and the second electrode is electrically connected with the first end of the third capacitor Cp2; the first end of the third capacitor Cp2 is also electrically connected with the processing sub-circuit 7, and the second end is electrically connected with the ground terminal GND.

[0099] Optionally, referring to Figure 7 As shown in the figure, the processing sub-circuit 7 at least includes an amplifier; the first end of the amplifier is electrically connected with the storage sub-circuit 6.

[0100] The processing sub-circuit at least including the amplifier refers to that the processing sub-circuit only includes the amplifier; or, the processing sub-circuit can include other elements in addition to the amplifier, for example: an ADC (Analog-to-digital Converter, analog-digital converter), a processor and the like. The processor can be an FPGA (Field Programmable Gate Array, field programmable logic array), a PC (Personal Computer, personal computer), a microprocessor and the like. Figure 7 Taking the processing sub-circuit including the instrument amplifier 71 and the ADC 72 as an example for illustration.

[0101] Here, the type of the above-mentioned amplifier is not specifically limited, for example, the above-mentioned amplifier can include an instrument amplifier.Figure 7 As shown, the instrumentation amplifier 71 has a first end Vi_P and a second end Vi_N, so that the electrical signal can be received through the first end Vi_P and the second end Vi_N.

[0102] Optionally, referring to Figure 9 As shown, the adjusting sub-circuit 8 includes at least one switching transistor M8+n and an adjusting capacitor C4+n; the control electrode of the switching transistor M8+n is electrically connected to the adjusting signal line Vgcn, the first electrode is electrically connected to the adjusting capacitor C4+n, and the second electrode is electrically connected to the third node W; the second end of the adjusting capacitor C4+n is electrically connected to the ground terminal GND, wherein n is an integer greater than or equal to zero.

[0103] The above-mentioned adjusting sub-circuit including at least one switching transistor and an adjusting capacitor means that the above-mentioned adjusting sub-circuit includes only one switching transistor and an adjusting capacitor; or the above-mentioned adjusting sub-circuit includes multiple switching transistors and adjusting capacitors, which are not specifically limited here. Figure 9 For example, the adjusting sub-circuit 8 includes the eighth transistor M8 and the fourth capacitor C4, the ninth transistor M9 and the fifth capacitor C5, the 8+n transistor M8+n and the 4+n capacitor C4+n.

[0104] If the ultrasonic sensor can receive multiple different intensity echoes, for example, the echo intensity received by the ultrasonic sensor is larger when the ultrasonic sensor is closer to the object, and the echo intensity received by the ultrasonic sensor is smaller when the ultrasonic sensor is farther away from the object. When a switching transistor and an adjusting capacitor are added to the ultrasonic control circuit, whether the adjusting capacitor is connected to the ultrasonic control circuit can be controlled by opening or closing the switching transistor. Specifically, when the ultrasonic sensor needs to receive an echo with a larger intensity, the adjusting capacitor can be connected, and as the number of adjusting capacitors increases, the adjusting capacitor and the first capacitor can achieve a larger total capacitance, thereby reducing the voltage of the echo signal. The number of adjusting capacitors that need to be opened can be determined according to actual needs. Of course, when the ultrasonic sensor needs to receive an echo with a smaller intensity, the adjusting capacitor can not be opened or only a small number of adjusting capacitors can be opened, and the specific number can be determined according to actual needs.

[0105] It should be noted that Figure 9 The adjusting signals of the adjusting signal line Vgc1, the adjusting signal line Vgc2, …, and the adjusting signal line Vgcn in the adjusting sub-circuit can be determined according to whether the 4+n capacitor C4+n corresponding to the 8+n transistor M8+n needs to be connected to the ultrasonic control circuit, that is, when the 4+n capacitor C4+n needs to be connected to the ultrasonic control circuit, the 8+n transistor M8+n can be controlled to be turned on; when the 4+n capacitor C4+n does not need to be connected to the ultrasonic control circuit, the 8+n transistor M8+n can be controlled to be turned off.

[0106] In order to make the process uniform, and to facilitate the subsequent circuit driving method simpler, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor and the 8+n transistor are all N-type transistors. Of course, all the transistors above can also be P-type transistors, and the design principle is similar to the present application when the transistors above are P-type transistors, and also belongs to the protection range of the present application.

[0107] The type of the transistor above is not limited, which can be a thin film transistor, and the thin film transistor can be a low-temperature polysilicon thin film transistor or an oxide thin film transistor.

[0108] The embodiment of the present application further provides an ultrasonic monitoring device, which comprises at least one ultrasonic control circuit.

[0109] Here, the specific number of the ultrasonic control circuit above is not limited, for example, the ultrasonic control circuit above can comprise one; or the ultrasonic control circuit above can comprise a plurality, which is not limited here. Figure 10 Taking the number of the ultrasonic control circuit as two as an example.

[0110] Taking the ultrasonic monitoring device comprising two ultrasonic control circuits electrically connected as an example.

[0111] Reference Figure 10 As shown, the column selection lines 11 of the two ultrasonic control circuits are electrically connected, so that when the fourth transistor M4 of one of the ultrasonic control circuits is opened and the fourth transistor M4 of the other ultrasonic control circuit is closed, the electrical signal of the ultrasonic control circuit with the opened fourth transistor M4 is read.

[0112] The embodiment of the present application provides an ultrasonic monitoring device, when the ultrasonic control circuit in the ultrasonic monitoring device is in a first state, since the first reset sub-circuit is configured to reset the first node under the control of the first reset signal of the first reset signal line, then whether the ultrasonic sensor transmits a return signal, the return signal will not affect the potential of the third node, the third node can maintain the first reset signal of the first reset signal line, at this time the ultrasonic control circuit can obtain a first electrical signal with a background noise. When the ultrasonic control circuit is in a second state, since the first reset sub-circuit does not work, then if the ultrasonic sensor transmits a return signal, the return signal will affect the potential of the third node, the potential of the third node changes, at this time the ultrasonic control circuit can obtain a second electrical signal with a background noise and an effective signal. Thus, the second electrical signal is subtracted from the first electrical signal, and the effective signal of the ultrasonic control circuit is obtained, and then the effective signal can be better analyzed.

[0113] The embodiment of the present application further provides a driving method for driving the ultrasonic control circuit.

[0114] The method comprises:

[0115] S1, in the first state stage, a first reset signal is written to a first reset signal line.

[0116] S2, in the second state stage, the first reset signal is not written to the first reset signal line.

[0117] In the following, the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, the eighth transistor, the ninth transistor, and the 8+n transistor are all N-type transistors, for example, the working principle of the ultrasonic control circuit as shown in Figure 6 is introduced in detail in combination with the timing diagram of each signal line as shown in Figure 9 . It should be noted that, Figures 11 to 16 in the figure, the transistor closing is marked by "X".

[0118] In the t1-t2 stage in Figure 6 , high level is input to the first control signal line Drst, the voltage signal line VDD, the gate signal line Gate, the first third control signal line Vg6, the second third control signal line Vg7, and the second reset signal line Reset2, and low level is input to the first reset signal line Reset1 and the second control signal line Vclose. At this time, as shown in Figure 11 , the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all opened, and the first transistor M1, the second transistor M2, the third transistor M3, the eighth transistor M8, the ninth transistor M9, and the 8+n transistor M8+n are all closed. Then, after the previous ultrasonic signal collection ends and before the next ultrasonic signal collection, since the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all opened, the sixth transistor M6 and the seventh transistor M7 can be reset and kept at 0 potential of the second capacitor Cp1 and the third capacitor Cp2.

[0119] In the t2-t3 stage in Figure 6 , high level is input to the first control signal line Drst and the voltage signal line VDD, and low level is input to the first reset signal line Reset1, the second reset signal line Reset2, the second control signal line Vclose, the gate signal line Gate, the first third control signal line Vg6, and the second third control signal line Vg7. At this time, all transistors are kept in the off state and no action is taken.

[0120] It should be noted that the t2-t3 stage can also be omitted.

[0121] exist Figure 6 During the t3-t4 phase, high-level signals are input to the first control signal line Drst, the voltage signal line VDD, the first reset signal line Reset1, and the second control signal line Vclose; while low-level signals are input to the second reset signal line Reset2, the gate signal line Gate, the first and third control signal lines Vg6, and the second and third control signal lines Vg7. At this time, the ultrasonic control circuit is in its first state, refer to... Figure 12 As shown, the first transistor M1 and the second transistor M2 are both turned on, while the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, the third transistor M3, the eighth transistor M8, the ninth transistor M9, and the (8+n)th transistor M8+n are all turned off. Since the first transistor M1 and the second transistor M2 are both turned on, the third node W (i.e., the control electrode of the third transistor M3) can be reset by the first control signal on the first control signal line Drst.

[0122] exist Figure 6 During stages t4 to t5, high-level signals are input to the first control signal line Drst, the voltage signal line VDD, the first reset signal line Reset1, the second control signal line Vclose, the gate signal line Gate, and the first and third control signal lines Vg6, while low-level signals are input to the second and third control signal lines Vg7, the first reset signal line Reset1, the second reset signal line Reset2, and the second control signal line Vclose. At this time, the reference... Figure 13 As shown, transistors M1, M2, M3, M4, and M6 are all turned on, while transistors M5, M7, M8, M9, and M8+n are all turned off. Transistor M3 is turned on because it holds the control signal for the first control signal line Drst. Since transistors M4 and M6 are also turned on, the echo-free electrical signal V1 can be stored in the second capacitor Cp1, giving signal V1 a noise floor.

[0123] exist Figure 6 During the t5-t6 phase, high-level signals are input to the first control signal line Drst, the voltage signal line VDD, the first reset signal line Reset1, and the second control signal line Vclose, while low-level signals are input to the second reset signal line Reset2, the gate signal line Gate, the first and third control signal lines Vg6, and the second and third control signal lines Vg7. At this time, the ultrasonic control circuit is in its second state, and the ultrasonic sensor PVDF transmits ultrasonic waves. Meanwhile, the reference... Figure 14As shown, transistors M1, M2, and M3 are all turned on, while transistors M4, M6, M5, M7, M8, M9, and M8+n are all turned off. This maintains the potential of node W at the third node before the echo begins to be acquired, where t6 is the time when the echo peak arrives.

[0124] exist Figure 6 During the t6-t7 phase, high-level signals are input to the first control signal line Drst, the voltage signal line VDD, and the second control signal line Vclose, while low-level signals are input to the gate signal line Gate, the first and third control signal lines Vg6, the second and third control signal lines Vg7, the first reset signal line Reset1, and the second reset signal line Reset2. At this time, the ultrasonic sensor PVDF transmits ultrasonic waves. Meanwhile, the reference... Figure 15 As shown, the second transistor M2 and the third transistor M3 are both turned on, while the first transistor M1, the fourth transistor M4, the sixth transistor M6, the fifth transistor M5, the seventh transistor M7, the eighth transistor M8, the ninth transistor M9, and the (8+n)th transistor M8+n are all turned off. Because the second transistor M2 and the third transistor M3 are both turned on and the first transistor M1 is turned off, the echo signal V2 can be collected and sent to the third node W. Furthermore, the echo peak value can be collected when the echo peak value arrives at time t6.

[0125] It should be noted that the second transistor M2 can be turned off at time t7, half a cycle after t6, i.e., maintaining t7-t6 = T / 2 (T being one cycle time). This allows for adjusting the start time of t6 in increments to capture the maximum signal amount, i.e., the echo peak value. Alternatively, the second transistor M2 can be left on at time t7, in which case the echo peak value may not be captured.

[0126] exist Figure 6 During the t7-t8 phase, a high-level signal is input to the first control signal line Drst and the voltage signal line VDD, while a low-level signal is input to the gate signal line Gate, the first and third control signal lines Vg6, the second and third control signal lines Vg7, the first reset signal line Reset1, the second reset signal line Reset2, and the second control signal line Vclose. At this time, the ultrasonic sensor PVDF transmits ultrasonic waves. This is the interval between echo signal acquisition and echo signal readout; all transistors remain off and do not operate, allowing the acquired echo signal to be held at the third node W (i.e., the control electrode of the third transistor M3).

[0127] It should be noted that stages t7 to t8 can be omitted.

[0128] exist Figure 6During stages t8 to t9, high-level signals are input to the first control signal line Drst, the voltage signal line VDD, the gate signal line Gate, and the second and third control signal lines Vg7, while low-level signals are input to the first and third control signal lines Vg6, the first reset signal line Reset1, the second reset signal line Reset2, and the second control signal line Vclose. At this time, the reference... Figure 16 As shown, transistors M2, M3, M4, and M7 are all on, while transistors M1, M6, M5, M8, M9, and M8+n are all off. Because transistors M2, M3, M4, and M7 are all on, the echo signal V2 from the third node W can be stored in the third capacitor Cp2.

[0129] exist Figure 6 In the t9 stage, the first terminal Vi_P of the instrumentation amplifier acquires the electrical signal V1 on the second capacitor Cp1, and the second terminal Vi_N acquires the electrical signal V2 on the second capacitor Cp2. After differential processing in the instrumentation amplifier, the signal is amplified and the background noise of the ultrasonic control circuit is removed. This also enables the ultrasonic control circuit to have strong anti-interference and anti-EMI (Electromagnetic Interference) capabilities.

[0130] Next, the differential signal within the instrumentation amplifier can be transmitted through, for example... Figure 9 The ADC72 shown performs analog-to-digital conversion.

[0131] It should be noted that the electrical signals V1 on the second capacitor Cp1 and V2 on the second capacitor Cp2 can also be amplified before differential processing, and no specific limitation is made here.

[0132] Figures 11-16 The explanation uses transistors M8 to M8+n being turned off as an example. Different echo signal intensities can be adjusted by changing the on / off state of transistors M8 to M8+n. Specifically, the required total capacitance value can be selected based on the actual situation, thereby determining the number of transistors to be turned on. Alternatively, by turning on different positions and different numbers of transistors, a wide range of adjustment of the capacitance value of the third node W (i.e., the control electrode of the third transistor M3) can be achieved, thus realizing a wide range of echo signal adjustment to obtain a high dynamic range APS-type ultrasonic control circuit.

[0133] It should be noted that when selecting capacitors, it is necessary to ensure that transistors M8 to M8+n remain in either the on or off state during one sampling process from t1 to t9.

[0134] The following takes the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor as an example, and introduces the working principle of the ultrasonic control circuit provided by the embodiment in detail in combination with the timing diagram of each signal line as shown in Figure 8 Figure 7

[0135] In the t1-t2 stage in Figure 8 , high level is input to the voltage signal line VDD, the gate signal line Gate, the first third control signal line Vg6, the second third control signal line Vg7, and the second reset signal line Reset2, and low level is input to the first reset signal line Reset1 and the second control signal line Vclose. At this time, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all open, and the first transistor M1, the second transistor M2, and the third transistor M3 are all closed. Then, after the end of the previous ultrasonic signal collection and before the next ultrasonic signal collection, since the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 are all open, the sixth transistor M6 and the seventh transistor M7 can be reset, and the second capacitor Cp1 and the third capacitor Cp2 can be kept at 0 potential.

[0136] In the t2-t3 stage in Figure 8 , high level is input to the voltage signal line VDD, and low level is input to the first reset signal line Reset1, the second reset signal line Reset2, the second control signal line Vclose, the gate signal line Gate, the first third control signal line Vg6, and the second third control signal line Vg7. At this time, all transistors are in the off state and no action is taken.

[0137] It should be noted that the t2-t3 stage can be omitted.

[0138] In the t3-t4 stage in Figure 8 , high level is input to the voltage signal line VDD, the first reset signal line Reset1, and the second control signal line Vclose, and low level is input to the second reset signal line Reset2, the gate signal line Gate, the first third control signal line Vg6, and the second third control signal line Vg7. At this time, in the case that the ultrasonic control circuit is in the first state, the first transistor M1 and the second transistor M2 are open, and the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the seventh transistor M7, and the third transistor M3 are closed. Since the first transistor M1 and the second transistor M2 are open, the voltage signal of the voltage signal line VDD can be used to reset the third node W (i.e., the control electrode of the third transistor M3).

[0139] In​​Figure 8 In the t4-t5 stage, a high level is input to the voltage signal line VDD, and low levels are input to the first reset signal line Reset1, the second control signal line Vclose, the gate signal line Gate, the first third control signal line Vg6, the second third control signal line Vg7, the first reset signal line Reset1, the second reset signal line Reset2, and the second control signal line Vclose. At this time, all the transistors are closed, and no action is performed.

[0140] It should be noted that the t4-t5 stage can be omitted.

[0141] In the t5-t6 stage, Figure 8 In the t5-t6 stage, a high level is input to the voltage signal line VDD, and low levels are input to the first reset signal line Reset1, the second control signal line Vclose, the gate signal line Gate, the first third control signal line Vg6, the second third control signal line Vg7, the first reset signal line Reset1, the second reset signal line Reset2, and the second control signal line Vclose. At this time, all the transistors are closed, and no action is performed.

[0142] In the t6-t7 stage, Figure 8 In the t6-t7 stage, a high level is input to the voltage signal line VDD, and low levels are input to the first reset signal line Reset1, the second control signal line Vclose, the gate signal line Gate, the first third control signal line Vg6, the second third control signal line Vg7, the first reset signal line Reset1, the second reset signal line Reset2, and the second control signal line Vclose. At this time, all the transistors are closed, and no action is performed.

[0143] It should be noted that the t6-t7 stage can be omitted.

[0144] In the t7-t8 stage, Figure 8In the t7-t8 stage, high level is input to the voltage signal line VDD and the second control signal line Vclose, low level is input to the gate signal line Gate, the first third control signal line Vg6, the second third control signal line Vg7, the first reset signal line Reset1 and the second reset signal line Reset2, at this time, the ultrasonic sensor PVDF transmits ultrasonic waves. At this time, the second transistor M2 and the third transistor M3 are opened, and the fourth transistor M4, the sixth transistor M6, the first transistor M1, the fifth transistor M5 and the seventh transistor M7 are closed. Because the second transistor M2 is opened and the ultrasonic sensor PVDF transmits ultrasonic waves, the electrical signal V2 of the echo can be collected to the third node W, and the peak value of the echo can be collected when the peak value of the echo arrives at the t7 moment.

[0145] It should be noted that the second transistor M2 can be closed at the t8 moment after t7 passes through half a period of time, that is, t8-t7=T / 2 (T is a period of time), so that the maximum signal amount, that is, the peak value of the echo, can be collected by adjusting the starting time of t7 in a certain step. Of course, the second transistor M2 can also not be closed at the t8 moment, at this time, the peak value of the echo can not be collected.

[0146] In the t8-t9 stage, Figure 8 In the t8-t9 stage, high level is input to the voltage signal line VDD, low level is input to the gate signal line Gate, the second third control signal line Vg7, the first third control signal line Vg6, the first reset signal line Reset1, the second reset signal line Reset2 and the second control signal line Vclose, at this time, the ultrasonic sensor PVDF transmits ultrasonic waves. This is the interval time between the collection of the echo signal and the reading of the echo signal, all transistors are kept off state, no action, and the collected echo signal can be kept on the third node W (that is, the control electrode of the third transistor M3).

[0147] It should be noted that the t8-t9 stage can be omitted.

[0148] In the t9-t10 stage, Figure 8 In the t9-t10 stage, high level is input to the second third control signal line Vg7, the gate signal line Gate and the voltage signal line VDD, low level is input to the first third control signal line Vg6, the first reset signal line Reset1, the second reset signal line Reset2 and the second control signal line Vclose. At this time, the third transistor M3, the fourth transistor M4 and the seventh transistor M7 are opened, and the second transistor M2, the sixth transistor M6, the first transistor M1 and the fifth transistor M5 are closed. Because the third transistor M3, the fourth transistor M4 and the seventh transistor M7 are opened, the echo signal V2 of the third node W can be stored in the third capacitor Cp2.

[0149] In Figure 8 , the first end Vi_P of the instrumentation amplifier obtains the electrical signal V1 on the second capacitor Cp1, and the second end Vi_N obtains the electrical signal V2 on the second capacitor Cp2. After differential processing in the instrumentation amplifier, the signal is amplified and the background noise of the ultrasonic control circuit is removed, and the ultrasonic control circuit has strong anti-interference and anti-EMI capabilities.

[0150] Then, the differential signal in the instrumentation amplifier can be converted into an analog signal through the ADC 72 as shown in Figure 7 .

[0151] It should be noted that the electrical signal V1 on the second capacitor Cp1 and the electrical signal V2 on the second capacitor Cp2 can be amplified and then differentially processed, which is not limited here.

[0152] It should be noted that Figure 7 other processes are similar to the above Figure 9 process, which will not be repeated here. Please refer to Figure 9 . Figure 7 The adjustment sub-circuit is added in , which will not be repeated here.

[0153] Figure 8 In the timing of , the first transistor M1 and the second transistor M2 are only turned on for a period of time after the column selection line is emptied and the second capacitor Cp1 and the third capacitor Cp2 are reset to zero. The control electrode of the third transistor M3 and the potential of the ultrasonic sensor PVDF without echo are reset to the voltage signal of the voltage signal line VDD. At this time, the pressure difference signal collected from the peak to the valley of the echo can still ensure that the third transistor M3 works in the saturation region.

[0154] The collection of the echo signal can be realized by controlling the opening and closing time t7-t8 of the second transistor M2, which also needs Figure 6 the same process of finding the best collection time.

[0155] Embodiments of the present application provide a driving method, by which, when the ultrasonic control circuit is in a first state, the first reset sub-circuit is configured to reset the first node under the control of the first reset signal of the first reset signal line, so that whether the ultrasonic sensor transmits a return signal or not, the return signal will not affect the potential of the third node, the third node can keep the first reset signal of the first reset signal line, at this time, the ultrasonic control circuit can obtain a first electric signal with a background noise. When the ultrasonic control circuit is in a second state, the first reset sub-circuit does not work, so that if the ultrasonic sensor transmits a return signal, the return signal will affect the potential of the third node, the potential of the third node changes, at this time, the ultrasonic control circuit can obtain a second electric signal with a background noise and an effective signal. Thus, the second electric signal is subtracted from the first electric signal, that is, the effective signal of the ultrasonic control circuit is obtained, and then the effective signal can be better analyzed according to the effective signal.

[0156] As used in the description of the application herein, the meaning of "embodiment" means that the specific features, structures or characteristics described in connection with the embodiment are included in at least one embodiment of the present application.

[0157] In the specification provided herein, a large number of specific details are described. However, it can be understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail in order not to obscure the understanding of the present specification.

[0158] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An ultrasonic control circuit, characterized by comprising: The ultrasonic control circuit comprises: an ultrasonic sensor electrically connected to the first node and configured to receive an echo signal of an object and write the echo signal to the first node; a first reset sub-circuit electrically connected to a first reset signal line, a first control signal line and the first node, configured to reset the first node under control of a first reset signal of the first reset signal line in a first state, and not to work in a second state; the first state is a state in which the ultrasonic sensor does not transmit a signal or the ultrasonic sensor transmits a signal that does not affect the potential of the third node; the second state is a state in which the ultrasonic sensor transmits a signal that affects the potential of the third node; a second reset sub-circuit electrically connected to a second reset signal line, a ground terminal and a second node, and configured to reset the second node under control of a second reset signal of the second reset signal line; a signal transmission sub-circuit electrically connected to a second control signal line, a third node and the first node, and configured to write a signal of the first node to the third node under control of a second control signal of the second control signal line; an output sub-circuit electrically connected to a gate signal line, the third node, a voltage signal line and the second node, and configured to write a voltage signal of the voltage signal line and the signal of the third node to the second node under control of a gate signal of the gate signal line and the signal of the third node; a storage sub-circuit electrically connected to the second node, a third control signal line and a processing sub-circuit, and configured to write the signal of the second node to the processing sub-circuit under control of a third control signal of the third control signal line; the processing sub-circuit is configured to receive and process the signal of the second node.

2. The ultrasonic control circuit of claim 1, wherein, The ultrasonic control circuit further comprises an adjustment sub-circuit electrically connected to the third node, an adjustment signal line and the ground terminal, and configured to control the electrical signal of the third node under control of an adjustment signal of the adjustment signal line.

3. The ultrasonic control circuit of claim 1, wherein, The first reset sub-circuit comprises a first transistor. The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode is electrically connected to the first control signal line, and the second electrode is electrically connected to the first node.

4. The ultrasonic control circuit of claim 1, wherein, The first reset sub-circuit comprises a first transistor. The control electrode of the first transistor is electrically connected to the first reset signal line, the first electrode is electrically connected to the voltage signal line, and the second electrode is electrically connected to the first node.

5. The ultrasonic control circuit of claim 1, wherein, The second reset sub-circuit comprises a fifth transistor. The control electrode of the fifth transistor is electrically connected to the second reset signal line, the first electrode is electrically connected to the ground terminal, and the second electrode is electrically connected to the second node.

6. The ultrasonic control circuit of claim 1, wherein, The signal transmission sub-circuit comprises a second transistor. The control electrode of the second transistor is electrically connected to the second control signal line, the first electrode is electrically connected to the first node, and the second electrode is electrically connected to the third node.

7. The ultrasonic control circuit of claim 1, wherein, The output sub-circuit comprises a third transistor, a fourth transistor and a first capacitor. The control electrode of the third transistor is electrically connected with the third node, the first electrode is electrically connected with the voltage signal line, and the second electrode is electrically connected with the second node; The control electrode of the fourth transistor is electrically connected with the gate signal line, the first electrode is electrically connected with the second node, and the second electrode is electrically connected with the third node; The first end of the first capacitor is electrically connected with the third node, and the second end is electrically connected with the ground terminal.

8. The ultrasonic control circuit of claim 1, wherein, The storage sub-circuit at least includes a sixth transistor and a second capacitor; The control electrode of the sixth transistor is electrically connected with a first third control signal line, the first electrode is electrically connected with the second node, and the second electrode is electrically connected with the first end of the second capacitor; The first end of the second capacitor is also electrically connected with the processing sub-circuit, and the second end is electrically connected with the ground terminal.

9. The ultrasonic control circuit of claim 8, wherein, The storage sub-circuit includes the sixth transistor, the second capacitor, a seventh transistor and a third capacitor; The control electrode of the seventh transistor is electrically connected with a second third control signal line, the first electrode is electrically connected with the second node, and the second electrode is electrically connected with the first end of the third capacitor; The first end of the third capacitor is also electrically connected with the processing sub-circuit, and the second end is electrically connected with the ground terminal.

10. The ultrasonic control circuit of claim 1, wherein, The processing sub-circuit at least includes an amplifier; The first end of the amplifier is electrically connected with the storage sub-circuit.

11. The ultrasonic control circuit of claim 2, wherein, The adjustment sub-circuit includes at least one switching transistor and an adjustment capacitor; The control electrode of the switching transistor is electrically connected with the adjustment signal line, the first electrode is electrically connected with the adjustment capacitor, and the second electrode is electrically connected with the third node; The second end of the adjustment capacitor is electrically connected with the ground terminal.

12. An ultrasound monitoring device, characterized by The method includes:

13. A driving method, comprising: In the first state stage, a first reset signal is written to a first reset signal line; In the second state stage, the first reset signal is not written to the first reset signal line. The method includes: In the first state stage, a first reset signal is written to a first reset signal line; In the second state stage, the first reset signal is not written to the first reset signal line.

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