A method for turning on a server hard disk and a server

Abstract

The embodiment of the present application discloses a kind of server hard disk's light-up method and server, the method comprises: first logic device obtains the serial light-up signal sent by processor in serial manner, serial light-up signal includes multiple light-up signals, each light-up signal includes VPP address;And each light-up signal is used to indicate light-up to one hard disk indicator unit;First logic device is parsed into multiple light-up signals including same address by serial light-up signal, and according to the correspondence between preset VPP address and communication link, each light-up signal is transmitted to second logic device in parallel;Second logic device receives each light-up signal transmitted in parallel by first logic device, indicates hard disk indicator light after parsing each light-up signal received by it.Light-up method of the present application is beneficial to reduce the address adaptation work in a large number in second logic device, so as to reduce the complexity of hard disk light-up.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of server hard disk lighting, and in particular to a server hard disk lighting method and a server. BACKGROUND

[0002] In recent years, with the rapid development of cloud computing, big data, the Internet of Things and other industries, the demand for data storage is growing, and traditional solid state drives (SSD) have been difficult to meet the diversified data storage needs in some scenarios. Due to its large capacity, fast read and write speed, low input and output delay, and other characteristics, Non-Volatile Memory Express (NVMe) SSD has been widely used in the server field. At present, the implementation of the hot plug lighting function of NVMe SSD requires a large amount of Virtual Pin Port (VPP) address configuration and adaptation, which results in a huge workload and increases the complexity of NVMe SSD lighting. SUMMARY

[0003] The present application provides a server hard disk lighting method and a server, the first logic device can convert the serial lighting signal sent by the processor into multiple lighting signals, and configure the address in the multiple lighting signals to be the same, then only one address needs to be configured in the second logic device at the hard disk backplane end to complete the analysis operation of the multiple lighting signals, thereby reducing the large amount of address adaptation work in the second logic device, which is conducive to reducing the complexity of hard disk lighting.

[0004] In a first aspect, the present application provides a server, which includes a mainboard, a hard disk backplane and a first logic device, the mainboard includes a processor, the processor includes multiple VPP addresses, the processor sends a serial lighting signal to the first logic device, the serial lighting signal includes multiple lighting signals; each lighting signal includes a VPP address; and each lighting signal is used to light up one hard disk indicator unit.

[0005] The hard disk backplane includes a second logic device and a hard disk indicator, the second logic device and the first logic device communicate through multiple communication links; the second logic device is electrically connected with the hard disk indicator;

[0006] The first logic device is used to parse the serial lighting signal into multiple lighting signals including the same address, and according to the preset correspondence between the VPP address and the communication link, transmit each lighting signal in parallel to the second logic device through the corresponding communication link, and the second logic device indicates the hard disk indicator to light up after parsing each received lighting signal.

[0007] It can be seen that, according to the VPP address in the serial lighting signal, the first logic device in the embodiment of the application can parse the serial lighting signal into a plurality of lighting signals including the same address, and transmit the converted plurality of lighting signals in parallel to the second logic device at the hard disk backboard end through the corresponding communication link, so that the second logic device can not need to perform a large amount of address adaptation with the BIOS, and the received lighting signal is parsed and then executed to perform the lighting operation in the adapted mode, thereby facilitating to reduce a large amount of address adaptation work at the hard disk backboard end, and further reducing the complexity of the hard disk lighting.

[0008] In some possible implementation manners, the mainboard includes a plurality of first connectors, the hard disk backboard includes a plurality of second connectors, and each communication link includes a first connector and a second connector; the first connector and the second connector are connected through a cable;

[0009] The first logic device transmits each lighting signal in parallel to the first connector of the communication link, and transmits each lighting signal to the second logic device through the first connector of the communication link and the second connector connected with the first connector of the communication link.

[0010] In the embodiment, since the first logic device transmits each lighting signal in parallel to the second logic device through the first connector on the corresponding communication link and the second connector connected with the first connector, the first logic device needs to convert the complex virtual address (i.e., the VPP address) into the hardware address (i.e., the address in the parsed plurality of lighting signals) of the connector when performing the conversion operation, and the hardware address of the connector does not need to be configured and adapted at the hard disk backboard end, thereby facilitating to save the workload.

[0011] In some possible implementation manners, the second logic device includes a normalized address, and the second logic device matches the address in each received lighting signal with the normalized address, and parses the lighting information from each received lighting signal in a case of successful matching.

[0012] In the embodiment, since the conversion operation of the first logic device on the serial lighting signal configures the VPP address in the plurality of lighting signals to be the same address, the second logic device only needs to configure one address (i.e., the normalized address) to complete the matching with all the VPP addresses, compared with the scheme that a large number of VPP addresses need to be adapted and matched to parse the lighting information, thereby facilitating to improve the matching efficiency of the VPP address at the hard disk backboard end, and further enabling the second logic device to parse the lighting information without adaptation.

[0013] In some possible implementation manners, the second logic device determines, according to a preset correspondence between the second connectors and the hard disks, at least one hard disk corresponding to each received lighting signal, and indicates the hard disk indicator light of the at least one hard disk to light up based on the lighting information in the lighting signal.

[0014] In this embodiment, the second logic device can determine, based on the one-to-one correspondence between the second connectors and the hard disks, at least one hard disk corresponding to the second connector with the matched address, and perform lighting operation on the hard disk indicator light of the at least one hard disk based on the lighting information in each lighting signal, so as to transfer the lighting operation based on the VPP address to the lighting operation based on the connector.

[0015] In some possible implementation manners, the first logic device parses, according to the VPP address in each lighting signal, the serial lighting signal into a plurality of lighting signals, and configures the VPP address in each lighting signal to be the same address, to obtain a plurality of lighting signals including the same address.

[0016] In this embodiment, since the first logic device configures the VPP address in the plurality of lighting signals to be the same address through the conversion operation on the serial lighting signal, the hard disk backplane end only needs to configure one address to parse the lighting signal, so as to avoid the need for the hard disk backplane end to perform a large amount of address adaptation with the BIOS to parse the lighting signal.

[0017] In a second aspect, an embodiment of the present application provides a lighting method of a server hard disk, applied to the server in the first aspect, and the method comprises the following steps.

[0018] The first logic device obtains a serial lighting signal sent by the processor in a serial manner, the serial lighting signal comprises a plurality of lighting signals, each lighting signal comprises a VPP address, and each lighting signal is used for lighting a hard disk indicator light unit.

[0019] The first logic device parses the serial lighting signal into a plurality of lighting signals including the same address, and transmits each lighting signal to the second logic device in parallel according to a preset correspondence between the VPP address and the communication link.

[0020] The second logic device receives each lighting signal transmitted in parallel by the first logic device, parses each received lighting signal, and indicates the hard disk indicator light to light up.

[0021] In some possible implementation manners, transmitting each lighting signal to the second logic device in parallel comprises:

[0022] The first logic device sends each lighting signal to a first connector of a corresponding communication link in parallel, and transmits each lighting signal to the second logic device through the first connector of the communication link and a second connector connected with the first connector of the communication link.

[0023] In some possible implementation manners, the second logic device comprises a normalized address, and after receiving each lighting signal transmitted in parallel by the first logic device, the method further comprises:

[0024] The second logic device matches the address in each received lighting signal with the normalized address.

[0025] The second logic device parses the lighting information from each received lighting signal in a case of successful matching.

[0026] In some possible implementation manners, the indication of the lighting of the hard disk indicator light comprises:

[0027] The second logic device determines at least one hard disk to which each received lighting signal is used for lighting according to a preset correspondence between the second connector and the hard disk.

[0028] The second logic device instructs the hard disk indicator light of the at least one hard disk to light based on the lighting information.

[0029] In some possible implementation manners, the first logic device parses a plurality of lighting signals from the serial lighting signal according to the VPP address in each lighting signal, configures the VPP address in each lighting signal as the same address, and obtains a plurality of lighting signals comprising the same address.

[0030] It should be noted that the implementation of each step in the second aspect can refer to the corresponding description of the server embodiment shown in the first aspect, and the same or similar beneficial effects can be achieved.

[0031] In a third aspect, an embodiment of the present application provides a computer readable storage medium, which stores a computer program for execution by a device, and the computer program is executed to implement the method in the second aspect.

[0032] In a fourth aspect, an embodiment of the present application provides a computer program product, which is run by a device to enable the device to execute the method in the second aspect. BRIEF DESCRIPTION OF DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background art, the drawings needed to be used in the embodiments of the present application or the background art will be described below.

[0034] Figure 1A hardware architecture diagram of a design method for realizing multi-NVMe hard disk backboard lighting according to a related art;

[0035] Figure 2 A flowchart diagram of a design method for realizing multi-NVMe hard disk backboard lighting according to a related art;

[0036] Figure 3 A schematic diagram of a hardware architecture provided by an embodiment of the present application;

[0037] Figure 4 A flowchart diagram of a server hard disk lighting method provided by an embodiment of the present application;

[0038] Figure 5 A schematic diagram of a server hard disk lighting provided by an embodiment of the present application;

[0039] Figure 6 A schematic diagram of a serial lighting signal provided by an embodiment of the present application;

[0040] Figure 7 A schematic diagram of a server structure provided by an embodiment of the present application;

[0041] Figure 8 A schematic diagram of another server structure provided by an embodiment of the present application. DETAILED DESCRIPTION

[0042] The terms "first", "second", "third", and "fourth" and the like in the description and in the claims of the present application are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the descriptive terms used herein are to be interpreted in the context as exercised by those of ordinary skill in the art. Furthermore, the term "comprising" or "containing" or "including" or "having" or "fronted with" as used herein is to be interpreted as an open term meaning that the named steps, features, components, integers, or steps can be present or combined, and is not intended to mean that there is no further steps, features, components, integers, or steps that are not named. Thus, the terms "comprising" or "containing" or "including" or "having" or "fronted with" as used herein are to be construed as referring to elements, components, or steps either open-ended or limiting, unless otherwise indicated.

[0043] Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. It is expressly understood that the embodiments described herein are merely examples from a multitude of embodiments that are of a potential use to one of ordinary skill in the art. It is recognized that some embodiments can not be encompassed in the claims below, and it is expressly noted that not all combinations of features are necessarily intended to be within the scope of the application.

[0044] As used in the present specification and claims, the terms "component," "module," "system" and the like are intended to refer to a computer-related entity, either hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a terminal device and the terminal device can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, partially and / or entirely, in one computer or distributed among two or more computers. In addition, these components can execute from various computer readable media having various data structures stored thereon. The components can communicate via local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal).

[0045] It should be noted that, in the description of the present application:

[0046] CPU (Central Processing Unit) is a central processor;

[0047] I2C (Inter-Integrated Circuit) is a serial bus;

[0048] PCIe (Peripheral Component Interconnect-express) is a high-speed serial computer expansion bus standard;

[0049] PLD (Programmable Logic Device) is a programmable logic device;

[0050] CPLD (Complex Programmable Logic Device) is a complex programmable logic device;

[0051] FPGA (Field Programmable Gate Array) is a programmable array logic;

[0052] BIOS (Basic Input Output System) is a basic input output system;

[0053] UBC (unionbus connector) is a high-speed line end IO connector.

[0054] In order to facilitate understanding of the embodiments of the present application, further analyze and propose the technical problems to be solved by the present application, the related technical solutions of the present application are briefly introduced as follows.

[0055] For example, see Figure 1 , Figure 1 A hardware architecture diagram of a design method for realizing multi-NVMe hard disk backboard lighting proposed by a related technology is shown in Figure 1 The CPU1 on the mainboard includes five ports of PCIe0, PCIe1, PCIe2, PCIe3 and PCIe4, wherein PCIe0 and PCIe1 have one PCIe 5.0x16 channel, PCIe2, PCIe3 and PCIe4 have two PCIe 5.0x8 channels, and each channel is connected with the backboard through the respective configured connector. The BIOS allocates VPP addresses for each PCIe port of the CPU1, and the VPP addresses finally point to the addresses or identifications of the NVMeSSD mounted under the CPU1 on the backboard. Based on the architecture, see Figure 2 , the related technology proposes a design method for realizing multi-NVMe hard disk backboard lighting, as shown in Figure 2 , which includes the following steps:

[0056] A group of VPP signal lines are connected on each controller of the mainboard, and the VPP signal lines are transmitted to the backboard through the connector side channel of each port;

[0057] The controller sends VPP addresses to the backboard end in a cycle, and the programmable logic of the backboard receives the data stream sent by the controller, and analyzes the address information sent by the controller;

[0058] If the VPP address simulated by the backboard channel is the same as the address sent by the controller, the controller sends the hard disk lighting information of the corresponding disk position to the programmable logic of the backboard;

[0059] The programmable logic of the backboard performs logical conversion on the hard disk lighting information sent by the controller, converts the serial data stream on the VPP into parallel signals, lights the backboard lamp of the corresponding port, and uploads the in-position information of the hard disk monitored by the backboard to the controller.

[0060] The related technology can realize flexible configuration of multiple NVMe SSDs, but in the development process, there are many NVMe backplanes, the VPP addresses and the number of each backplane configuration are different, the workload of integrating the addresses in the BIOS is relatively large, and the backplane CPLD needs to adapt the address of each hard disk, which undoubtedly brings a large amount of adaptation workload to the backplane end. If the address adaptation needs to be done every time the backplane is lit, the lighting efficiency will be greatly affected. In addition, there is often a situation of backplane borrowing between projects. A large number of VPP addresses need to be re-integrated into the BIOS of the new backplane, and the backplane end also needs to be adapted again, which is relatively cumbersome. Based on the above two points, it can be seen that when expanding the hard disk configuration, the BIOS and the backplane end also need to re-integrate new VPP addresses, and the adaptation work of the backplane end is always ongoing.

[0061] In view of the defects and deficiencies of the related technology, the technical problems to be solved by the embodiments of the present application are mainly as follows: how to perform VPP address adaptation-free on the backplane end to reduce the complexity of hard disk lighting and improve the lighting efficiency.

[0062] The server hard disk lighting method and server provided by the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0063] Based on the above technical problems, please refer to Figure 3 , Figure 3 A schematic diagram of a hardware architecture provided by the embodiments of the present application is shown in Figure 3 , which includes a mainboard and a hard disk backplane. The mainboard includes one or more CPUs (such as CPU1, CPU2, etc.), a CPLD, and a plurality of connectors (such as connector1, connector2, …, connectorn). The hard disk backplane includes a plurality of connectors, a CPLD, a plurality of inserted hard disks (such as hard disk0, hard disk1, …, hard diskn), and a hard disk indicator light for each hard disk. Each CPU on the mainboard is connected to the CPLD through a hot plug I2C communication line, such as CPU1 connected to the CPLD through hot plug I2C1, and CPU2 connected to the CPLD through hot plug I2C2. The CPLD is connected to the plurality of connectors through an I2C communication line. The plurality of connectors are respectively connected to the plurality of connectors on the mainboard through cables to form a plurality of communication links between the mainboard end CPLD and the hard disk backplane end CPLD, such as connector1 connected to connector1 on the mainboard, connector2 connected to connector2 on the mainboard, and so on. The CPLD on the hard disk backplane end performs lighting on the corresponding hard disk indicator light based on the lighting signals received by each connector, such as the lighting signals received by connector1 used for lighting of hard disk0 and hard disk1, the lighting signals received by connector2 used for lighting of hard disk2 and hard disk3, and so on.

[0064] Please refer to Figure 4 , Figure 4 A flowchart of a server hard disk lighting method provided by an embodiment of the present application. The method can be implemented based on the architecture shown in Figure 3 , and can be specifically applied to a server. The server includes a motherboard, a hard disk backplane, and a first logic device. The motherboard includes a processor, and the processor includes multiple virtual ports. Each virtual port has a corresponding VPP address. The hard disk backplane includes a second logic device, multiple inserted hard disks (which can be NVMe SSDs), and a hard disk indicator light. The second logic device communicates with the first logic device through multiple communication links. The second logic device is electrically connected to the hard disk indicator light. As shown in Figure 4 , the method can include steps 401-403:

[0065] 401: The first logic device acquires a serial lighting signal sent by the processor in a serial manner.

[0066] In an embodiment of the present application, the first logic device can be a logic device located on the motherboard or a logic device located elsewhere outside the motherboard, which is not limited in the present application. The processor sends a serial lighting signal to the first logic device. The serial lighting signal includes multiple lighting signals, each lighting signal includes a VPP address and lighting information, and each lighting signal is used to light up a hard disk indicator light unit. A hard disk indicator light unit includes the hard disk indicator light of at least one hard disk, such as a hard disk group. The processor can be any CPU on the motherboard, such as CPU1 or CPU2 in Figure 3 . The VPP address in each lighting signal can be an address assigned by BIOS to the PCIe port of the CPU. Each VPP address corresponds to at least one hard disk in the multiple hard disks, such as the VPP address of PCIe0 corresponding to hard disk0 or a hard disk group consisting of hard disk0 and hard disk1. The processor generates a corresponding lighting command based on the VPP address of each PCIe port. Each lighting command includes a VPP address and lighting information, such as indicating that the Active light of the corresponding hard disk is always green or flashing green. For example, if the VPP address of PCIe0 corresponds to hard disk0 and hard disk1, the lighting commands for hard disk0 and hard disk1 are the same. The processor sends multiple lighting commands in a serial manner through the hot plug I2C signal line, i.e., a serial lighting signal. Each lighting command is a lighting signal in the serial lighting signal.

[0067] For example, please refer to Figure 5, the BIOS assigns VPP addresses to the five PCIe ports of the CPU 1 respectively, then the CPU 1 sends the five lighting commands to the first logic device in a serial manner through the hot plug I2C signal line, and the serial lighting signal received by the first logic device is the serial lighting signal.

[0068] 402: The first logic device parses the serial lighting signal into multiple lighting signals including the same address, and transmits each lighting signal to the second logic device in parallel according to the preset correspondence between the VPP address and the communication link.

[0069] In the embodiment of the application, for the first logic device end, each lighting command is a lighting signal, and the first logic device end parses each lighting signal from the serial lighting signal according to the VPP address in the serial lighting signal, thereby obtaining multiple lighting signals in the serial lighting signal. For example, as shown in Figure 6 Figure 5 If the five lighting commands in the serial lighting signal are "VPP0+lighting information 0, VPP1+lighting information 1, …, VPP4+lighting information 4" respectively, the first logic device can obtain the lighting information corresponding to each VPP address according to each VPP address, thereby obtaining the corresponding lighting signal. For example, the lighting information 0 is obtained according to VPP0, thereby parsing the corresponding lighting signal 1; the lighting signal 1 is obtained according to VPP1, thereby parsing the corresponding lighting signal 2; the lighting signal 4 is obtained according to VPP4, thereby parsing the corresponding lighting signal 5; and so on.

[0070] The first logic device configures the VPP address in each lighting signal as the same address, repackages the address and the lighting information as a new lighting command, thereby obtaining multiple new lighting commands. The first logic device is configured with the correspondence between the VPP address and the communication link, for example, VPP0 corresponds to communication link 1, VPP1 corresponds to communication link 2, and so on. The first logic device places the multiple new lighting commands on different communication links based on the correspondence, thereby generating multiple lighting signals including the same address (i.e., multiple parallel lighting signals). The address replacing the VPP address can be a preconfigured address in the first logic device, for example, the address can be ×40.

[0071] In this embodiment, since the conversion operation of the first logic device on the serial lighting signal configures the VPP addresses in multiple lighting signals as the same address, the hard disk backplane end only needs to configure one address to parse the lighting signal, thereby avoiding the need for the hard disk backplane end to perform a large amount of address adaptation with the BIOS to parse the lighting signal.

[0072] ​Exemplarily, the mainboard includes a plurality of first connectors, the hard disk backboard includes a plurality of second connectors, each communication link includes a first connector and a second connector, and the first connector and the second connector are connected through a cable, for example, the first connector 1 is connected with the second connector 1, the first connector 2 is connected with the second connector 2, and so on. Wherein, each communication link can be an I2C communication link.

[0073] The first logic device transmits each lighting signal to the second logic device in parallel, including:

[0074] The first logic device transmits each lighting signal to the first connector of the corresponding communication link, and transmits each lighting signal to the second logic device through the first connector of the communication link and the second connector connected with the first connector of the communication link.

[0075] Exemplarily, please continue to refer to Figure 5 , the first logic device transmits five new lighting commands to the second logic device in parallel through five I2C communication links, for example: the lighting command 1 needs to be transmitted to the second logic device through the communication link 1, and the communication link 1 includes the first connector 1 located on the mainboard and the second connector 1 located on the hard disk backboard, then the first logic device transmits the lighting command 1 to the first connector 1 on the I2C communication line (that is, generates the lighting signal 1), and transmits the lighting signal 1 to the second logic device through the first connector 1 and the second connector 1 connected with the first connector 1.

[0076] Exemplarily, the plurality of first connectors and the plurality of second connectors can be UBC connectors. The first logic device and the second logic device can be PLD, CPLD, FPGA, etc.

[0077] In this embodiment, since the first logic device transmits each lighting signal to the second logic device in parallel through the first connector on the corresponding communication link and the second connector connected with the first connector, it is necessary for the first logic device to convert the complex virtual address (that is, VPP address) into the hardware address of the connector (that is, the address in the plurality of lighting signals after analysis) when performing the conversion operation, and the hardware address of the connector does not need to be configured and adapted a lot on the hard disk backboard side, which is beneficial to save workload.

[0078] 403: The second logic device receives each lighting signal transmitted in parallel by the first logic device, and indicates the hard disk indicator light to light after analyzing each received lighting signal.

[0079] In the embodiment of the present application, corresponding to the mainboard end, since the first logic device sends multiple lighting signals in parallel through multiple first connectors, the second logic device at the hard disk backboard end acquires multiple lighting signals through multiple second connectors. Specifically, the multiple second connectors are connected to the second logic device through multiple I2C communication lines, and after the multiple lighting signals are transmitted to the multiple second connectors in parallel, the multiple lighting signals are transmitted to the second logic device through the multiple I2C communication lines.

[0080] For example, the second logic device includes a normalized address, and after receiving each lighting signal transmitted in parallel by the first logic device, the method further includes:

[0081] The second logic device matches the address in each received lighting signal with the normalized address.

[0082] The second logic device parses the lighting information from each received lighting signal in the case of successful matching.

[0083] In the embodiment of the present application, the second logic device is configured with a normalized address, such as ×40. For each lighting signal transmitted to the second logic device by each second connector, the second logic device first extracts the address in the lighting signal, then matches the address with the normalized address, and in the case that the address is the same as the normalized address, parses the lighting information from the lighting signal. For example, if the address in a lighting signal is also ×40, the matching is successful, and the second logic device parses the lighting information from the lighting signal. Conversely, if the address in the received lighting signal does not match the normalized address, the second logic device cannot parse the lighting information from the lighting signal.

[0084] In this embodiment, since the first logic device configures the VPP address in multiple lighting signals to be the same address through the conversion operation on the serial lighting signal, the second logic device only needs to configure one address (i.e., the normalized address) to complete the matching with all VPP addresses. Compared with the scheme that needs to adapt to a large number of VPP addresses to parse the lighting information, this scheme is advantageous in improving the matching efficiency of the VPP address at the hard disk backboard end, and also enables the second logic device to parse the lighting information without adaptation.

[0085] For example, indicating the lighting of the hard disk indicator light includes:

[0086] The second logic device determines at least one hard disk for which each received lighting signal is used for lighting according to a preset correspondence between the second connector and the hard disk.

[0087] The second logic device indicates the lighting of the hard disk indicator light of the at least one hard disk based on the lighting information.

[0088] In the embodiment, the second logic device is configured with a correspondence relationship between the plurality of hard disks at the backplane end of the hard disk and the plurality of second connectors, for example, the second connector 1 corresponds to the hard disk 0 (or a hard disk group composed of the hard disk 0 and the hard disk 1), and the correspondence relationship can be an association relationship between the identifier of the hard disk and the second connector. For the target second connector with the same address as the normalized address in the received light-up signal in the plurality of second connectors, based on the correspondence relationship, the second logic device can determine at least one hard disk (i.e., the hard disk to be lighted up) corresponding to the target second connector from the plurality of hard disks, and then perform the light-up information to light up the hard disk indicator of the at least one hard disk. For example: Figure 5 In the embodiment, the address in each light-up signal received by the second logic device is x40, and then the hard disk group corresponding to each second connector is determined, and then the hard disks in the hard disk group are lighted up based on the light-up information. For example, when the hard disk is in the hot plug process, the light-up information indicates that the Active light flashes and the Fault light flashes.

[0089] In the embodiment, based on the one-to-one correspondence relationship between the plurality of second connectors and the plurality of hard disks, the second logic device can determine at least one hard disk corresponding to the second connector with the successful address matching, so as to perform the light-up operation of the hard disk indicator of the at least one hard disk based on the light-up information in each light-up signal, and transfer the light-up operation based on the VPP address to the light-up operation based on the connector.

[0090] It can be seen that in the embodiment, the first logic device can parse the serial light-up signal into a plurality of light-up signals with the same address according to the VPP address in the serial light-up signal, which makes the second logic device at the backplane end of the hard disk not need to do a lot of address adaptation work with the BIOS. After receiving the plurality of light-up signals sent in parallel by the first logic device, the second logic device only needs to match the address configured with all the addresses in the light-up signal to parse the light-up information in the corresponding light-up signal, realizes the normalization of the VPP address at the backplane end of the hard disk, and the backplane end of the hard disk can parse the light-up signal and perform the light-up operation without adaptation, which is beneficial to reduce a large amount of address adaptation work at the backplane end of the hard disk, thereby reducing the complexity of the hard disk light-up. In addition, the backplane end of the hard disk only needs to be configured with one address, which solves the problem of inflexible VPP address configuration, and the number of addresses to be configured is greatly reduced, which is more conducive to management and maintenance. Since the first logic device can convert all the VPP addresses sent by the processor into the same address, when the backplane needs to be expanded, it is not necessary to reconfigure the backplane end of the hard disk, and the scalability of the software and hardware system is improved.

[0091] The embodiment of the present application also provides a server. Please refer to Figure 7 , Figure 7This is a schematic diagram of the structure of a server 700 provided in an embodiment of this application. The server 700 includes at least a motherboard 701, a hard disk backplane 702, and a first logic device 703. The motherboard 701 includes a processor 7011, which includes multiple VPP addresses. The processor 7011 sends serial LED signals to the first logic device 703. The serial LED signals include multiple LED signals. Each LED signal includes a VPP address and is used to illuminate a hard disk indicator unit. The first logic device 703 can be a logic device located on the motherboard 701 or a logic device located elsewhere outside the motherboard 701.

[0092] The hard disk backplane 702 includes a second logic device 7021, an inserted hard disk 7022, and a hard disk indicator light 7023. The second logic device 7021 communicates with the first logic device 703 through multiple communication links 704. The second logic device 7021 is electrically connected to the hard disk indicator light 7023.

[0093] The first logic device 703 is used to parse the serial LED signal into multiple LED signals with the same address, and according to the preset correspondence between the VPP address and the communication link, transmit each LED signal in parallel through the corresponding communication link 704 to the second logic device 7021. The second logic device 7021 parses each received LED signal and instructs the hard disk indicator 7023 to light up.

[0094] For example, please see Figure 8 The motherboard 701 includes multiple first connectors 7012, the hard disk backplane 702 includes multiple second connectors 7024, and each communication link 704 includes one first connector 7012 and one second connector 7024; the first connector 7012 and the second connector 7024 are connected by a cable.

[0095] The first logic device 703 sends each lighting signal in parallel to the first connector 7012 of the communication link 704, and transmits each lighting signal to the second logic device 7021 through the first connector 7012 of the communication link 704 and the second connector 7024 connected to the first connector 7012 of the communication link 704.

[0096] For example, the second logic device 7021 includes a normalized address. The second logic device 7021 matches the address in each received lamp signal with the normalized address. If the match is successful, the lamp information is parsed from each received lamp signal.

[0097] For example, the second logic device 7021 determines at least one hard disk for which each received lighting signal is used to light up according to the preset correspondence between the second connector and the hard disk, and instructs the hard disk indicator light 7023 of the at least one hard disk to light up based on the lighting information.

[0098] For example, the first logic device 703 configures the VPP address in each lighting signal to be the same address, and obtains a plurality of lighting signals including the same address, according to the VPP address in each lighting signal.

[0099] The specific implementation in the server 700 can refer to the related description of the embodiments shown in Figure 4 and achieve the same or similar beneficial effects.

[0100] As can be seen, in the server 700, the first logic device 703 can parse the serial lighting signal into a plurality of lighting signals including the same address according to the VPP address in the serial lighting signal, which makes the second logic device 7021 at the end of the hard disk backplane 702 not need to do a lot of address adaptation work with the BIOS. After receiving the plurality of lighting signals sent in parallel by the first logic device 703, the second logic device 7021 only needs to match the address in all lighting signals with the configured address to parse the lighting information in the corresponding lighting signal, thereby realizing the normalization of the VPP address at the end of the hard disk backplane 702, and the end of the hard disk backplane 702 can parse the lighting signal and perform the lighting operation without adaptation, which is conducive to reducing a large amount of address adaptation work at the end of the hard disk backplane 702, thereby reducing the complexity of hard disk lighting.

[0101] For example, the server 700 can further include a memory, which includes but is not limited to a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), or a compact disc read-only memory (CD-ROM), and is used to store related computer programs and data.

[0102] The first logic device 703 and the second logic device 7021 in the server 700 are used to read one or more programs stored in the above-mentioned memory to execute the operations in the firmware information acquisition method in the above-mentioned server.

[0103] It should be noted that although the server 700 only shows the mainboard 701, the processor 7011, the hard disk backboard 702, the first logic device 703, the second logic device 7021, the hard disk 7022, the hard disk indicator 7023, the plurality of communication links 704, the plurality of first connectors 7012, the plurality of second connectors 7024, in the specific implementation process, those skilled in the art should understand that the server 700 also includes other devices necessary for normal operation, such as: input and output devices, fans, network cards, power modules, etc. At the same time, according to the specific needs, those skilled in the art should understand that the server 700 can also include hardware devices that realize other additional functions. In addition, those skilled in the art should understand that the server 700 can also only include devices necessary for the implementation of the embodiments of the present application, and does not have to include all the above-mentioned devices.

[0104] The embodiments of the present application also provide a computer readable storage medium (Memory), which is a memory device in the server 700, used to store a computer program for device execution, when it runs on the server 700, Figure 4 The method flow shown is realized. It can be understood that the computer readable storage medium here can include the built-in storage medium in the server 700, and of course can also include the extended storage medium supported by the server 700. The computer readable storage medium provides a storage space, which stores the operating system of the server 700. And in the storage space, one or more computer programs suitable for being loaded and executed by the first logic device and the second logic device are also stored. It should be noted that the computer readable storage medium here can be a high-speed RAM, or a non-volatile memory, for example, at least one disk memory; optionally, it can also be at least one computer readable storage medium located away from the aforementioned network card and PLD.

[0105] The embodiments of the present application also provide a computer program product, when the computer program product is run by the device, Figure 4 The method flow shown is realized.

[0106] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0107] It should be understood that the processor mentioned in the embodiments of the present application can be a CPU, and can also be other general-purpose processors, Digital Signal Processors (DSP), Application Specific Integrated Circuits (ASIC), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor.

[0108] It should also be understood that the memory mentioned in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a ROM, a Programmable ROM (PROM), an EPROM, an Electrically Erasable Programmable Read-Only Memory (EEPROM), or a flash memory. The volatile memory can be a RAM used as an external cache. By way of example and not limitation, many forms of RAM can be used, such as Static RAM (SRAM), Dynamic RAM (DRAM), Synchronous Dynamic RAM (SDRAM), Double Data Rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DR RAM).

[0109] It should be noted that when the processor is a general-purpose processor, a DSP, an ASIC, an FPGA, or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, the memory (storage module) is integrated in the processor.

[0110] It should be noted that the memory described herein is intended to include, but not limited to, these and any other suitable types of memory.

[0111] It should be understood that in various embodiments of the present application, the size of the sequence number of each process described above does not mean the order of execution, the execution order of each process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0112] In several embodiments provided in the present application, it should be understood that the disclosed system, device and method can be implemented in other manners. For example, the described device embodiments are merely exemplary. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0113] The units described as separate components can or can not be physically separate, and the components shown as units can or can not be physical units, that is, can be located in one place, or can be distributed on multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0114] In addition, each functional unit in the various embodiments of the present application can be integrated into one processing unit, or each unit can exist physically, or two or more units can be integrated into one unit. When the above integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer readable storage medium.

[0115] In the present application, "at least one" means one or more, and "multiple" means two or more. "And / or" describes the association relationship between the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the following three cases: A exists alone, A and B exist together, and B exists alone, where A and B can be singular or plural. In the textual description of the present application, the character " / ", generally indicates that the front and rear associated objects are in an "or" relationship.

[0116] The steps in the method embodiments of the present application can be adjusted, combined and deleted according to actual needs.

[0117] The modules in the device embodiments of the present application can be combined, divided and deleted according to actual needs.

[0118] The above embodiments are only used to illustrate the technical solutions of the present application, rather than limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacements for some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A server, characterized in that, The system includes a motherboard, a hard drive backplane, and a first logic device. The motherboard includes a processor, which includes multiple VPP addresses. The processor sends serial LED signals to the first logic device. The serial LED signals include multiple LED signals. Each LED signal includes a VPP address. Each LED signal is used to illuminate a hard drive indicator light unit. The hard disk backplane includes a second logic device and a hard disk indicator light. The second logic device communicates with the first logic device through multiple communication links. The second logic device is electrically connected to the hard disk indicator light. The first logic device is used to parse the serial LED signal into multiple LED signals including the same address, and transmit each LED signal in parallel to the second logic device through the corresponding communication link according to the preset correspondence between VPP address and communication link. The second logic device parses each received LED signal and instructs the hard disk indicator light to light up. The first logic device parses the multiple LED signals from the serial LED signal according to the VPP address in each LED signal, configures the VPP address in each LED signal to the same address, and obtains multiple LED signals including the same address.

2. The server according to claim 1, characterized in that, The motherboard includes multiple first connectors, the hard drive backplane includes multiple second connectors, and each communication link includes one first connector and one second connector; the first connector and the second connector are connected by a cable. The first logic device sends each lighting signal in parallel to the first connector of the communication link, and transmits each lighting signal to the second logic device through the first connector of the communication link and the second connector connected to the first connector of the communication link.

3. The server according to claim 1 or 2, characterized in that, The second logic device includes a normalized address. The second logic device matches the address in each received lamp-lighting signal with the normalized address. If the match is successful, the lamp-lighting information is parsed from each received lamp-lighting signal.

4. The server according to claim 3, characterized in that, The second logic device determines, based on the preset correspondence between the second connector and the hard disk, at least one hard disk for which each received lighting signal is used to light up, and instructs the hard disk indicator light of the at least one hard disk to light up based on the lighting information.

5. A method for activating LEDs on a server hard drive, characterized in that, Applied to the server according to any one of claims 1-4, the method comprises: The first logic device acquires a serial LED signal sent by the processor in a serial manner. The serial LED signal includes multiple LED signals, each LED signal including a VPP address; and each LED signal is used to illuminate a hard disk indicator unit. The first logic device parses the serial lighting signal into multiple lighting signals that include the same address, and transmits each lighting signal in parallel to the second logic device according to the preset correspondence between the VPP address and the communication link. The second logic device receives each LED signal transmitted in parallel by the first logic device, and after parsing each received LED signal, instructs the hard disk indicator light to turn on. The step of parsing the serial LED signal into multiple LED signals that share the same address includes: The first logic device parses the plurality of lighting signals from the serial lighting signals based on the VPP address in each lighting signal; The first logic device configures the VPP address in each lighting signal to the same address, resulting in multiple lighting signals including the same address.

6. The method according to claim 5, characterized in that, The step of transmitting each lighting signal in parallel to the second logic device includes: The first logic device sends each lighting signal in parallel to the first connector of the corresponding communication link, and transmits each lighting signal to the second logic device through the first connector of the communication link and the second connector connected to the first connector of the communication link.

7. The method according to claim 5 or 6, characterized in that, The second logic device includes a normalized address, and after receiving each LED signal transmitted in parallel by the first logic device, the method further includes: The second logic device matches the address in each received lamp-lighting signal with the normalized address; If a match is successful, the second logic device parses the lighting information from each received lighting signal.

8. The method according to claim 7, characterized in that, The indicator light for the hard drive is turned on includes: The second logic device determines, based on a preset correspondence between the second connector and the hard disk, at least one hard disk for each received lighting signal to be used to light up the lamp; The second logic device instructs the hard drive indicator lights of at least one hard drive to turn on based on the lighting information.

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