signal generating device

Abstract

The embodiment of the present application relates to a kind of signal generating device, the device includes: communication module, master module, first external interface module, power supply control backplane and function module.By increasing communication module and master module, the FC bus signal received from outside is transmitted to master module by communication module, and after being transmitted to function module by power supply control backplane, the generation of radio frequency continuous wave signal and wideband vector modulation signal is completed.Thereby, the technical effects of high-speed data transmission and signal generation based on FC bus can be realized.

Description

Technical Field

[0001] This invention relates to the field of signal processing technology, and more particularly to a signal generating device. Background Technology

[0002] With the development of communication technology, data transmission methods have been greatly enriched. Transmission methods using optical fiber as a medium are widely used. FC (Fibre Channel) bus is valued by various industries because of its advantages such as high bandwidth, light weight and strong anti-interference ability.

[0003] However, while existing FC bus-based products include terminal network cards, switches, video transmission equipment, network analyzers, and fault injection cards, there are no FC bus-based signal generation devices. The closest product is the LXI bus microwave instrument, which cannot meet the high-speed data transmission requirements of the host. Summary of the Invention

[0004] In view of this, in order to solve the technical problem that the FC bus cannot meet the technical requirements in the field of signal processing, the present invention provides a signal generating device.

[0005] In a first aspect, embodiments of the present invention provide a signal generating apparatus, comprising:

[0006] Communication module, main control module, first external interface module, power supply control backplane and functional modules;

[0007] The communication module includes an Ethernet port physical layer and a first FPGA chip. The input of the Ethernet port physical layer is electrically connected to the first output of the first external interface module, and the output of the Ethernet port physical layer is electrically connected to the first input of the main control module.

[0008] The input terminal of the first FPGA chip is electrically connected to the second output terminal of the first external interface module, the first output terminal is electrically connected to the second input terminal of the main control module, and the second output terminal is electrically connected to the first input terminal of the power supply control backplane.

[0009] The third output terminal of the first external interface module is electrically connected to the third input terminal of the main control module;

[0010] The second input terminal of the power supply control backplane is electrically connected to the output terminal of the main control module, and the multiple output terminals of the power supply control backplane are sequentially electrically connected to the multiple input terminals of the functional module.

[0011] In one possible implementation, the first FPGA chip includes:

[0012] PCIe interface IP, Ethernet IP, and synchronization logic unit;

[0013] The output terminal of the PCIe interface IP is electrically connected to the second input terminal of the main control module;

[0014] The input terminal of the Ethernet IP is electrically connected to the second output terminal of the first external interface module;

[0015] The first input terminal of the synchronous logic unit is electrically connected to the fourth output terminal of the first external interface module, the second input terminal is electrically connected to the fifth output terminal of the first external interface module, and the output terminal is electrically connected to the first input terminal of the power supply control backplane.

[0016] In one possible implementation, the functional module includes:

[0017] Baseband signal generation submodule, RF upconversion submodule, local oscillator submodule, and switching attenuation submodule;

[0018] The input terminal of the baseband signal generation submodule is electrically connected to the first output terminal of the power supply control backplane, the first output terminal is electrically connected to the first input terminal of the RF upconversion submodule, and the second output terminal is electrically connected to the first input terminal of the local oscillator submodule.

[0019] The second input terminal of the local oscillator module is electrically connected to the second output terminal of the power supply control backplane, and the output terminal is electrically connected to the second input terminal of the radio frequency upconversion submodule.

[0020] The third input terminal of the RF upconversion submodule is electrically connected to the third output terminal of the power supply control backplane, and the output terminal is electrically connected to the first input terminal of the switch attenuation submodule.

[0021] The second input terminal of the switch attenuation submodule is electrically connected to the fourth output terminal of the power supply control backplane, and the output terminal is connected to the output interface.

[0022] In one possible implementation, the baseband signal generation submodule includes:

[0023] The second FPGA chip, DA acquisition unit, first clock unit, and conditioning unit;

[0024] The input terminal of the second FPGA chip is electrically connected to the first output terminal of the power supply control backplane, and the output terminal is electrically connected to the input terminal of the DA acquisition unit.

[0025] The DA acquisition unit includes a wideband DA acquisition subunit and a calibration DA acquisition subunit. The input terminal of the wideband DA acquisition subunit is electrically connected to the first output terminal of the second FPGA chip. The output terminal of the wideband DA acquisition subunit is electrically connected to the input terminal of the conditioning unit and the output terminal of the calibration DA acquisition subunit. The input terminal of the calibration DA acquisition subunit is electrically connected to the second output terminal of the second FPGA chip.

[0026] The output terminal of the first clock unit is electrically connected to the second input terminal of the local oscillator module;

[0027] The output terminal of the conditioning unit is electrically connected to the first input terminal of the RF upconversion submodule.

[0028] In one possible implementation, the local oscillator module includes:

[0029] Second clock unit, frequency multiplication unit, broadband low phase noise sweep frequency unit and point frequency source unit;

[0030] The input terminal of the second clock unit is electrically connected to the second output terminal of the baseband signal generation submodule, and the output terminal is electrically connected to the input terminal of the frequency multiplication unit, the first input terminal of the broadband low phase noise sweep frequency unit, and the point frequency source unit, respectively.

[0031] The output terminal of the frequency multiplier unit is electrically connected to the second input terminal of the broadband low phase noise sweep frequency unit;

[0032] The output terminal of the broadband low phase noise sweep frequency unit is electrically connected to the second input terminal of the radio frequency upconversion submodule;

[0033] The local oscillator module also includes a first power control unit. The input terminal of the first power control unit is electrically connected to the second output terminal of the power supply control backplane. The output terminal of the first power control unit is electrically connected to another input terminal of the second clock unit, another input terminal of the frequency multiplier unit, a third input terminal of the broadband low phase noise sweep frequency unit, and another input terminal of the point frequency source unit.

[0034] In one possible implementation, the radio frequency upconversion submodule includes:

[0035] IQ modulation unit, filtering unit, low-frequency signal generation unit, and gain conditioning unit;

[0036] The first input terminal of the IQ modulation unit is electrically connected to the first output terminal of the baseband signal generation submodule, the second input terminal is electrically connected to the output terminal of the local oscillator module, the first output terminal is electrically connected to the input terminal of the low-frequency signal generation unit, and the second output terminal is electrically connected to the input terminal of the filtering unit.

[0037] The output terminal of the low-frequency signal generation unit is electrically connected to the first input terminal of the gain conditioning unit;

[0038] The output terminal of the filtering unit is electrically connected to the second input terminal of the gain conditioning unit;

[0039] The output terminal of the gain conditioning unit is electrically connected to the second input terminal of the switching attenuation submodule;

[0040] The RF upconversion submodule also includes a second power control unit. The input terminal of the second power control unit is electrically connected to the third output terminal of the power supply control backplane. The output terminal of the second power control unit is electrically connected to the third input terminal of the IQ modulation unit, the second input terminal of the filtering unit, the second input terminal of the low-frequency signal generation unit, and the third input terminal of the gain conditioning unit, respectively.

[0041] In one possible implementation, the switching attenuation submodule includes:

[0042] Programmable attenuation unit and third power supply control unit;

[0043] The first input terminal of the programmable attenuation unit is electrically connected to the output terminal of the RF upconversion submodule, the second input terminal is electrically connected to the output terminal of the third power control unit, and the output terminal is connected to the output interface.

[0044] The input terminal of the third power control unit is electrically connected to the fourth output terminal of the power supply control backplane.

[0045] In one possible implementation, the first external interface module includes:

[0046] Debugging interface, display and control interface, FC fiber optic interface, SMB second pulse interface and trigger signal interface;

[0047] The output of the debugging interface is electrically connected to the first input of the communication module;

[0048] The output terminal of the display and control interface is electrically connected to the second input terminal of the communication module;

[0049] The output end of the FC fiber optic interface is electrically connected to the third input end of the communication module;

[0050] The output terminal of the SMB second pulse interface is electrically connected to the fourth input terminal of the communication module;

[0051] The output terminal of the trigger signal interface is electrically connected to the fifth input terminal of the communication module.

[0052] In one possible implementation, the device further includes a second external interface module;

[0053] The input terminal of the second external interface module is sequentially electrically connected to the baseband signal generation submodule in the functional module.

[0054] In one possible implementation, the second external interface module includes: a four-channel external modulation interface, a reference interface, and a trigger interface;

[0055] The output terminal of the four-channel external modulation interface is electrically connected to another input terminal of the conditioning unit;

[0056] The reference interface is electrically connected to the first clock unit;

[0057] The trigger interface is electrically connected to the second FPGA chip.

[0058] In one possible implementation, the device further includes a power source;

[0059] The power supply is electrically connected to the power supply control backplane via an AC-DC converter.

[0060] The signal generating device provided in this embodiment of the invention comprises a communication module, a main control module, a first external interface module, a power supply control backplane, and functional modules. The communication module includes an Ethernet port physical layer and a first FPGA chip. The input terminal of the port physical layer is electrically connected to the first output terminal of the first external interface module, and the output terminal of the port physical layer is electrically connected to the first input terminal of the main control module. The input terminal of the first FPGA chip is electrically connected to the second output terminal of the first external interface module, the first output terminal is electrically connected to the second input terminal of the main control module, and the second output terminal is electrically connected to the first input terminal of the power supply control backplane. The third output terminal of the first external interface module is electrically connected to the third input terminal of the main control module. The second input terminal of the power supply control backplane is electrically connected to the output terminal of the main control module, and multiple output terminals of the power supply control backplane are sequentially electrically connected to multiple input terminals of the functional modules. By adding a communication module and a main control module connected to the power supply control backplane, the externally received FC bus signals are transmitted to the main control module via the communication module, and then transmitted to the functional modules via the power supply control backplane, thus generating radio frequency continuous wave signals and broadband vector modulation signals. This solution achieves the technical effect of high-speed data transmission and signal generation based on the FC bus. Attached Figure Description

[0061] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0062] Figure 1 This is a schematic diagram of the structure of a signal generating device provided in an embodiment of the present invention;

[0063] Figure 2 This is a schematic diagram of another signal generating device provided in an embodiment of the present invention;

[0064] Figure 3 This is a schematic diagram of the structure of an FPGA chip in a communication module provided by an embodiment of the present invention;

[0065] Figure 4 This is a schematic diagram of another signal generating device provided in an embodiment of the present invention;

[0066] Figure 5 This is a schematic diagram of the structure of another signal generating device provided in an embodiment of the present invention;

[0067] Figure 6 This is a schematic diagram of the structure of an external interface of a signal generating device provided in an embodiment of the present invention. Detailed Implementation

[0068] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0069] In this invention, the terms "comprising" and "having" are used to indicate an open-ended inclusion, meaning that additional elements / components / etc. may exist besides those listed. The terms "first" and "second," etc., are used only as labels and are not intended to limit the number of objects. Furthermore, the different elements and areas in the drawings are only schematic, and therefore the invention is not limited to the dimensions or distances shown in the drawings.

[0070] To facilitate understanding of the embodiments of the present invention, further explanations and descriptions will be provided below with reference to the accompanying drawings and specific embodiments. These embodiments do not constitute a limitation on the embodiments of the present invention.

[0071] Fibre Channel (FC), with its high speed and high reliability, has become one of the interconnection standards for complex avionics systems. It supports upper-layer protocols such as FC-AE-ASM and FC-FS, and the link rate can be configured to multiple transmission rates including 1Gbps, 2Gbps, and 4Gb / s. When used under the Windows operating system, it can simulate the functions of a main manager and ordinary terminals, supporting customized data transmission and reception of short and long messages, simulation verification of time servers and clients, network management function simulation, and other functions, enabling functional, performance, protocol, and stress testing of connected switches and terminals.

[0072] Figure 1 This is a schematic diagram of a signal generating device provided in an embodiment of the present invention. (Reference) Figure 1 The provided diagram shows that the signal generating device specifically includes:

[0073] The system includes a communication module 10, a main control module 20, a first external interface module 30, a power supply control backplane 40, and a functional module 50.

[0074] according to Figure 1 The provided diagram shows the internal structure of the signal generator, which specifically includes:

[0075] The communication module 10 is provided with an Ethernet port physical layer 11 and a first FPGA chip 12. The input end of the Ethernet port physical layer 11 is electrically connected to the first output end of the first external interface module 30, and the output end of the Ethernet port physical layer 11 is electrically connected to the first input end of the main control module 20.

[0076] The input terminal of the first FPGA chip 12 is electrically connected to the second output terminal of the first external interface module 30, the first output terminal is electrically connected to the second input terminal of the main control module 20, and the second output terminal is electrically connected to the first input terminal of the power supply control backplane 40.

[0077] The third output terminal of the first external interface module 30 is electrically connected to the third input terminal of the main control module 20;

[0078] The second input terminal of the power supply control backplane 40 is electrically connected to the output terminal of the main control module 20, and the multiple output terminals of the power supply control backplane 40 are sequentially electrically connected to the multiple input terminals of the functional module 50.

[0079] The main control module 20 is used to run the operating system, protocol stack and device application services to realize device access control, data processing and transmission.

[0080] according to Figure 1The provided diagram shows that the fiber optic signal is input to the communication module 10 through the first external interface module 30. After being converted into a bandwidth vector modulation signal through the Ethernet port physical layer 11 and the first FPGA chip 12, the fiber optic signal is input to the main control module 20 and the power supply control backplane 40. According to the communication protocol selected in the main control module 20, a synchronous clock and a timing trigger signal are output. The synchronous clock and the timing trigger signal are also sent to the power supply control backplane 40. The power supply control backplane 40 transmits the bandwidth vector modulation signal, the synchronous clock, and the timing trigger signal to the functional module 50. The functional module 50 performs signal generation and frequency conversion processing, outputs the final radio frequency continuous wave signal, and outputs it through the output interface. This completes the generation of the radio frequency continuous wave signal and the frequency conversion signal, thereby realizing signal generation based on the FC bus and achieving the technical effect of high-speed data transmission.

[0081] This invention provides a signal generating device comprising a communication module, a main control module, a first external interface module, a power supply control backplane, and functional modules. The communication module includes an Ethernet port physical layer and a first FPGA chip. The input of the port physical layer is electrically connected to the first output of the first external interface module, and the output of the port physical layer is electrically connected to the first input of the main control module. The input of the first FPGA chip is electrically connected to the second output of the first external interface module, the first output is electrically connected to the second input of the main control module, and the second output is electrically connected to the first input of the power supply control backplane. The third output of the first external interface module is electrically connected to the third input of the main control module. The second input of the power supply control backplane is electrically connected to the output of the main control module, and multiple outputs of the power supply control backplane are sequentially electrically connected to multiple inputs of the functional modules. By adding a communication module and a main control module connected to the power supply control backplane, externally received FC bus signals are transmitted to the main control module via the communication module, and then transmitted to the functional modules via the power supply control backplane, thus generating radio frequency continuous wave signals and broadband vector modulation signals. This solution enables high-speed data transmission and signal generation based on the FC bus.

[0082] In an optional embodiment of the present invention, the first FPGA chip includes: a PCIe interface IP, an Ethernet IP, and a synchronization logic unit; the output terminal of the PCIe interface IP is electrically connected to the second input terminal of the main control module; the input terminal of the Ethernet IP is electrically connected to the second output terminal of the first external interface module; the first input terminal of the synchronization logic unit is electrically connected to the fourth output terminal of the first external interface module, the second input terminal is electrically connected to the fifth output terminal of the first external interface module, and the output terminal is electrically connected to the first input terminal of the power supply control backplane.

[0083] In an optional embodiment of the present invention, the functional module includes: a baseband signal generation submodule, an RF upconversion submodule, a local oscillator submodule, and a switching attenuation submodule; the input terminal of the baseband signal generation submodule is electrically connected to the first output terminal of the power supply control backplane, the first output terminal is electrically connected to the first input terminal of the RF upconversion submodule, and the second output terminal is electrically connected to the first input terminal of the local oscillator submodule; the second input terminal of the local oscillator submodule is electrically connected to the second output terminal of the power supply control backplane, and the output terminal is electrically connected to the second input terminal of the RF upconversion submodule; the third input terminal of the RF upconversion submodule is electrically connected to the third output terminal of the power supply control backplane, and the output terminal is electrically connected to the first input terminal of the switching attenuation submodule; the second input terminal of the switching attenuation submodule is electrically connected to the fourth output terminal of the power supply control backplane, and the output terminal is connected to an output interface.

[0084] In an optional embodiment of the present invention, the baseband signal generation submodule includes: a second FPGA chip, a DA acquisition unit, a first clock unit, and a conditioning unit; the input terminal of the second FPGA chip is electrically connected to the first output terminal of the power supply control backplane, and the output terminal is electrically connected to the input terminal of the DA acquisition unit; the DA acquisition unit includes a broadband DA acquisition subunit and a calibration DA acquisition subunit, the input terminal of the broadband DA acquisition subunit is electrically connected to the first output terminal of the second FPGA chip, the output terminal of the broadband DA acquisition subunit is electrically connected to the input terminal of the conditioning unit and the output terminal of the calibration DA acquisition subunit, and the input terminal of the calibration DA acquisition subunit is electrically connected to the second output terminal of the second FPGA chip; the output terminal of the first clock unit is electrically connected to the second input terminal of the local oscillator module; and the output terminal of the conditioning unit is electrically connected to the first input terminal of the RF up-conversion submodule.

[0085] In an optional embodiment of the present invention, the oscillator module includes: a second clock unit, a frequency multiplier unit, a broadband low-phase-noise sweep frequency unit, and a point frequency source unit; the input terminal of the second clock unit is electrically connected to the second output terminal of the baseband signal generation submodule, and the output terminal is electrically connected to the input terminal of the frequency multiplier unit, the first input terminal of the broadband low-phase-noise sweep frequency unit, and the point frequency source unit, respectively; the output terminal of the frequency multiplier unit is electrically connected to the second input terminal of the broadband low-phase-noise sweep frequency unit; the output terminal of the broadband low-phase-noise sweep frequency unit is electrically connected to the second input terminal of the RF up-conversion submodule; the oscillator module further includes a first power control unit, the input terminal of the first power control unit is electrically connected to the second output terminal of the power supply control backplane, and the output terminal of the first power control unit is electrically connected to another input terminal of the second clock unit, another input terminal of the frequency multiplier unit, a third input terminal of the broadband low-phase-noise sweep frequency unit, and another input terminal of the point frequency source unit, respectively.

[0086] In an optional embodiment of the present invention, the RF upconversion submodule includes: an IQ modulation unit, a filtering unit, a low-frequency signal generation unit, and a gain conditioning unit; the first input terminal of the IQ modulation unit is electrically connected to the first output terminal of the baseband signal generation submodule, the second input terminal is electrically connected to the output terminal of the local oscillator submodule, the first output terminal is electrically connected to the input terminal of the low-frequency signal generation unit, and the second output terminal is electrically connected to the input terminal of the filtering unit; the output terminal of the low-frequency signal generation unit is electrically connected to the first input terminal of the gain conditioning unit; the output terminal of the filtering unit is electrically connected to the second input terminal of the gain conditioning unit; the output terminal of the gain conditioning unit is electrically connected to the second input terminal of the switching attenuation submodule; the RF upconversion submodule further includes a second power control unit, the input terminal of the second power control unit is electrically connected to the third output terminal of the power supply control backplane, and the output terminal of the second power control unit is electrically connected to the third input terminal of the IQ modulation unit, the second input terminal of the filtering unit, the second input terminal of the low-frequency signal generation unit, and the third input terminal of the gain conditioning unit, respectively.

[0087] In an optional embodiment of the present invention, the switching attenuation submodule includes: a programmable attenuation unit and a third power control unit; the first input terminal of the programmable attenuation unit is electrically connected to the output terminal of the RF upconversion submodule, the second input terminal is electrically connected to the output terminal of the third power control unit, and the output terminal is connected to the output interface; the input terminal of the third power control unit is electrically connected to the fourth output terminal of the power supply control backplane.

[0088] In an optional embodiment of the present invention, the first external interface module includes: a debugging interface, a display and control interface, an FC fiber optic interface, an SMB second pulse interface, and a trigger signal interface; the output of the debugging interface is electrically connected to the first input of the communication module; the output of the display and control interface is electrically connected to the second input of the communication module; the output of the FC fiber optic interface is electrically connected to the third input of the communication module; the output of the SMB second pulse interface is electrically connected to the fourth input of the communication module; and the output of the trigger signal interface is electrically connected to the fifth input of the communication module.

[0089] In an optional embodiment of the present invention, the device further includes a second external interface module; the input terminal of the second external interface module is sequentially electrically connected to the baseband signal generation submodule in the functional module.

[0090] In an optional embodiment of the present invention, the second external interface module includes: a four-channel external modulation interface, a reference interface, and a trigger interface; the output terminal of the four-channel external modulation interface is electrically connected to another input terminal of the conditioning unit; the reference interface is electrically connected to the first clock unit; and the trigger interface is electrically connected to the second FPGA chip.

[0091] In an optional embodiment of the present invention, the device further includes a power supply; the power supply is electrically connected to the power supply control backplane via an AC-DC converter.

[0092] The following description will focus on the main control module, the first FPGA chip (including PCIe interface IP, Ethernet IP, and synchronization logic unit), the power supply control backplane, the first external interface module (including debug interface, display and control interface, FC fiber optic interface, SMB second pulse interface, and trigger signal interface), the functional modules (including baseband signal generation submodule, RF up-conversion submodule, local oscillator submodule, and switching attenuation submodule), the second external interface module, and the power supply. (Refer to...) Figure 2 The diagram illustrates a different signal generating device according to an embodiment of the present invention. This signal generating device is described based on the previous signal generating device. Figure 2 As shown, the signal generating device specifically also includes:

[0093] The system includes a communication module 10, a main control module 20, a first external interface module 30, a power supply control backplane 40, and a functional module 50.

[0094] The communication module 10 includes an Ethernet port physical layer 11 and a first FPGA chip 12.

[0095] according to Figure 2 The provided diagram shows that the first FPGA chip 12 specifically includes:

[0096] PCIe interface IP13, Ethernet IP14 and synchronization logic unit 15.

[0097] The output of PCIe interface IP13 is electrically connected to the second input of the main control module 20; the input of Ethernet IP14 is electrically connected to the second output of the first external interface module 30; the first input of the synchronous logic unit 15 is electrically connected to the fourth output of the first external interface module, the second input is electrically connected to the fifth output of the first external interface module, and the output is electrically connected to the first input of the power supply control backplane.

[0098] according to Figure 2The provided diagram shows that the communication module 10 is based on a high-capacity first FPGA chip 12. It uses the Internet Protocol (IP) core, namely Ethernet IP 14, inside the first FPGA chip 12 to implement the Media Access Control (MAC) and Ethernet port physical layer 11 (PHY) functions of 10 Gigabit Ethernet. At the same time, it works with the processor to run the synchronization and triggering logic of the synchronization logic unit 15 of the precision clock synchronization protocol standard (IEEE1588) of the network measurement and control system, and outputs the synchronization clock, timed trigger and 1PPS pulse synchronization functions.

[0099] Furthermore, Figure 3 This is a schematic diagram of the structure of an FPGA chip in a communication module provided by an embodiment of the present invention. Figure 3 The provided diagram shows that PCIe interface IP13 is used to implement the PCIe 2.0 x4 link interface, responsible for interaction with the main control module 20; Ethernet IP14 implements the 10 Gigabit Ethernet MAC and PHY functions, where the 10 Gigabit Ethernet MAC is responsible for message transmission and reception and buffering, and performs functions such as frame gap, preamble, CRC, timestamp, and statistics on messages; the 10 Gigabit Ethernet process control system (PCS) is responsible for encoding and decoding; the high-speed transceiver realizes the interconnection function with the photoelectric conversion module. The IEEE1588 synchronization logic in the synchronization logic unit 15 is used to implement the high-precision network synchronization protocol based on 10 Gigabit Ethernet, and provides the second pulse signal, synchronization clock, and trigger signal.

[0100] Optionally, the main control module 20 uses a CPU as an embedded processor to run an operating system, an IEEE 1588 V2 protocol stack, and device application services. As the device's communication interface and data processing unit, it implements an external 10 Gigabit Ethernet FC fiber optic interface to receive instructions and data from the main control computer and achieves distributed time synchronization via the IEEE 1588V2 protocol (PTP). Internally, it communicates with various PCIe functional modules via the PCIe bus and outputs a synchronization clock and timing trigger signal via the PTP protocol to achieve synchronous triggering of the front-end conditioning circuit.

[0101] like Figure 2 The structure shown includes, specifically, the first external interface module 30, which comprises:

[0102] Debugging interface, display and control interface, FC fiber optic interface, SMB second pulse interface and trigger signal interface.

[0103] The output of the debugging interface is electrically connected to the first input of the communication module; the output of the display and control interface is electrically connected to the second input of the communication module; the output of the FC fiber optic interface is electrically connected to the third input of the communication module; the output of the SMB second pulse interface is electrically connected to the fourth input of the communication module; and the output of the trigger signal interface is electrically connected to the fifth input of the communication module.

[0104] Reference Figure 2 The provided diagram illustrates how the signal generator communicates remotely with an external FC bus via an FC fiber optic interface; how it achieves network synchronization with the communication module via an SMB second pulse interface; how it uses a trigger signal interface to control the synchronization logic unit in the communication module, triggering the synchronization and logic of the IEEE 1588 protocol; how the debugging interface is typically an IQ external modulation interface, used to input external I+, I-, Q+, and Q- four-channel modulation signals; and how the display and control interface serves as an auxiliary interface, used to connect to the main control module and control the main control module to display the generated signal parameters or to provide keyboard and mouse input / output interfaces.

[0105] Optionally, the power supply control module 40 is used to supply power to the communication module 10, the main control module 20 and the functional module 50. The interface is designed to use a PCIe Gen2.0 x4 link to realize bus communication and expansion, monitor and control the power supply and temperature of the control platform, and control the operation of the cooling fans installed on both sides of the device.

[0106] refer to Figure 2 The provided diagram contains 50 functional modules, specifically including:

[0107] Baseband signal generation submodule 51, RF upconversion submodule 52, local oscillator submodule 53, and switching attenuation submodule 54;

[0108] Optionally, the device is provided with an external output interface 55, which is electrically connected to the functional modules in the device.

[0109] The input terminal of the baseband signal generation submodule 51 is electrically connected to the first output terminal of the power supply control backplane 40, the first output terminal is electrically connected to the first input terminal of the RF upconversion submodule 52, and the second output terminal is electrically connected to the first input terminal of the local oscillator submodule 53.

[0110] The second input terminal of the local oscillator module 53 is electrically connected to the second output terminal of the power supply control backplane 40, and the output terminal is electrically connected to the second input terminal of the RF upconversion submodule 52.

[0111] The third input terminal of the RF upconversion submodule 52 is electrically connected to the third output terminal of the power supply control backplane 40, and the output terminal is electrically connected to the first input terminal of the switching attenuation submodule 54.

[0112] The second input terminal of the switch attenuation submodule 54 is electrically connected to the fourth output terminal of the power supply control backplane 40, and the output terminal is connected to the output interface 55.

[0113] according to Figure 2 The provided diagram shows that the baseband signal generation submodule 51 receives signals from the power supply control backplane and completes baseband signal processing and storage functions. Simultaneously, it transmits the generated signal to the RF upconversion submodule 52, which performs frequency conversion processing on the baseband signal for different frequency bands, adjusts the gain, and outputs it to the switching attenuation submodule 54. The local oscillator submodule 53 receives synchronous clock logic control from the baseband signal generation submodule, providing a wideband, small-step local oscillator signal to the RF upconversion submodule 52. The switching attenuation submodule 54 attenuates the received gain signal to achieve high-power dynamic range signal output, which is then output through the output interface.

[0114] refer to Figure 2 The provided diagram shows that the signal generating device also includes a second external interface module 60.

[0115] The input terminal of the second external interface module 60 is sequentially electrically connected to the baseband signal generation submodule 51 in the functional module 50.

[0116] refer to Figure 2 The provided diagram shows that the signal generating device also includes a power supply.

[0117] The power supply outputs a stable DC voltage via a 220V AC-DC converter and is electrically connected to the power supply control backplane 40.

[0118] The second external interface module 60 is used to realize signal transmission with the functional module. The power supply is installed inside the device to provide power to the device.

[0119] This invention provides a signal generating device comprising a communication module, a main control module, a first external interface module, a power supply control backplane, and functional modules. The communication module includes an Ethernet port physical layer and a first FPGA chip. Signals received from multiple external interfaces are transmitted via the Ethernet port physical layer and the first FPGA chip to the main control module and the power supply control module. The power supply control backplane then transmits the bus signal to a baseband signal generation submodule within the functional modules. After signal processing, the generated frequency-converted signal is output to an RF up-conversion submodule and a local oscillator submodule. The RF up-conversion submodule processes the signal and outputs it to a switching attenuation submodule. Simultaneously, the baseband signal generation submodule maintains clock synchronization with the local oscillator submodule using a synchronous clock signal, controlling the local oscillator submodule to output its signal to the RF up-conversion submodule. Finally, the output signal is processed by the switching attenuation submodule and output through an output interface, thus generating both RF continuous wave signals and broadband vector modulation signals. This solution achieves high-speed data transmission and signal generation based on the FC bus.

[0120] The following description will use the communication module, main control module, first external interface module, power supply control backplane, baseband signal generation submodule (including the second FPGA chip, DA acquisition unit, first clock unit, and conditioning unit), local oscillator module (including the second clock unit, frequency multiplier unit, broadband low phase noise sweep frequency unit, and point frequency source unit), RF upconversion submodule (including IQ modulation unit, filtering unit, low-frequency signal generation unit, and gain conditioning unit), switching attenuation submodule (including programmable attenuation unit and third power control unit), and second external interface module (including a four-channel external modulation interface, reference interface, and trigger interface) and power supply as examples. (Refer to...) Figure 4 This diagram illustrates the structure of yet another signal generating device provided in an embodiment of the present invention. This signal generating device is described based on the first signal generating device. Figure 4 As shown, the signal generating device specifically also includes:

[0121] The system includes a communication module 10, a main control module 20, a first external interface module 30, a power supply control backplane 40, a baseband signal generation submodule 51, an RF upconversion submodule 52, a local oscillator submodule 53, a switching attenuation submodule 54, a second external interface module 60, and a power supply.

[0122] Optionally, the communication module and the main control module are combined into a controller, which uses an optical fiber interface to realize FC bus communication function, and at the same time acts as a server to receive remote commands, control various functional modules, and realize the instrument function of the device; internally, a synthesized instrument architecture is adopted, which divides the vector signal generation into functional modules such as baseband signal generation submodule, RF upconversion submodule, local oscillator submodule and switching attenuation submodule to realize signal generation and frequency conversion; the internal backplane bus in the peripheral components adopts PCIe bus, and the connection between the controller and each functional module adopts bus slot design.

[0123] refer to Figure 4 The provided diagram shows that the baseband signal generation submodule 51 specifically includes:

[0124] The second FPGA chip, DA acquisition unit, first clock unit, and conditioning unit.

[0125] The input terminal of the second FPGA chip is electrically connected to the first output terminal of the power supply control backplane, and the output terminal is electrically connected to the input terminal of the DA acquisition unit. The DA acquisition unit includes a wideband DA acquisition subunit and a calibration DA acquisition subunit. The input terminal of the wideband DA acquisition subunit is electrically connected to the first output terminal of the second FPGA chip, and the output terminal of the wideband DA acquisition subunit is electrically connected to the input terminal of the conditioning unit and the output terminal of the calibration DA acquisition subunit. The input terminal of the calibration DA acquisition subunit is electrically connected to the second output terminal of the second FPGA chip. The output terminal of the first clock unit is electrically connected to the second input terminal of the local oscillator module. The output terminal of the conditioning unit is electrically connected to the first input terminal of the RF up-conversion submodule.

[0126] according to Figure 4 The provided diagram shows that the DA acquisition unit may include a broadband DAC and a calibration DAC. The second FPGA chip contained in the baseband signal generation submodule completes the data transmission and communication with the control backplane bus, as well as the algorithm generation of the baseband IQ signal waveform. The DA acquisition unit realizes the common-mode voltage fine-tuning function of four orthogonal differential baseband signal inputs.

[0127] Optionally, power control processing circuits are provided in the baseband signal generation submodule 51, the local oscillator submodule 53, and the radio frequency upconversion submodule 52 to provide the required power supply for each submodule.

[0128] refer to Figure 4 The provided diagram shows that this oscillator module 53 specifically includes:

[0129] Second clock unit, frequency multiplication unit, broadband low phase noise sweep frequency unit and point frequency source unit;

[0130] The input terminal of the second clock unit is electrically connected to the second output terminal of the baseband signal generation submodule, and the output terminal is electrically connected to the input terminal of the frequency multiplier unit, the first input terminal of the broadband low phase noise sweep unit, and the point frequency source unit, respectively. The output terminal of the frequency multiplier unit is electrically connected to the second input terminal of the broadband low phase noise sweep unit. The output terminal of the broadband low phase noise sweep unit is electrically connected to the second input terminal of the RF upconversion submodule. The oscillator module also includes a first power control unit, the input terminal of which is electrically connected to the second output terminal of the power supply control backplane, and the output terminal of which is electrically connected to the other input terminal of the second clock unit, the other input terminal of the frequency multiplier unit, the third input terminal of the broadband low phase noise sweep unit, and the other input terminal of the point frequency source unit, respectively.

[0131] according to Figure 4 The provided diagram shows the clock unit, frequency multiplier unit, wideband low phase noise sweep frequency unit, and point frequency source unit in the local oscillator module 53. A multi-ring phase-locked loop scheme is employed to generate one 100MHz–20GHz wideband microwave signal and three 3GHz–20GHz wideband microwave signals, providing the local oscillator signals required for signal frequency conversion to the RF upconversion submodule.

[0132] refer to Figure 4 The provided diagram shows that the RF upconversion submodule 52 specifically includes:

[0133] IQ modulation unit, filtering unit, low-frequency signal generation unit, and gain conditioning unit.

[0134] The first input terminal of the IQ modulation unit is electrically connected to the first output terminal of the baseband signal generation submodule, and the second input terminal is electrically connected to the output terminal of the local oscillator submodule. The first output terminal is electrically connected to the input terminal of the low-frequency signal generation unit, and the second output terminal is electrically connected to the input terminal of the filtering unit. The output terminal of the low-frequency signal generation unit is electrically connected to the first input terminal of the gain conditioning unit. The output terminal of the filtering unit is electrically connected to the second input terminal of the gain conditioning unit. The output terminal of the gain conditioning unit is electrically connected to the second input terminal of the switching attenuation submodule. The RF upconversion submodule also includes a second power control unit. The input terminal of the second power control unit is electrically connected to the third output terminal of the power supply control backplane, and the output terminal of the second power control unit is electrically connected to the third input terminal of the IQ modulation unit, the second input terminal of the filtering unit, the second input terminal of the low-frequency signal generation unit, and the third input terminal of the gain conditioning unit, respectively.

[0135] according to Figure 4 The provided diagram shows that the RF upconversion submodule includes an IQ modulation unit, a low-frequency signal generation unit, a filtering unit, and a gain conditioning unit. The RF upconversion is achieved by combining two channels: 1MHz to 6GHz and 6GHz to 20GHz. After undergoing multiple stages of frequency conversion, filtering, amplification, and conditioning, the signals are sent to the switching attenuation submodule.

[0136] refer to Figure 4 The provided diagram shows that the switch attenuation submodule 54 specifically includes:

[0137] Programmable attenuation unit and third power supply control unit.

[0138] The first input terminal of the programmable attenuation unit is electrically connected to the output terminal of the RF upconversion submodule, the second input terminal is electrically connected to the output terminal of the third power control unit, and the output terminal is connected to the output interface; the input terminal of the third power control unit is electrically connected to the fourth output terminal of the power supply control backplane.

[0139] according to Figure 4 The provided diagram shows that the switching attenuation submodule includes a programmable attenuator and a power control processing circuit. It combines signals from two frequency bands, 1MHz to 6GHz and 6GHz to 20GHz, through a switching combination, and then unifies them through the programmable attenuator to achieve a low-power, high dynamic range signal output.

[0140] refer to Figure 4 The provided diagram shows that the second external interface module 60 specifically includes:

[0141] Four-channel external modulation interface, reference interface, and trigger interface.

[0142] The output of the four-channel external modulation interface is electrically connected to another input of the conditioning unit; the reference interface is electrically connected to the first clock unit; and the trigger interface is electrically connected to the second FPGA chip.

[0143] according to Figure 4 The provided diagram shows that the four-channel external modulation interface in the second external interface module 60 is used to output external four-channel modulation signals. The reference interface and trigger interface provide user-output synchronization logic signals and synchronization clock signals.

[0144] This invention provides a signal generating device that, through a main control module and a communication module, provides synchronization and logic signals to a first FPGA chip via an FC bus interface. These signals are then transmitted to a power supply control backplane via the main control module. After transmitting the signals to various functional submodules of the baseband signal generation submodule, a frequency conversion signal and a synchronization clock signal are output. Under the control of the synchronization clock signal, the device connects to a local oscillator module and outputs a radio frequency continuous wave signal and a broadband vector modulation signal to the radio frequency up-conversion submodule. After attenuation processing, the final high-precision radio frequency continuous wave signal and broadband vector modulation signal are output through the output interface. This achieves the technical effect of high-speed transmission and signal generation based on the FC bus.

[0145] Figure 5 This is a schematic diagram of another signal generating device provided in an embodiment of the present invention. Figure 5 This introduction is based on the first type of signal generating device. According to... Figure 5 The provided diagram and signal generating device specifically include:

[0146] Controller 100, power supply 200, PCIe backplane 40, functional module 50, baseband signal generation submodule 51, RF upconversion submodule 52, local oscillator submodule 53, and switching attenuation submodule 54.

[0147] Among them, corresponding Figure 1 The communication module 10 and main control chip 20 in the signal generator are components of the controller 100, which is plugged into the PCIe backplane 40 as a card. The power supply 200 mentioned here corresponds to... Figure 1 The provided signal generator consists of a power supply and an AC-DC combination module. The PCIe backplane 40 mentioned here refers to... Figure 1 The corresponding power supply control backplane is 40. (Refer to...) Figure 5 The provided diagram shows that the baseband signal generation submodule 51, the RF upconversion submodule 52, the local oscillator submodule 53, and the switching attenuation submodule 54 are all independent functional modules 50, which are inserted into the PCIe backplane 40 in the form of plug-in cards.

[0148] Optionally, the signal generating device also includes a fan 300 mounted on both sides of the signal generating device.

[0149] Optionally, the device may also include the following on the exterior of its front panel:

[0150] RF output interface 600, status indicator light 700 and chassis switch 800.

[0151] according to Figure 5 The provided diagram shows that the device output interface 600 is used for signal output. The status indicator light 700 displays the device's operating status; a lit light indicates normal operation. The chassis switch 800 controls the power supply to the device. Through the signal generator, it can output radio frequency continuous wave signals in the range of 1MHz to 20GHz and broadband vector modulation signals. The device achieves a communication transmission rate of 12.5Gbps through an FC-type fiber optic interface.

[0152] The signal generating device provided in this embodiment of the invention combines a 10 Gigabit Ethernet communication module and a main control module to form a controller. It utilizes an optical fiber interface to realize FC bus communication and simultaneously acts as a server to receive remote commands, control various functional modules, and realize the instrument functions of the device. Internally, it adopts a synthesized instrument architecture, dividing vector signal generation into functional modules such as a baseband signal generation submodule, an RF up-conversion submodule, a local oscillator submodule, and a switching attenuation submodule to realize signal frequency conversion and generation. The internal backplane bus in the peripheral components adopts a PCIe bus, and the connection between the controller and each functional module adopts a bus slot design, which can realize the technical effect of high-speed data transmission and signal generation based on the FC bus.

[0153] Figure 6 This is a schematic diagram of the structure of an external interface of a signal generating device provided in an embodiment of the present invention. Figure 6 This introduction is based on the first type of signal generating device. According to... Figure 6 The provided diagram shows the external interface of the signal generator, specifically including:

[0154] 1-Power supply, 2-Reference input / output, 3-Trigger input / output, 4-Trigger signal interface, 5-Second pulse, 6-2-channel FC interface, 7-2-channel Ethernet port and 2-channel USB, 8-IQ external modulation.

[0155] according to Figure 6 The provided diagram shows: 1- Power supply for device power. 2- Reference input / output for clock reference synchronization. 3- Trigger input / output, including one trigger input and one trigger output interface for signal trigger input and output. 4- Trigger signal interface for 1588 triggering. 5- Second pulse for network synchronization. 6- Two FC interfaces for FC bus fiber optic communication. 7- Two Ethernet ports and two USB ports; the Ethernet ports are for debugging the device under Gigabit Ethernet; the USB ports are for keyboard / mouse or storage interfaces. 8- IQ external modulation for input of external four-channel modulation signals.

[0156] In one possible scenario, the FC bus-based signal generator can be installed in a 19-inch rack and connected to a remote control computer via fiber optic cable to complete remote data transmission and signal generation. The IEEE 1588 protocol supports high-precision synchronization between different FC bus instruments. User interaction is achieved through the remote control computer. The signal generator provided by this invention can provide a standard signal source output for frequency range measurement, bandwidth measurement, power measurement, sensitivity measurement, anti-interference characteristic testing, and comprehensive testing of radio equipment, achieving the technical effects of high-speed data transmission and signal generation based on the FC bus.

[0157] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A signal generating device, characterized in that, include: Communication module, main control module, first external interface module, power supply control backplane and functional modules; The communication module includes an Ethernet port physical layer and a first FPGA chip. The input of the Ethernet port physical layer is electrically connected to the first output of the first external interface module, and the output of the Ethernet port physical layer is electrically connected to the first input of the main control module. The input terminal of the first FPGA chip is electrically connected to the second output terminal of the first external interface module, the first output terminal is electrically connected to the second input terminal of the main control module, and the second output terminal is electrically connected to the first input terminal of the power supply control backplane. The third output terminal of the first external interface module is electrically connected to the third input terminal of the main control module; The second input terminal of the power supply control backplane is electrically connected to the output terminal of the main control module, and the multiple output terminals of the power supply control backplane are sequentially electrically connected to the multiple input terminals of the functional module. The functional modules include: a baseband signal generation submodule, an RF upconversion submodule, a local oscillator submodule, and a switching attenuation submodule; The input terminal of the baseband signal generation submodule is electrically connected to the first output terminal of the power supply control backplane, the first output terminal is electrically connected to the first input terminal of the RF upconversion submodule, and the second output terminal is electrically connected to the first input terminal of the local oscillator submodule. The second input terminal of the local oscillator module is electrically connected to the second output terminal of the power supply control backplane, and the output terminal is electrically connected to the second input terminal of the radio frequency upconversion submodule. The third input terminal of the RF upconversion submodule is electrically connected to the third output terminal of the power supply control backplane, and the output terminal is electrically connected to the first input terminal of the switch attenuation submodule. The second input terminal of the switch attenuation submodule is electrically connected to the fourth output terminal of the power supply control backplane, and the output terminal is connected to the output interface.

2. The apparatus according to claim 1, characterized in that, The first FPGA chip includes: PCIe interface IP, Ethernet IP, and synchronization logic unit; The output terminal of the PCIe interface IP is electrically connected to the second input terminal of the main control module; The input terminal of the Ethernet IP is electrically connected to the second output terminal of the first external interface module; The first input terminal of the synchronous logic unit is electrically connected to the fourth output terminal of the first external interface module, the second input terminal is electrically connected to the fifth output terminal of the first external interface module, and the output terminal is electrically connected to the first input terminal of the power supply control backplane.

3. The apparatus according to claim 1, characterized in that, The baseband signal generation submodule includes: The second FPGA chip, DA acquisition unit, first clock unit, and conditioning unit; The input terminal of the second FPGA chip is electrically connected to the first output terminal of the power supply control backplane, and the output terminal is electrically connected to the input terminal of the DA acquisition unit. The DA acquisition unit includes a wideband DA acquisition subunit and a calibration DA acquisition subunit. The input terminal of the wideband DA acquisition subunit is electrically connected to the first output terminal of the second FPGA chip. The output terminal of the wideband DA acquisition subunit is electrically connected to the input terminal of the conditioning unit and the output terminal of the calibration DA acquisition subunit. The input terminal of the calibration DA acquisition subunit is electrically connected to the second output terminal of the second FPGA chip. The output terminal of the first clock unit is electrically connected to the first input terminal of the local oscillator module; The output terminal of the conditioning unit is electrically connected to the first input terminal of the RF upconversion submodule.

4. The apparatus according to claim 1, characterized in that, The oscillator module includes: Second clock unit, frequency multiplication unit, broadband low phase noise sweep frequency unit and point frequency source unit; The input terminal of the second clock unit is electrically connected to the second output terminal of the baseband signal generation submodule, and the output terminal is electrically connected to the input terminal of the frequency multiplication unit, the first input terminal of the broadband low phase noise sweep frequency unit, and the point frequency source unit, respectively. The output terminal of the frequency multiplier unit is electrically connected to the second input terminal of the broadband low phase noise sweep frequency unit; The output terminal of the broadband low phase noise sweep frequency unit is electrically connected to the second input terminal of the radio frequency upconversion submodule; The local oscillator module also includes a first power control unit. The input terminal of the first power control unit is electrically connected to the second output terminal of the power supply control backplane. The output terminal of the first power control unit is electrically connected to another input terminal of the second clock unit, another input terminal of the frequency multiplier unit, a third input terminal of the broadband low phase noise sweep frequency unit, and another input terminal of the point frequency source unit.

5. The apparatus according to claim 1, characterized in that, The radio frequency upconversion submodule includes: IQ modulation unit, filtering unit, low-frequency signal generation unit, and gain conditioning unit; The first input terminal of the IQ modulation unit is electrically connected to the first output terminal of the baseband signal generation submodule, the second input terminal is electrically connected to the output terminal of the local oscillator module, the first output terminal is electrically connected to the input terminal of the low-frequency signal generation unit, and the second output terminal is electrically connected to the input terminal of the filtering unit. The output terminal of the low-frequency signal generation unit is electrically connected to the first input terminal of the gain conditioning unit; The output terminal of the filtering unit is electrically connected to the second input terminal of the gain conditioning unit; The output terminal of the gain conditioning unit is electrically connected to the first input terminal of the switching attenuation submodule; The RF upconversion submodule also includes a second power control unit. The input terminal of the second power control unit is electrically connected to the third output terminal of the power supply control backplane. The output terminal of the second power control unit is electrically connected to the third input terminal of the IQ modulation unit, the second input terminal of the filtering unit, the second input terminal of the low-frequency signal generation unit, and the third input terminal of the gain conditioning unit, respectively.

6. The apparatus according to claim 1, characterized in that, The switching attenuation submodule includes: Programmable attenuation unit and third power supply control unit; The first input terminal of the programmable attenuation unit is electrically connected to the output terminal of the RF upconversion submodule, the second input terminal is electrically connected to the output terminal of the third power control unit, and the output terminal is connected to the output interface. The input terminal of the third power control unit is electrically connected to the fourth output terminal of the power supply control backplane.

7. The apparatus according to claim 1, characterized in that, The first external interface module includes: Debugging interface, display and control interface, FC fiber optic interface, SMB second pulse interface and trigger signal interface; The output of the debugging interface is electrically connected to the first input of the communication module; The output terminal of the display and control interface is electrically connected to the second input terminal of the communication module; The output end of the FC fiber optic interface is electrically connected to the third input end of the communication module; The output terminal of the SMB second pulse interface is electrically connected to the fourth input terminal of the communication module; The output terminal of the trigger signal interface is electrically connected to the fifth input terminal of the communication module.

8. The apparatus according to claim 3, characterized in that, The device also includes a second external interface module; The input terminal of the second external interface module is sequentially electrically connected to the baseband signal generation submodule in the functional module.

9. The apparatus according to claim 8, characterized in that, The second external interface module includes: a four-channel external modulation interface, a reference interface, and a trigger interface; The output terminal of the four-channel external modulation interface is electrically connected to another input terminal of the conditioning unit; The reference interface is electrically connected to the first clock unit; The trigger interface is electrically connected to the second FPGA chip.

10. The apparatus according to claim 1, characterized in that, The device also includes a power supply; The power supply is electrically connected to the power supply control backplane via an AC-DC converter.

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