Method, device, system and storage medium for data transmission between FPGA chips

Abstract

The embodiment of the application discloses a FPGA chip inter data transmission method, device, system and storage medium, and the technical scheme provided by the application establishes a data link between a master FPGA chip and a slave FPGA chip, then the master FPGA chip and the slave FPGA chip transmit data based on the data link, since the data link only transmits data information and does not transmit control information, therefore the data transmission efficiency is improved; in addition, the user data is crossed from a user clock domain to a transmission clock domain when data is transmitted, and the received data is crossed from the transmission clock domain to the user clock domain when received, so that continuous data transmission is realized, and the data transmission rate is further improved; when multiple data links exist, a synchronous buffer is arranged at the sending end or the receiving end, so that the data of each data link is aligned, the data reliability is improved, and the problem that the data overhead is large and the high-speed data transmission is not suitable in the prior art is solved.

Description

Technical Field

[0001] This invention relates to the fields of FPGA and communication technology, and more particularly to a method, apparatus, system and storage medium for data transmission between FPGA chips. Background Technology

[0002] Massive MIMO is one of the key technologies in 5G NR (New Radio). In a Massive MIMO system, the number of antennas can typically reach 64 or even more, such as 128 or 256. As the number of antennas increases, the system capacity also increases exponentially, as does the complexity of the system implementation. Therefore, the amount of data to be processed is enormous, and the requirements for data transmission rate and stability are also very high. To implement a Massive MIMO system, multiple FPGAs (Field Programmable Gate Arrays) typically need to work together; therefore, how to stably transmit data between multiple FPGAs is crucial.

[0003] In systems where multiple FPGAs work together, PCIe, Serial RapidIO (SRIO), and Aurora64B / 66B are three commonly used protocols for data transmission. PCIe defines the physical layer, data link layer, transaction layer, and software layer; SRIO defines the physical layer, transport layer, and logic layer; while Aurora64B / 66B only defines the data link layer and physical layer. Compared to PCIe and SRIO, the Aurora64B / 66B protocol is simpler, has lower overhead, and offers more flexibility in selecting the number of links and link rates. Therefore, Aurora64B / 66B is one of the commonly used protocols for interconnecting multiple FPGAs.

[0004] Taking a system with a hardware design architecture based on Xilinx FPGA as an example, assume that the entire system has 5 FPGAs, one of which is the master chip, which mainly implements the functions of ETH MAC and ORAN interface, and the other 4 FPGAs are slave chips, which mainly implement the transmission of downlink data and the reception of uplink data. In this way, the data received from the upper layer by the ORAN interface, as well as the data that needs to be uploaded to the upper layer by the ORAN interface, need to be transmitted between the master chip and several slave chips.

[0005] Because the Aurora64B / 66B requires periodic clock compensation, data transmission is discontinuous. This means that the Aurora64B / 66B's receive and transmit clocks are mismatched with the actual parallel clock rate of data transmission. Therefore, data buffering is necessary. When the data line rate is high and there are many data links, data buffering consumes a large amount of BRAM (Block RAM) resources. Consequently, existing master-slave transmission schemes have high data overhead and are unsuitable for high-speed data transmission.

[0006] To balance data overhead, speed, and link performance, there is an urgent need to propose a simple and lightweight data transmission method between FPGA chips. This method can enable continuous data transmission when multiple FPGAs are interconnected, improving data transmission efficiency and reliability. It also addresses the problem that existing technologies are unsuitable for high-speed data transmission due to high data overhead. Summary of the Invention

[0007] In view of this, embodiments of the present invention provide a method, apparatus, system, and storage medium for data transmission between FPGA chips. The technical solution provided by the present invention establishes a data link between a master FPGA chip and a slave FPGA chip, and then the master and slave FPGA chips transmit data based on this data link. Since this data link only transmits data information and not control information, the data transmission efficiency is improved. Furthermore, by crossing the user data from the user clock domain to the transmission clock domain when sending data, and then crossing the received data from the transmission clock domain to the user clock domain when receiving data, the data remains in the user clock domain before and after transmission, eliminating the need for additional processing, reducing data overhead, and thus achieving continuous data transmission, further improving the data transmission rate. In the case of multiple data links, by setting a synchronization buffer at the sending or receiving end, the data of each data link can be aligned, thereby improving data reliability and solving the problem that the existing technology is unsuitable for high-speed data transmission due to large data overhead. Testing showed no bit errors during long-term operation at room temperature, and very low bit error rates during long-term operation at both high and low temperatures.

[0008] In a first aspect, embodiments of the present invention provide a data transmission method, the method comprising:

[0009] The master FPGA chip and the slave FPGA chip perform initialization operations; wherein, the master FPGA chip and the slave FPGA chip are interconnected through a high-speed serial interface;

[0010] The master FPGA chip determines whether both the slave FPGA chip and the master FPGA chip have completed the initialization operation;

[0011] After both the master FPGA chip and the slave FPGA chip have completed the initialization operation, the master FPGA chip and the slave FPGA chip establish a data link based on at least one pair of high-speed serial interfaces defined by the preset handshake signal.

[0012] After a data link is successfully established, the master FPGA chip and the slave FPGA chip transmit data based on the data link.

[0013] Preferably, the master FPGA chip and the slave FPGA chip include a high-speed serial transceiver module, and the initialization operation specifically includes:

[0014] Reset the clock module in the high-speed serial transceiver module;

[0015] Determine whether the clock module is locked, and if the clock module is locked, reset the data transmission module and / or data reception module in the high-speed serial transceiver module.

[0016] Preferably, the method for determining whether both the master FPGA chip and the slave FPGA chip have completed initialization operations is as follows:

[0017] When the main FPGA chip performs initialization operations, it sends a main chip initialization start indication signal to the slave FPGA chip.

[0018] When the slave FPGA chip receives the master chip initialization start indication signal, it determines whether the local initialization operation has been completed. If the initialization operation has been completed, it replies to the master FPGA chip with a slave chip initialization complete indication signal.

[0019] When the master FPGA chip receives the slave chip initialization completion indication signal, it determines whether the initialization operation has been completed locally. If the initialization operation has been completed, it sends the master chip initialization completion indication signal to the slave FPGA chip.

[0020] When the FPGA chip receives the main chip initialization completion indication signal, it replies to the main FPGA chip to confirm receipt of the main chip initialization completion indication signal.

[0021] When the main FPGA chip receives the confirmation signal indicating that the master chip initialization is complete, it determines that both the main FPGA chip and the slave FPGA chip have completed the initialization operation.

[0022] Preferably, the step of establishing a data link between the master FPGA chip and the slave FPGA chip based on at least one pair of high-speed serial interfaces defined by the preset handshake signal specifically includes:

[0023] The master FPGA chip and the slave FPGA chip perform a handshake according to a preset handshake step. When the number of consecutive successful handshakes reaches a preset number, the master FPGA chip and the slave FPGA chip successfully establish a data link between the preset high-speed serial interface for handshake signal transmission. When the data link is successfully established, the master FPGA chip sends a data link establishment success indication signal to the slave FPGA chip.

[0024] The preset handshake signal includes a preset first handshake signal and a preset second handshake signal, and the handshake steps are as follows:

[0025] The master FPGA chip sends the preset first handshake signal to the slave FPGA chip;

[0026] When the FPGA chip receives the preset first handshake signal, it replies with the preset second handshake signal to the main FPGA chip.

[0027] When the main FPGA chip receives the preset second handshake signal sent by the slave FPGA chip, a handshake is successfully completed.

[0028] Preferably, when the master FPGA chip and the slave FPGA chip establish multiple data links based on multiple pairs of high-speed serial interfaces defined by the preset handshake signal, the method further includes:

[0029] When the main FPGA chip or the slave FPGA chip receives a preset handshake signal sent by the other party, the moment when the preset handshake signal is received in each data link is recorded.

[0030] The link delay of each data link is determined based on the time when the preset handshake signal is received in each data link;

[0031] Configure the receiver synchronization buffer for each data link using the link delay of each data link, or send the link delay of each data link to the other party so that the other party can configure the sender synchronization buffer for the corresponding data link.

[0032] Preferably, the master FPGA chip and the slave FPGA chip include high-speed serial transceiver IP cores, and the master FPGA chip and the slave FPGA chip transmit data based on the data link, specifically including:

[0033] When the master FPGA chip or the slave FPGA chip sends user data to the other party based on the data link, the following operations are performed:

[0034] User data is processed across clock cycles to obtain the first processed data;

[0035] Add a data synchronization header to the first processed data to obtain the second processed data;

[0036] The data in the second processed data, excluding the data synchronization header, is scrambled to obtain the third processed data; wherein the third processed data includes the data synchronization header and the data after scrambling.

[0037] The third processed data is sent to the high-speed serial transceiver IP core, which processes it and then sends it to the other party.

[0038] When the main FPGA chip or the slave FPGA chip receives data sent from the other party via the data link, the following operations are performed:

[0039] The received data is obtained through the high-speed serial transceiver IP core;

[0040] The received data is descrambled.

[0041] Determine if multiple data links exist. If they do, cache the descrambled received data in the current data link's receiver synchronization buffer, and then read the descrambled received data from the current data link's receiver synchronization buffer to synchronize the data of each data link.

[0042] The descrambled received data is then processed across clock cycles.

[0043] Preferably, the master FPGA chip and the slave FPGA chip include high-speed serial transceiver IP cores, and the master FPGA chip and the slave FPGA chip transmit data based on the data link, specifically including:

[0044] When the master FPGA chip or the slave FPGA chip sends user data to the other party based on the data link, the following operations are performed:

[0045] User data is processed across clock cycles to obtain the first processed data;

[0046] Determine whether multiple data links exist. If they do, cache the first processed data in the current data link's sender synchronization buffer, and then read the first processed data from the current data link's sender synchronization buffer to synchronize the data of each data link.

[0047] Add a data synchronization header to the first processed data to obtain the second processed data;

[0048] The data in the second processed data, excluding the data synchronization header, is scrambled to obtain the third processed data; wherein the third processed data includes the data synchronization header and the data after scrambling.

[0049] The third processed data is sent to the high-speed serial transceiver IP core, which processes it and then sends it to the other party.

[0050] When the main FPGA chip or the slave FPGA chip receives data sent from the other party via the data link, the following operations are performed:

[0051] The received data is obtained through the high-speed serial transceiver IP core;

[0052] The received data is descrambled.

[0053] The descrambled received data is then processed across clock cycles.

[0054] Preferably, wherein,

[0055] The cross-clock processing of user data specifically includes:

[0056] The user data is transferred from the user clock to the transmission clock;

[0057] The cross-clock processing of the descrambled received data specifically includes:

[0058] The descrambled received data is transferred from the transmission clock to the user clock.

[0059] Secondly, embodiments of the present invention provide an inter-FPGA chip data transmission device, the device comprising:

[0060] An initialization module is configured to perform initialization operations on the master FPGA chip and the slave FPGA chip; wherein the master FPGA chip and the slave FPGA chip are interconnected via a high-speed serial interface;

[0061] The initialization completion judgment module is configured to determine whether both the master FPGA chip and the slave FPGA chip have completed the initialization operation.

[0062] The link establishment module is configured to establish a data link between the main FPGA chip and the slave FPGA chip based on at least one pair of high-speed serial interfaces defined by the preset handshake signal after both the main FPGA chip and the slave FPGA chip have completed the initialization operation.

[0063] The data transmission module is configured to transmit data between the main FPGA chip and the slave FPGA chip based on the data link after a data link is successfully established.

[0064] Thirdly, embodiments of the present invention provide a data transmission system, including: a master FPGA chip and one or more slave FPGA chips, wherein the master FPGA chip and the slave FPGA chips are interconnected via a high-speed serial interface;

[0065] The main FPGA chip is configured to perform an initialization operation and determine whether both the main FPGA chip and the slave FPGA chip have completed the initialization operation. After both the main FPGA chip and the slave FPGA chip have completed the initialization operation, the main FPGA chip establishes a data link with the slave FPGA chip based on at least one pair of high-speed serial interfaces defined by the preset handshake signal according to the preset handshake signal. After the data link is successfully established, the main FPGA chip transmits data with the slave FPGA chip based on the data link.

[0066] The slave FPGA chip is configured to perform an initialization operation. After both the slave and master FPGA chips complete the initialization operation, the slave chip establishes a data link with the master FPGA chip based on at least one pair of high-speed serial interfaces defined by the preset handshake signal. After successfully establishing the data link, the slave chip transmits data with the master FPGA chip based on the data link.

[0067] Fourthly, embodiments of the present invention provide a storage medium for storing a computer program for implementing the method described in the first aspect. Attached Figure Description

[0068] The above and other objects, features and advantages of the present invention will become clearer from the following description of embodiments of the invention with reference to the accompanying drawings, in which:

[0069] Figure 1 This is a flowchart of an FPGA chip-to-chip data transmission method according to an embodiment of the present invention;

[0070] Figure 2 This is a flowchart illustrating how the master FPGA chip determines whether both the slave FPGA chip and the master FPGA chip have completed the initialization operation, according to an embodiment of the present invention.

[0071] Figure 3 This is a handshake flowchart of the main FPGA chip and the slave FPGA chip establishing a data link based on a high-speed serial interface in an embodiment of the present invention.

[0072] Figure 4 This is a flowchart of the data transmission processing of the user data sending end when multi-data link data synchronization processing is performed at the data receiving end according to an embodiment of the present invention;

[0073] Figure 5This is a flowchart of the data receiving end's transmission processing of received data when multi-data link data synchronization processing is performed on the data receiving end according to an embodiment of the present invention;

[0074] Figure 6 This is a flowchart of the data transmission processing of the user data sending end when multi-data link data synchronization processing is performed on the data sending end according to an embodiment of the present invention;

[0075] Figure 7 This is a flowchart of the data receiving end's transmission processing of received data when multi-data link data synchronization processing is performed at the data sender according to an embodiment of the present invention.

[0076] Figure 8 This is a schematic diagram of the structure of a data transmission device according to an embodiment of the present invention;

[0077] Figure 9 This is a schematic diagram of the data transmission module structure in an embodiment of the present invention when there is a single data link between the master FPGA chip and the slave FPGA chip;

[0078] Figure 10 This is a schematic diagram of the data transmission module structure in an embodiment of the present invention when there are multiple data links between the master FPGA chip and the slave FPGA chip, and the data synchronization processing of the multiple data links is performed on the data sender.

[0079] Figure 11 This is a schematic diagram of the data transmission module structure in an embodiment of the present invention when there are multiple data links between the master FPGA chip and the slave FPGA chip and the data synchronization processing of the multiple data links is performed on the data receiver.

[0080] Figure 12 This is a schematic diagram of the data transmission system (O-RU) structure of a specific exemplary embodiment of the present invention. Detailed Implementation

[0081] The present invention is described below based on embodiments, but the invention is not limited to these embodiments. In the detailed description of the invention below, certain specific details are described in detail. Those skilled in the art will fully understand the invention even without these details. To avoid obscuring the essence of the invention, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0082] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0083] Furthermore, it should be understood that in the following description, "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by electrical or electromagnetic connections. When an element or circuit is said to be "connected" to another element or "connected" between two nodes, it can be directly coupled or connected to another element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected" to another element, it means that there are no intermediate elements between them.

[0084] Unless the context explicitly requires it, words such as "including" or "contains" in the instruction manual should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0085] In the description of this invention, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0086] The hardware design architecture of this invention is based on a Xilinx FPGA system, which comprises multiple FPGAs, one of which acts as the master chip, and the remaining one or more FPGAs as slave chips. Taking this Xilinx FPGA system used for O-RU as an example, the master chip primarily implements the functions of the ETH MAC and ORAN interfaces, responsible for distributing downlink data to slave chips and transmitting it out, as well as receiving uplink data from slave chips, aggregating it, and uploading it to the upper layer. Each FPGA employs a high-speed serial transceiver IP core to achieve high-speed serial communication between the master and slave chips.

[0087] It should be noted that the technical solution of this invention runs the same set of program code on both the master and slave chips. That is, a single FPGA contains both the functions executed by the master chip and the functions executed by the slave chip. For each FPGA, master and slave are simply functional modes. Each FPGA can be configured as either master or slave mode. When an FPGA is configured as master mode, it runs in master mode and executes the functions of the master chip; when an FPGA is configured as slave mode, it runs in slave mode and executes the functions of the slave chip.

[0088] Figure 1 This is a flowchart of an FPGA chip-to-chip data transmission method according to an embodiment of the present invention. Specifically, as follows... Figure 1 As shown, the method includes the following steps:

[0089] Step S110: The master FPGA chip and the slave FPGA chip perform initialization operations; wherein, the master FPGA chip and the slave FPGA chip are interconnected through a high-speed serial interface.

[0090] Xilinx integrates one or more high-speed serial transceiver modules, called SERDES (Multi-Gigabit Serializer / Deserializer), into many of its FPGAs, including Artix7, Kintex7, and Virtex7, to enable high-speed serial communication between the FPGA and external systems. The "initialization operation" involved in this step mainly refers to the reset operation performed on the high-speed serial transceiver module within the FPGA chip. This high-speed serial transceiver module includes a clock module, a data transmission module, and a data reception module. The initialization operation specifically includes: resetting the clock module within the high-speed serial transceiver module; determining whether the clock module is locked; and resetting the data transmission module and / or data reception module if the clock module is locked.

[0091] In practical applications, which part of these modules is reset depends on the system requirements. In a specific example, according to the SERDES reset requirements, the SERDES QPLL (Quadrature Phase Locked Loop) is first reset. Then, it is determined whether the QPLL is locked. If the QPLL is locked, the TX DATAPATH (transmit data link) in the SERDES data transmission module and / or the RX DATAPATH (receive data link) in the data reception module are reset.

[0092] Additionally, by providing reset interaction data to the FPGA's PS (Processing System), the PS can promptly reset the corresponding parts of the high-speed serial interface when needed (e.g., in case of data link failure). The provided reset interaction data includes the following four elements:

[0093] 1. QPLL reset, used to reset the QPLL of SERDES;

[0094] 2. GTRESET is used to reset the TX DATAPATH (transmit data path) and RX DATAPATH (receive data path) of SERDES.

[0095] 3. GTTXRESET is used to reset the TX DATAPATH (transmit data path) of SERDES;

[0096] 4. GTRXREST is used to reset the RX DATAPATH (receive data link) of SERDES.

[0097] In addition, the "initialization" involved in this step can be during the FPGA power-on or reset process, when the data link is abnormal, when the user instructs the FPGA to perform initialization via the host computer, or other scenarios that require initialization.

[0098] It should be noted that, in addition to the SERDES initialization mentioned above, the initialization operations involved in this step also include other routine initializations performed by the FPGA after power-on.

[0099] Step S120: The main FPGA chip determines whether both the main FPGA chip and the slave FPGA chip have completed the initialization operation.

[0100] When establishing a data link between the master FPGA chip and the slave FPGA chip, the master FPGA chip takes the lead. Before establishing the data link, both chips need to complete initialization operations. Specifically, as follows... Figure 2 As shown, the main FPGA chip determines whether both the main and slave FPGA chips have completed the initialization operation through the following steps:

[0101] Step S121: When the main FPGA chip performs initialization operation, it sends a main chip initialization start indication signal to the slave FPGA chip.

[0102] Step S122: After the slave FPGA chip receives the master chip initialization start indication signal, it determines whether the local initialization operation has been completed. If the initialization operation has been completed, it replies to the master FPGA chip with a slave chip initialization completion indication signal.

[0103] Step S123: When the master FPGA chip receives the slave chip initialization completion indication signal, it determines whether the initialization operation has been completed locally. If the initialization operation has been completed, it sends the master chip initialization completion indication signal to the slave FPGA chip.

[0104] Step S124: After receiving the main chip initialization completion indication signal from the FPGA chip, the chip sends a confirmation message to the main FPGA chip confirming receipt of the main chip initialization completion indication signal.

[0105] Step S125: When the main FPGA chip receives the confirmation signal indicating that the main chip initialization is complete, it is determined that both the main FPGA chip and the slave FPGA chip have completed the initialization operation.

[0106] The signals transmitted between the master FPGA chip and the slave FPGA chip in steps S121-125 above consist of two parts: a synchronization header and the information content. The information content is fixed at 8 bytes; if it is less than 8 bytes, it is padded with 0s at the high bits. The specific information content can be customized according to system needs; they can be different from each other, or the signals sent by the master FPGA and / or the signals sent by the slave FPGA can be defined to be the same. The synchronization header is fixed at "10", indicating that the following information content is control information. By transmitting the above signals between the master FPGA chip and the slave FPGA chip through the high-speed serial interface, the master FPGA chip can clearly know that both sides have completed initialization, thereby determining the timing of link establishment.

[0107] In a specific example, the master FPGA chip in this invention sends a master chip initialization start indication signal and a master chip initialization completion indication signal respectively in steps S121 and S123, both of which are "1000bcbc78", where the first two "10"s are the synchronization header and "00bcbc78" is the information content; the slave FPGA chip sends a slave chip initialization completion indication signal and a confirmation of receipt of the master chip initialization completion indication signal respectively in steps S122 and S124, both of which are "1000000078", where the first two "10"s are the synchronization header and "00000078" is the information content.

[0108] If, through step S120, it is determined that both the master FPGA chip and the slave FPGA chip have completed the initialization operation, then step S130 is executed; otherwise, if neither has completed the initialization operation or one of them has not completed it, then step S110 is executed.

[0109] Step S130: After both the master FPGA chip and the slave FPGA chip have completed the initialization operation, the master FPGA chip and the slave FPGA chip establish a data link based on at least one pair of high-speed serial interfaces defined by the preset handshake signal.

[0110] Xilinx FPGAs designed for Gigabit applications typically integrate high-speed serial interfaces, collectively referred to as Gigabit Transceivers (GTx). These GTxes, arranged in ascending order of transmission rate, include: GTP, GTR, GTX, GTH, GTZ, and GTY. Different FPGA series integrate different GTxes. In a specific example, this invention selects an FPGA with a higher integrated transmission rate, either GTY or GTH. The master FPGA chip and slave FPGA chip are connected via GTY or GTH to achieve a higher transmission rate.

[0111] The "establishing a data link" step in this section refers to establishing a data link between each pair of transceiver interfaces in the master FPGA chip and the slave FPGA chip. This data link is dedicated to transmitting data information between the master and slave FPGA chips. Taking Xilinx Kintex7 / Virttex7 as an example, each GTX / GTH contains one clock module, four data transmission modules, and four data reception modules, which means it contains four pairs of transceiver interfaces. If both the master and slave FPGA chips are Xilinx Kintex7 / Virttex7, a maximum of four data links can be established between them, that is, each data link corresponds to one high-speed transceiver GT.

[0112] Specifically, based on a preset handshake signal, the master FPGA chip and the slave FPGA chip establish a data link using at least one pair of high-speed serial interfaces defined by the preset handshake signal, specifically including:

[0113] The master FPGA chip and the slave FPGA chip perform a handshake according to a preset handshake procedure. When the number of consecutive successful handshakes reaches a preset number, the master FPGA chip and the slave FPGA chip successfully establish a data link between the preset high-speed serial interface for handshake signal transmission. When the data link is successfully established, the master FPGA chip sends a data link establishment success indication signal to the slave FPGA chip.

[0114] The preset handshake signal includes a preset first handshake signal and a preset second handshake signal, and the handshake steps are as follows:

[0115] The master FPGA chip sends the preset first handshake signal to the slave FPGA chip;

[0116] When the FPGA chip receives the preset first handshake signal, it replies with the preset second handshake signal to the main FPGA chip.

[0117] When the main FPGA chip receives the preset second handshake signal sent by the slave FPGA chip, a handshake is successfully completed.

[0118] The preset number of consecutive successful handshakes and the preset handshake signal sent in each handshake can be set according to system needs. The preset first handshake signal can be the same as or different from the preset second handshake signal. Similar to the signals involved in step S120, the handshake signal in this step S130 also includes a synchronization header and information content. The synchronization header is also "10", and the information content can also be customized. In a specific example, such as... Figure 3As shown, taking the example of three consecutive successful handshakes, each handshake being a different preset handshake signal sent by the main FPGA chip, and the first preset handshake signal being the same as the second preset handshake signal, this step S130 will be explained in detail:

[0119] Step S131: The master FPGA chip sends a first handshake signal to the slave FPGA chip.

[0120] In a specific example, if the master FPGA chip and the slave FPGA chip use Aurora64B / 66B encoding and decoding, the first handshake signal can be defined as "1000bcbc78", where the first two "10"s are the synchronization header.

[0121] Step S132: After receiving the first handshake signal from the FPGA chip, the first handshake signal is sent back to the main FPGA chip.

[0122] Step S133: The main FPGA chip determines whether it has received the first handshake signal sent by the slave FPGA chip. If so, the handshake is successful once, and step S134 is executed.

[0123] Additionally, if, under predetermined conditions, such as within a predetermined time, the main FPGA chip does not receive the first handshake signal sent by the secondary FPGA chip (the reason may be that the secondary FPGA chip did not receive the first handshake signal sent by the main FPGA chip, or that the secondary FPGA chip replied with the first handshake signal but the main FPGA chip did not receive it), then step S131 is re-executed.

[0124] Step S134: The master FPGA chip sends a second handshake signal to the slave FPGA chip.

[0125] In a specific example, if the master FPGA chip and the slave FPGA chip use Aurora64B / 66B encoding and decoding, the second handshake signal can be defined as "100055bc78", where the first two "10"s are the synchronization header.

[0126] Step S135: After receiving the second handshake signal from the FPGA chip, the second handshake signal is sent back to the main FPGA chip.

[0127] Step S136: The main FPGA chip determines whether it has received the second handshake signal sent by the slave FPGA chip. If so, the handshake is successful twice, and step S137 is executed.

[0128] If the main FPGA chip does not receive the second handshake signal sent by the slave FPGA chip, then step S131 is executed again.

[0129] Step S137: The master FPGA chip sends a third handshake signal to the slave FPGA chip.

[0130] In a specific example, if the master FPGA chip and the slave FPGA chip use Aurora64B / 66B encoding and decoding, the third handshake signal can be defined as "1000aabc78", where the first two "10"s are the synchronization header.

[0131] Step S138: After receiving the third handshake signal from the FPGA chip, the third handshake signal is sent back to the main FPGA chip.

[0132] Step S139: The main FPGA chip determines whether it has received the third handshake signal sent by the slave FPGA chip. If so, the handshake is successful after three handshakes and the data link is successfully established.

[0133] If the main FPGA chip does not receive the third handshake signal sent by the slave FPGA chip, then step S131 is executed again.

[0134] Step S13A: When the data link is successfully established, the master FPGA chip sends a data link establishment success indication signal to the slave FPGA chip.

[0135] Furthermore, the inventors of this invention discovered during actual project development that when the master FPGA chip and the slave FPGA chip transmit data between multiple pairs of transceiver interfaces, the receiver does not receive the transmitted data simultaneously when the sender (e.g., the master FPGA chip) transmits data to the receiver (e.g., the slave FPGA chip) through different transceiver interfaces at the same time. To solve this problem, this invention provides a multi-data-link data synchronization scheme. Specifically, when establishing a data link between multiple pairs of transceiver interfaces, the delay of each data link at the receiving end is calculated by sending a handshake signal and utilizing the delay of receiving the handshake signal at the receiving end. This delay is then configured in the synchronization buffer of that data link for reading data, i.e., the data is read after the configured delay, thereby synchronizing the data across multiple data links. Specifically, when the main FPGA chip or the slave FPGA chip receives a preset handshake signal sent by the other party, the time when the preset handshake signal is received in each data link is recorded; the link delay of each data link is determined based on the time when the preset handshake signal is received in each data link; the receiving end synchronization buffer of each data link is configured using the link delay of each data link, or the link delay of each data link is sent to the other party so that the other party can configure the sending end synchronization buffer of the corresponding data link.

[0136] In a specific example, the receiver synchronization buffer or the sender synchronization buffer can be implemented using a small amount of RAM.

[0137] It should be noted that, unlike existing technologies that transmit both data and control information, as well as mixed information, between each pair of transceivers, this invention establishes a dedicated data link between the main FPGA chip and the slave FPGA chip. This improves data transmission stability because the link is established before data transmission and is less prone to disconnection. Furthermore, it increases data transmission efficiency by transmitting only data information.

[0138] Step S140: After successfully establishing a data link, the main FPGA chip and the slave FPGA chip transmit data based on the data link.

[0139] Xilinx provides two Aurora IP cores: Aurora 8B / 10B and Aurora 64B / 66B. Aurora 8B / 10B encoding can balance the DC and has sufficient transitions to recover the clock, but it incurs a 20% bandwidth overhead. Aurora 64B / 66B encoding uses the first two bits to represent the synchronization header, with an overhead of approximately 3%. Compared to Aurora 8B / 10B encoding, Aurora 64B / 66B encoding has lower data overhead, resulting in higher data transmission efficiency.

[0140] In a specific example, the "FPGA chip" (including the master FPGA chip and the slave FPGA chip) involved in this invention uses a high-speed serial transceiver IP core, specifically employing Aurora64B / 66B encoding and decoding. Combined with a high-speed serial interface GTY or GTH, the data line rate can reach over 16Gbps, thereby achieving a higher transmission rate. The FPGA chip may contain one or more high-speed serial transceiver IP cores. The aforementioned high-speed serial transceiver module is contained within a high-speed serial transceiver IP core.

[0141] In this invention, when multiple data links exist, the data synchronization processing of multiple data links can be performed at the data sender or at the data receiver. In specific implementation, either one can be selected.

[0142] Specifically, when multi-data link data synchronization processing is performed at the data receiver, the master FPGA chip and the slave FPGA chip transmit data based on the data link, as described below:

[0143] Before the master or slave FPGA chip transmits the received user data to the high-speed serial transceiver IP core at the other end, it needs to process the user data. Specifically, this involves... Figure 4 As shown, it includes the following steps:

[0144] Step S1410: Perform cross-clock processing on the user data to obtain the first processed data.

[0145] Step S1411: Add a data synchronization header to the first processed data to obtain the second processed data.

[0146] Specifically, the "data synchronization header" here is fixed at "01", indicating that the following information is data information.

[0147] Step S1412: Scramble the data in the second processed data except for the data synchronization header to obtain the third processed data; wherein the third processed data includes the data synchronization header and the data after scrambling.

[0148] In a specific example, the polynomial used for scrambling is G(x) = 1 + x³⁹ + x⁵⁸.

[0149] This step can also be implemented in the following way:

[0150] The system determines whether scrambling is required based on preset scrambling / descrambling configuration values. These "scrambling / descrambling configuration values" are user-defined settings that determine whether scrambling occurs before or within the high-speed serial transceiver IP core, and whether descrambling occurs after or within the high-speed serial transceiver IP core. If scrambling occurs before entering the high-speed serial transceiver IP core, and descrambling occurs after, then the scrambling and descrambling operations within the high-speed serial transceiver IP core must be disabled.

[0151] It should be noted that the data synchronization header does not need to be scrambled. Only the data portion following the data synchronization header is scrambled. After scrambling, the scrambled data is added to the data synchronization header to form the third-processed data.

[0152] Step S1413: Send the third processed data to the high-speed serial transceiver IP core, which processes it and then sends it to the other party.

[0153] Specifically, the high-speed serial transceiver IP core encodes, converts, and equalizes the received data, and then sends it to the other party through a high-speed serial interface.

[0154] It should be noted that the "user data" here is processed in 64-bit units according to steps S141 to S144.

[0155] Similarly, when the main FPGA chip or slave FPGA chip receives data sent from the other party, after it is received by the high-speed serial transceiver IP core, it also needs to process the received data, specifically as follows: Figure 5 As shown, it includes the following steps:

[0156] Step S1420: Receive data is obtained through the high-speed serial transceiver IP core.

[0157] Specifically, in the high-speed serial transceiver IP core, the received data is received through a high-speed serial interface and processed by equalization, serial-to-parallel conversion, decoding, and other methods.

[0158] Step S1421: Descramble the received data.

[0159] Similarly, for this step S1420, it can be done in the same way as step S1412 above, determining whether descrambling is needed based on the preset scrambling / descrambling configuration values. If descrambling is needed, then step S1420 is executed; otherwise, step S1421 is executed directly.

[0160] Step S1422: Determine if there are multiple data links. If so, proceed to step S1423; otherwise, proceed to step S1424.

[0161] Step S1423: Buffer the descrambled received data into the receiver synchronization buffer of the current data link, and then read the descrambled received data from the receiver synchronization buffer of the current data link to synchronize the data of each data link.

[0162] Step S1424: Perform cross-clock processing on the descrambled received data.

[0163] Regarding the "cross-clock processing" involved in step S1424 and step S1410 above, in a specific example, suppose the master FPGA chip sends data to the slave FPGA chip and it receives the data. Because the clock sources used by the sender and receiver are different, there will be clock differences leading to clock mismatch. This may result in data packet loss. For the stability and reliability of the data, in this invention, the master FPGA chip or the slave FPGA chip needs to perform cross-clock processing on the data to be sent to the other party before sending it to the other party. Correspondingly, after the slave FPGA chip or the master FPGA chip receives the data sent by the other party, it also needs to perform cross-clock processing on the data received from the other party.

[0164] Specifically, step S1410 involves performing cross-clock processing on the user data, which includes: transferring the user data from the user clock to the transmission clock.

[0165] The cross-clock processing of the received data or descrambled received data in step S1424 specifically includes: transferring the received data or descrambled received data from the transmission clock to the user clock.

[0166] In a specific example, a low-resource RAM is used to transfer data from the user clock domain to the transmission clock domain, or vice versa. When transferring user data from the user clock domain to the transmission clock domain, the specific operation is as follows: one end uses the user clock to store the user data, and the other end uses the transmission clock to read the user data. Similarly, when transferring received data or descrambled received data from the transmission clock domain to the user clock domain, the specific operation is as follows: one end uses the transmission clock to store the received data or descrambled received data, and the other end uses the user clock to read the received data or descrambled received data. Here, the transmission clock refers to the clock used by the high-speed serial interface to send or receive data. If the high-speed serial interface is GTY, then the transmission clock is the GTY transmission clock.

[0167] Regarding the synchronization operation involved in step S1423, in a specific example, it is assumed that three data links need to be established between the master FPGA chip and the slave FPGA chip (i.e., each side has three pairs of transmit and receive interfaces). The master FPGA chip simultaneously sends handshake signals to the slave FPGA chip through the three transmit interfaces. After the slave FPGA chip receives the handshake signal at the corresponding receive interface, it records the reception time. Assuming that the first data link is received at 2:02:02, the second data link is received at 2:02:04, and the third data link is received at 2:02:01, the final delay determined according to the recorded reception time is: the first data link delay is 2 seconds, the second data link delay is 0 seconds (no delay is needed), and the third data link delay is 3 seconds. The calculated delay is then configured in the corresponding data link's receiver synchronization buffer. When the FPGA chip receives data from the main FPGA chip on the first data link, the data needs to be buffered in the receiving end synchronization buffer of the first data link for a delay of 2 seconds before being read from the receiving end synchronization buffer of the first data link. The same applies to the third data link. In this way, the data of each data link is read at the same time, thereby achieving the technical goal of synchronous reception of data from multiple data links.

[0168] Similarly, the same applies to the main FPGA chip. By receiving the handshake signal sent from the FPGA chip, the delay on each data link is calculated, and the delay of each data link is used to configure the receiving end synchronization buffer of each data link on the main FPGA chip side. Thus, when receiving data from the FPGA chip, it is also buffered before reading, so that the data from multiple data links is received synchronously.

[0169] When multi-data-link data synchronization processing is performed at the data sender, the master FPGA chip and the slave FPGA chip transmit data based on the data link, as described in detail below:

[0170] Before the master or slave FPGA chip transmits the received user data to the high-speed serial transceiver IP core at the other end, it needs to process the user data. Specifically, this involves... Figure 6 As shown, it includes the following steps:

[0171] Step S1430: Perform cross-clock processing on the user data to obtain the first processed data.

[0172] Step S1431: Determine if there are multiple data links. If so, proceed to step S1432; otherwise, proceed to step S1433.

[0173] Step S1432: Cache the first processed data in the sender synchronization buffer of the current data link, and then read the first processed data from the sender synchronization buffer of the current data link to synchronize the data of each data link.

[0174] Step S1433: Add a data synchronization header to the first processed data to obtain the second processed data.

[0175] Step S1434: Scramble the data in the second processed data, excluding the data synchronization header, to obtain the third processed data; wherein the third processed data includes the data synchronization header and the data after scrambling.

[0176] Step S1435: Send the third processed data to the high-speed serial transceiver IP core, which processes it and then sends it to the other party.

[0177] Similarly, when the main FPGA chip or slave FPGA chip receives data sent from the other party, after it is received by the high-speed serial transceiver IP core, it also needs to process the received data, specifically as follows: Figure 7 As shown, it includes the following steps:

[0178] Step S1440: Receive data is obtained through the high-speed serial transceiver IP core.

[0179] Step S1441: Descramble the received data.

[0180] Step S1442: Perform cross-clock processing on the descrambled received data.

[0181] As can be seen from the above steps, this embodiment of the invention establishes a data link between the master FPGA chip and the slave FPGA chip, and then the master FPGA chip and the slave FPGA chip transmit data based on this data link. Since this data link only transmits data information and not control information, the data transmission efficiency is improved. In addition, by crossing the user data from the user clock domain to the transmission clock domain when sending data, and then crossing the received data from the transmission clock domain to the user clock domain when receiving data, the data can be kept in the user clock domain before and after transmission without the need for additional processing, thereby realizing continuous data transmission and further improving the data transmission rate. In the case of multiple data links, by setting a synchronization buffer at the sending end or receiving end, the data of each data link can be aligned, thereby improving the reliability of data and solving the problem that the existing technology is not suitable for high-speed data transmission due to large data overhead.

[0182] Figure 8 This is a schematic diagram of the structure of an inter-FPGA chip data transmission device according to an embodiment of the present invention, which is disposed on an FPGA chip, such as... Figure 8 As shown, the FPGA chip-to-chip data transmission device 8 of this embodiment includes: an initialization module 810, configured to perform initialization operations on the master FPGA chip and the slave FPGA chip; wherein the master FPGA chip and the slave FPGA chip are interconnected through a high-speed serial interface; an initialization completion judgment module 820, configured to determine whether both the master FPGA chip and the slave FPGA chip have completed the initialization operation; a link establishment module 830, configured to establish a data link between the master FPGA chip and the slave FPGA chip based on at least one pair of high-speed serial interfaces defined by a preset handshake signal after both the master FPGA chip and the slave FPGA chip have completed the initialization operation; wherein the master FPGA chip and the slave FPGA chip are interconnected through a high-speed serial interface; and a data transmission module 840, configured to transmit data between the master FPGA chip and the slave FPGA chip based on the data link after the data link is successfully established.

[0183] When there is a single data link between the master FPGA chip and the slave FPGA chip, for the data transmission module 840, specifically as follows: Figure 9 As shown, it includes the following modules:

[0184] The transmitting end cross-clock processing module 8410 is configured to perform cross-clock processing on user data, obtain the first processed data, and send it to the data synchronization header adding module 911.

[0185] The data synchronization header adding module 8411 is configured to add a data synchronization header to the first processed data, obtain the second processed data, and send it to the scrambling module 912.

[0186] The scrambling module 8412 is configured to scramble the data in the second processed data except for the data synchronization header to obtain the third processed data, and send it to the high-speed serial transceiver IP core 913. The third processed data includes the data synchronization header and the data after scrambling.

[0187] The high-speed serial transceiver IP core 8413 is configured to process the third processed data and send it to the other party, and receive received data from the other party.

[0188] The descrambling module 8414 is configured to descramble the received data and send the descrambled received data to the receiving end cross-clock processing module 915.

[0189] The receiving end cross-clock processing module 8415 is configured to perform cross-clock processing on the descrambled received data.

[0190] When there are multiple data links between the master FPGA chip and the slave FPGA chip, and when the multi-data-link data synchronization processing is performed on the data sender, for the data transmission module 840, specifically as follows: Figure 10 As shown, compared to Figure 9 As shown, between the trans-clock processing module 8410 and the data synchronization header addition module 8411, there is an additional transmission synchronization processing module 8420, which is configured to cache the first processed data sent by the trans-clock processing module 8410 to the transmission synchronization buffer of the current data link, and then read the first processed data from the transmission synchronization buffer of the current data link to synchronize the data of each data link.

[0191] When multi-data-link data synchronization processing is performed at the data receiver, for the data transmission module 840, specifically as follows: Figure 11 As shown, compared to Figure 9 As shown, between the descrambling module 8414 and the receiving end cross-clock processing module 8415, there is an additional receiving synchronization processing module 8430, which is configured to buffer the descrambled received data sent by the descrambling module 8414 into the receiving end synchronization buffer of the current data link, and then read the descrambled received data from the receiving end synchronization buffer of the current data link to synchronize the data of each data link.

[0192] This invention also provides an inter-FPGA chip data transmission system, which includes at least one master FPGA chip and one or more slave FPGA chips, wherein the master FPGA chip and the slave FPGA chips are interconnected via a high-speed serial interface.

[0193] The main FPGA chip is configured to perform an initialization operation and determine whether both the main FPGA chip and the slave FPGA chip have completed the initialization operation. After both the main FPGA chip and the slave FPGA chip have completed the initialization operation, the main FPGA chip establishes a data link with the slave FPGA chip based on at least one pair of high-speed serial interfaces defined by the preset handshake signal according to the preset handshake signal. After the data link is successfully established, the main FPGA chip transmits data with the slave FPGA chip based on the data link.

[0194] The slave FPGA chip is configured to perform an initialization operation. After both the slave and master FPGA chips complete the initialization operation, the slave chip establishes a data link with the master FPGA chip based on at least one pair of high-speed serial interfaces defined by the preset handshake signal. After successfully establishing the data link, the slave chip transmits data with the master FPGA chip based on the data link.

[0195] In one specific embodiment, the data transmission system is an ORAN network radio frequency unit (O-RU). Taking the base station radio frequency unit O-RU12, which includes a main FPGA chip 1210, a slave FPGA chip 1220, and a slave FPGA chip 1230, as an example, the specific structural diagram is as follows. Figure 12 As shown, the main FPGA chip 1210 is connected to the O-DU (ORAN Network Distributed Unit) and mainly implements the functions of ETHMAC and ORAN interface. It is responsible for uploading the uplink data received from the antenna by the FPGA chip 1220 and the FPGA chip 1230 to the O-DU, and distributing the downlink data transmitted from the O-DU to the FPGA chips 1220 and 1230. The FPGA chips 1220 and 1230 are connected to the antenna and mainly transmit the downlink data distributed by the main FPGA chip 1210 through the antenna, as well as receive uplink data and upload it to the main FPGA chip 1210.

[0196] This invention provides a storage medium for storing a computer program that implements the FPGA chip data transmission method described in any of the above method embodiments.

[0197] This invention provides a chip for supporting receiving devices (e.g., terminal devices, network devices, etc.) in implementing the functions shown in this invention. Specifically, the chip is used in a chip system, which can be composed of chips or include chips and other discrete components. When the chip implementing the above method is within a receiving device, the chip includes a processing unit. Further, the chip may also include a communication unit. The processing unit may be, for example, a processor. When the chip includes a communication unit, the communication unit may be, for example, an input / output interface, pins, or circuits. The processing unit executes all or part of the actions performed by the various processing modules in this invention, and the communication unit can perform corresponding receiving or transmitting actions. In another specific embodiment, the processing module of the receiving device in this invention can be the processing unit of the chip, and the receiving module or transmitting module of the control device is the communication unit of the chip.

[0198] Those skilled in the art will understand that embodiments of this application can be provided as methods, apparatus (devices), or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product embodied on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0199] This application is described with reference to flowchart illustrations of methods, apparatus (devices), and computer program products according to embodiments of this application. It should be understood that each step in the flowchart can be implemented by computer program instructions.

[0200] These computer program instructions may be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including an instruction means, the implementation process of which is described in the instruction means. Figure 1 The function specified in one or more processes.

[0201] These computer program instructions may also be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing device, produce instructions for implementing processes. Figure 1 A device for a function specified in one or more processes.

[0202] Another embodiment of the present invention relates to a non-volatile storage medium for storing a computer-readable program for use by a computer to execute some or all of the above-described method embodiments.

[0203] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program specifying the relevant hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0204] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. For those skilled in the art, the present invention can be modified and varied in various ways. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for FPGA chip-to-chip data transfer, the method comprising: The method comprises: The master FPGA chip and the slave FPGA chip perform initialization operation; wherein the master FPGA chip and the slave FPGA chip are interconnected through high-speed serial interface; The master FPGA chip judges whether the master FPGA chip and the slave FPGA chip have completed initialization operation; After the master FPGA chip and the slave FPGA chip have completed initialization operation, according to preset handshake signal, the master FPGA chip and the slave FPGA chip establish data link based on at least one pair of high-speed serial interfaces defined by the preset handshake signal, the data link is only used for transmitting data information, the data information is further added with synchronization header for representing information content as data information, and the handshake signal comprises synchronization header for representing information content as control information; After successfully establishing data link, the master FPGA chip and the slave FPGA chip transmit data based on the data link; When the master FPGA chip and the slave FPGA chip establish data link between multiple pairs of high-speed serial interfaces, the delay of each data link at the receiving end is calculated by sending the handshake signal and utilizing the delay of receiving the handshake signal at the receiving end, and the delay is configured to the synchronization buffer reading data end of the data link, so as to synchronize data of multiple data links.

2. The method of claim 1, wherein, The master FPGA chip and the slave FPGA chip comprise high-speed serial transceiver module, and the initialization operation specifically comprises: Resetting the clock module in the high-speed serial transceiver module; Judging whether the clock module is locked, and resetting the data sending module and / or data receiving module in the high-speed serial transceiver module after the clock module is locked. The master FPGA chip and the slave FPGA chip are judged whether the master FPGA chip and the slave FPGA chip have completed initialization operation by the following method:

3. The method of claim 1, wherein, When the master FPGA chip performs initialization operation, the master chip initialization start instruction signal is sent to the slave FPGA chip; After the slave FPGA chip receives the master chip initialization start instruction signal, it is judged whether local initialization operation is completed, if the initialization operation is completed, the slave chip initialization completion instruction signal is returned to the master FPGA chip; After the master FPGA chip receives the slave chip initialization completion instruction signal, it is judged whether local initialization operation is completed, if the initialization operation is completed, the master chip initialization completion instruction signal is sent to the slave FPGA chip; After the slave FPGA chip receives the master chip initialization completion instruction signal, the master FPGA chip is replied to confirm that the master chip initialization completion instruction signal is received; When the master FPGA chip receives the confirmation that the master chip initialization completion instruction signal is received, it is judged that the master FPGA chip and the slave FPGA chip have completed initialization operation. According to the preset handshake signal, the master FPGA chip and the slave FPGA chip establish data link based on at least one pair of high-speed serial interfaces defined by the preset handshake signal, specifically comprising: ​ 4. The method of claim 1, wherein, ​ The master FPGA chip and the slave FPGA chip perform handshake according to a preset handshake procedure, when the number of continuous successful handshakes reaches a preset number, the master FPGA chip and the slave FPGA chip successfully establish a data link between the high-speed serial interfaces of the preset handshake signal transmission, when the data link is successfully established, the master FPGA chip sends a data link establishment success indication signal to the slave FPGA chip; The preset handshake signal includes a preset first handshake signal and a preset second handshake signal, and the handshake procedure is as follows: The master FPGA chip sends the preset first handshake signal to the slave FPGA chip; When the slave FPGA chip receives the preset first handshake signal, it returns the preset second handshake signal to the master FPGA chip; When the master FPGA chip receives the preset second handshake signal sent by the slave FPGA chip, it is successfully handshake once.

5. The method of claim 4, wherein, When the master FPGA chip and the slave FPGA chip establish multiple data links based on multiple pairs of high-speed serial interfaces defined by the preset handshake signal, the method further comprises: When the master FPGA chip or the slave FPGA chip receives the preset handshake signal sent by the other party, record the time when the preset handshake signal is received in each data link; According to the time when the preset handshake signal is received in each data link, determine the link delay of each data link; Use the link delay of each data link to configure the receiving end synchronous buffer of each data link, or send the link delay of each data link to the other party to configure the sending end synchronous buffer of the corresponding data link.

6. The method of claim 5, wherein, The master FPGA chip and the slave FPGA chip include high-speed serial transceiver IP cores, and the master FPGA chip and the slave FPGA chip transmit data based on the data link, specifically including: When the master FPGA chip or the slave FPGA chip sends user data to the other party based on the data link, the following operations are performed: Cross-clock processing is performed on the user data to obtain first processing data; A data synchronization header is added to the first processing data to obtain second processing data; The data in the second processing data except the data synchronization header is scrambled to obtain third processing data; wherein the third processing data includes the data synchronization header and the data after scrambling operation; The third processing data is sent to the high-speed serial transceiver IP core and sent to the other party after processing by the high-speed serial transceiver IP core; When the master FPGA chip or the slave FPGA chip receives data sent from the other party based on the data link, the following operations are performed: The high-speed serial transceiver IP core is used to obtain received data, and the received data is descrambled; If there are multiple data links, the descrambled received data is cached to the receiving end synchronous buffer of the current data link, and the descrambled received data is read from the receiving end synchronous buffer of the current data link to synchronize the data of each data link. ​ The descrambled received data is cross-clock processed.

7. The method of claim 5, wherein, Wherein, The master FPGA chip and the slave FPGA chip include high-speed serial transceiver IP cores, and the master FPGA chip and the slave FPGA chip transmit data based on the data link, specifically including: When the master FPGA chip or the slave FPGA chip sends user data to the other party based on the data link, the following operations are performed: Cross-clock processing is performed on the user data to obtain first processing data; It is judged whether there are multiple data links, if so, the first processing data is cached to the sending end synchronous buffer of the current data link, and the first processing data is read from the sending end synchronous buffer of the current data link to make the data of each data link synchronized; A data synchronization header is added to the first processing data to obtain second processing data; The data in the second processing data except the data synchronization header is scrambled to obtain third processing data; wherein the third processing data includes the data synchronization header and the data after the scrambling operation; The third processing data is sent to the high-speed serial transceiver IP core and sent to the other party after being processed by the high-speed serial transceiver IP core; When the master FPGA chip or the slave FPGA chip receives data sent from the other party based on the data link, the following operations are performed: The received data is obtained through the high-speed serial transceiver IP core; The received data is descrambled; The descrambled received data is cross-clock processed.

8. The method according to claim 6 or 7, characterized in that, Wherein, The cross-clock processing on the user data specifically includes: The user data is crossed from the user clock to the transmission clock; The cross-clock processing on the descrambled received data specifically includes: The descrambled received data is crossed from the transmission clock to the user clock.

9. An FPGA chip-to-chip data transfer apparatus, comprising: The device includes: An initialization module is set to initialize the master FPGA chip and the slave FPGA chip; wherein the master FPGA chip and the slave FPGA chip are interconnected through high-speed serial interfaces; An initialization completion judgment module is set to judge whether the master FPGA chip and the slave FPGA chip have completed the initialization operation; A link establishment module is set to, after the master FPGA chip and the slave FPGA chip have completed the initialization operation, establish a data link based on at least one pair of high-speed serial interfaces defined by a preset handshake signal, the data link is only used for transmitting data information, the data information is further added with a synchronization header for representing the information content as data information, and the handshake signal includes a synchronization header for representing the information content as control information; A data transmission module is set to, after successfully establishing the data link, transmit data based on the data link by the master FPGA chip and the slave FPGA chip; The FPGA chip inter-data transmission device is further configured to, when the master FPGA chip and the slave FPGA chip establish data links between multiple pairs of high-speed serial interfaces, calculate the delay of each data link at the receiving end by using the delay of the receiving end receiving the handshake signal while sending the handshake signal, and configure the delay to a synchronous buffer reading data end of the data link, so as to synchronize the data of multiple data links.

10. A data transmission system, characterized by Comprise: a master FPGA chip and one or more slave FPGA chips, wherein the master FPGA chip and the slave FPGA chips are interconnected through high-speed serial interfaces; The master FPGA chip is configured to perform an initialization operation, and determine whether the slave FPGA chips have all completed the initialization operation. After the slave FPGA chips have all completed the initialization operation, the master FPGA chip establishes a data link with the slave FPGA chips based on at least one pair of high-speed serial interfaces defined by a preset handshake signal, transmits data with the slave FPGA chips based on the data link after successfully establishing the data link, and the data link is only used for transmitting data information. The data information is further added with a synchronization header for representing the information content as data information. The handshake signal comprises a synchronization header for representing the information content as control information. The slave FPGA chip is configured to perform an initialization operation, and after the master FPGA chip and the slave FPGA chips have all completed the initialization operation, the slave FPGA chip establishes a data link with the master FPGA chip based on at least one pair of high-speed serial interfaces defined by a preset handshake signal, and transmits data with the master FPGA chip based on the data link after successfully establishing the data link. When the master FPGA chip and the slave FPGA chip establish data links between multiple pairs of high-speed serial interfaces, the delay of each data link at the receiving end is calculated by using the delay of the receiving end receiving the handshake signal while sending the handshake signal, and the delay is configured to a synchronous buffer reading data end of the data link, so as to synchronize the data of multiple data links.

11. A storage medium, characterized by The storage medium is used to store a computer program, and the computer program is used to implement the method of any one of claims 1-8. The storage medium is used to store a computer program, and the computer program is used to implement the method of any one of claims 1-8.

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