Pixel driving circuit, display panel and control method thereof

Abstract

The application provides a pixel driving circuit, a display panel and a control method, and relates to the technical field of display. The pixel driving circuit comprises a driving sub-circuit, a data storage sub-circuit, a writing sub-circuit, a compensation sub-circuit and a light-emitting control sub-circuit. The data storage sub-circuit is connected with a first node, a data signal end and a first scanning signal end. The writing sub-circuit is connected with the first node, a second node and a second scanning signal end. The driving sub-circuit is connected with the second node, a third node and a fourth node. The compensation sub-circuit is connected with the third node, the fourth node and a third scanning signal end. The light-emitting control sub-circuit is connected with a first voltage end, an enabling signal end, the second node, the third node and a light-emitting device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a pixel driving circuit, a display panel and a control method. BACKGROUND

[0002] The display screen of a wearable device has higher and higher requirements for narrow frame and low power consumption, and therefore a data selection circuit is usually provided in the display screen of the wearable device. However, after the data selection circuit is provided, the writing time of a data signal is significantly shortened. SUMMARY

[0003] Embodiments of the present application provide a pixel driving circuit, a display panel and a control method, and the writing time of a data signal is increased.

[0004] To achieve the above object, embodiments of the present application adopt the following technical solutions:

[0005] In one aspect, a pixel driving circuit is provided, which comprises a driving sub-circuit, a data storage sub-circuit, a writing sub-circuit, a compensation sub-circuit and a light-emitting control sub-circuit. The data storage sub-circuit is connected with a first node, a data signal terminal and a first scanning signal terminal, and is configured to store a data signal of the data signal terminal in the first node in response to a control signal of the first scanning signal terminal in a pre-writing stage. The writing sub-circuit is connected with the first node, a second node and a second scanning signal terminal, and is configured to write a signal of the first node into the second node in response to a control signal of the second scanning signal terminal in a writing stage. The driving sub-circuit is connected with the second node, a third node and a fourth node, and is configured to write a signal of the second node into the third node under the control of a potential of the fourth node. The compensation sub-circuit is connected with the third node, the fourth node and a third scanning signal terminal, and is configured to write a signal of the third node into the fourth node in response to a control signal of the third scanning signal terminal in the writing stage. The light-emitting control sub-circuit is connected with a first voltage terminal, an enable signal terminal, the second node, the third node and a light-emitting device, and is configured to drive the light-emitting device to emit light in cooperation with the driving sub-circuit in response to an enable signal of the enable signal terminal in a light-emitting stage.

[0006] In some embodiments, the data storage sub-circuit comprises a first transistor and a first capacitor. The gate of the first transistor is connected with the first scanning signal terminal, the first pole of the first transistor is connected with the data signal terminal, and the second pole of the first transistor is connected with the first node. The first pole plate of the first capacitor is connected with the first node.

[0007] In some embodiments, a second plate of the first capacitor is connected with the first voltage terminal.

[0008] In some embodiments, further comprising a storage sub-circuit, the storage sub-circuit being connected with the first voltage terminal and the fourth node, the storage sub-circuit being configured to store a signal of the fourth node.

[0009] In some embodiments, the storage sub-circuit comprises a second capacitor, a first plate of the second capacitor being connected with the fourth node, a second plate of the second capacitor being connected with the first voltage terminal.

[0010] In some embodiments, the driving sub-circuit comprises a driving transistor, a first electrode of the driving transistor being connected with the second node, a second electrode of the driving transistor being connected with the third node, a gate of the driving transistor being connected with the fourth node.

[0011] In some embodiments, the writing sub-circuit comprises a second transistor, a first electrode of the second transistor being connected with the first node, a second electrode of the second transistor being connected with the second node, a gate of the second transistor being connected with the second scan signal terminal.

[0012] In some embodiments, the compensation sub-circuit comprises a third transistor, a first electrode of the third transistor being connected with the third node, a second electrode of the third transistor being connected with the fourth node, a gate of the third transistor being connected with the third scan signal terminal.

[0013] In some embodiments, the light-emitting control sub-circuit comprises a fourth transistor and a fifth transistor;

[0014] a first electrode of the fourth transistor being connected with the first voltage terminal, a second electrode of the fourth transistor being connected with the second node, a gate of the fourth transistor being connected with the enable signal terminal; a first electrode of the fifth transistor being connected with the third node, a second electrode of the fifth transistor being connected with an anode of the light-emitting device, a gate of the fifth transistor being connected with the enable signal terminal.

[0015] In some embodiments, further comprising a first reset sub-circuit, the first reset sub-circuit being connected with the fourth node, a first reset signal terminal and a fourth scan signal terminal, the first reset sub-circuit being configured to write a signal of the first reset signal terminal to the fourth node in response to a control signal of the fourth scan signal terminal.

[0016] In some embodiments, the first reset sub-circuit comprises a sixth transistor, a first electrode of the sixth transistor is connected with the first reset signal terminal, a second electrode of the sixth transistor is connected with the fourth node, and a gate of the sixth transistor is connected with the fourth scan signal terminal.

[0017] In some embodiments, a second reset sub-circuit is further included, the second reset sub-circuit is connected with the anode of the light-emitting device, a second reset signal terminal and a fifth scan signal terminal, and the second reset sub-circuit is configured to write a signal of the second reset signal terminal into the light-emitting device in response to a control signal of the fifth scan signal terminal.

[0018] In some embodiments, the second reset sub-circuit comprises a seventh transistor, a first electrode of the seventh transistor is connected with the second reset signal terminal, a second electrode of the seventh transistor is connected with the second electrode of the light-emitting device, and a gate of the seventh transistor is connected with the fifth scan signal terminal.

[0019] In another aspect, a display panel is provided, comprising a substrate, a plurality of pixel driving circuits as claimed in any one of claims 1-13 disposed on the substrate, and a light-emitting device connected with the pixel driving circuits; the plurality of pixel driving circuits comprises a first pixel driving circuit and a second pixel driving circuit, and the display panel further comprises a first terminal, a first data selection circuit, a second data selection circuit, a first data line and a second data line; the first terminal is connected with the first data selection circuit and the second data selection circuit, the first data selection circuit is connected with the first data line, the second data selection circuit is connected with the second data line, the first data line is connected with a data signal terminal of the first pixel driving circuit, and the second data line is connected with a data signal terminal of the second pixel driving circuit.

[0020] In still another aspect, a display panel control method is provided for controlling the display panel, a light-emitting period of the light-emitting device comprises a pre-writing stage, a writing stage and a light-emitting stage, the pre-writing stage comprises a first stage and a second stage, and the method comprises:

[0021] In the first stage, a first data signal is provided to the first terminal, the first data selection circuit is controlled to be open, the second data selection circuit is controlled to be closed, and a control signal is provided to the first scan signal terminal of the first pixel driving circuit so as to write the first data signal into the first node in the first pixel driving circuit;

[0022] In the second stage, a second data signal is provided to the first terminal, the second data selection circuit is controlled to be open, the first data selection circuit is controlled to be closed, and a control signal is provided to the first scan signal terminal of the second pixel driving circuit, so that the second data signal is written into the first node in the second pixel driving circuit;

[0023] In the writing stage, control signals are provided to the second scan signal terminal and the third scan signal terminal respectively, so that the data signal stored in the first node is sequentially written into the second node, the third node and the fourth node;

[0024] In the light emitting stage, an enable signal is provided to the enable signal terminal, so that the light emitting control sub-circuit cooperates with the driving sub-circuit to drive the light emitting device to emit light.

[0025] The pixel driving circuit and the display panel provided by the embodiments of the present application have the first light emitting device connected with the first pixel driving circuit and the second light emitting device connected with the second pixel driving circuit. When the first light emitting device and the second light emitting device are controlled to emit light, the first data selection circuit for writing the data signal into the first pixel driving circuit and the second data selection circuit for writing the data signal into the second pixel driving circuit are open in one frame range, and the writing sub-circuit in the first pixel driving circuit and the writing sub-circuit in the second pixel driving circuit are conductive in another frame range. That is, the opening of the data selection circuit and the conduction of the writing sub-circuit are located in two different frames respectively. In the related art, the opening of the data selection circuit and the conduction of the writing sub-circuit are located in the same frame range, and the opening time of the data selection circuit and the conduction time of the writing sub-circuit are obviously increased. BRIEF DESCRIPTION OF DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0027] Figure 1 A structural schematic diagram of a display device provided by the embodiments of the present application;

[0028] Figure 2 A structural schematic diagram of a display panel provided by the embodiments of the present application;

[0029] Figure 3 A circuit principle diagram of a display panel in the related art;

[0030] Figure 4 A circuit principle diagram of a pixel driving circuit in the related art;

[0031] Figure 5 For Figure 3 And Figure 4 A timing diagram of control signals in

[0032] Figure 6 A circuit schematic of a display panel provided by an embodiment of the present application;

[0033] Figure 7 A structural diagram of a pixel driving circuit provided by an embodiment of the present application;

[0034] Figure 8 For Figure 6 And Figure 7 A timing diagram of control signals in

[0035] Figures 9 to 13 A structural diagram of a pixel driving circuit provided by an embodiment of the present application;

[0036] Figure 14 A flowchart of a display panel control method provided by an embodiment of the present application. DETAILED DESCRIPTION

[0037] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0038] In the embodiments of the present application, the terms “first”, “second”, “third”, “fourth” and the like are used to distinguish the same items or similar items with basically the same functions and effects, only for the purpose of clearly describing the technical solutions in the embodiments of the present application, and cannot be understood as indicating or implying the relative importance of the indicated technical features or implicitly indicating the number of the indicated technical features.

[0039] In the embodiments of the present application, “a plurality of” means two or more, and “at least one” means one or more, unless otherwise explicitly and specifically limited.

[0040] In the embodiments of the present application, the terms “upper”, “lower” and the like indicate the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the indicated devices or elements must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0041] In describing some embodiments, the use of "connection" and variations thereof can be used. For example, the term "connection" can be used in describing some embodiments to indicate that two or more components have direct physical or electrical contact with each other. However, the term "connection" can also refer to two or more components that do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0042] The circuit structure (for example, a pixel driving circuit) provided by the embodiments of the present application can use a thin film transistor (TFT), a metal oxide semiconductor (MOS), or other specific same switching device as a transistor, and the embodiments of the present application are described by taking the thin film transistor as an example.

[0043] In the circuit structure provided by the embodiments of the present application, the first pole of each transistor is one of the source and the drain, and the second pole of each transistor is the other of the source and the drain. Since the source and the drain of the transistor can be symmetrical in structure, the source and the drain can be indistinguishable in structure. For example, in the case of a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; in the case of an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

[0044] In the circuit structure provided by the embodiments of the present application, the nodes such as the first node, the second node, the third node, and the fourth node are not actual components, but are convergence points of related connections in a circuit diagram, that is, these nodes are equivalent nodes formed by the convergence points of the related connections in the circuit diagram.

[0045] The transistors included in the circuit structure provided by the embodiments of the present application can all be N-type transistors, or can all be P-type transistors, or part of them can be N-type transistors and the other part can be P-type transistors. In the present application, "effective level" refers to a level that can turn on the transistor. The P-type transistor can be turned on under the control of a low-level signal, and the N-type transistor can be turned on under the control of a high-level signal.

[0046] The display device provided by the embodiments of the present application can be a mobile phone, a notebook computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), a wearable device, a virtual reality device, or a mobile computing device, and other devices with a display panel, which are not limited in the embodiments of the present application. For convenience of description, the display device is taken as an example of a smart watch.

[0047] Figure 1A structural schematic diagram of a display device is provided in the embodiments of the present application. As shown in Figure 1 The display device can include a body 1000 and a watchband 2000. The body 1000 serves as the main structure of the display device, and is used to realize the main functions of the display device (for example, calling, motion monitoring, health monitoring, etc.). The watchband 2000 is connected to the body 1000, and is used to detachably wear the body 1000 on the wrist of a user. For example, as shown in Figure 1 The display device includes two watchbands 2000, one of which is connected to the upper side of the body 1000, and the other of which is connected to the lower side of the body 1000. When worn, the two watchbands 2000 wrap around the wrist of the user and are connected through a buckle structure (not shown in the figure). It can be understood that the body can also be worn on the wrist of the user in other ways in actual application, and the embodiments of the present application do not limit this.

[0048] The body 1000 is provided with a display panel 100. The display panel 100 can display images, and show information to the user through the display images. For example, the display panel 100 shows the calling state, motion monitoring data, health monitoring data, etc. of the display device to the user through the display images. The images displayed by the display panel 100 can be static images or dynamic images, and the content of the images can be text, pictures, or both text and pictures.

[0049] The display panel 100 can be an electroluminescent display panel or a photoluminescent display panel. In the case where the display panel 100 is an electroluminescent display panel, the electroluminescent display panel can be an organic electroluminescent diode (English: Organic Light-Emitting Diode, abbreviated as: OLED) display panel, a quantum dot electroluminescent diode (English: Quantum Dot Light Emitting Diodes, abbreviated as: QLED) display panel, or an active matrix organic light emitting diode (English: Active-matrix organic light emitting diode, abbreviated as: AMOLED) display panel. The organic light emitting diode display panel has the advantages of self-emission, low driving voltage, high luminous efficiency, fast response speed, and flexible display, and has been widely used in the display field. Therefore, only the OLED display panel is taken as an example for description in the embodiments of the present application.

[0050] Figure 2 A structural diagram of a display panel is provided in the embodiments of the present application. As shown in Figure 2As shown, the display panel 100 includes a substrate 110, a plurality of pixel driving circuits 120 arranged on one side of the substrate 110, and a plurality of light emitting devices 130 arranged on the side of the plurality of pixel driving circuits 120 away from the substrate 110. The pixel driving circuit 120 is connected to the light emitting device 130.

[0051] For example, the substrate 110 can be a flexible substrate or a rigid substrate.

[0052] For example, when the substrate 110 is a flexible substrate, the material of the substrate 110 can be dimethylsiloxane, PI (Polyimide), PET (Polyethylene Terephthalate), or the like, which has high elasticity.

[0053] For example, when the substrate 110 is a rigid substrate, the material of the substrate 110 can be glass or the like.

[0054] In some examples, the plurality of pixel driving circuits 120 and the plurality of light emitting devices 130 can be one-to-one corresponding and connected. In other examples, one pixel driving circuit 120 can be connected to a plurality of light emitting devices 130, or a plurality of pixel driving circuits 120 can be connected to one light emitting device 130. The embodiment of the present application only takes one pixel driving circuit 120 connected to one light emitting device 130 as an example to schematically illustrate the structure of the display panel 100.

[0055] One pixel driving circuit 120 and one light emitting device 130 form one pixel. The display panel 100 is provided with a plurality of pixels, and the plurality of pixels can be arranged in an array to form a plurality of pixel rows and a plurality of pixel columns. Each pixel column is provided with a data line connected to the pixel driving circuit in the pixel column to provide a data signal to the pixel driving circuit in the pixel column.

[0056] In order to reduce the frame and power consumption of the display panel 100, the display panel 100 is further provided with a data selection circuit (Multiplexer, referred to as MUX), and the data line is connected to the driving chip through the data selection circuit. The selection ratio of the data selection circuit can be 1:6, 1:9, 1:12, etc., which is not limited in the embodiment of the present application.

[0057] Figure 3 For the circuit principle diagram of the display panel in the related art, Figure 4 For the circuit principle diagram of the pixel driving circuit in the related art. Figure 3 The box marked with Pixel in the middle represents Figure 4The part of the middle pixel driving circuit except the T0 transistor, Data1, Data2, Data3 represent three data lines, MUX1, MUX2, MUX3 represent three data selection circuits, Source represents the data signal from the driving chip, Cdata_line represents the parasitic capacitance, Gate(n-1), Gate(n), Gate(n+1) represent three gate lines respectively. Among them, Figure 3 and Figure 4 The T0 transistor in Figure 5 is the same transistor. Figure 3 Figure 4 is a timing diagram of the control signals. The area between the two adjacent vertical dotted lines in the figure represents a frame.

[0058] As shown in Figures 3 to 5 , the working process of the display panel in the related art is as follows.

[0059] In the S1 stage:

[0060] MUX1 is opened, and MUX2, MUX3 are closed, and T0 is closed. The data signal output by the driving chip is written into the parasitic capacitance Cdata_line connected with Data1 through Data1;

[0061] MUX2 is opened, and MUX1, MUX3 are closed, and T0 is closed. The data signal output by the driving chip is written into the parasitic capacitance Cdata_line connected with Data2 through Data2;

[0062] MUX3 is opened, and MUX1, MUX2 are closed, and T0 is closed. The data signal output by the driving chip is written into the parasitic capacitance Cdata_line connected with Data3 through Data3.

[0063] At this time, the parasitic capacitance Cdata_line connected with Data1, the parasitic capacitance Cdata_line connected with Data2 and the parasitic capacitance Cdata_line connected with Data3 are all written with the data signal.

[0064] In the S2 stage:

[0065] MUX1, MUX2, MUX3 are all closed, one of the gate signal lines Gate(n) inputs an effective level, so that the three T0 transistors connected with Gate(n) are opened, so that the data signals stored in the three parasitic capacitances Cdata_line are written into the corresponding pixel driving circuits respectively, so as to drive the light emitting device to emit light corresponding to the data signal.

[0066] However, by Figure 5 ​It can be seen that the opening stage (S1 stage) of the three data selection circuits MUX and the opening stage (S2 stage) of the T0 transistor are completed within a frame time range, resulting in a short opening time of the T0 transistor, i.e., a short time for data signal writing and compensation. Moreover, in the case of a certain frame time range, the greater the selection ratio of the data selection circuit (1:6, 1:9, 1:12 in turn), the shorter the opening time of the T0 transistor.

[0067] On the other hand, when the shape of the display panel 100 is a non-rectangular shape such as a circular shape, the lengths of different pixel columns are different, resulting in different capacitance values of the parasitic capacitances Cdata_line formed by different pixel columns. In order to ensure that the capacitance values of the Cdata_line of different pixel columns are the same, it is necessary to perform capacitance compensation on the Cdata_line.

[0068] Therefore, the display panel provided by the embodiments of the present application no longer uses a parasitic capacitance to store a data signal, solves the problem of short data signal writing and compensation time, and does not need to perform capacitance compensation on the parasitic capacitance because the parasitic capacitance is not needed.

[0069] The display panel provided by the embodiments of the present application includes a first terminal, a first data selection circuit, a second data selection circuit, a first data line, and a second data line.

[0070] The driving chip for driving the display panel is provided with a plurality of output ports, each of which can output a data signal. Correspondingly, the display panel includes a plurality of terminals. After the driving chip is bound to the display panel, the plurality of output ports and the plurality of terminals are one-to-one corresponding and electrically connected, so that the display panel receives the data signal of the driving chip through the terminals. The first terminal is one of the plurality of terminals.

[0071] The first terminal is connected with the first data selection circuit and the second data selection circuit, the first data selection circuit is connected with the first data line, and the second data selection circuit is connected with the second data line. The plurality of pixel driving circuits includes a first pixel driving circuit and a second pixel driving circuit, the first data line is connected with a data signal end of the first pixel driving circuit, and the second data line is connected with a data signal end of the second pixel driving circuit.

[0072] Figure 6 A circuit principle diagram of a display panel provided by the embodiments of the present application.

[0073] Exemplarily, as Figure 6As shown, the display panel includes a first pixel driving circuit 120a, a second pixel driving circuit 120b, a third pixel driving circuit 120c, a first data line Data1, a second data line Data2, a third data line Data3, a first data selection circuit MUX1, a second data selection circuit MUX2, and a third data selection circuit MUX3. The first terminal is connected with the first pixel driving circuit 120a through the first data selection circuit MUX1 and the first data line Data1, connected with the second pixel driving circuit 120b through the second data selection circuit MUX2 and the second data line Data2, and connected with the third pixel driving circuit 120c through the third data selection circuit MUX3 and the third data line Data3.

[0074] It should be noted that the above only takes the selection ratio of the data selection circuit as 1:3, and the display panel 100 only includes the first terminal as an example for description. In actual application, the selection ratio of the data selection circuit can be 1:6, 1:9, 1:12, etc., and the display panel can also include a second terminal, a third terminal, and the like.

[0075] Figure 7 A structural diagram of a pixel driving circuit provided by an embodiment of the present application.

[0076] As shown in Figure 7 The pixel driving circuit includes a driving sub-circuit 30, a data storage sub-circuit 10, a writing sub-circuit 20, a compensation sub-circuit 40, and a light-emitting control sub-circuit 50.

[0077] The data storage sub-circuit 10 is connected with the first node N1, a data signal terminal Data, and a first scanning signal terminal Reset. The data storage sub-circuit 10 is configured to, in a pre-writing stage, store a data signal of the data signal terminal Data in the first node N1 in response to a control signal of the first scanning signal terminal Reset.

[0078] The writing sub-circuit 20 is connected with the first node N1, a second node N2, and a second scanning signal terminal G2. The writing sub-circuit 20 is configured to, in a writing stage, write a signal of the first node N1 into the second node N2 in response to a control signal of the second scanning signal terminal G2.

[0079] The driving sub-circuit 30 is connected with the second node N2, a third node N3, and a fourth node N4. The driving sub-circuit 30 is configured to write a signal of the second node N2 into the third node N3 under the control of a potential of the fourth node N4.

[0080] The compensation sub-circuit 40 is connected with the third node N3, the fourth node N4 and the third scan signal terminal G3, and is configured to write the signal of the third node N3 into the fourth node N4 in response to the control signal of the third scan signal terminal G3 in the writing stage.

[0081] The light emitting control sub-circuit 50 is connected with the first voltage terminal VDD, the enable signal terminal EM, the second node N2, the third node N3 and the light emitting device, and is configured to transmit the driving signal to the light emitting device in cooperation with the driving sub-circuit 30 in response to the enable signal of the enable signal terminal EM in the light emitting stage.

[0082] The working process of the pixel driving circuit is as follows.

[0083] In the pre-writing stage, the data storage sub-circuit 10 writes and stores the data signal of the data signal terminal Data in response to the control signal received by the first scan signal terminal Reset.

[0084] In the writing stage, the writing sub-circuit 20 writes the data signal stored in the data storage sub-circuit 10 into the second node N2 in response to the control signal of the second scan signal terminal G2; the data signal becomes the compensation signal after passing through the driving sub-circuit 30, and the compensation signal is transmitted to the fourth node N4 through the compensation sub-circuit 40, that is, the writing of the compensation signal is completed, and the compensation of the threshold voltage of the driving sub-circuit 30 is also achieved.

[0085] In the light emitting stage, the light emitting control sub-circuit 50 transmits the first potential provided by the first voltage terminal VDD to the first electrode of the light emitting device through the second node N2 and the third node N3 in cooperation with the driving sub-circuit 30 in response to the enable signal of the enable signal terminal EM, so as to drive the light emitting device to emit light in cooperation with the second potential provided by the second voltage terminal VSSVSS on the second electrode of the light emitting device.

[0086] It should be noted that, Figure 6 The block region marked with Pixel in the figure represents Figure 7 the part of the pixel driving circuit. Figure 6 In the first pixel driving circuit 120a, the data storage sub-circuit is the first data storage sub-circuit 10a, in the second pixel driving circuit 120b, the data storage sub-circuit is the second data storage sub-circuit 10b, in the third pixel driving circuit 120c, the data storage sub-circuit is the third data storage sub-circuit 10c, and the structures of the three data storage sub-circuits can be the same.

[0087] Furthermore, the control signals received by the Reset terminal of the first scan signal terminal in the first data temporary storage sub-circuit 10a, the second data temporary storage sub-circuit 10b, and the third data temporary storage sub-circuit 10c can be the same or different. For example, as shown... Figure 6 As shown, the first scan signal terminal Reset of the three temporary storage sub-circuits is connected to the Reset(n) line, that is, they receive the same control signal.

[0088] For example, such as Figure 6 As shown, the display panel includes multiple rows and columns of pixel driving circuits. The first pixel driving circuit 120a, the second pixel driving circuit 120b, and the third pixel driving circuit 120c are located in the same row of pixel driving circuits, but in different columns. A data line (Data1, Data2, or Data3) is connected to one column of pixel driving circuits, and a strobe line [Reset(n-1), Reset(n), or Reset(n+1)] is connected to one row of pixel driving circuits.

[0089] For example, the display panel includes a first pixel driving circuit column 120a, a second pixel driving circuit column 120b, and a third pixel driving circuit column 120c. A first data line Data1 is connected to the data signal terminal Data of the data buffer sub-circuit 10 in the first pixel driving circuit column 120a; a second data line Data2 is connected to the data signal terminal Data of the data buffer sub-circuit 10 in the second pixel driving circuit column 120b; and a third data line Data3 is connected to the data signal terminal Data of the data buffer sub-circuit 10 in the third pixel driving circuit column 120c. A first terminal is connected to the first data line Data1 via a first data selection circuit MUX1; a first terminal is connected to the second data line Data2 via a second data selection circuit MUX2; and a first terminal is connected to the third data line Data3 via a third data selection circuit MUX3.

[0090] Figure 8 For about Figure 6 and Figure 7 A timing diagram of control signals in China. Figure 8 The area between two adjacent vertical dashed lines constitutes one frame. For example, as shown... Figures 6 to 8 As shown, the operation of the display panel is as follows.

[0091] Within the first frame:

[0092] MUX1 is opened, MUX2 and MUX3 are closed, and the input of Reset(n) is at an effective level, so that the first scanning signal terminal ResetReset of the first data temporary storage sub-circuit 1010a connected with Reset(n) and Data1 receives an effective level, and thus the data signal received by the first terminal is written into and stored in the first data temporary storage sub-circuit 10a connected with Reset(n) and Data1 through the first data selection circuit MUX1 and the first data line Data1.

[0093] MUX2 is opened, MUX1 and MUX3 are closed, and the input of Reset(n) is at an effective level, so that the first scanning signal terminal ResetReset of the second data temporary storage sub-circuit 1010b connected with Reset(n) and Data2 receives an effective level, and thus the data signal received by the first terminal is written into and stored in the second data temporary storage sub-circuit 10b connected with Reset(n) and Data2 through the second data selection circuit MUX2 and the second data line Data2.

[0094] MUX3 is opened, MUX1 and MUX2 are closed, and the input of Reset(n) is at an effective level, so that the first scanning signal terminal ResetReset of the third data temporary storage sub-circuit 10c connected with Reset(n) and Data3 receives an effective level, and thus the data signal received by the first terminal is written into and stored in the third data temporary storage sub-circuit 10c connected with Reset(n) and Data3 through the third data selection circuit MUX3 and the third data line Data3.

[0095] At this time, the data signal is stored in the first data temporary storage sub-circuit 10a, the second data temporary storage sub-circuit 10b and the third data temporary storage sub-circuit 10c.

[0096] In the second frame range:

[0097] The input of Reset(n) is at an ineffective level, and the input of Gate(n) is at an effective level, so that the data temporary storage sub-circuit 10 storing the data signal in the first frame range writes the data signal into the second node N2N2 through the write-in sub-circuit 20.

[0098] In the third frame range:

[0099] The data signal of the second node N2 becomes a compensation signal after passing through the drive sub-circuit 30, and the compensation signal is transmitted to the fourth node N4 through the compensation sub-circuit 40, that is, the writing-in of the compensation signal is completed, and the threshold voltage of the drive sub-circuit 30 is also compensated.

[0100] In the fourth frame range:

[0101] The enable signal terminal EM receives a valid level, so that the light emitting control sub-circuit 50 cooperates with the driving sub-circuit 30 to transmit the first potential provided by the first voltage terminal VDD to the first electrode of the light emitting device through the second node N2 and the third node N3 in turn, so as to cooperate with the second potential provided by the second voltage terminal VSS on the second electrode of the light emitting device, and drive the light emitting device to emit light.

[0102] One light emitting period of the light emitting device can include a pre-writing stage, a writing stage and a light emitting stage. Exemplarily, the pre-writing stage can include Figure 8 the first frame, the writing stage can include Figure 8 the second frame and the third frame, and the light emitting stage can include Figure 8 the fourth frame.

[0103] Wherein, the pre-writing stage can be divided into multiple stages according to the number of data selection circuits turned on in the pre-writing stage. For example, if there are two data selection circuits turned on in the pre-writing stage, the pre-writing stage can include a first stage and a second stage; if there are three data selection circuits turned on in the pre-writing stage, the pre-writing stage can include a first stage, a second stage and a third stage, and so on.

[0104] The light emitting device connected with the first pixel driving circuit 120a is a first light emitting device, and the light emitting device connected with the second pixel driving circuit 120b is a second light emitting device. It can be known from Figure 7 and Figure 8 that when the first light emitting device and the second light emitting device are controlled to emit light, the first data selection circuit for writing the data signal for the first pixel driving circuit 120a and the second data selection circuit for writing the data signal for the second pixel driving circuit 120b are turned on in one frame range, and the writing sub-circuit 20 in the first pixel driving circuit 120a and the second pixel driving circuit 120b is turned on in another frame range. That is, the turning on of the data selection circuit and the turning on of the writing sub-circuit 20 are located in two different frames respectively. Compared with the related art, the turning on of the data selection circuit and the turning on of the writing sub-circuit 20 are located in the same frame range, and the turning on time of the data selection circuit and the turning on time of the writing sub-circuit 20 are obviously increased.

[0105] Exemplarily, it can be known from Figure 8 that the sum of the turning on time of the three data selection circuits is close to the time of one frame, and the turning on time of the writing sub-circuit 20 is also close to the time of one frame.

[0106] As shown in Figure 9 , the pixel driving circuit can further include a storage sub-circuit 60, and the storage sub-circuit 60 is connected with the first voltage terminal VDD and the fourth node N4. The storage sub-circuit 60 is configured to store the signal of the fourth node N4.

[0107] The write sub-circuit 20 is turned on under the control of the control signal transmitted by the second scan signal terminal G2, at which time the data signal of the first node N1 is transmitted to the second node N2. The drive sub-circuit 30 is turned on, and the compensation sub-circuit 40 is turned on under the control of the control signal received by the third scan signal terminal G3, so that the signal of the second node N2 is written to the fourth node N4 through the third node N3 and stored in the storage sub-circuit 60.

[0108] As shown in Figure 10 The pixel driving circuit further includes a first reset sub-circuit 70, which is connected with the fourth node N4, a first reset signal terminal V1 and a fourth scan signal terminal G4. The first reset sub-circuit 70 is configured to write the signal of the first reset signal terminal V1 to the fourth node N4 in response to the control signal of the fourth scan signal terminal G4.

[0109] The first reset sub-circuit 70 is turned on under the control of the control signal received from the fourth scan signal terminal G4, and transmits the first reset signal received by the first reset signal terminal V1 to the fourth node N4, so as to reset the fourth node N4. This makes the transistors in the drive sub-circuit 30 fixed in the initial state before the write stage, so as to facilitate the transistors in the drive sub-circuit 30 to be in a stable state during the write stage, and greatly improve the hysteresis effect of the transistors in the drive sub-circuit 30.

[0110] The first reset sub-circuit 70 can be turned on in the pre-write stage. For example, the control signals received by the first scan signal terminal Reset and the fourth scan signal terminal G4 are synchronized, i.e., the data temporary storage sub-circuit 10 and the first reset sub-circuit 70 are turned on at the same time. Of course, the control signals received by the first scan signal terminal Reset and the fourth scan signal terminal G4 can also be asynchronous. For example, the first scan signal terminal Reset receives the Reset signal of the nth pixel row, i.e., Reset(n), and the fourth scan signal terminal G4 receives the Reset signal of the (n-1)th pixel row, i.e., Reset(n-1).

[0111] In some examples, the fourth node N4 can be reset multiple times by the first reset sub-circuit 70, which is more conducive to ensuring the stability of the voltage of the fourth node N4. The number of times of resetting the fourth node N4 is not limited in the embodiments of the present application, and can be 1, 2 or 3.

[0112] As shown in Figure 11 In some embodiments, the pixel driving circuit further includes a second reset sub-circuit 80, which is connected with the anode of the light emitting device, a second reset signal terminal V2 and a fifth scan signal terminal G5. The second reset sub-circuit 80 is configured to write the signal of the second reset signal terminal V2 to the anode of the light emitting device in response to the control signal of the fifth scan signal terminal G5.

[0113] The second reset circuit 80 is turned on under the control of the control signal received from the fifth scan signal terminal G5, and transmits the second reset signal received from the second reset signal terminal V2 to the light-emitting device to reset the anode of the light-emitting device and improve the stability of the light-emitting device.

[0114] The second reset circuit 80 can be turned on during the write phase or during the pre-write phase.

[0115] For example, the control signal received by the fifth scan signal terminal G5 can be synchronized with the control signal received by the second scan signal terminal G2.

[0116] For example, the control signal received by the fifth scan signal terminal G5 can be synchronized with the control signal received by the first scan signal terminal Reset.

[0117] As shown in Figure 12, in some embodiments, the pixel driving circuit may simultaneously include a storage sub-circuit 60, a first reset sub-circuit 70, and a second reset sub-circuit 80.

[0118] like Figure 13 As shown, in some embodiments, the data buffer sub-circuit 10 includes a first transistor T1 and a first capacitor C1. The gate of the first transistor T1 is connected to the first scan signal terminal Reset, the first terminal of the first transistor T1 is connected to the data signal terminal Data, and the second terminal of the first transistor T1 is connected to the first node N1. The first plate of the first capacitor C1 is connected to the first node N1.

[0119] During the pre-write stage, the first transistor T1 is turned on under the control of the control signal received by the first scan signal terminal Reset, so that the data signal of the data signal terminal Data is written into the first node N1 through the first and second terminals of the first transistor T1, and the first capacitor C1 is charged and stored in the capacitor.

[0120] The second plate of the first capacitor C1 can be connected to the first voltage terminal VDD. Of course, the second plate can also be connected to other voltage terminals, as long as the first capacitor C1 can store data signals. When the second plate is connected to the first voltage terminal VDD, there is no need to set up an additional trace to connect to the second plate, which simplifies the structure of the pixel driving circuit.

[0121] The storage sub-circuit 60 includes a second capacitor C2, the first plate of the second capacitor C2 is connected to the fourth node N4, and the second plate of the second capacitor C2 is connected to the first voltage terminal VDD.

[0122] In the data writing stage, the write sub-circuit 20, the drive sub-circuit 30 and the compensation sub-circuit 40 are turned on, charge movement occurs between the first plate of the first capacitor C1 and the first plate of the second capacitor C2, so that the potential of the first plate of the second capacitor C2 rises, when the potential difference between the first plate of the first capacitor C1 and the first plate of the second capacitor C2 is equal to the threshold voltage of the drive transistor TD, the drive transistor TD is turned off, no charge movement occurs between the first capacitor C1 and the second capacitor C2, and the compensation of the threshold voltage is completed.

[0123] The drive sub-circuit 30 includes a drive transistor TD, the first electrode of the drive transistor TD is connected with the second node N2, the second electrode of the drive transistor TD is connected with the third node N3, and the gate electrode of the drive transistor TD is connected with the fourth node N4.

[0124] The write sub-circuit 20 includes a second transistor T2, the first electrode of the second transistor T2 is connected with the first node N1, the second electrode of the second transistor T2 is connected with the second node N2, and the gate electrode of the second transistor T2 is connected with a second scan signal end G2.

[0125] The compensation sub-circuit 40 includes a third transistor T3, the first electrode of the third transistor T3 is connected with the third node N3, the second electrode of the third transistor T3 is connected with the fourth node N4, and the gate electrode of the third transistor T3 is connected with a third scan signal end G3.

[0126] The control signal received by the second scan signal end G2 is synchronized with the control signal received by the third scan signal end G3.

[0127] The light emission control sub-circuit 50 includes a fourth transistor T4 and a fifth transistor T5. The first electrode of the fourth transistor T4 is connected with a first voltage end VDD, the second electrode of the fourth transistor T4 is connected with the second node N2, and the gate electrode of the fourth transistor T4 is connected with an enable signal end EM. The first electrode of the fifth transistor T5 is connected with the third node N3, the second electrode of the fifth transistor T5 is connected with the anode of the light emitting device 130, and the gate electrode of the fifth transistor T5 is connected with the enable signal end EM.

[0128] The first reset sub-circuit 70 includes a sixth transistor T6, the first electrode of the sixth transistor T6 is connected with a first reset signal end V1, the second electrode of the sixth transistor T6 is connected with the fourth node N4, and the gate electrode of the sixth transistor T6 is connected with a fourth scan signal end G4.

[0129] The second reset sub-circuit 80 includes a seventh transistor T7, the first electrode of the seventh transistor T7 is connected with a second reset signal end V2, the second electrode of the seventh transistor T7 is connected with the second electrode of the light emitting device 130, and the gate electrode of the seventh transistor T7 is connected with a fifth scan signal end G5.

[0130] One light emitting period of the light emitting device 130 can include a pre-writing stage, a writing stage and a light emitting stage. The pre-writing stage can include Figure 8 the first frame, the writing stage can include Figure 8 the second frame and the third frame, and the light emitting stage can include Figure 8 the fourth frame.

[0131] Figure 14 A flow chart of a display panel control method provided by an embodiment of the present application is shown in FIG. 2. The display panel control method includes the following steps. Figure 14

[0132] In step S100, in a first stage, a first data signal is provided to a first terminal, a first data selection circuit is controlled to be open, a second data selection circuit is controlled to be closed, and a control signal is provided to a first scanning signal terminal of a first pixel driving circuit, so that the first data signal is written into a first node in the first pixel driving circuit.

[0133] The first data selection circuit is open, so that the first data signal received by the first terminal is transmitted to the first data line, and the second data selection circuit is closed, so that no signal is transmitted to the second data line. After the control signal is provided to the first scanning signal terminal of the first pixel driving circuit, a data temporary storage sub-circuit in the first pixel driving circuit is turned on, so that the first data signal in the first data line is written into the first node in the first pixel driving circuit.

[0134] In step S200, in a second stage, a second data signal is provided to the first terminal, the second data selection circuit is controlled to be open, the first data selection circuit is controlled to be closed, and a control signal is provided to a first scanning signal terminal of a second pixel driving circuit, so that the second data signal is written into a first node in the second pixel driving circuit.

[0135] The second data selection circuit is open, so that the second data signal is transmitted to the first terminal through the second data line, and the first data selection circuit is closed, so that no signal is transmitted to the first data line. After the control signal is provided to the first scanning signal terminal of the second pixel driving circuit, a data temporary storage sub-circuit in the second pixel driving circuit is turned on, so that the second data signal in the second data line is written into the first node in the second pixel driving circuit.

[0136] In step S300, in the writing stage, control signals are provided to the second scanning signal terminal and the third scanning signal terminal respectively, so that the data signal stored in the first node is sequentially written into the second node, the third node and the fourth node.

[0137] ​The providing the control signals to the second scan signal end and the third scan signal end respectively includes: providing the control signals to the second scan signal end and the third scan signal end in the first pixel driving circuit respectively, and providing the control signals to the second scan signal end and the third scan signal end in the second pixel driving circuit respectively. The first pixel driving circuit and the second pixel driving circuit can receive the control signals simultaneously or in sequence, which is not limited in the embodiment of the application.

[0138] For example, the second scan signal end and the third scan signal end of the first pixel driving circuit and the second scan signal end and the third scan signal end of the second pixel driving circuit are connected with the same gate line.

[0139] In the step S400, an enable signal is provided to the enable signal end in the light emitting stage, so that the light emitting control sub-circuit cooperates with the driving sub-circuit to drive the light emitting device to emit light.

[0140] The display panel control method provided in the embodiment of the application includes: providing a first data selection circuit and a second data selection circuit, the first data selection circuit being used for writing a data signal to a first pixel driving circuit, and the second data selection circuit being used for writing a data signal to a second pixel driving circuit; providing a first write sub-circuit and a second write sub-circuit, the first write sub-circuit being used for writing the data signal to the first pixel driving circuit, and the second write sub-circuit being used for writing the data signal to the second pixel driving circuit; and providing a first light emitting device and a second light emitting device, the first light emitting device being connected with the first pixel driving circuit, and the second light emitting device being connected with the second pixel driving circuit. When the first light emitting device and the second light emitting device emit light, the first data selection circuit and the second data selection circuit are turned on in a frame range, and the first write sub-circuit and the second write sub-circuit are turned on in another frame range. That is, the turning on of the data selection circuit and the turning on of the write sub-circuit are located in two different frames respectively. Compared with the related art, the turning on of the data selection circuit and the turning on of the write sub-circuit are located in the same frame range, and the turning on time of the data selection circuit and the turning on time of the write sub-circuit are obviously increased.

[0141] The above merely provides the specific implementation of the application, but the protection scope of the application is not limited to this. Any person skilled in the art can easily think of the changes or replacements within the technical range disclosed in the application, which should be covered in the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.

Claims

1. A pixel driving circuit, characterized by comprising: The driving sub-circuit, the data storage sub-circuit, the writing sub-circuit, the compensation sub-circuit and the light-emitting control sub-circuit are connected with each other. The data storage sub-circuit is connected with the first node, the data signal terminal and the first scanning signal terminal, and is configured to store the data signal of the data signal terminal in the first node in response to the control signal of the first scanning signal terminal in the pre-writing stage. The writing sub-circuit is connected with the first node, the second node and the second scanning signal terminal, and is configured to write the signal of the first node into the second node in response to the control signal of the second scanning signal terminal in the writing stage. The driving sub-circuit is connected with the second node, the third node and the fourth node, and is configured to write the signal of the second node into the third node under the control of the potential of the fourth node. The compensation sub-circuit is connected with the third node, the fourth node and the third scanning signal terminal, and is configured to write the signal of the third node into the fourth node in response to the control signal of the third scanning signal terminal in the writing stage. The light-emitting control sub-circuit is connected with the first voltage terminal, the enabling signal terminal, the second node, the third node and the light-emitting device, and is configured to drive the light-emitting device to emit light in cooperation with the driving sub-circuit in response to the enabling signal of the enabling signal terminal in the light-emitting stage. The data storage sub-circuit comprises a first transistor and a first capacitor. The gate of the first transistor is connected with the first scanning signal terminal, the first pole of the first transistor is connected with the data signal terminal, and the second pole of the first transistor is connected with the first node. The first pole plate of the first capacitor is connected with the first node.

2. The pixel driving circuit according to claim 1, wherein The second pole plate of the first capacitor is connected with the first voltage terminal.

3. The pixel driving circuit of claim 1, wherein, The storage sub-circuit is connected with the first voltage terminal and the fourth node, and is configured to store the signal of the fourth node.

4. The pixel driving circuit of claim 3, wherein, The storage sub-circuit comprises a second capacitor, the first pole plate of the second capacitor is connected with the fourth node, and the second pole plate of the second capacitor is connected with the first voltage terminal.

5. The pixel driving circuit of claim 1, wherein, The driving sub-circuit comprises a driving transistor, the first pole of the driving transistor is connected with the second node, the second pole of the driving transistor is connected with the third node, and the gate of the driving transistor is connected with the fourth node.

6. The pixel driving circuit of claim 1, wherein, The writing sub-circuit comprises a second transistor, the first pole of the second transistor is connected with the first node, the second pole of the second transistor is connected with the second node, and the gate of the second transistor is connected with the second scanning signal terminal.

7. The pixel driving circuit of claim 1, wherein, The compensation sub-circuit comprises a third transistor, the first pole of the third transistor is connected with the third node, the second pole of the third transistor is connected with the fourth node, and the gate of the third transistor is connected with the third scanning signal terminal.

8. The pixel driving circuit of claim 1, wherein, The light-emitting control sub-circuit comprises a fourth transistor and a fifth transistor. The first electrode of the fourth transistor is connected with the first voltage terminal, the second electrode of the fourth transistor is connected with the second node, and the gate electrode of the fourth transistor is connected with the enable signal terminal; The first electrode of the fifth transistor is connected with the third node, the second electrode of the fifth transistor is connected with the anode of the light emitting device, and the gate electrode of the fifth transistor is connected with the enable signal terminal.

9. The pixel driving circuit according to any one of claims 1-8, wherein, The first reset sub-circuit is further connected with the fourth node, a first reset signal terminal and a fourth scan signal terminal, and is configured to write a signal of the first reset signal terminal into the fourth node in response to a control signal of the fourth scan signal terminal.

10. The pixel driving circuit of claim 9, wherein, The first reset sub-circuit comprises a sixth transistor, the first electrode of the sixth transistor is connected with the first reset signal terminal, the second electrode of the sixth transistor is connected with the fourth node, and the gate electrode of the sixth transistor is connected with the fourth scan signal terminal.

11. The pixel driving circuit according to any one of claims 1-8, wherein, The second reset sub-circuit is further connected with the anode of the light emitting device, a second reset signal terminal and a fifth scan signal terminal, and is configured to write a signal of the second reset signal terminal into the light emitting device in response to a control signal of the fifth scan signal terminal.

12. The pixel driving circuit of claim 11, wherein, The second reset sub-circuit comprises a seventh transistor, the first electrode of the seventh transistor is connected with the second reset signal terminal, the second electrode of the seventh transistor is connected with the second electrode of the light emitting device, and the gate electrode of the seventh transistor is connected with the fifth scan signal terminal.

13. A display panel, characterized by The display panel comprises a substrate, a plurality of pixel driving circuits as claimed in any one of claims 1-12 disposed on the substrate, and a light emitting device connected with the pixel driving circuits; the plurality of pixel driving circuits comprises a first pixel driving circuit and a second pixel driving circuit, and the display panel further comprises a first terminal, a first data selection circuit, a second data selection circuit, a first data line and a second data line. The first terminal is connected with the first data selection circuit and the second data selection circuit, the first data selection circuit is connected with the first data line, the second data selection circuit is connected with the second data line, the first data line is connected with a data signal terminal of the first pixel driving circuit, and the second data line is connected with a data signal terminal of the second pixel driving circuit.

14. A display panel control method for controlling the display panel according to claim 13, characterized by, One light emitting period of the light emitting device comprises a pre-writing stage, a writing stage and a light emitting stage, the pre-writing stage comprises a first stage and a second stage, and the method comprises: In the first stage, a first data signal is provided to the first terminal, the first data selection circuit is controlled to be opened, the second data selection circuit is controlled to be closed, a control signal is provided to the first scan signal terminal of the first pixel driving circuit, so that the first data signal is written into the first node in the first pixel driving circuit; In the second stage, a second data signal is provided to the first terminal, the first data selection circuit is controlled to be closed, the second data selection circuit is controlled to be opened, a control signal is provided to the second scan signal terminal of the first pixel driving circuit, so that the second data signal is written into the second node in the first pixel driving circuit; In the second stage, a second data signal is provided to the first terminal, the second data selection circuit is controlled to be open, the first data selection circuit is controlled to be closed, a control signal is provided to the first scanning signal terminal of the second pixel driving circuit, so that the second data signal is written into the first node in the second pixel driving circuit; In the writing stage, control signals are provided to the second scanning signal terminal and the third scanning signal terminal respectively, so that the data signal stored in the first node is sequentially written into the second node, the third node and the fourth node; In the light emitting stage, an enable signal is provided to the enable signal terminal, so that the light emitting control sub-circuit cooperates with the driving sub-circuit to drive the light emitting device to emit light.

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