A bidirectional low-capacitance vertical device for ESD protection

Abstract

The application belongs to the field of electronic science and technology, and particularly relates to a bidirectional low-capacitance vertical device for ESD protection, which comprises an n+ type substrate (01), a p type buried layer (02), a p type epitaxial layer (03), an n type buried layer (04), a first n type epitaxial layer (051), a second n type epitaxial layer (052), a first isolation region (31), a second isolation region (32), a third isolation region (33), a pwell region (06), an N+ contact region (11), a P+ region (21), a first input / output port (41) and a second input / output port (42); the application realizes bidirectional conduction and effectively reduces the parasitic capacitance by introducing the p type buried layer, the p type epitaxial layer, the n type buried layer and the series-connected vertical structure diode.

Description

TECHNICAL FIELD

[0001] The present application belongs to the field of electronic science and technology, and relates to an electro static discharge (ESD) protection technology, in particular to a bidirectional low-capacitance vertical device for ESD protection. BACKGROUND

[0002] Electro static discharge is an ancient natural phenomenon. ESD exists in every corner of people's daily life. However, such a common electrical phenomenon is a fatal threat to precision integrated circuits.

[0003] With the improvement of integrated circuit manufacturing process, the minimum line width has been reduced to the sub-micron or even nanometer level, which brings about the improvement of chip performance, but also greatly reduces the anti-ESD attack capability, thus the electrostatic damage is more serious. Most of the ESD can cause non-fatal damage to integrated circuits, thereby reducing the service life and reliability of the integrated circuits, and further causing the degradation of system functions, which greatly hinders the realization of large-scale high-reliability integration.

[0004] Nowadays, a kind of data transmission interface is also included in the interface of electronic equipment. For this kind of interface, in addition to the basic ESD protection function provided by the ESD protection device used, the device needs to be in a "completely invisible" state when the system is working normally, that is, it cannot interfere with the integrity of the data transmission signal. This puts strict requirements on the parasitic capacitance of the ESD protection device used. Therefore, with the increasing speed of data transmission today, how to make the ESD protection device reduce the capacitance as much as possible while ensuring sufficient ESD protection capability to maintain the signal integrity of the high-speed data interface has become a new and severe challenge. SUMMARY

[0005] In view of the above problems, the present application provides a bidirectional low-capacitance vertical device for ESD protection, which comprises an n+ type substrate 01, a p type buried layer 02, a p type epitaxial layer 03, an n type buried layer 04, a first n type epitaxial layer 051, a second n type epitaxial layer 052, a first isolation region 31, a second isolation region 32, a third isolation region 33, a pwell region 06, an N+ contact region 11, a P+ region 21, a first input / output port 41, and a second input / output port 42, wherein:

[0006] The p type buried layer 02 is formed by implantation on the n+ type substrate 01, and the p type epitaxial layer 03 is formed by epitaxy on the p type buried layer 02;

[0007] Three isolation regions are inserted on the p-type epitaxial layer 03 to form a spacing structure, the spacing structure is formed by two equally spaced spacing regions on the p-type epitaxial layer 03 by the isolation regions, namely a first spacing region and a second spacing region;

[0008] The first n-type epitaxial layer 051 is formed on the p-type epitaxial layer 03 in the first spacing region by epitaxy, and the N+ contact region 11 is formed by surface injection of the first n-type epitaxial layer 051;

[0009] The n-type buried layer 04 is formed by injection on the p-type epitaxial layer 03 in the second spacing region, and the second n-type epitaxial layer 052 is formed on the n-type buried layer 04 by epitaxy, and the pwell region 06 is formed by surface injection of the second n-type epitaxial layer 052, and the P+ region 21 is formed by surface injection of the pwell region 06;

[0010] The N+ contact region 11 and the P+ region 21 are short-circuited by metal on the surface to form a first input / output port 41 of the device, and the lower surface of the n+ substrate serves as a second input / output port 42 of the device.

[0011] Further, the thickness of the p-type epitaxial layer 03 in the first spacing region is greater than the thickness of the p-type epitaxial layer 03 in the second spacing region, and is less than the sum of the thickness of the p-type epitaxial layer 03 in the second spacing region and the thickness of the n-type buried layer 04.

[0012] The application also provides a bidirectional low-capacitance vertical device for ESD protection, which comprises the isolation structure of the bidirectional low-capacitance vertical device for ESD protection in two or more of the preceding claims 1, and a plurality of isolation structures are arranged on the p-type epitaxial layer 03, each isolation structure is spaced apart by a third n-type epitaxial layer 053, the N+ contact region and the P+ region of each isolation structure are short-circuited together by metal on the surface to form a first input / output port 41 of the device, and the lower surface of the n+ substrate serves as a second input / output port 42 of the device.

[0013] Further, the distance between the spacing structures is greater than the distance between the two adjacent isolation regions in the spacing structure and is less than the overall width of the spacing structure.

[0014] The bidirectional vertical NPN device for ESD protection provided by the application realizes bidirectional conduction and effectively reduces the parasitic capacitance by introducing a p-type buried layer, a p-type epitaxial layer, an n-type buried layer and a series-connected vertical structure diode. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A schematic diagram of one of the preferred embodiments of the bidirectional low-capacitance vertical device structure for ESD protection provided by the application;

[0016] Figure 2 A schematic diagram of another preferred embodiment of the bidirectional low-capacitance vertical device structure for ESD protection provided by the application;

[0017] Figure 3 Fig. 3 is a schematic diagram of a third preferred embodiment of a bidirectional low-capacitance vertical device structure for ESD protection according to the present application;

[0018] Figure 4 Fig. 4 is a schematic diagram of a fourth preferred embodiment of a bidirectional low-capacitance vertical device structure for ESD protection according to the present application;

[0019] 01, n+ type substrate;

[0020] 02, first p type buried layer;

[0021] 03, first p type epitaxial layer; 31, first isolation region; 32, second isolation region; 33, third isolation region; 34, fourth isolation region; 35, fifth isolation region; 36, sixth isolation region;

[0022] 04, n type buried layer; 041, first n type buried layer; 042, second n type buried layer; 04n, nth n type buried layer;

[0023] 051, first n type epitaxial layer; 052, second n type epitaxial layer; 053, third n type epitaxial layer; 054, fourth n type epitaxial layer; 055, fifth n type epitaxial layer; 05n, nth n type epitaxial layer;

[0024] 06, pwell region; 061, first pwell region; 062, second pwell region; 06n, nth pwell region;

[0025] 11, first N+ contact region; 12, second N+ contact region; 1n, nth N+ contact region; 21, first P+ region; 22, second P+ region; 2n, nth P+ region;

[0026] 41, first input / output port; 42, second input / output port; 51, p+ type substrate; 61, n type buried layer;

[0027] 71, fourth n type epitaxial layer; 81, second p type buried layer; 91, second p type epitaxial layer; 92, third p type epitaxial layer; 07, nwell region. DETAILED DESCRIPTION

[0028] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0029] The application provides a bidirectional low-capacitance vertical device for ESD protection, which comprises an n+ substrate 01, a p buried layer 02, a p epitaxial layer 03, an n buried layer 04, a first n epitaxial layer 051, a second n epitaxial layer 052, a first isolation region 31, a second isolation region 32, a third isolation region 33, a pwell region 06, an N+ contact region 11, a P+ region 21, a first input / output port 41 and a second input / output port 42, wherein:

[0030] The p buried layer 02 is formed by implantation on the n+ substrate 01, and the p epitaxial layer 03 is formed by epitaxy on the p buried layer 02;

[0031] Three isolation regions are inserted on the p epitaxial layer 03 to form a spacing structure, and the spacing structure is formed by using the isolation regions to form two equally-spaced spacing regions, i.e., a first spacing region and a second spacing region, on the p epitaxial layer 03;

[0032] The first n epitaxial layer 051 is formed by epitaxy on the p epitaxial layer 03 in the first spacing region, and the N+ contact region 11 is formed by implantation on the surface of the first n epitaxial layer 051;

[0033] The n buried layer 04 is formed by implantation on the p epitaxial layer 03 in the second spacing region, the second n epitaxial layer 052 is formed by epitaxy on the n buried layer 04, the pwell region 06 is formed by implantation on the surface of the second n epitaxial layer 052, and the P+ region 21 is formed by implantation on the surface of the pwell region 06;

[0034] The N+ contact region 11 and the P+ region 21 are short-circuited by metal on the surface to form the first input / output port 41 of the device, and the lower surface of the n+ substrate serves as the second input / output port 42 of the device.

[0035] Embodiment 1

[0036] Specifically, in the embodiment, as Figure 1 A bidirectional low-capacitance vertical device for ESD protection is provided, which comprises an n+ substrate 01, a p buried layer 02, a p epitaxial layer 03, an n buried layer 04, a first n epitaxial layer 051, a second n epitaxial layer 052, a first isolation region 31, a second isolation region 32, a third isolation region 33, a pwell region 06, an N+ contact region 11, a P+ region 21, a first input / output port 41 and a second input / output port 42, and the connection relationship among these structures comprises the following:

[0037] The n+ substrate 01;

[0038] The p buried layer 02 is formed by implantation on the n+ substrate 01;

[0039] The p epitaxial layer 03 is formed by epitaxy on the p buried layer 02;

[0040] An n-type epitaxial layer 051 is formed on the p-type epitaxial layer 03, and then three isolation regions are formed through the n-type epitaxial layer 051 from the upper surface to the inside of the p-type epitaxial layer 03 (without penetrating the p-type epitaxial layer 03), so that the p-type epitaxial layer 03 and the part above it are divided into two parts, and the three isolation regions are respectively located at the left end, the center and the right end of the p-type epitaxial layer 03, forming two equally spaced interval regions, i.e. a first interval region and a second interval region.

[0041] Figure 1 The left side of the first interval region is the first interval region, and the first n-type epitaxial layer 051 is formed on the p-type epitaxial layer 03, and the N+ contact region 11 is formed on the surface of the first n-type epitaxial layer 051 by surface injection.

[0042] The n-type buried layer 04 is formed on the p-type epitaxial layer 03 in the second interval region, the second n-type epitaxial layer 052 is formed on the n-type buried layer 04 by epitaxy, and the pwell region 06 is formed on the surface of the second n-type epitaxial layer 052 by surface injection, and the P+ region 21 is formed on the surface of the pwell region 06 by surface injection.

[0043] The N+ contact region 11 and the P+ region 21 are short-circuited by metal on the surface, forming the first input / output port 41 of the device; and the lower surface of the n+ type substrate serves as the second input / output port 42 of the device.

[0044] In this embodiment, the thickness of the p-type epitaxial layer 03 in the first interval region is greater than the thickness of the p-type epitaxial layer 03 in the second interval region, and is less than the sum of the thickness of the p-type epitaxial layer 03 and the thickness of the n-type buried layer 04 in the second interval region.

[0045] Embodiment 2

[0046] Specifically, in this embodiment, as Figure 2 , the embodiment increases the repeating unit on the basis of embodiment 1 to improve the current capacity.

[0047] The definition of the repeating unit is: the corresponding unit composed of the first isolation region 31, the second isolation region 32, the third isolation region 33, the first n-type buried layer 041, the first n-type epitaxial layer 051, the second n-type epitaxial layer 052, the first pwell region 061, the first N+ contact region 11 and the first P+ region 21.

[0048] The structure of the increased unit corresponds to the structure of the original unit: the fourth isolation region 34, the fifth isolation region 35, the sixth isolation region 36, the second n-type buried layer 042, the fourth n-type epitaxial layer 054, the fifth n-type epitaxial layer 055, the second pwell region 061, the second N+ contact region 12 and the second P+ region 22. There is a third n-type epitaxial layer 053 between the two units.

[0049] Furthermore, the first N+ contact region 11, the first P+ region 21, the second N+ contact region 12 and the second P+ region 22 are shorted by metal on the surface, forming a new first input / output port 41.

[0050] Embodiment 3

[0051] Specifically, in this embodiment, as Figure 3 , this embodiment continues to increase the repeating units on the basis of Embodiment 2, forming an array, and such a structure is still based on the idea of the first variant structure shown. Figure 2

[0052] Similarly, on the basis of Embodiment 2, the repeating units are increased, as Figure 3 , if a total of n repeating units are included, the nth repeating unit includes an nth N+ contact region 1n, an nth P+ region 2n, an nth pwell region 06n, an nth n-type epitaxial layer 05n, an nth n-type buried layer 04n, and other regions.

[0053] Embodiment 4

[0054] Specifically, in this embodiment, as Figure 4 , this embodiment replaces the original n-type doping with p-type doping and replaces the original p-type doping with n-type doping on the basis of Embodiment 1, so the original npn is replaced with pnp.

[0055] Specifically, as Figure 4 , the replaced device includes a p+ substrate 51, an n-type buried layer 61, an n-type epitaxial layer 71, a p-type buried layer 81, a first p-type epitaxial layer 91, a second p-type epitaxial layer 92, a first isolation region 31, a second isolation region 32, a third isolation region 33, an nwell region 07, an N+ contact region 11, a P+ region 21; a first input / output port 41, a second input / output port 42; the connection relationship between these structures includes the following:

[0056] The p+ substrate 51;

[0057] The n-type buried layer 61 is formed by implantation on the p+ substrate 51;

[0058] The n-type epitaxial layer 71 is formed by epitaxy on the n-type buried layer 61;

[0059] The first p-type epitaxial layer 91 is formed by epitaxy on the n-type epitaxial layer 71, and then three isolation regions are used to penetrate the first p-type epitaxial layer 91 from the upper surface, until reaching the inside of the n-type epitaxial layer 71 (not penetrating the n-type epitaxial layer 71), the n-type epitaxial layer 71 and the part above it are divided into two parts, and the three isolation regions are located at the leftmost end, the center and the rightmost end of the n-type epitaxial layer 71, forming two equally spaced interval regions, i.e., a first interval region and a second interval region; ​

[0060] Figure 4 The first interval region is formed by epitaxially forming a first p-type epitaxial layer 91 on the n-type epitaxial layer 71, and forming a P+ region 21 by surface implantation of the first p-type epitaxial layer 91;

[0061] The p-type buried layer 81 is formed by implantation on the n-type epitaxial layer 71 of the second interval region, the second p-type epitaxial layer 92 is formed by epitaxy on the p-type buried layer 81, and the nwell region 07 is formed by surface implantation of the second p-type epitaxial layer 92, and the N+ contact region 11 is formed by surface implantation of the nwell region 07;

[0062] The N+ contact region 11 and the P+ region 21 are short-circuited by metal on the surface, forming a first input / output port 41 of the device; and the lower surface of the p+ substrate 51 serves as a second input / output port 42 of the device.

[0063] Similarly, the device with the pnp structure described in the embodiment can include two or more repeated units as in Embodiments 2 and 3, and the same principle applies, so the present application will not be described again.

[0064] The working principle of the device structure of the present application is as follows:

[0065] When the ESD voltage is input from the first input / output port 41, the pn junction between the pwell region 06 and the second n-type epitaxial layer 052 is forward-biased, forming a diode current, and as the input ESD voltage gradually increases, the current gradually increases, and when the current increases to a pressure drop generated by the p-type epitaxial layer 03 and the p-type buried layer 02 sufficient to open the npn composed of the n-type buried layer 04, the p-type epitaxial layer 03, the p-type buried layer 02 and the n+ substrate 01, the current will flow through the npn and be output from the second input / output port 42. Conversely, when the ESD voltage is input from the second input / output port 42, the device will start to work until the ESD voltage increases to the npn composed of the n+ substrate 01, the p-type buried layer 02, the p-type epitaxial layer 03 and the first n-type epitaxial layer 051, and the current will flow through the N+ contact region 11 and be output from the first input / output port 31.

[0066] In the description of the present application, it should be understood that the terms "coaxial", "bottom", "one end", "top", "middle", "the other end", "upper", "one side", "top", "inner", "outer", "front", "central", "both ends" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0067] In the present application, unless otherwise explicitly specified and limited, the terms "mounting", "setting", "connecting", "fixing", "rotating" and other terms should be understood in a broad sense, for example, can be fixedly connected, or can be detachably connected, or can be integrated; can be mechanically connected, or can be electrically connected; can be directly connected, or can be indirectly connected through an intermediate medium, can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise explicitly limited, the above-mentioned terms in the present application can be understood according to the specific meaning of the above-mentioned terms in the present application by the person skilled in the art.

[0068] Although the embodiments of the present application have been shown and described, it can be understood by those skilled in the art that various changes, modifications, replacements and variations can be made to the embodiments without departing from the principles and spirits of the present application, the scope of the present application is defined by the appended claims and their equivalents.

Claims

1. A bidirectional low-capacitance vertical device for ESD protection, characterized in that, The device comprises an n+ substrate (01), a p buried layer (02), a p epitaxial layer (03), an n buried layer (04), a first n epitaxial layer (051), a second n epitaxial layer (052), a first isolation region (31), a second isolation region (32), a third isolation region (33), a pwell region (06), an N+ contact region (11), a P+ region (21), a first input / output port (41), and a second input / output port (42). The p buried layer (02) is formed by implantation on the n+ substrate (01), and the p epitaxial layer (03) is formed by epitaxy on the p buried layer (02). Three isolation regions are inserted on the p epitaxial layer (03) to form a spacing structure, and the spacing structure comprises two equidistant regions, i.e., a first spacing region and a second spacing region, formed by the isolation regions on the p epitaxial layer (03). The first n epitaxial layer (051) is formed by epitaxy on the p epitaxial layer (03) in the first spacing region, and the N+ contact region (11) is formed by implantation on the surface of the first n epitaxial layer (051). The n buried layer (04) is formed by implantation on the p epitaxial layer (03) in the second spacing region, and the second n epitaxial layer (052) is formed by epitaxy on the n buried layer (04). The pwell region (06) is formed by implantation on the surface of the second n epitaxial layer (052), and the P+ region (21) is formed by implantation on the surface of the pwell region (06). The N+ contact region (11) and the P+ region (21) are short-circuited by metal on the surface, thereby forming the first input / output port (41) of the device, and the lower surface of the n+ substrate serves as the second input / output port (42) of the device.

2. A bidirectional low-capacitance vertical device for ESD protection according to claim 1, wherein, The thickness of the p epitaxial layer (03) in the first spacing region is greater than the thickness of the p epitaxial layer (03) in the second spacing region, and is less than the sum of the thickness of the p epitaxial layer (03) in the second spacing region and the thickness of the n buried layer (04).

3. A bidirectional low-capacitance vertical device for ESD protection, characterized in that, The device comprises two or more isolation structures as claimed in claim 1, and a plurality of isolation structures are arranged on the p epitaxial layer (03). Each isolation structure is separated by a third n epitaxial layer (053), and the N+ contact region and the P+ region of each isolation structure are short-circuited by metal on the surface, thereby forming the first input / output port (41) of the device, and the lower surface of the n+ substrate serves as the second input / output port (42) of the device.

4. A bidirectional low-capacitance vertical device for ESD protection according to claim 3, wherein, In each isolation structure, the thickness of the p epitaxial layer (03) in the first spacing region is greater than the thickness of the p epitaxial layer (03) in the second spacing region, and is less than the sum of the thickness of the p epitaxial layer (03) in the second spacing region and the thickness of the n buried layer (04).

5. A bidirectional low-capacitance vertical device for ESD protection according to claim 3, wherein, The distance between the spacing structures is greater than the distance between the two isolation regions in the spacing structure and is less than the overall width of the spacing structure.

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