A method for hindering the growth of dislocations in GaN by covering it with SiO2

Abstract

A method for hindering the growth of dislocations in GaN by covering it with SiO2. Step S1: In the MOCVD reaction chamber, a GaN nucleation layer is prepared on a sapphire substrate. Step S2: Etching. The substrate and GaN are transferred out of the reaction chamber and selectively etched using KOH. Step S3: Deposition of silicon dioxide. The substrate is transferred to the PECVD reaction chamber, and a SiO2 thin film is deposited on the surface of the nucleation layer. Step S4: Etching of silicon dioxide. The SiO2 thin film on the surface is removed by photolithography etching. Step S5: Continuing the growth of gallium nitride. The substrate is transferred into the MOCVD reaction chamber, and the GaN epitaxial growth is continued. The present invention utilizes the principle that the corrosion rates are different at the defective and non-defective parts of the gallium nitride material, and corrosion pits can be formed at the parts with threading dislocations through selective corrosion. Depositing SiO2 on the surface of gallium nitride can hinder the further growth of threading dislocations, and removing the deposited SiO2 by photolithography means can accurately control whether there is SiO2 on the surface of the GaN nucleation layer after photolithography, reducing the threading dislocation density of the subsequently grown GaN.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor microelectronics, and is applied to a non-polar photodiode. Specifically, it is a method for hindering the growth of dislocations in GaN by covering with SiO2. Background Art

[0002] Micro LED display technology refers to a display technology that uses self-luminous micron-scale LEDs as light-emitting pixel units and assembles them onto a driving panel to form a high-density LED array. Due to the characteristics of small size, high integration, and self-luminescence of micro LED chips, it has greater advantages in terms of brightness, resolution, contrast, energy consumption, service life, response speed, and thermal stability compared with LCD and OLED in the field of display.

[0003] Gallium nitride (GaN)-based high electron mobility transistors (HEMTs) have been widely used in the fields of power electronic devices such as high temperature, high frequency, high voltage, and high power due to the advantages of large bandgap width, high breakdown electric field strength, and high carrier saturation mobility of gallium nitride materials.

[0004] Currently, several mainstream technologies for fabricating gallium nitride enhancement devices include gate recess, fluoride ion implantation, and p-type gallium nitride gate, etc. The gate recess technology requires an etching process, and the damage caused by the etching process will lead to an increase in gate leakage and uneven threshold voltage; the use of fluoride ion implantation technology will have problems with poor stability of the threshold voltage under high field and high temperature stress; the p-type gallium nitride gate technology requires an additional growth of a layer of p-type gallium nitride epitaxy. This technology has a high cost. The growth uniformity of p-type gallium nitride and the activation of magnesium (Mg) are the difficulties of this technology. Moreover, it is necessary to etch away the p-type gallium nitride outside the gate region, and this process will also cause etching damage, resulting in poor interface characteristics of the transistor. At the same time, the p-type gallium nitride gate has a low breakdown voltage, usually less than +7V, which increases the difficulty of circuit design.

[0005] Selective-area growth (SAG) technology has been used for the growth of p-type gallium nitride, and enhanced transistors fabricated with this technology have also been reported one after another. This technology mainly uses a metal-organic chemical vapour deposition (MOCVD) system with silicon oxide as a hard mask to selectively grow p-type gallium nitride in the gate region of an aluminum gallium nitride / gallium nitride heterostructure. The advantage of this technology is that it does not require the etching step in the conventional p-type gallium nitride fabrication process for enhanced transistors, avoids etching damage to the aluminum gallium nitride surface, and can effectively reduce the current collapse effect caused by surface defects.

[0006] Since the luminescence spectra of group-III nitrides and their alloys not only cover the entire visible light spectrum, but also extend to the infrared and ultraviolet spectra, they have great development prospects in optoelectronic devices. In addition, GaN is a direct-bandgap semiconductor, which enables optoelectronic devices based on GaN-based materials to have high luminescence efficiency. Currently, the main growth method of GaN thin films is heteroepitaxy, usually using materials such as SiC, sapphire, or Si as substrates. Due to the differences in lattice constants and thermal expansion coefficients between the substrate and GaN-based materials, there will be lattice mismatch and thermal mismatch, and these mismatches are the most important factors causing high-density defects in the material, seriously affecting the performance of gallium nitride-based devices.

[0007] As non-radiative recombination centers, dislocations can promote the non-radiative recombination of hole-electron pairs in semiconductor devices, reducing the generation of photons and seriously affecting the internal quantum efficiency of the devices. When used in high-power devices such as gallium nitride lasers, it may also cause a large leakage current, affecting the service life of the devices.

[0008] Therefore, it is necessary to propose a new growth process to inhibit the growth of high-density threading dislocations generated by heteroepitaxy in GaN thin films and improve the luminescence efficiency and service life of optoelectronic devices. Summary of the Invention

[0009] The purpose of the present invention is to introduce a silicon dioxide blocking layer in the gallium nitride nucleation layer to prevent the continued growth of threading dislocations during the subsequent growth of gallium nitride. To solve the problems of leakage current and reduced quantum efficiency caused by the large number of threading dislocations, the technical solutions provided by the present invention are as follows:

[0010] A method for hindering the growth of dislocations in GaN by covering with SiO2, step S1: In the MOCVD reaction chamber, prepare a GaN nucleation layer on a sapphire substrate,

[0011] It is characterized in that it further includes:

[0012] Step S2: Etching

[0013] Transfer the substrate and GaN out of the reaction chamber, and use KOH for selective etching to create the deposition groove positions; Step S3: Deposit silicon dioxide

[0014] Transfer the substrate to the PECVD reaction chamber, wash it with deionized water, and deposit a layer of SiO2 film on the surface of the nucleation layer to cover the groove positions;

[0015] Step S4: Etch silicon dioxide

[0016] Transfer the product to the RIE etching chamber, introduce CHF3, and use reactive ion etching to remove the SiO2 film on the surface, but retain the silicon dioxide in the deposition groove;

[0017] Step S5: Continue growing gallium nitride

[0018] Transfer the substrate into the MOCVD reaction chamber and continue the GaN epitaxial growth.

[0019] Preferably, the thickness of the gallium nitride nucleation layer in step S1 is 90 - 120 nm.

[0020] Preferably, an inverted triangular groove is etched in step S2.

[0021] Preferably, the etching process in step S2 is as follows: First, ultrasonically clean the sample with acetone, ethanol, and deionized water to remove surface organic contaminants; then heat the sample to 250 °C using microwave, apply molten potassium hydroxide to the surface of the gallium nitride epitaxial wafer, etch, and utilize the characteristic that the penetration dislocations are prone to corrosion to etch the deposition grooves on the substrate gallium nitride, facilitating the coverage of SiO2.

[0022] Preferably, the thickness of the deposited SiO2 thin film layer in step S3 is 80 - 100 nm.

[0023] Furthermore, the specific content of step S5 is: At a temperature of 1000 - 1100 °C, place the gallium nitride substrate on a tray, introduce trimethylgallium and ammonia gas, and grow a gallium nitride epitaxial layer on the surface of the gallium nitride substrate.

[0024] Based on the principle that the corrosion rate of gallium nitride material is different at the defective and non - defective parts, corrosion pits can be formed at the parts with threading dislocations through selective corrosion. Depositing SiO2 on the gallium nitride surface can hinder the further growth of threading dislocations. Removing the deposited SiO2 using photolithography means can precisely control whether there is SiO2 on the surface of the GaN nucleation layer after photolithography, reducing the threading dislocation density of the subsequently grown GaN.

[0025] The present invention introduces a silicon dioxide blocking layer into the gallium nitride nucleation layer to prevent the penetration dislocations from growing further during the subsequent gallium nitride growth process, solving the problems of leakage current and reduced quantum efficiency caused by the large number of penetration dislocations. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is the process flow chart of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0027] The following will describe the specific embodiments of the present invention in more detail with reference to the schematic diagrams. According to the following description and the scope of the patent application, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non - precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0028] A method for hindering the growth of dislocations in GaN by covering with SiO2, comprising:

[0029] Step S1: In the MOCVD reaction chamber, a GaN nucleation layer is prepared on a sapphire substrate.

[0030] The thickness of the gallium nitride nucleation layer is 90 - 120 nm, and in this embodiment, it is 100 nm.

[0031] Step S2: Etching

[0032] Transfer the substrate and GaN out of the reaction chamber, and use KOH for selective etching to form deposition groove positions; first, ultrasonically clean the sample with acetone, ethanol, and deionized water to remove surface organic contaminants; then heat the sample to 250 °C using microwave, apply molten potassium hydroxide to the surface of the gallium nitride epitaxial wafer, and etch. Utilize the characteristic that the penetration dislocation is easy to corrode to etch the substrate gallium nitride to form a deposition groove for convenient SiO2 coverage.

[0033] The shape of the etched deposition groove is an inverted triangular groove position, which is the optimal groove shape under the influence of gravity during the etching process.

[0034] Step S3: Deposit silicon dioxide

[0035] Transfer the substrate to the PECVD reaction chamber. After washing with deionized water, deposit a layer of SiO2 film on the nucleation layer surface to cover the groove positions. The thickness of the deposited SiO2 film layer is 80 - 100 nm, and in this embodiment, it is 90 nm.

[0036] Step S4: Etch silicon dioxide

[0037] Transfer the product into the RIE etching chamber, introduce CHF3, and use reactive ion etching to remove the SiO2 film on the surface, but retain the silicon dioxide in the deposition groove.

[0038] Step S5: Continue growing gallium nitride

[0039] Transfer the substrate into the MOCVD reaction chamber and continue GaN epitaxial growth.

[0040] Specifically: At a temperature of 1000 - 1100 °C, place the gallium nitride substrate on a tray, introduce trimethylgallium and ammonia, and grow a gallium nitride epitaxial layer on the surface of the gallium nitride substrate.

[0041] Based on the principle that the corrosion rates are different at the defective and defect-free sites of gallium nitride materials, corrosion pits can be formed at the sites with threading dislocations through selective corrosion. Depositing SiO2 on the surface of gallium nitride can hinder the further growth of threading dislocations. Removing the deposited SiO2 by lithography can precisely control whether there is SiO2 on the surface of the GaN nucleation layer after lithography, reducing the threading dislocation density of the subsequently grown GaN.

[0042] Through the detailed description of the above preferred specific embodiments, it is hoped that the features and spirit of the present invention can be more clearly described, rather than limiting the scope of the present invention by the above-disclosed preferred specific embodiments. On the contrary, the purpose is to hope to cover various changes and equivalent arrangements within the scope of the claims to be applied for the present invention.

Claims

1. A method for hindering the growth of dislocations in GaN by covering with SiO2. Step S1: In the MOCVD reaction chamber, a GaN nucleation layer is prepared on a sapphire substrate. It is characterized in that It also includes: Step S2: Etching Transfer the substrate and GaN out of the reaction chamber, and use KOH for selective etching to create the deposition groove positions. Step S3: Depositing silicon dioxide Transfer the substrate to the PECVD reaction chamber. After washing with deionized water, deposit a layer of SiO2 film on the surface of the nucleation layer to cover the groove positions. Step S4: Etching silicon dioxide Transfer the product into the RIE etching chamber, introduce CHF3, and use reactive ion etching to remove the SiO2 film on the surface, but retain the silicon dioxide in the deposition groove. Step S5: Continuing to grow gallium nitride Transfer the substrate into the MOCVD reaction chamber and continue the GaN epitaxial growth.

2. The method for hindering the growth of dislocations in GaN by covering with SiO2 according to claim 1, wherein In the step S1, the thickness of the GaN nucleation layer is 90 - 120 nm.

3. The method for hindering the growth of dislocations in GaN by covering with SiO2 according to claim 2, characterized in that, In the step S2, inverted triangular groove positions are etched.

4. The method for hindering the growth of dislocations in GaN by covering with SiO2 according to claim 1, characterized in that The etching process of the step S2 is as follows: First, ultrasonically clean the sample with acetone, ethanol, and deionized water to remove surface organic contaminants; then heat the sample to 250 °C using microwave, apply molten potassium hydroxide to the surface of the GaN epitaxial wafer for corrosion, and utilize the characteristic that the penetration dislocations are prone to corrosion to etch the substrate GaN to create the deposition groove for easy SiO2 coverage.

5. The method for hindering the growth of dislocations in GaN by covering with SiO2 according to claim 1, characterized in that In the step S3, the thickness of the deposited SiO2 film layer is 80 - 100 nm.

6. The method for hindering the growth of dislocations in GaN by covering with SiO2 according to claim 1, characterized in that The step S5 is specifically: At a temperature of 1000 - 1100 °C, place the GaN substrate on the tray, introduce trimethylgallium and ammonia gas, and grow a GaN epitaxial layer on the surface of the GaN substrate.

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