Soft start circuit based on frequency foldback

Abstract

The present application relates to the field of switching power supplies and discloses a soft-start circuit based on frequency foldback, the soft-start circuit comprising: a soft-start unit for generating a first switching control signal by soft-starting the switching power supply; a frequency-dividing unit for dividing the first switching control signal to obtain a frequency-dividing signal when frequency foldback occurs; a logic unit for receiving foldback signals of different frequency foldback stages generated when frequency foldback occurs, performing a logical operation on the first switching control signal, the frequency-dividing signal, and the foldback signal, outputting a second switching control signal with a constant frequency, and using the second switching control signal as a soft-start control signal, thereby controlling the output waveform of the soft-start switching power supply to remain unchanged. In the embodiment of the present application, the frequency-dividing unit and the logic unit offset the frequency change of the switching power supply caused by the frequency foldback, thereby keeping the output waveform of the switching power supply unchanged.

Description

Technical Field

[0001] The present application relates to the field of switching power supplies, and in particular to a soft start circuit based on frequency foldback. Background Art

[0002] In the prior art, to accommodate wide-frequency-range applications, a soft-start circuit is typically constructed in such a way that the soft-start time (i.e., the soft-start time) is inversely proportional to the soft-start control frequency to achieve soft-start of the switching power supply. Furthermore, the overload condition of the chip connected to the soft-start circuit is detected by the level of feedback voltage. This causes the switching frequency of the switching power supply to undergo a sudden change during the soft-start process due to triggering frequency foldback. If the soft-start control frequency and the switching frequency are the same, the output waveform of the soft-start circuit will rise in the form of a broken line with a doubled slope, ultimately causing distortion of the output waveform of the switching power supply system. Summary of the Invention

[0003] In view of this, in order to address the deficiencies in the prior art, the present application provides a soft start circuit based on frequency foldback and an output waveform control method for soft start of a switching power supply.

[0004] In a first aspect, the present application provides a soft start circuit based on frequency foldback, comprising a soft start unit, a frequency division unit, and a logic unit;

[0005] The soft start unit is used to generate a first switch control signal by soft starting the switching power supply;

[0006] The frequency dividing unit is used to divide the frequency of the first switch control signal to obtain a frequency-divided signal when frequency foldback occurs;

[0007] The logic unit is used to receive the return signals of different frequency return stages generated when frequency foldback occurs, perform logical operations on the first switch control signal, the frequency division signal and the return signal, output a second switch control signal with unchanged frequency, and use the second switch control signal as the soft start control signal of the switch in the soft start unit, thereby controlling the output waveform of the soft start switching power supply to remain unchanged.

[0008] In an optional embodiment, the frequency division unit includes at least one frequency divider, each of which divides the first switch control signal in turn and outputs a corresponding frequency-divided signal; wherein the frequency of each of the frequency-divided signals changes in a step-by-step manner as the number of frequency division processes increases.

[0009] In an optional embodiment, the frequency dividing unit includes three frequency dividers;

[0010] The first frequency divider is used to divide the frequency of the first switch control signal and output a first frequency-divided signal; wherein the frequency of the first frequency-divided signal is 1 / 4 of the frequency of the first switch control signal;

[0011] The second frequency divider is used to divide the first frequency-divided signal and output a second frequency-divided signal; wherein the frequency of the second frequency-divided signal is 1 / 2 of the frequency of the first switch control signal;

[0012] The third frequency divider is used to divide the second frequency-divided signal and output a third frequency-divided signal; wherein the frequency of the third frequency-divided signal is equal to the frequency of the first switch control signal.

[0013] In an optional embodiment, the frequency of the second switch control signal is equal to the frequency of the first frequency-divided signal; wherein the first frequency-divided signal is the frequency-divided signal output after the frequency-dividing unit performs a first frequency division on the first switch control signal.

[0014] In an optional embodiment, the logic unit is used to input the folded signals of different frequency folded stages and the frequency-divided signal of the same frequency folded stage into a first logic gate for a first logic operation;

[0015] Inputting the result of the first logic operation into the second logic gate for performing a second logic operation;

[0016] The result of the second logic operation and the first switch control signal are input into a third logic gate to perform a third logic operation, and a second switch control signal is output.

[0017] In an optional embodiment, the first logic gate is a NOR gate; the second logic gate is an XOR gate; and the third logic gate is a NAND gate.

[0018] In an optional embodiment, the soft start unit includes a switching power supply, a switch and a capacitor;

[0019] The switching power supply is grounded via the capacitor, and the switch is connected in series with the switching power supply and the capacitor, respectively, for controlling the soft start of the switching power supply by turning the switch on and off.

[0020] In an optional embodiment, the second switch control signal is used to control the on-off state of the switch, thereby controlling the soft-start frequency of the switching power supply.

[0021] In an optional implementation, the frequency divider is a D flip-flop.

[0022] In a second aspect, the present application provides a method for controlling an output waveform of a soft start of a switching power supply, which is applied to the aforementioned soft start circuit based on frequency foldback, the method comprising:

[0023] The soft start unit generates a first switch control signal through a soft start switch power supply;

[0024] When frequency foldback occurs, the frequency dividing unit divides the first switch control signal to obtain a frequency-divided signal;

[0025] The logic unit receives the foldback signals of different frequency foldback stages generated when frequency foldback occurs, performs a logic operation on the first switch control signal, the frequency division signal and the foldback signal, and outputs a second switch control signal with a constant frequency; and uses the second switch control signal as the soft start control signal of the switch in the soft start unit, thereby controlling the output waveform of the soft start switching power supply to remain unchanged.

[0026] The embodiments of the present application have the following beneficial effects:

[0027] An embodiment of the present application provides a soft start circuit based on frequency foldback, comprising a soft start unit, a frequency division unit, and a logic unit, wherein the soft start unit is used to generate a first switch control signal by soft starting a switching power supply; the frequency division unit is used to divide the first switch control signal to obtain a frequency division signal when frequency foldback occurs; the logic unit is used to receive foldback signals of different frequency foldback stages generated when frequency foldback occurs, perform a logical operation on the first switch control signal, the frequency division signal, and the foldback signal, output a second switch control signal with a constant frequency, use the second switch control signal as a soft start control signal, and thereby control the output waveform of the soft started switching power supply to remain unchanged. In the embodiment of the present application, when frequency foldback occurs, the frequency change of the switching power supply caused by the frequency foldback is offset by the frequency division unit and the logic unit, so as to control the frequency of the control signal used to control the soft start of the switching power supply to remain unchanged, thereby making the output waveform of the switching power supply remain unchanged, so as to avoid the output waveform of the switching frequency being distorted due to the occurrence of frequency foldback. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solution of this application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of this application and should not be regarded as limiting the scope of protection of this application. In each of the drawings, similar components are numbered similarly.

[0029] Figure 1 A schematic structural diagram of a soft start circuit based on frequency foldback in an embodiment of the present application is shown;

[0030] Figure 2 A structural schematic diagram of a soft start unit of a soft start circuit based on frequency foldback in an embodiment of the present application is shown;

[0031] Figure 3 A schematic diagram showing waveform changes of various signals of a soft start circuit based on frequency foldback in an embodiment of the present application is shown;

[0032] Figure 4 A schematic structural diagram of a frequency division unit of a soft start circuit based on frequency foldback in an embodiment of the present application is shown;

[0033] Figure 5 A schematic structural diagram of a logic unit of a soft start circuit based on frequency foldback in an embodiment of the present application is shown;

[0034] Figure 6 A schematic diagram illustrating an implementation of a method for controlling an output waveform of a soft start of a switching power supply in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0035] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0036] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0037] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0038] Furthermore, the terms “first,” “second,” “third,” etc., are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0039] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0040] Frequency Foldback mode: The frequency is reduced in stages to extend the demagnetization time of the inductor, allowing the starting current of the inductor magnetization to return to the starting point in each switching cycle, thereby avoiding inductor saturation.

[0041] Existing soft-start solutions are generally divided into built-in soft-start circuits and external soft-start circuits. The soft-start solution of the external soft-start circuit generally adjusts the soft-start time by adjusting the external capacitor, but this external soft-start circuit often adds a pin and capacitor, which increases production costs. The soft-start solution of the built-in soft-start circuit is generally designed to have a fixed soft-start time or a soft-start time that is inversely proportional to the soft-start control frequency. The fixed soft-start time method is obviously not flexible enough in wide frequency range applications. The method of inversely proportional soft-start time with frequency can achieve a compromise between system startup time and inductor current overshoot, but when integrated with frequency foldback technology, it is easy to cause the switching frequency of the switching power supply to change, resulting in distortion of the output waveform of the switching power supply.

[0042] Specifically, in the prior art, the overload condition of the chip connected to the soft-start circuit is identified by the level of feedback voltage. This causes the switching frequency to suddenly change due to the trigger frequency foldback during the soft-start process. If the control frequency of the soft-start is the same as the switching frequency, the output waveform of the soft-start will rise in the form of a broken line with a doubled slope, ultimately causing the output waveform of the switching power supply system to be distorted.

[0043] Based on this, the present application provides a soft start circuit based on frequency foldback and an output waveform control method for soft start of a switching power supply applied to the soft start circuit. The present application sets the frequency of the control signal of the switch used to control the soft start to a fixed frequency through the combined action of a frequency divider and a logic gate, so that the output waveform of the switching power supply remains unchanged.

[0044] like Figure 1 As shown, the present application provides a soft start circuit based on frequency foldback, which includes a soft start unit 100 , a frequency division unit 200 and a logic unit 300 .

[0045] For example, Figure 2 As shown, the soft start unit 100 includes a switching power supply 110, a switch 120, and a capacitor 130; wherein the switching power supply 110 is grounded through the capacitor 130, and the switch 120 is connected in series with the switching power supply 110 and the capacitor 130, respectively, for controlling the soft start of the switching power supply and the time and frequency of the soft start by turning the switch 120 on and off.

[0046] In this embodiment, the soft-start unit 100 is configured to generate a first switch control signal (ie, CLK) by soft-starting the switching power supply 110 .

[0047] It can be understood that the first switch control signal is used to control the on / off of the switch 120 in the soft start unit 100 , thereby controlling the soft start of the switching power supply 110 . That is, the frequency of the first switch control signal is the switching frequency of the switching power supply 110 .

[0048] Furthermore, before triggering the soft start of the switching power supply, this embodiment uses the received feedback voltage (i.e., FB) to identify any overload conditions in the chip of the external circuit of the switching power supply 110. When the feedback voltage is greater than the reference voltage (i.e., VREF), the inductor current of the external circuit is prevented from overshooting due to a short demagnetization time, triggering frequency foldback in the external circuit to reduce the switching frequency used to control the soft start of the switching power supply 110.

[0049] When frequency foldback occurs, the switching frequency of the switching power supply 110 is reduced, that is, the frequency of the first switch control signal is reduced to generate a corresponding foldback signal. Therefore, the frequency of the foldback signal is lower than the frequency of the first switch control signal.

[0050] Since frequency foldback occurs, which causes a change in the switching frequency of the soft start, and thus causes distortion of the output waveform of the switching power supply 110, the embodiment of the present application offsets the frequency change caused by the frequency foldback through the frequency division unit set up, so that the switching frequency of the soft start control remains unchanged.

[0051] In this embodiment, the frequency dividing unit 200 is used to divide the frequency of the first switch control signal when frequency foldback occurs, and obtain a corresponding frequency-divided signal.

[0052] Exemplarily, the frequency divider unit 200 includes at least one frequency divider, each of which sequentially divides the first switch control signal and outputs a corresponding divided frequency signal. Each frequency divider performs a single signal division process; the frequency of each divided signal changes in a step-wise manner as the number of division processes increases. The number of frequency dividers can be set based on actual needs. For example, the number of frequency dividers can be two, three, five, or eight, without limitation.

[0053] In addition, if there are two or more frequency dividers, the multiple frequency dividers are connected in cascade; when performing frequency division, the first frequency divider divides the first switch control signal and outputs it to the second frequency divider for frequency division processing, and so on until the frequency division is completed.

[0054] It can be understood that frequency division is to adjust the frequency of a single frequency signal to 1 / N of the original frequency. In this embodiment, the frequency division unit 200 is used to output a frequency division signal corresponding to the frequency division number, and as the frequency division number increases, the frequency of the frequency division signal corresponding to different frequency division numbers changes in a step-by-step manner.

[0055] It should be noted that when the first switch control signal is divided, the frequency change value of the signal can be set accordingly according to actual needs and is not limited here. For example, the first switch control signal can be divided in sequence according to a ratio of 1 / 4, 1 / 2, 1, etc., or the first switch control signal can be divided in sequence according to a ratio of 1 / 8, 1 / 4, 1 / 2, etc.

[0056] As an optional embodiment, the frequency divider unit 200 includes three frequency dividers. Exemplarily, the first frequency divider is configured to divide the first switch control signal and output a first frequency-divided signal, wherein the frequency of the first frequency-divided signal is 1 / 4 of the frequency of the first switch control signal; the second frequency divider is configured to divide the first frequency-divided signal and output a second frequency-divided signal, wherein the frequency of the second frequency-divided signal is 1 / 2 of the frequency of the first switch control signal; and the third frequency divider is configured to divide the second frequency-divided signal and output a third frequency-divided signal, wherein the frequency of the third frequency-divided signal is equal to the frequency of the first switch control signal.

[0057] Optionally, the frequency divider uses a D flip-flop (i.e., DFFRB); wherein, the D flip-flop is an information storage device with a memory function and two stable states, and the frequency division of the signal can be achieved through the D flip-flop. The D flip-flop includes multiple interfaces or pins (such as D, Q, CK, QB, RB interfaces or pins), and the D flip-flop inputs or outputs the corresponding signal through the interface or pin.

[0058] In this embodiment, the logic unit 300 is configured to receive foldback signals generated at different frequency foldback stages when frequency foldback occurs, perform a logical operation on the clock signal, the frequency-divided signal, and the foldback signal, and output a second switch control signal. The second switch control signal is configured to control the soft-start frequency of the switching power supply 110 by controlling the on / off state of the switch in the soft-start unit 100, i.e., the soft-start switching frequency.

[0059] It can be understood that the second switch control signal is a control signal for controlling the soft start of the switching power supply 110. That is, the second switch control signal is used to control the on and off of the switch in the soft start unit 100 to achieve control of the soft start time. The frequency of the second switch control signal is the switching frequency of the soft start of the switching power supply 110.

[0060] Further optionally, the frequency of the second switch control signal output by the logic unit 300 is equal to the frequency of the first frequency-divided signal; wherein the first frequency-divided signal is the frequency-divided signal output after the frequency-dividing unit 200 performs a first frequency division on the first switch control signal.

[0061] It can be understood that in this embodiment, the switching frequency of the soft start of the switching power supply 110 is set to the frequency of the divided signal output after the first frequency division. Furthermore, when the logic unit 300 performs a logical operation to output the second switch control with a constant frequency, the switching frequency of the soft start of the switching power supply 110 is ensured to remain unchanged, thereby ensuring that the output waveform of the switching power supply 110 is not distorted due to frequency foldback.

[0062] Specifically, the logic unit 300 is used to input the return signals of different frequency return stages and the divided signal of the same frequency return stage into the first logic gate for a first logic operation; input the result of the first logic operation into the second logic gate for a second logic operation; input the result of the second logic operation and the first switch control signal into the third logic gate for a third logic operation, and output the second switch control signal.

[0063] The first logic gate is a NOR gate, the second logic gate is an XOR gate, and the third logic gate is a NAND gate. In other words, the first logic operation is a NOR logic operation, the second logic operation is an XOR logic operation, and the third logic operation is a NAND logic operation.

[0064] It should be noted that when the logic unit 300 performs logic operations on the foldback signal, the frequency division signal and the first switch control signal in each frequency foldback stage, the logic unit 300 outputs a second switch control signal with a constant frequency no matter how many times the frequency foldback occurs.

[0065] In this embodiment, the second switch control signal is used as the soft start control signal for the switch in the soft start unit 100 . Since the frequency of the second switch control signal remains unchanged, the output waveform of the soft start switching power supply 110 remains unchanged.

[0066] As an optional implementation, please refer to Figure 3 、 Figure 4 and Figure 5Assuming three frequency foldbacks occur, and the frequency divider unit 200 includes three frequency dividers, illustratively, if the feedback voltage (i.e., FB) is greater than the reference voltage (i.e., VREF1, VREF2, or VREF3), the soft-start circuit is triggered to perform frequency foldback, generating a foldback signal (i.e., FOLD1, FOLD2, or FOLD3). During each frequency foldback phase, the frequency divider unit 200 divides the first switching control signal (i.e., CLK) to generate a divided signal (i.e., CLK_1, CLK_2, or CLK_3). The logic unit 300 then performs a logical operation on the divided signal and the foldback signal to output a second switching control signal with a constant frequency, thereby ensuring that the soft-start switching frequency (i.e., CLK_SS) remains constant.

[0067] Specifically, if Figure 3 As shown in FIG, it is assumed that the first switch control signal changes according to the change rule of 1 / 8, 1 / 4, 1 / 2, and 1. When frequency foldback occurs, the switching frequency (CLK) is reduced to 1 / 8 of the original frequency; then, the switching frequency increases with the increase of the FB voltage. When the voltage value of FB is greater than VREF1, the foldback signal FOLD1 is flipped (from high level to low level), and the frequency division unit 200 divides the CLK frequency to convert the CLK frequency from the original 1 / 8 to 1 / 4. That is, as shown in FIG. Figure 4 As shown, the frequency dividing unit 200 inputs the CLK into the first frequency divider for frequency division processing to output a first frequency-divided signal (ie, CLK_1 ). The frequency of the CLK_1 is 1 / 4 of the original frequency of CLK.

[0068] Furthermore, when FB gradually increases until its voltage value is greater than VREF2, the corresponding foldback signal FOLD2 flips its level (from high level to low level), and the frequency division unit 200 divides the CLK (divides CLK_1 to output CLK_2) to convert the frequency of CLK from 1 / 4 to 1 / 2.

[0069] Similarly, when FB gradually increases until its voltage value is greater than VREF3, the corresponding foldback signal FOLD3 undergoes a level flip (from a high level to a low level), and the frequency division unit 200 performs a frequency division process on the CLK (divides CLK_2 to output CLK_3), thereby converting the frequency of CLK from 1 / 4 to 1, that is, the frequency of CLK at this time is equal to the frequency of the original CLK.

[0070] After the frequency division is completed three times, the logic unit 300 performs a logic operation among the frequency division signal, the foldback signal and the first switch control signal to output a second switch control signal.

[0071] like Figure 5As shown, the logic unit 300 performs a NOR logic operation on the frequency-divided signal and the folded-back signal in the same frequency folded-back stage. Since the folded-back signals are both at a low level at this time, the logic gate outputs the frequency-divided signal after the NOR logic operation. Then, the output frequency-divided signal is subjected to an XOR logic operation. At this time, the logic gate outputs a signal CLK_1 according to the corresponding levels of each frequency-divided signal. Finally, a NAND logic operation is performed on the signal CLK_1 and the original signal CLK. According to the corresponding levels, the logic gate outputs the signal CLK_1. Then, the pulse generator (i.e., pulse generator) outputs the second switch control signal (CLK_SS), wherein the frequency of the signal CLK_SS is consistent with the frequency of the signal CLK_1. Furthermore, due to the logic algorithm of the logic unit 300, the logic unit 300 can ensure that the output frequency of the signal CLK_SS remains constant, thereby ensuring that the frequency of the signal CLK_SS is 1 / 8 of the original CLK frequency. When the soft start is controlled accordingly by the signal CLK_SS with a constant frequency, the output waveform (i.e., SS) of the soft-start switching power supply 110 can be linearly changed.

[0072] In the embodiment of the present application, a first switch control signal for controlling the soft-start switching frequency is divided by a frequency division unit 200, and then a logic operation is performed by a logic unit 300 to output a second switch control signal with a constant frequency. The second switch control signal is used to control the soft start of the switching power supply 110. Then, based on the correspondence between the frequency of the second switch control signal (i.e., the corresponding switching frequency) and the soft-start time, the output waveform of the soft-start switching power supply 110 changes linearly to avoid distortion of the output waveform due to frequency foldback.

[0073] Furthermore, if Figure 6 As shown, the present application provides a method for controlling an output waveform of a soft start of a switching power supply 110, which is applied to the above-mentioned soft start circuit based on frequency foldback, and includes:

[0074] S10 , the soft start unit 100 generates a first switch control signal through the soft start switching power supply 110 .

[0075] S20 , when frequency foldback occurs, the frequency dividing unit 200 divides the first switch control signal to obtain at least one divided frequency signal.

[0076] S30, the logic unit 300 receives the foldback signals of different frequency foldback stages generated when frequency foldback occurs, performs logical operations on the clock signal, the frequency division signal and the foldback signal, outputs a second switch control signal with a constant frequency, and uses the second switch control signal as the soft start control signal of the switch in the soft start unit 100, thereby controlling the output waveform of the soft start switching power supply 110 to remain unchanged.

[0077] It can be understood that the output waveform control method for soft starting of the switching power supply 110 in this embodiment corresponds to the above-mentioned soft starting circuit based on frequency foldback. Any optional options of the above-mentioned embodiment are also applicable to this embodiment, so they are not described in detail here.

[0078] In this embodiment, when frequency foldback occurs, the frequency change of the switching power supply 110 caused by the frequency foldback is offset by the frequency division unit 200 and the logic unit 300, so as to control the frequency of the control signal used to control the soft start of the switching power supply 110 to remain unchanged, thereby keeping the output waveform of the switching power supply 110 unchanged.

[0079] The above is only a specific implementation method of the present application, but the scope of protection of the present application is not limited thereto. Any technician familiar with this technical field can easily think of changes or replacements within the technical scope disclosed in this application, which should be covered by the scope of protection of the present application.

Claims

1. A soft start circuit based on frequency foldback, characterized in that: Including soft start unit, frequency division unit, and logic unit; The soft start unit is used to generate a first switch control signal by soft starting the switching power supply; The frequency dividing unit is used to divide the frequency of the first switch control signal to obtain a frequency-divided signal when frequency foldback occurs; The logic unit is used to receive the return signals of different frequency return stages generated when frequency foldback occurs, perform logical operations on the first switch control signal, the frequency division signal and the return signal, output a second switch control signal with unchanged frequency, and use the second switch control signal as the soft start control signal of the switch in the soft start unit, thereby controlling the output waveform of the soft start switching power supply to remain unchanged.

2. The soft start circuit based on frequency foldback according to claim 1, characterized in that: The frequency division unit includes at least one frequency divider, each of which divides the first switch control signal in turn and outputs a corresponding frequency-divided signal; wherein the frequency of each frequency-divided signal changes in a step-by-step manner as the number of frequency division processes increases.

3. The soft start circuit based on frequency foldback according to claim 1 or 2, characterized in that: The frequency division unit includes three frequency dividers; The first frequency divider is used to divide the frequency of the first switch control signal and output a first frequency-divided signal; wherein the frequency of the first frequency-divided signal is 1 / 4 of the frequency of the first switch control signal; The second frequency divider is used to divide the first frequency-divided signal and output a second frequency-divided signal; wherein the frequency of the second frequency-divided signal is 1 / 2 of the frequency of the first switch control signal; The third frequency divider is used to divide the second frequency-divided signal and output a third frequency-divided signal; wherein the frequency of the third frequency-divided signal is equal to the frequency of the first switch control signal.

4. The soft start circuit based on frequency foldback according to claim 1, characterized in that: The frequency of the second switch control signal is equal to the frequency of the first frequency-divided signal; wherein the first frequency-divided signal is the frequency-divided signal outputted after the frequency-dividing unit performs a first frequency division on the first switch control signal.

5. The soft start circuit based on frequency foldback according to claim 1, characterized in that: The logic unit is used to input the folded signals of different frequency folded stages and the frequency-divided signal of the same frequency folded stage into the first logic gate for a first logic operation; Inputting the result of the first logic operation into the second logic gate for performing a second logic operation; The result of the second logic operation and the first switch control signal are input into a third logic gate to perform a third logic operation, and a second switch control signal is output.

6. The soft start circuit based on frequency foldback according to claim 5, characterized in that: The first logic gate is a NOR gate; the second logic gate is an XOR gate; and the third logic gate is a NAND gate.

7. The soft start circuit based on frequency foldback according to claim 1, characterized in that: The soft start unit includes a switching power supply, a switch and a capacitor; The switching power supply is grounded via the capacitor, and the switch is connected in series with the switching power supply and the capacitor, respectively, for controlling the soft start of the switching power supply by turning the switch on and off.

8. The soft start circuit based on frequency foldback according to claim 7, characterized in that: The second switch control signal is used to control the on-off state of the switch, thereby controlling the soft-start frequency of the switching power supply.

9. The soft start circuit based on frequency foldback according to claim 2, characterized in that: The frequency divider is a D flip-flop.

10. A method for controlling the output waveform of a switching power supply soft start, characterized in that: Applied to the soft start circuit based on frequency foldback according to any one of claims 1 to 9, the method comprising: The soft start unit generates a first switch control signal through a soft start switch power supply; When frequency foldback occurs, the frequency dividing unit divides the first switch control signal to obtain a frequency-divided signal; The logic unit receives the foldback signals of different frequency foldback stages generated when frequency foldback occurs, performs a logic operation on the first switch control signal, the frequency division signal and the foldback signal, and outputs a second switch control signal with a constant frequency; and uses the second switch control signal as the soft start control signal of the switch in the soft start unit, thereby controlling the output waveform of the soft start switching power supply to remain unchanged.

Images