A frequency domain beam synthesis device based on FPGA

Abstract

The application relates to a frequency domain beam synthesis device based on FPGA, and belongs to the field of communication countermeasures. The device comprises a high-speed serial transceiver interface module, a wideband digital down-conversion module, a high-speed sampling point calibration module, a beam coefficient cache module, a high-speed calibration synthesis module, a synchronous signal generation and forwarding module, a high-speed frequency domain inter-board synchronous data exchange module, a high-speed frequency domain intra-board synchronous data exchange module and a high-speed interface module; two different protocols of the high-speed interface share one bank interface, multi-phase parallel wideband frequency domain beam synthesis technology is realized through a frequency domain beam adaptive clipping mode, the wideband beam synthesis function can be completed, the multi-element, super wideband and multi-beam beam synthesis function can be completed by using less FPGA resources, and the generated beam is phase-continuous in the wideband. The device is suitable for the pretreatment of the super long distance super wideband signal reconnaissance and direction finding function, has the advantages of high data processing rate, large signal bandwidth, high calibration precision, high synthesis precision, continuous beam phase and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to a kind of broadband digital beam synthesis devices in communication related field, by FPGA inside involves communication reconnaissance field to the reconnaissance processing of signal. BACKGROUND

[0002] Under the background of information age nowadays, information technology develops rapidly, wireless communication technology has made unprecedented progress. Digital beam forming is a key technology in the field of phased array of wireless communication, its essence is a kind of digital space filtering, enhance the signal incident to array in certain direction, improve signal-to-noise ratio, suppress other direction interference and noise, provide necessary conditions for subsequent signal processing. In view of the development trend of wide open in frequency domain and wide open in space of beam synthesis technology, wideband calibration and wideband multi-beam forming method based on traditional time domain method, there are problems such as complex process, high filter order, large hardware resource consumption. SUMMARY

[0003] The present application needs to solve the above-mentioned problems existing in reality, to innovate the beam synthesis direction of reconnaissance receiver, provide a kind of FPGA implementation device of frequency domain beam synthesis under high-speed sampling.

[0004] The technical scheme adopted by the present application is:

[0005] A kind of frequency domain beam synthesis device based on FPGA implementation, including high-speed serial transceiver interface module 1, wideband digital down conversion module 2, high-speed sampling point calibration module 3, beam coefficient cache module 4, high-speed calibration synthesis module 5, synchronous signal generation forwarding module 6, high-speed frequency domain inter-board synchronous data exchange module 7, high-speed frequency domain intra-board synchronous data exchange module 8 and high-speed interface module 9;

[0006] High-speed serial transceiver interface module 1 is used to receive the high-speed sampling data transmitted by high-speed sampling board card, and is sent into wideband digital down conversion module 2, also used to send the secondary synthesis data sent by high-speed calibration synthesis module 5 to photoelectric conversion interface;

[0007] Wideband digital down conversion module 2 is used for orthogonal digital down conversion processing to the high-speed sampling data sent by high-speed serial transceiver interface module 1, and the zero intermediate frequency signal after orthogonal down conversion is sent to high-speed sampling point calibration module 3;

[0008] High-speed sampling point calibration module 3 is used for integer sampling point calibration processing to the zero intermediate frequency signal received from wideband digital down conversion module 2, and the signal after completing integer sampling point calibration is sent to high-speed calibration synthesis module 5;

[0009] Beam coefficient cache module 4 is used for receiving calibration synthesis coefficient and caching, and the cached calibration synthesis coefficient is sent to high-speed calibration synthesis module 5;

[0010] The high-speed calibration synthesis module 5 is used to load calibration synthesis coefficients onto the signal after integer sampling point calibration sent by the high-speed sampling point calibration module 3, and to perform phase and fractional point delay calibration on the signal after integer sampling point calibration. The calibrated signal is then synthesized. During synthesis, the signal is processed by FFT frequency domain conversion in block floating-point mode. The converted data and block floating-point factors are sent to the high-speed frequency domain inter-board synchronous data exchange module 7. At the same time, the module receives frequency domain data from other boards and performs primary synthesis on the frequency domain data of each board. The module also sends the primary synthesized data to the high-speed frequency domain intra-board synchronous data exchange module 8 and receives the primary synthesized data from another FPGA on the board and performs secondary synthesis on the secondary synthesized data. The secondary synthesized data is then sent to the high-speed serial transceiver interface module 1.

[0011] The synchronization signal generation and forwarding module 6 is used to generate synchronization pulses for synchronization with other FPGAs and send them to the other modules respectively.

[0012] The high-speed frequency domain inter-board synchronization data exchange module 7 is used to receive the frequency-domain converted data and block floating-point factors sent by the high-speed calibration synthesis module 5, as well as the synchronization pulse generated by the synchronization signal generation and forwarding module 6. It then synchronizes and packages the frequency-domain converted data and block floating-point factors with the synchronization pulse as a reference, and sends the packaged data to the high-speed interface module 9. It is also used to receive the frequency-domain converted data and block floating-point factors from other boards sent by the high-speed interface module 9, and to compensate the spectral amplitude through the block floating-point factors. The compensated frequency domain data is then sent to the high-speed calibration synthesis module 5.

[0013] The high-speed frequency domain board-based synchronous data exchange module 8 is used to receive the primary synthesized data sent by the high-speed calibration synthesis module 5, as well as the synchronization pulse generated by the synchronization signal generation and forwarding module 6. The primary synthesized data is synchronously packaged using the synchronization pulse as a reference, and the packaged data is sent to the high-speed interface module 9. It is also used to receive the primary synthesized data input from another FPGA in the board sent by the high-speed interface module 9, and send the primary synthesized data to the high-speed calibration synthesis module 5.

[0014] Furthermore, the high-speed serial transceiver interface module 1 includes a high-speed sampling data receiving module 101 and a high-speed data transmitting module 102, and the two modules share the same high-speed interface resource; the high-speed sampling data receiving module 101 uses the receiving end of the high-speed interface and adopts the JESD204B protocol, and the high-speed data transmitting module 102 uses the transmitting end of the high-speed interface and adopts the AURORA64 / 66B protocol.

[0015] The high-speed sampling data receiving module 101 is configured to receive high-speed sampling data transmitted by a high-speed sampling board card and send the high-speed sampling data to the wideband digital down-conversion module 2; and the high-speed data sending module 102 is configured to receive secondary synthesis data generated by the high-speed calibration synthesis module 5 and send the secondary synthesis data to the photoelectric conversion interface through a backplane.

[0016] Further, the high-speed inter-board data exchange module 7 comprises a high-speed inter-board data packing module 701, a high-speed inter-board data synchronization processing module 702 and a high-speed inter-board data unpacking module 703.

[0017] The high-speed inter-board data packing module 701 is configured to receive data converted from a frequency domain and a block floating factor sent by the high-speed calibration synthesis module 5, pack the two kinds of data, and send the packed data to the high-speed inter-board data synchronization processing module 702.

[0018] The high-speed inter-board data synchronization processing module 702 is configured to receive a synchronization pulse generated by the synchronization signal generation and forwarding module 6 and the packed data of the high-speed inter-board data packing module 701, perform synchronization processing on the packed data with reference to the synchronization pulse, and send the synchronized data to the high-speed interface module 9.

[0019] The high-speed inter-board data unpacking module 703 is configured to receive data converted from a frequency domain and a block floating factor of other board cards sent by the high-speed interface module 9, compensate the spectral amplitude with reference to the block floating factor, and send the compensated frequency domain data to the high-speed calibration synthesis module 5.

[0020] Further, the high-speed intra-board data exchange module 8 comprises a high-speed intra-board data packing module 801, a high-speed intra-board data synchronization processing module 802 and a high-speed intra-board data unpacking module 803.

[0021] The high-speed intra-board data packing module 801 is configured to receive primary synthesis data sent by the high-speed calibration synthesis module 5 and pack the primary synthesis data, and send the packed data to the high-speed intra-board data synchronization processing module 802.

[0022] The high-speed intra-board data synchronization processing module 802 is configured to receive a synchronization pulse generated by the synchronization signal generation and forwarding module 6 and the packed data of the high-speed intra-board data packing module 801, perform synchronization processing on the packed data with reference to the synchronization pulse, and send the synchronized data to the high-speed interface module 9.

[0023] The high-speed intra-board data unpacking module 803 is configured to receive primary synthesis data generated by another FPGA in a board card and sent by the high-speed interface module 9, unpack the sent primary synthesis data, and send the unpacked primary synthesis data to the high-speed calibration synthesis module 5.

[0024] Further, the synchronization signal generation and forwarding module 6 generates a synchronization pulse with the sampling card synchronization reference pulse as a reference, the synchronization pulse is synchronized with the synchronization pulse generated by the synchronization signal generation and forwarding module in the FPGA of each slot position and the sampling data, and the synchronization pulse is sent to the high-speed serial transceiver interface module 1, the wideband digital down conversion module 2, the high-speed sampling point calibration module 3, the beam coefficient cache module 4, the high-speed calibration synthesis module 5, the high-speed frequency domain inter-board synchronization data exchange module 7, the high-speed frequency domain intra-board synchronization data exchange module 8 and the high-speed interface module 9.

[0025] Compared with the prior art, the present application has the following advantages:

[0026] 1. The present application uses 204B protocol in the receiving port of the high-speed transceiver serial bus and uses AURARO64 / 66B protocol in the sending port, and the high-speed protocol multiplexing can save the high-speed interface of the FPGA and can be widely used in the miniaturized cabinet of the multi-beam array element.

[0027] 2. The present application uses the synchronization transceiving processing based on the frequency domain dynamic clipping, greatly reduces the data transmission amount between the FPGAs, and reduces the number of full exchanges under the condition of the multi-element multi-beam.

[0028] 3. The present application uses the signal synchronized with the sampling board as the synchronization reference, generates the synchronization pulse synchronized with the sampling, and the phase difference of each array element is consistent after the last power-on after power-off and restart. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 The principle block diagram of the present application is shown.

[0030] Figure 2 The schematic diagram of running two different protocols on the high-speed Serdes interface resource is shown.

[0031] Figure 3 The processing flow chart of the high-speed frequency domain inter-board synchronization data exchange module 7 is shown.

[0032] Figure 4 The processing flow chart of the high-speed frequency domain intra-board synchronization data exchange module 8 is shown. DETAILED DESCRIPTION

[0033] The present application is further described in detail below with reference to the accompanying drawings.

[0034] Figure 1The principle block diagram of the application is shown: a frequency domain beam synthesis device based on FPGA, comprising a high-speed serial transceiver interface module 1, a wideband digital down conversion module 2, a high-speed sampling point calibration module 3, a beam coefficient cache module 4, a high-speed calibration synthesis module 5, a synchronous signal generation and forwarding module 6, a high-speed frequency domain inter-board synchronous data exchange module 7 based on dynamic clipping, a high-speed frequency domain intra-board synchronous data exchange module 8 and a high-speed interface module 9;

[0035] The high-speed serial transceiver interface module 1 is used for receiving high-speed sampling data transmitted by a high-speed sampling board card and sending the data to the wideband digital down conversion module 2, and is also used for sending secondary synthesis data sent by the high-speed calibration synthesis module 5 to an optoelectronic conversion interface;

[0036] The wideband digital down conversion module 2 is used for performing quadrature digital down conversion processing on high-speed sampling data sent by the high-speed serial transceiver interface module 1, and sending the zero intermediate frequency signal after quadrature down conversion to the high-speed sampling point calibration module 3;

[0037] The high-speed sampling point calibration module 3 is used for performing integer sampling point calibration processing on the zero intermediate frequency signal received from the wideband digital down conversion module 2, and sending the signal after integer sampling point calibration to the high-speed calibration synthesis module 5;

[0038] The beam coefficient cache module 4 is used for receiving and caching calibration synthesis coefficients, and sending the cached calibration synthesis coefficients to the high-speed calibration synthesis module 5;

[0039] The high-speed calibration synthesis module 5 is used for loading the calibration synthesis coefficients on the signal after integer sampling point calibration sent by the high-speed sampling point calibration module 3, performing phase and fractional point delay calibration on the signal after integer sampling point calibration, performing synthesis processing on the signal after calibration, performing FFT frequency domain conversion processing on the signal in block floating point mode during synthesis, sending the data after frequency domain conversion and block floating point factors to the high-speed frequency domain inter-board synchronous data exchange module 7, receiving frequency domain data sent by other board cards received by the high-speed frequency domain inter-board synchronous data exchange module 7, and performing primary synthesis on the frequency domain data of each board card; the high-speed calibration synthesis module 5 is also used for sending the primary synthesis data to the high-speed frequency domain intra-board synchronous data exchange module 8, receiving primary synthesis data of another FPGA in the board card received by the high-speed frequency domain intra-board synchronous data exchange module 8, performing secondary synthesis, and sending the secondary synthesis data to the high-speed serial transceiver interface module 1;

[0040] The synchronous signal generation and forwarding module 6 is used for generating a synchronization pulse for synchronization processing with other FPGAs, and sending the synchronization pulse to each module respectively;

[0041] The high-speed frequency domain inter-board synchronous data exchange module 7 is configured to receive the frequency domain converted data and the block floating factor sent by the high-speed calibration and synthesis module 5 and the synchronization pulse generated by the synchronization signal generation and forwarding module 6, and to synchronize and pack the frequency domain converted data and the block floating factor with the synchronization pulse as a reference, and to send the packed data to the high-speed interface module 9; and is further configured to receive the frequency domain converted data and the block floating factor of other boards sent by the high-speed interface module 9, to compensate the spectrum amplitude through the block floating factor, and to send the compensated frequency domain data to the high-speed calibration and synthesis module 5.

[0042] The high-speed frequency domain intra-board synchronous data exchange module 8 is configured to receive the primary synthesis data sent by the high-speed calibration and synthesis module 5 and the synchronization pulse generated by the synchronization signal generation and forwarding module 6, to synchronize and pack the primary synthesis data with the synchronization pulse as a reference, and to send the packed data to the high-speed interface module 9, and is further configured to receive the primary synthesis data input by another FPGA in the board sent by the high-speed interface module 9, and to send the primary synthesis data to the high-speed calibration and synthesis module 5.

[0043] As shown in Figure 2 , the high-speed serial transceiver interface module 1 comprises a high-speed sampling data receiving module 101 and a high-speed data sending module 102, and the two modules share the same high-speed interface resource; the high-speed sampling data receiving module 101 uses the receiving end of the high-speed interface and adopts the JESD204B protocol, and the high-speed data sending module 102 uses the sending end of the high-speed interface and adopts the AURORA64 / 66B protocol.

[0044] The high-speed sampling data receiving module 101 is configured to receive the high-speed sampling data transmitted by the high-speed sampling board and to send the high-speed sampling data to the wideband digital down-conversion module 2; and the high-speed data sending module 102 is configured to receive the secondary synthesis data generated by the high-speed calibration and synthesis module 5 and to send the secondary synthesis data to the photoelectric conversion interface through the backplane.

[0045] The synchronization signal generation and forwarding module 6 generates a synchronization pulse with the synchronization reference pulse of the sampling card as a reference, and the synchronization pulse is synchronized with the synchronization pulse generated by the synchronization signal generation and forwarding module in the sampling data and the FPGA in each slot, and is sent to the high-speed serial transceiver interface module 1, the wideband digital down-conversion module 2, the high-speed sampling point calibration module 3, the beam coefficient cache module 4, the high-speed calibration and synthesis module 5, the high-speed frequency domain inter-board synchronous data exchange module 7, the high-speed frequency domain intra-board synchronous data exchange module 8 and the high-speed interface module 9.

[0046] As shown in Figure 3 , the high-speed frequency domain inter-board synchronous data exchange module 7 comprises a high-speed inter-board data packing module 701, a high-speed inter-board data synchronization processing module 702 and a high-speed inter-board data unpacking module 703.

[0047] The high-speed inter-board data packing module 701 is used for receiving the frequency domain converted data and the block floating factor sent by the high-speed calibration synthesis module 5, packing the two kinds of data, and sending the packed data to the high-speed inter-board data synchronization processing module 702.

[0048] The high-speed inter-board data synchronization processing module 702 is used for receiving the synchronization pulse generated by the synchronization signal generation and forwarding module 6 and the packed data of the high-speed inter-board data packing module 701, synchronously processing the packed data with reference to the synchronization pulse, and sending the synchronized data to the high-speed interface module 9.

[0049] The high-speed inter-board data unpacking module 703 is used for receiving the frequency domain converted data and the block floating factor of another board sent by the high-speed interface module 9, compensating the frequency spectrum amplitude with reference to the block floating factor, and sending the compensated frequency domain data to the high-speed calibration synthesis module 5.

[0050] As shown in Figure 4 The high-speed inter-board data packing module 701 is used for receiving the frequency domain converted data and the block floating factor sent by the high-speed calibration synthesis module 5, packing the two kinds of data, and sending the packed data to the high-speed inter-board data synchronization processing module 702.

[0051] The high-speed inter-board data packing module 801 is used for receiving the primary synthesis data sent by the high-speed calibration synthesis module 5, and packing the data.

[0052] The high-speed inter-board data synchronization processing module 802 is used for receiving the synchronization pulse generated by the synchronization signal generation and forwarding module 6 and the packed data of the high-speed inter-board data packing module 801, synchronously processing the packed data with reference to the synchronization pulse, and sending the synchronized data to the high-speed interface module 9.

[0053] The high-speed inter-board data unpacking module 803 is used for receiving the primary synthesis data generated by another FPGA in the board sent by the high-speed interface module 9, unpacking the sent primary synthesis data, and sending the unpacked primary synthesis data to the high-speed calibration synthesis module 5.

Claims

1. A frequency domain beam synthesis device based on FPGA implementation, comprising a high-speed serial transceiver interface module (1), a wideband digital down conversion module (2), a high-speed sampling point calibration module (3), a beam coefficient cache module (4) and a high-speed interface module (9), characterized in that, It also includes high-speed calibration synthesis module (5), synchronous signal generation forwarding module (6), high-speed frequency domain inter-board synchronous data exchange module (7) and high-speed frequency domain intra-board synchronous data exchange module (8); High-speed serial transceiver interface module (1) is used for receiving high-speed sampling data transmitted by high-speed sampling board card and sending it into wideband digital down conversion module (2), and also used for sending secondary synthesis data sent by high-speed calibration synthesis module (5) to photoelectric conversion interface; Wideband digital down conversion module (2) is used for carrying out quadrature digital down conversion processing on high-speed sampling data sent by high-speed serial transceiver interface module (1), and sending zero intermediate frequency signal after quadrature down conversion into high-speed sampling point calibration module (3); High-speed sampling point calibration module (3) is used for carrying out integer sampling point calibration processing on zero intermediate frequency signal received from wideband digital down conversion module (2), and sending signal after completing integer sampling point calibration into high-speed calibration synthesis module (5); Beam coefficient cache module (4) is used for receiving calibration synthesis coefficients and carrying out caching, and sending cached calibration synthesis coefficients into high-speed calibration synthesis module (5); High-speed calibration synthesis module (5) is used for loading calibration synthesis coefficients on signal after completing integer sampling point calibration sent by high-speed sampling point calibration module (3), and carrying out phase and fractional point delay calibration on signal after integer sampling point calibration, carrying out synthesis processing on calibration completed signal, using block floating point mode to carry out FFT frequency domain conversion processing on signal during synthesis, and sending data after completing frequency domain conversion and block floating point factor into high-speed frequency domain inter-board synchronous data exchange module (7), while receiving frequency domain data sent by other board cards received by high-speed frequency domain inter-board synchronous data exchange module (7), carrying out primary synthesis on frequency domain data of each board card, and also used for sending primary synthesis data into high-speed frequency domain intra-board synchronous data exchange module (8), while receiving primary synthesis data of another piece of FPGA in the board card received by high-speed frequency domain intra-board synchronous data exchange module (8), carrying out secondary synthesis, and sending secondary synthesized data into high-speed serial transceiver interface module (1); Synchronous signal generation forwarding module (6) is used for generating synchronous pulses for synchronous processing with other FPGAs, and sending them into other modules respectively; High-speed frequency domain inter-board synchronous data exchange module (7) is used for receiving frequency domain converted data and block floating point factor sent by high-speed calibration synthesis module (5) and synchronous pulses generated by synchronous signal generation forwarding module (6), and carrying out synchronous packaging on frequency domain converted data and block floating point factor with synchronous pulses as reference, and sending packaged data into high-speed interface module (9); it is also used for receiving frequency domain converted data and block floating point factor of other board cards sent by high-speed interface module (9), and compensating spectrum amplitude through block floating point factor, and sending compensated frequency domain data into high-speed calibration synthesis module (5); The high-speed frequency domain intra-board synchronous data exchange module (8) is configured to receive the primary synthesis data sent by the high-speed calibration synthesis module (5) and the synchronization pulse generated by the synchronization signal generation and forwarding module (6), to synchronize and pack the primary synthesis data with the synchronization pulse as a reference, to send the packed data to the high-speed interface module (9), and to receive the primary synthesis data input by another FPGA in the board card and sent by the high-speed interface module (9), and to send the primary synthesis data to the high-speed calibration synthesis module (5).

2. The frequency domain beam synthesizing device based on FPGA implementation according to claim 1, characterized in that, The high-speed serial transceiver interface module (1) comprises a high-speed sampling data receiving module (101) and a high-speed data sending module (102), and the two modules share the same high-speed interface resource; the high-speed sampling data receiving module (101) uses the receiving end of the high-speed interface and adopts the JESD204B protocol, and the high-speed data sending module (102) uses the sending end of the high-speed interface and adopts the AURORA64 / 66B protocol. The high-speed sampling data receiving module (101) is configured to receive the high-speed sampling data transmitted by the high-speed sampling board card and send the high-speed sampling data to the wideband digital down-conversion module (2); and the high-speed data sending module (102) is configured to receive the secondary synthesis data generated by the high-speed calibration synthesis module (5) and send the secondary synthesis data to the photoelectric conversion interface through the backplane.

3. The frequency domain beam synthesizing device based on FPGA implementation according to claim 1, characterized in that, The high-speed frequency domain inter-board synchronous data exchange module (7) comprises a high-speed inter-board data packing module (701), a high-speed inter-board data synchronization processing module (702) and a high-speed inter-board data unpacking module (703). The high-speed inter-board data packing module (701) is configured to receive the frequency domain converted data and the block floating factor sent by the high-speed calibration synthesis module (5), to pack the two kinds of data, and to send the packed data to the high-speed inter-board data synchronization processing module (702). The high-speed inter-board data synchronization processing module (702) is configured to receive the synchronization pulse generated by the synchronization signal generation and forwarding module (6) and the packed data of the high-speed inter-board data packing module (701), to synchronize and process the packed data with the synchronization pulse as a reference, and to send the synchronized data to the high-speed interface module (9). The high-speed inter-board data unpacking module (703) is configured to receive the frequency domain converted data and the block floating factor of other board cards sent by the high-speed interface module (9), to compensate the spectral amplitude with reference to the block floating factor, and to send the compensated frequency domain data to the high-speed calibration synthesis module (5).

4. The frequency domain beam synthesizing device based on FPGA implementation according to claim 1, characterized in that, The high-speed frequency domain intra-board synchronous data exchange module (8) comprises a high-speed intra-board data packing module (801), a high-speed intra-board data synchronization processing module (802) and a high-speed intra-board data unpacking module (803). The high-speed intra-board data packing module (801) is configured to receive the primary synthesis data sent by the high-speed calibration synthesis module (5) and to pack the primary synthesis data, and to send the packed data to the high-speed intra-board data synchronization processing module (802). The high-speed intra-board data synchronization processing module (802) is configured to receive the synchronization pulse generated by the synchronization signal generation and forwarding module (6) and the packaged data generated by the high-speed intra-board data packaging module (801), and perform synchronization processing on the packaged data with reference to the synchronization pulse. The synchronized data is sent to the high-speed interface module (9). The high-speed intra-board data unpacking module (803) is configured to receive the primary synthesis data generated by another FPGA in the board card and perform unpacking processing on the received primary synthesis data. The unpacked primary synthesis data is sent to the high-speed calibration synthesis module (5).

5. The frequency domain beam synthesizing device based on FPGA implementation according to claim 1, characterized in that, The synchronization signal generation and forwarding module (6) generates a synchronization pulse with reference to the synchronization reference pulse of the sampling card. The synchronization pulse is synchronized with the sampling data and the synchronization pulses generated by the synchronization signal generation and forwarding modules in the FPGAs of the other slots. The synchronization pulse is sent to the high-speed serial transceiver interface module (1), the wideband digital down conversion module (2), the high-speed sampling point calibration module (3), the beam coefficient cache module (4), the high-speed calibration synthesis module (5), the high-speed frequency domain inter-board synchronization data exchange module (7), the high-speed frequency domain intra-board synchronization data exchange module (8) and the high-speed interface module (9).

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