A SATA signal quality testing method, device and storage medium

Abstract

The present invention relates to a SATA signal quality test method, device and storage medium. In the process of writing a test code, the transmitting end of the SATA main control chip independently and gradually adjusts the voltage and time of the sending signal. The transmitting end of the SATA main control chip uses the sending signal to write a test code to a SATA hard disk connected to the SATA main control chip. The SATA main control chip reads the test code from the SATA hard disk, and compares the test code written and read at each voltage and time to obtain the error code; the receiving end of the SATA main control chip records the error code between the test code written and read at each voltage and time to form a test eye diagram, and evaluates the SATA signal quality according to the test eye height and test eye width of the test eye diagram. The present application plugs in a SATA hard disk to realize the entire test process. The test process can take into account the influence of the SATA hard disk, and the test results obtained are close to the actual working conditions.

Description

Technical Field

[0001] The present invention relates to the technical field of SATA signal testing, and in particular to a SATA signal quality testing method, device and storage medium. Background Art

[0002] The current signal testing method for the SATA interface standard includes: using a bit error tester to perform a jitter tolerance test on the SATA interface.

[0003] like Figure 1 As shown, the test connects the SATA interface to the bit error tester. The test process is as follows: Set the SATA main control chip on the motherboard or SATA backplane to enter the Rx BIST loopback mode. In this mode, the SATA main control chip sends the data received at Rx to the bit error tester through Tx. During the test, the bit error tester sends the test pattern to the Rx of the SATA interface to be tested through its own Tx, and adds jitter to the test pattern signal to verify the ability of the interface to be tested to receive signals; the SATA main control chip sends the data received at Rx to the Rx of the bit error tester through Tx. The bit error tester Rx compares the received pattern with the sent test pattern, calculates the bit error rate, and then evaluates the signal quality of the SATA interface to be tested. The test point is the position of the interface to be tested. There is a PCB trace from the ideal test position (inside the SATA main control chip), which will cause the test result to be inaccurate; the entire test process does not consider the impact of the hard disk, and no hard disk is added during the test process. It is impossible to test the quality of the SATA receiving end signal when the SATA main control chip and the hard disk are working under real usage conditions. Summary of the invention

[0004] In order to solve the above technical problem or at least partially solve the above technical problem, the present invention provides a SATA signal quality test method, device and storage medium.

[0005] In the first aspect, the present invention provides a SATA signal quality test method, including: in the process of writing a test code, the transmitting end of the SATA master control chip independently and gradually adjusts the voltage and time of the transmission signal, and the transmitting end of the SATA master control chip uses the transmission signal to write the test code to the SATA hard disk connected to the SATA master control chip; the receiving end of the SATA master control chip reads the test code from the SATA hard disk, compares the test code written and read at each voltage and time to obtain the error situation and records the error situation to form a test eye diagram, and evaluates the SATA signal quality according to the test eye height and test eye width of the test eye diagram. Furthermore, the transmitting end of the SATA master control chip independently and gradually adjusts the voltage and time of the transmission signal, including:

[0006] Encapsulate the voltage value and time delay of the transmitted signal into test points;

[0007] Arrange the test points in order to form a test domain, wherein the time delay between any two adjacent test points in the horizontal direction gradually increases or decreases, and the voltage value between any two adjacent test points in the vertical direction gradually increases or decreases;

[0008] The test domain is traversed to obtain the test points, and a sending signal is adjusted according to the voltage value and time delay in the test points.

[0009] Furthermore, the voltage value is adjusted to make the transmission signal move in the vertical direction, and the time delay is adjusted to make the transmission signal move in the horizontal direction.

[0010] Furthermore, the receiving end of the SATA master control chip compares the test codes written and read at each voltage and time to obtain a bit error condition and records the bit error condition to form a test eye diagram, including:

[0011] The SATA master control chip receiving end maintains a test eye diagram domain, the time delay corresponding to any two adjacent points in the horizontal direction of the test eye diagram domain gradually increases or decreases, and the voltage value corresponding to any two adjacent points in the vertical direction of the test eye diagram domain gradually increases or decreases;

[0012] The receiving end of the SATA master control chip compares the test codes written and read under the same voltage value and time delay, and calculates the bit error rate between the two;

[0013] If the bit error rate is 0, the corresponding point in the test eye diagram domain is recorded as success; if the bit error rate is not 0, the corresponding point in the test eye diagram domain is recorded as failure, and the area composed of successful points in the test eye diagram domain is the effective area of ​​the eye diagram.

[0014] Furthermore, the receiving end of the SATA master control chip compares the test codes written and read under the same voltage value and time delay, including:

[0015] Matching the original test code to be compared from the second mapping relationship according to the voltage value of the sending signal and the time delay, obtaining the logic address of the target test code to be compared from the third mapping relationship, and then reading the target test code according to the logic address;

[0016] Comparing the original test code with the target test code realizes comparing the test codes written and read under the same voltage value and time delay.

[0017] Furthermore, in the process of writing the test code, a first mapping relationship is established between the original test code and the corresponding logical address, and a second mapping relationship is established between the original test code and the corresponding sending signal voltage value and time delay. According to the first mapping relationship and the second mapping relationship, a third mapping relationship between the voltage value and time delay of the sending signal and the logical address is obtained.

[0018] Furthermore, the test eye width is obtained by multiplying the number of points contained in the longest row of the effective area of ​​the eye diagram by the step time of the time delay; and the test eye height is obtained by multiplying the number of points contained in the longest column of the effective area of ​​the eye diagram by the step voltage of the voltage value.

[0019] Furthermore, an eye width threshold and an eye height threshold are preset as detection indicators, and the eye width threshold and the test eye width, and the eye height threshold and the test eye height are compared. If the test eye height and the test eye width both meet the requirements, the SATA signal quality test passes.

[0020] In a second aspect, the present invention provides a SATA signal quality testing device, characterized in that it includes: a SATA master control chip, the SATA master control chip is connected to a SATA hard disk via a SATA bus, the SATA master control chip is connected to a storage medium storing a computer program, and the computer program implements the SATA signal quality testing method when executed by the SATA master control chip.

[0021] In a third aspect, the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program implements the SATA signal quality test method when executed by a SATA master control chip.

[0022] The above technical solution provided by the embodiment of the present invention has the following advantages compared with the prior art:

[0023] The SATA master chip of the present application adjusts the voltage value and time delay of the transmission signal during the process of writing the test code to the SATA hard disk to change the size of the horizontal and vertical directions of the transmission signal, and gradually scans out the test eye diagram. The receiving end of the SATA master chip reads the test code from the SATA hard disk, compares the test code written and read at each voltage and time to obtain the bit error situation and records the bit error situation to form a test eye diagram, and evaluates the SATA signal quality according to the test eye length and test eye width of the test eye diagram. The larger the eye length and eye width, the better the signal quality, and vice versa, the worse the signal quality. The present application plugs in the SATA hard disk used during normal operation to realize the entire test process, so that the test process can take into account the influence of the SATA hard disk and obtain test results close to the actual working conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention.

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0026] Figure 1 The schematic diagram of the circuit structure of the existing bit error meter for measuring the quality of SATA signals;

[0027] Figure 2 A schematic diagram of a SATA signal quality testing device provided by an embodiment of the present invention;

[0028] Figure 3 A flow chart of a SATA signal quality testing method provided by an embodiment of the present invention;

[0029] Figure 4 A schematic diagram of a test domain provided by an embodiment of the present invention;

[0030] Figure 5 A flowchart of independently and gradually adjusting the voltage and time of a sending signal provided in an embodiment of the present invention, and using the adjusted sending signal to write a test code to a SATA hard disk connected to the SATA master control chip;

[0031] Figure 6 A flowchart of comparing the test codes written and read at each voltage and time to obtain bit error conditions and recording the bit error conditions to form a test eye diagram provided by an embodiment of the present invention;

[0032] Figure 7 A schematic diagram of a test eye diagram domain provided by an embodiment of the present invention;

[0033] Figure 8 A flow chart for evaluating the quality of a SATA signal according to a test eye height and a test eye width of a test eye diagram provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0036] Example 1

[0037] An embodiment of the present invention provides a SATA signal quality testing method. In the SATA signal quality testing method, a SATA main control chip is controlled to write a test code to a SATA hard disk connected to the SATA main control chip, the SATA main control chip reads the test code from the SATA hard disk, and the written and read test codes are compared to obtain a bit error situation; in the process of writing the test code, a sending end of the SATA main control chip independently and stepwise adjusts the voltage and time of a sending signal, a receiving end of the SATA main control chip records the bit error situation corresponding to the voltage and time to form a test eye diagram, and the SATA signal quality is evaluated according to the test eye height and the test eye width of the test eye diagram.

[0038] Compared with the existing method of testing the SATA signal quality by detecting the bit error rate through a bit error meter, refer to Figure 2 As shown, in the SATA signal quality test method, the SATA interface on the motherboard or SATA backplane is connected to the SATA hard disk through the SATA link, and the entire test process is performed by the SATA main control chip. The SATA hard disk used in the normal operation process is plugged in to realize the entire test process, so that the test process can take into account the influence of the SATA hard disk and obtain the test results close to the actual working conditions.

[0039] During the specific implementation process, see Figure 3 As shown, the steps of the SATA signal quality testing method include:

[0040] S100, during the process of writing the test code, the transmitting end of the SATA master chip independently and gradually adjusts the voltage and time of the transmitting signal, and uses the adjusted transmitting signal to write the test code to the SATA hard disk connected to the SATA master chip. Figure 5 As shown, step S100 includes:

[0041] S101, encapsulate the voltage value and time delay of the sending signal used to write the test code to the SATA hard disk into a test point. Specifically, the voltage value and time delay are encapsulated in the form of an array to obtain the test point, such as: [voltage value 00 , time delay 00 ]……

[0042] S102, arranging the test points in order into a test domain, wherein the time delay between any two adjacent test points in the horizontal direction gradually increases or decreases, and a constant step time is used when the time delay increases or decreases. The voltage value between any two adjacent test points in the vertical direction gradually increases or decreases; a constant step voltage is used when the voltage value increases or decreases. Figure 4 As shown, the data format of the formed test domain is: [

[0044] [[Voltage value 00 , time delay 00 ], ... [voltage value 0y , time delay 0y ]],

[0045] [[Voltage value 10 , time delay 10 ], ... [voltage value 1y , time delay 1y ]],

[0046] …

[0047] [[Voltage value x0 , time delay x0 ], ... [voltage value xy , time delay xy ]], ]

[0049] The dimensions of the test domain are x+1 rows and y+1 columns.

[0050] S103, the sending end of the SATA master control chip traverses each row and each column of the test domain to obtain the test point.

[0051] S104, the transmitting end of the SATA master control chip adjusts the transmission signal according to the voltage value and time delay in the test point obtained by traversal, and uses the adjusted transmission signal to write a test code to the SATA hard disk connected to the SATA master control chip. The voltage value is adjusted by traversing the test points in the test domain so that the transmission signal moves in the vertical direction, and the time delay is adjusted by traversing the test points in the test domain so that the transmission signal moves in the horizontal direction.

[0052] S200, in the process of the transmitting end of the SATA master chip writing the test code to the SATA hard disk, the SATA master chip records the voltage value and time delay of the transmission signal used to transmit the original test code, and records and stores the original logical address of the test code. Through this process, a first mapping relationship between the original test code and the corresponding logical address is established, and a second mapping relationship between the original test code and the corresponding voltage value and time delay of the transmission signal is established. According to the first mapping relationship and the second mapping relationship, a third mapping relationship between the voltage value and time delay of the transmission signal and the logical address can be obtained.

[0053] S300, the receiving end of the SATA master control chip reads the test code from the SATA hard disk, and uses the first mapping relationship, the second mapping relationship and the third mapping relationship to compare the test code written and read at each voltage and time to obtain the bit error situation and record the bit error situation to form a test eye diagram.

[0054] During the specific implementation process, see Figure 6 As shown, step S300 includes:

[0055] S301, the SATA master chip receiving end maintains the test eye diagram domain. Figure 7 As shown, the specification of the test eye diagram domain is consistent with the test domain, both of which are x+1 rows and y+1 columns, and each point in the test eye diagram domain corresponds to the test point in the test domain one by one. That is, the time delay corresponding to any two adjacent points in the horizontal direction of the test eye diagram domain gradually increases or decreases, and the step time is used when the time delay increases or decreases, and the voltage value corresponding to any two adjacent points in the vertical direction of the test eye diagram domain gradually increases or decreases, and the step voltage is used when the voltage value increases or decreases.

[0056] Each point in the test eye diagram domain is used to record the bit error situation. Specifically, if the bit error rate is 0, the corresponding point in the test eye diagram domain is recorded as success (Pass); if the bit error rate is not 0, the corresponding point in the test eye diagram domain is recorded as failure (Fail), and the area composed of successful points in the test eye diagram domain is the effective area of ​​the eye diagram. Figure 7 In the figure, the diamond area recording the Pass is the effective area of ​​the eye diagram.

[0057] S302, the receiving end of the SATA master control chip compares the test codes written and read under the same voltage value and time delay to obtain the bit error situation. In the specific implementation process, the receiving end of the SATA master control chip uses the voltage value and time delay of the original test code's sending signal to obtain the original test code to be compared from the second mapping relationship. The receiving end of the SATA master control chip uses the voltage value and time delay of the original test code's sending signal to be compared to match the logical address from the third mapping relationship, and then reads the target test code according to the logical address. Thus, the test code written and read under the same voltage value and time delay is obtained by using the third mapping relationship and the second mapping relationship. Specifically, the receiving end of the SATA master control chip compares the test codes written and read under the same voltage value and time delay, and calculates the bit error rate between the two.

[0058] S303, detecting whether the bit error rate is 0, if the bit error rate is 0, executing S304, if the bit error rate is not 0, executing S305.

[0059] S304, recording the corresponding point in the test eye diagram domain as successful;

[0060] S305, recording the corresponding point in the test eye diagram domain as failure.

[0061] S400, evaluates the SATA signal quality based on the test eye height and test eye width of the test eye diagram. Figure 8 As shown, the step S400 includes:

[0062] S401, presetting an eye width threshold and an eye height threshold as detection indicators.

[0063] S402, obtain the test eye width and test eye height according to the test eye diagram domain. Specifically, the area composed of successful points in the test eye diagram domain is the effective area of ​​the eye diagram. The test eye width is obtained by multiplying the number of points contained in the longest row of the effective area of ​​the eye diagram by the step time of the time delay, and the test eye height is obtained by multiplying the number of points contained in the longest column of the effective area of ​​the eye diagram by the step voltage of the voltage value.

[0064] S403, comparing the eye width threshold and the test eye width, the eye height threshold and the test eye height, to detect whether the test eye height and the test eye width meet the requirements, if yes, execute S404, otherwise execute S405.

[0065] S404, SATA signal quality test passed.

[0066] S405, SATA signal quality test failed.

[0067] Example 2

[0068] See also Figure 2 As shown, an embodiment of the present invention provides a SATA signal quality testing device, comprising: a SATA main control chip, the SATA main control chip is connected to a SATA hard disk through a SATA bus, the SATA main control chip is connected to a storage medium storing a computer program, and the computer program is executed by the SATA main control chip to implement the SATA signal quality testing method, comprising: in the process of writing a test code, the sending end of the SATA main control chip independently and stepwise adjusts the voltage and time of the sending signal, the sending end of the SATA main control chip uses the sending signal to write a test code to the SATA hard disk connected to the SATA main control chip; the receiving end of the SATA main control chip reads the test code from the SATA hard disk, compares the test code written and read under each voltage and time to obtain a bit error situation and records the bit error situation to form a test eye diagram, and evaluates the SATA signal quality according to the test eye height and test eye width of the test eye diagram.

[0069] Example 3

[0070] An embodiment of the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a SATA master control chip, the SATA signal quality test method is implemented, comprising: in the process of writing a test code, a sending end of the SATA master control chip independently and stepwise adjusts the voltage and time of a sending signal, and the sending end of the SATA master control chip uses the sending signal to write a test code to a SATA hard disk connected to the SATA master control chip; a receiving end of the SATA master control chip reads the test code from the SATA hard disk, compares the test code written and read under each voltage and time to obtain a bit error situation, records the bit error situation to form a test eye diagram, and evaluates the SATA signal quality according to the test eye height and test eye width of the test eye diagram.

[0071] In the embodiments provided by the present invention, it should be understood that the disclosed structures and methods can be implemented in other ways. For example, the structural embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, structures or units, which can be electrical, mechanical or other forms.

[0072] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0073] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0074] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A SATA signal quality test method, It is characterized in that include: In the process of writing the test code, the transmitting end of the SATA main control chip independently and gradually adjusts the voltage and time of the sending signal, and the transmitting end of the SATA main control chip uses the sending signal to write the test code to the SATA hard disk connected to the SATA main control chip; the receiving end of the SATA main control chip reads the test code from the SATA hard disk, compares the test code written and read under each voltage and time to obtain the error situation and records the error situation to form a test eye diagram, including: the receiving end of the SATA main control chip maintains the test eye diagram domain, the time delay corresponding to any two adjacent points in the horizontal direction of the test eye diagram domain gradually increases or decreases, and the voltage value corresponding to any two adjacent points in the vertical direction of the test eye diagram domain gradually increases or decreases; the receiving end of the SATA main control chip compares the test code written and read under the same voltage value and time delay, and calculates the bit error rate between the two; if the bit error rate is 0, the corresponding point in the test eye diagram domain is recorded as success; if the bit error rate is not 0, the corresponding point in the test eye diagram domain is recorded as failure, and the area composed of successful points in the test eye diagram domain is the effective area of ​​the eye diagram; Evaluate SATA signal quality based on the test eye height and test eye width of the test eye diagram.

2. The SATA signal quality testing method according to claim 1, It is characterized in that The sending end of the SATA master control chip independently and gradually adjusts the voltage and time of the sending signal, including: Encapsulate the voltage value and time delay of the transmitted signal into test points; Arrange the test points in order to form a test domain, wherein the time delay between any two adjacent test points in the horizontal direction gradually increases or decreases, and the voltage value between any two adjacent test points in the vertical direction gradually increases or decreases; The test domain is traversed to obtain the test points, and a sending signal is adjusted according to the voltage value and time delay in the test points.

3. The SATA signal quality testing method according to claim 2, It is characterized in that The voltage value is adjusted to move the transmission signal in the vertical direction, and the time delay is adjusted to move the transmission signal in the horizontal direction.

4. The SATA signal quality testing method according to claim 1, It is characterized in that The receiving end of the SATA master control chip compares the test codes written and read under the same voltage value and time delay, including: Matching the original test code to be compared from the second mapping relationship according to the voltage value of the sending signal and the time delay, obtaining the logical address of the target test code to be compared from the third mapping relationship, and then reading the target test code according to the logical address; Comparing the original test code with the target test code realizes comparing the test codes written and read under the same voltage value and time delay.

5. The SATA signal quality testing method according to claim 4, It is characterized in that During the process of writing the test code, a first mapping relationship is established between the original test code and the corresponding logical address, and a second mapping relationship is established between the original test code and the corresponding sending signal voltage value and time delay. According to the first mapping relationship and the second mapping relationship, a third mapping relationship between the voltage value and time delay of the sending signal and the logical address is obtained.

6. The SATA signal quality testing method according to claim 1, It is characterized in that The test eye width is obtained by multiplying the number of points contained in the longest row of the effective area of ​​the eye diagram by the step time of the time delay; the test eye height is obtained by multiplying the number of points contained in the longest column of the effective area of ​​the eye diagram by the step voltage of the voltage value.

7. The SATA signal quality testing method according to claim 1, It is characterized in that An eye width threshold and an eye height threshold are preset as detection indicators, and the eye width threshold and the test eye width are compared, and the eye height threshold and the test eye height are compared. If the test eye height and the test eye width both meet the requirements, the SATA signal quality test passes.

8. A SATA signal quality test device, It is characterized in that include: A SATA master control chip, wherein the SATA master control chip is connected to a SATA hard disk via a SATA bus, and the SATA master control chip is connected to a storage medium storing a computer program, and when the computer program is executed by the SATA master control chip, the SATA signal quality test method according to any one of claims 1 to 7 is implemented.

9. A computer-readable storage medium storing a computer program, It is characterized in that When the computer program is executed by the SATA master control chip, the SATA signal quality testing method as described in any one of claims 1 to 7 is implemented.

Images