A flow processing system and method

Abstract

The embodiment of the present invention provides a traffic processing system and method, which relates to the field of communication, wherein a receiving module receives data, an on-chip cache module stores the data, a queue number generating module generates a queue number for the data, and sends the data to the corresponding queue. Based on the number of descriptor information sent to each queue and the length threshold corresponding to the queue, the descriptor information exceeding the length threshold is added to the DMA queue. The queue scheduling module schedules the descriptor information in different queues based on the scheduling rule. The data output module receives the descriptor information, obtains the corresponding data to be processed from the on-chip cache module based on the descriptor information, and outputs the data to be processed. The external large-capacity cache particles are used to temporarily store the data corresponding to the descriptor information in the DMA queue. This avoids packet loss when burst traffic occurs.

Description

Technical Field

[0001] The present invention relates to the field of communications, and in particular to a traffic processing system and method. Background Art

[0002] In the prior art, in order to control chip area / cost, the on-chip cache specifications of the switching chip are generally limited. For example, the on-chip cache of a common access switching chip is between 1 and 2 MB. In the scenario of network traffic bursts, for example, multiple input ports send traffic to one output port. Since the output bandwidth is smaller than the input bandwidth, the burst input network traffic needs to be temporarily stored in the on-chip cache. Due to the limited on-chip cache capacity, burst network traffic causes packet loss, which ultimately affects the traffic processing effect. Summary of the invention

[0003] The object of the present invention is to provide a traffic processing system and method, which can process burst network traffic and avoid packet loss of burst traffic.

[0004] In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:

[0005] In a first aspect, an embodiment of the present application provides a traffic processing system, the system comprising:

[0006] Data receiving module, queue number generating module, queue scheduling module, data output module, external large-capacity cache particles, on-chip cache module;

[0007] The receiving module is used to receive data;

[0008] The on-chip cache module is used to store data;

[0009] The queue number generating module is used to generate a queue number according to the real destination port in the descriptor information of the data, send the descriptor information corresponding to the data to the corresponding queue based on the queue number, determine the number of descriptor information sent to each queue and the length threshold of the queue, and add the descriptor information exceeding the length threshold to the DMA queue, wherein the descriptor information of the data includes the real destination port of the data;

[0010] The queue scheduling module is used to schedule the descriptor information in different queues based on the scheduling rules;

[0011] The data output module is used to receive the descriptor information scheduled by the queue scheduling module, obtain the corresponding to-be-processed data from the on-chip cache module based on the scheduled descriptor information, and output the to-be-processed data;

[0012] The external large-capacity cache particle is used to temporarily store data corresponding to the descriptor information in the DMA queue.

[0013] In an optional embodiment, the queue number generating module is also used to compare the length of each queue with a length threshold corresponding to the queue. When the length of the queue is equal to the length threshold, the state of the queue is set to a congested state. When the first data sent to the congested state is received from the data receiving module, the descriptor information of the first data is added to the DMA queue.

[0014] In an optional embodiment, the system further comprises a DMA;

[0015] The DMA is used to transmit the received data whose destination port is DMA;

[0016] The DMA is further used to send first data to an external large-capacity cache particle, wherein the first data is data sent to a target queue, and the target queue is a queue in a congested state.

[0017] In an optional implementation manner, the queue number generating module is further used to update the storage enable in the descriptor information of the first data to temporary storage, and add the destination port as DMA in the descriptor information of the first data.

[0018] In an optional embodiment, the system further includes a CPU;

[0019] The CPU is used to determine the storage space of the on-chip cache module, and after detecting that the storage space of the target queue is released, obtain the second data corresponding to the target queue from the external large-capacity cache particles, and send the second data to the data receiving module, wherein the on-chip cache module includes different storage spaces, and the different storage spaces are used to store data corresponding to the descriptor information in queues other than the DMA queue.

[0020] In an optional implementation, the data receiving module sends the second data to the queue number generating module, and the queue number generating module sends the descriptor information corresponding to the second data to the target queue.

[0021] In an optional implementation manner, the external large-capacity cache particles are also used to determine the storage quantity of data of different external queues in real time;

[0022] The data receiving module is also used to receive new data. When the storage quantity of the target plug-in queue stored in the plug-in large-capacity cache particles is cleared and the queue length of the target queue is less than the length threshold, the descriptor information corresponding to the new data is sent to the target queue of the queue number generating module, and the congestion state of the target queue is updated to a non-congested state, wherein the target plug-in queue is consistent with the queue number of the target queue.

[0023] In an optional embodiment, the data output module is specifically used to: receive the descriptor information to be processed scheduled by the queue scheduling module, obtain the data to be processed from the on-chip cache module based on the descriptor information to be processed, determine the real destination port of the data to be processed based on the descriptor information to be processed, and send the data to be processed to the real destination port.

[0024] In an optional implementation, the external large-capacity cache particle includes a double data rate synchronous dynamic random access memory or a quadruple data rate static random access memory.

[0025] In a second aspect, an embodiment of the present application provides a traffic processing method, which processes traffic through the traffic processing system.

[0026] This application has the following beneficial effects:

[0027] The present application designs a traffic processing system, which includes a data receiving module, a queue number generating module, a queue scheduling module, a data output module, an external large-capacity cache particle, and an on-chip cache module. The receiving module is used to receive data, the on-chip cache module is used to store data, the queue number generating module is used to generate a queue number for the data, and the descriptor information of the data is sent to the corresponding queue, the number of descriptor information sent to each queue and the length threshold of the queue are determined, and the descriptor information exceeding the length threshold is added to the DMA queue. The queue scheduling module is used to schedule the descriptor information in different queues based on the scheduling rules, the data output module is used to receive the descriptor information scheduled by the queue scheduling module, and the corresponding data to be processed is obtained from the on-chip cache module based on the scheduled descriptor information, and the data to be processed is output, and the external large-capacity cache particle is used to temporarily store the data corresponding to the descriptor information in the DMA queue. When burst traffic occurs, the burst network traffic is diverted to the external large-capacity cache particle for caching, and then the cached data is looped back to the data receiving module for normal forwarding, so as to meet the requirements of message output order preservation and avoid data packet loss when burst traffic occurs. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the following will describe the technical solution required in the embodiment.

[0029] The accompanying drawings are briefly introduced. It should be understood that the following drawings only illustrate some embodiments of the present invention and should not be regarded as limiting the scope. For ordinary technicians in this field,

[0030] Without any creative effort, other related drawings can be obtained based on these drawings.

[0031] Figure 1 A schematic diagram of the structure of a flow processing system provided by an embodiment of the present invention;

[0032] Figure 2 One of the flow charts of a flow processing method provided by an embodiment of the present invention;

[0033] Figure 3 A second flow chart of a flow processing method provided by an embodiment of the present invention;

[0034] Figure 4 A third flow chart of a flow processing method provided by an embodiment of the present invention;

[0035] Figure 5 A fourth flow chart of a traffic processing method provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0036] To make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the following will be combined with the present invention to

[0037] The accompanying drawings in the embodiments of the present invention clearly and completely describe the technical solutions in the embodiments of the present invention. It is obvious that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments.

[0038] The components of the embodiments of the present invention described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

[0039] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit

[0040] The present invention does not limit the scope of the invention to be protected, but only represents selected embodiments of the present invention. All other embodiments obtained by ordinary technicians in the field without creative work based on the embodiments of the present invention are within the scope of protection of the present invention.

[0041] It should be noted that similar reference numerals and letters denote similar items in the following drawings, and therefore, once an item is defined in one drawing, further definition and explanation thereof is not required in subsequent drawings.

[0042] 5 In the description of the present invention, it should be noted that if the terms "upper", "lower", "inner" and "outer" appear

[0043] The orientations or positional relationships indicated are based on the orientations or positional relationships shown in the drawings, or are the orientations or positional relationships in which the inventive product is usually placed when in use. They are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, they cannot be understood as a limitation on the invention.

[0044] In addition, the terms “first”, “second”, etc., if used, are merely used to distinguish between the descriptions and should not be understood as indicating or implying relative importance.

[0045] In the description of this application, it should also be noted that, unless otherwise clearly specified and limited, the terms "set", "install", "connect", and "connect" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0046] After extensive research, the inventors found that in the prior art, in order to control chip area / cost, the on-chip cache specifications of the switching chip are generally limited. For example, the on-chip cache of a common access switching chip is between 1 and 2 MB. In the scenario of network traffic bursts, for example, multiple input ports send traffic to one output port. Since the output bandwidth is smaller than the input bandwidth, the burst input network traffic needs to be temporarily stored in the on-chip cache. Due to the limited on-chip cache capacity, burst network traffic causes packet loss, which ultimately affects the traffic processing effect.

[0047] In view of the discovery of the above problems, the present embodiment provides a traffic processing system and method, which can be used for receiving data through a receiving module of the traffic processing system, an on-chip cache module of the traffic processing system for storing data, a queue number generating module of the traffic processing system for generating queue numbers for the data, and sending descriptor information based on the data to the corresponding queue, determining the number of descriptor information sent to each queue and the length threshold of the queue, and adding the descriptor information exceeding the length threshold to the DMA queue, a queue scheduling module of the traffic processing system for scheduling the descriptor information in different queues based on scheduling rules, a data output module of the traffic processing system for receiving the descriptor information scheduled by the queue scheduling module, obtaining the corresponding data to be processed from the on-chip cache module based on the scheduled descriptor information, and outputting the data to be processed, and the external large-capacity cache particles of the traffic processing system are used to temporarily store the data corresponding to the descriptor information in the DMA queue. When burst traffic occurs, the burst network traffic is diverted to the external large-capacity cache particles for caching, and then the cached data is looped back to the data receiving module for normal forwarding, meeting the requirements of message output order preservation and avoiding data packet loss when burst traffic occurs. The solution provided in this embodiment is explained in detail below.

[0048] The traffic processing system also includes a traffic processing device, a memory and a processor.

[0049] The memory and processor components are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other via one or more communication buses or signal lines. The flow processing device includes at least one software function module that can be stored in the memory in the form of software or firmware or fixed in the operating system (OS) of the flow processing device. The processor is used to execute executable modules stored in the memory, such as software function modules and computer programs included in the flow processing device.

[0050] The memory may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable read-only memory (EEPROM), etc. The memory is used to store a program, and the processor executes the program after receiving an execution instruction.

[0051] Please refer to Figure 1 , which is a structural diagram of a traffic processing system. The following describes in detail the various modules of the system.

[0052] The system includes: a data receiving module 111, a queue number generating module 112, a queue scheduling module 113, a data output module 114, an external large-capacity cache particle 115, and an on-chip cache module 116;

[0053] The data receiving module 111 is used to receive data; the on-chip cache module 116 is used to store data; the queue number generating module 112 is used to generate a queue number according to the real destination port in the descriptor information of the data, send the descriptor information corresponding to the data to the corresponding queue based on the queue number, determine the number of descriptor information sent to each queue and the length threshold of the queue, and add the descriptor information exceeding the length threshold to the DMA queue, wherein the descriptor information of the data includes the real destination port of the data; the queue scheduling module 113 is used to schedule the descriptor information in different queues based on scheduling rules; the data output module 114 is used to receive the descriptor information scheduled by the queue scheduling module, obtain the corresponding data to be processed from the on-chip cache module based on the scheduled descriptor information, and output the data to be processed; the external large-capacity cache particle 115 is used to temporarily store the data corresponding to the descriptor information in the DMA queue.

[0054] In one example, the traffic processing system also includes DMA117 (Direct Memory Access), which is used to transmit data received by a receiving module whose destination port is DMA. DMA is also used to send first data to an external large-capacity cache particle, where the first data is data sent to a target queue, and the target queue is a queue in a congested state.

[0055] In one example, the data receiving module receives 10 data packets from the interface unit 1, and the data receiving module performs compliance checks on the 10 received data packets. If the data packets that meet the requirements of the rules have sufficient cache space in the on-chip cache module, the data packets are written into the on-chip cache module. The data receiving module determines the descriptor information of each data packet, and the descriptor information includes the length of the data packet, the storage address of the on-chip cache module, the real destination port of the data packet, the priority information, the type of the data packet, etc. The data receiving module sends the descriptor information of the 10 data packets to the queue number generation module.

[0056] The queue number generating module generates queue numbers for the descriptor information corresponding to the 10 data packets based on the real destination ports in the descriptor information of the 10 data packets sent by the data receiving module. When the real destination port of data packets No. 1 to 10 among the 10 data packets is interface unit 2, the queue numbers corresponding to the descriptors corresponding to the 10 data packets are all the queues corresponding to interface unit 2, and the descriptor information corresponding to the 10 data packets is sent to the queue corresponding to interface unit 2.

[0057] In another example, the queue number generating module is based on the real destination port and priority information in the descriptor information of 10 data packets sent by the data receiving module. When the real destination port of data packets 1-10 is interface unit 2, and the priority of data packets 1-7 is the first priority, and the priority of data packets 8-10 is the second priority, the descriptor information of data packets 1-7 is sent to the queue corresponding to the first priority in interface unit 2, and the descriptor information of data packets 8-10 is sent to the queue corresponding to the second priority in interface unit 2.

[0058] Before traffic processing, length thresholds are set in advance for queues with different queue numbers. For example, the length threshold of the queue with queue number interface unit 1 is set to 5. When the number of descriptor information of data packets sent to interface unit 1 exceeds the length threshold, the descriptor information of 6-10 data packets exceeding the length threshold is added to the DMA queue, and the descriptor information of 1-5 data packets is added to the queue corresponding to interface unit 1.

[0059] The queue scheduling module sends the data packets of 6-10 descriptor information in the DMA queue to the external large-capacity cache particles through the DMA channel for temporary storage.

[0060] In one example, when the data receiving unit receives 10 data packets whose real destination port is interface unit 1, the descriptor information of data packets 1-5 is sent to the queue with queue number being interface unit 1, and the length threshold of the queue with queue number being interface unit 1 is 5, data packets 1-5 are stored in the on-chip cache module, and data packets 6-10 are cached in the external large-capacity cache particles. When the queue scheduling module schedules the descriptor information of data packet No. 1 in the queue of interface unit 1, data packet No. 1 is obtained from the on-chip cache module, and data packet No. 1 is output from the data output module. At this time, the storage space originally storing data packet No. 1 is released in the on-chip cache module, and data packet No. 6 in the queue with queue number being interface unit 1 is obtained from the external large-capacity cache particles, and data packet No. 6 is sent to the data receiving module. The data receiving module receives data packet No. 6 and determines the descriptor information of data packet No. 6. The queue number generating module generates a queue number of interface unit 1 for the descriptor information of data packet No. 6 based on the descriptor information of data packet No. 6, and sends the descriptor information corresponding to data packet No. 6 to the queue with queue number as interface unit 1. The descriptor information of data packet No. 6 is arranged after the descriptor information of data packet No. 5, and data packet No. 6 is stored in the on-chip cache module. When the queue scheduling module schedules the descriptor information corresponding to data packet No. 6 based on the scheduling rule, the data output module reads the data packet corresponding to the descriptor information corresponding to data packet No. 6 from the on-chip cache module, determines the real destination port in the descriptor information of data packet No. 6, and sends data packet No. 6 to the corresponding real destination port.

[0061] In order to process the traffic in sequence, such as Figure 2 As shown, it is a flow chart of traffic processing steps, which is applied to the queue number generation module of the traffic processing system, and specifically includes the following steps:

[0062] Step 201: Compare the length of each queue with a length threshold corresponding to the queue.

[0063] Capture 202: When the length of the queue is equal to the length threshold, the state of the queue is set to a congested state.

[0064] Step 203: when receiving the first data sent to the congested state from the data receiving module, add the descriptor information of the first data to the DMA queue.

[0065] The length of each queue is determined. The length of each queue is determined based on the descriptor information contained in each queue. When a queue contains three descriptor information, the length of the queue is determined to be 3.

[0066] A length threshold is set for each queue. Since the data corresponding to each descriptor information in the queue is stored in the on-chip cache module, the on-chip cache module contains different storage spaces.

[0067] The data corresponding to different descriptor information in different queue numbers are stored, and a length threshold value 5 is set for each queue, which is the upper limit of each storage space in the on-chip cache module.

[0068] The length of each queue is compared with the length threshold corresponding to the queue. For example, when a queue A is included, the length threshold of queue A is 5, and it is determined that the length of queue A is also 5, then the length of queue A is equal to the length threshold of queue A, and queue A is set to a congested state. When the length of queue A is 4, the length of queue A is less than the length threshold of queue A, and the state of queue A is 0, which is not congested. When the state of queue A is a congested state, when the data receiving module receives a new data packet 11, the queue number generating module determines that the queue number of data packet 11 is queue A. At this time, the state of queue A is a congested state, and the descriptor information corresponding to data packet 11 is added to the DMA queue. At this time, the descriptor information of data packet 11 is no longer added to queue A to avoid congestion due to on-chip cache.

[0069] The storage space of queue A in the module is full, so data packet 11 is discarded, resulting in the inability to forward data packet 115.

[0070] In order to distinguish the data sent to DMA, the queue number generation module applied to the traffic processing system is used, such as Figure 3 As shown, it is a flow chart of traffic processing steps, which is applied to the queue number generation module of the traffic processing system, and specifically includes the following steps:

[0071] Step 301: Receive first data sent to a target queue.

[0072] Step 302: Update the storage enable in the descriptor information of the first data to temporary storage.

[0073] The destination port is added as DMA in the descriptor information of the first data.

[0074] Once the queue number generating module receives the first data sent to the target queue in the congested state, the storage enable in the descriptor information of the data packet corresponding to the first data is updated to temporary storage, and

[0075] A destination port is added as DMA in the descriptor information of the data packet of the first data, and based on the destination port DMA in the descriptor information, the queue number of the first data packet is forcibly modified to be a DMA queue.

[0076] The traffic processing system also includes a CPU to process burst traffic, such as Figure 4 The figure shows a flow chart of the flow processing steps, which specifically includes the following steps:

[0077] Step 401: The CPU determines the storage space of the on-chip cache.

[0078] Step 402: after detecting that the storage space of the target queue is released, obtaining second data corresponding to the target queue from the external large-capacity cache particle.

[0079] Step 403: Send the second data to the data receiving module.

[0080] Step 404: The data receiving module sends the second data to the queue number generating module.

[0081] Step 405: The queue number generating module sends the descriptor information corresponding to the second data to the target queue.

[0082] The CPU may determine the storage space of the on-chip cache in a manner that: the CPU reads the storage space value of the on-chip cache in real time through a register access interface of the chip.

[0083] Data exceeding the length threshold is burst traffic. When data exceeding the length threshold is stored in the external large-capacity cache particles, for processing burst traffic, the CPU monitors the storage space of the on-chip cache module in real time, monitors whether the storage space of the target queue of the on-chip cache module is released, and obtains the second data corresponding to the target queue from the external large-capacity cache particles after monitoring the storage space release of the target queue of the on-chip cache module, and sends the second data to the data receiving module for processing. Exemplarily, after the CPU detects that the space of queue A in the congested state in the on-chip cache module is released, the second data of queue A is obtained from the external large-capacity cache particles, and the second data is sent to the receiving module for processing.

[0084] It should be noted that the data of different external queues in the external large-capacity storage particle are stored according to the receiving order of the data receiving module, and the queue numbers of the external queues in the external large-capacity storage particle correspond one-to-one with the queue numbers of the on-chip cache.

[0085] The data stored in different plug-in queues are stored in the order of reception, and when reading data from the plug-in large-capacity cache particles, the data is read based on the order of storage. The plug-in large-capacity cache particles include double-rate synchronous dynamic random access memory or quadruple-data-rate static random access memory.

[0086] In order to achieve data order preservation, such as Figure 5 The figure shows a flow chart of the flow processing steps, which specifically includes the following steps:

[0087] Step 501: The external large-capacity cache particle determines the storage quantity of data of different external queues in real time.

[0088] Step 502: The data receiving module receives new data, and when the storage quantity of the target external queue stored in the external large-capacity cache particle is cleared and the queue length of the target queue is less than the length threshold, the descriptor information corresponding to the new data is sent to the target queue of the queue number generating module, and the congestion state of the target queue is updated to a non-congested state.

[0089] The target external queue and the target queue have the same queue number.

[0090] There are multiple implementations for determining the storage quantity of data of different plug-in queues in the plug-in large-capacity storage cache particles. In one implementation, a counter is set for each different plug-in queue cached in the plug-in large-capacity cache particle. When the queue number generation module sends a data packet to the plug-in queue, the counter of the corresponding plug-in queue in the plug-in large-capacity cache particle is increased by 1. When the data receiving module receives a data packet returned from the plug-in large-capacity cache particle, the corresponding plug-in queue counter is reduced by 1. The storage quantity of data of different plug-in queues is determined based on different counters.

[0091] The external large-capacity cache particles determine the storage quantity of data in different external queues in real time based on the data reading situation. When the storage quantity of the target external queue is cleared and the queue length of the target queue is less than the length threshold, the congestion state of the target queue in the queue number generation module is updated to a non-congested state. When the data receiving module receives new data sent to the target queue, the descriptor information of the new data is sent to the target queue of the queue number generation module, so that the queue scheduling module schedules the new data.

[0092] In the embodiments provided in the present application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to the multiple embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of a code, and the module, a program segment or a part of a code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or the flowchart, and the combination of boxes in the block diagram and / or the flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0093] In addition, each functional module in each embodiment of the present application can be integrated together to form an independent part, or each module can exist separately, or two or more modules can be integrated to form an independent part. If the function is implemented in the form of a software functional module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a disk or an optical disk.

[0094] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0095] The above are only various implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A flow processing system, characterized in that: The system comprises: Data receiving module, queue number generating module, queue scheduling module, data output module, external large-capacity cache particles, on-chip cache module; The receiving module is used to receive data; The on-chip cache module is used to store data; The queue number generating module is used to generate a queue number according to the real destination port in the descriptor information of the data, send the descriptor information corresponding to the data to the corresponding queue based on the queue number, determine the number of descriptor information sent to each queue and the length threshold of the queue, and add the descriptor information exceeding the length threshold to the DMA queue, wherein the descriptor information of the data includes the real destination port of the data; The queue scheduling module is used to schedule the descriptor information in different queues based on the scheduling rules; The data output module is used to receive the descriptor information scheduled by the queue scheduling module, obtain the corresponding to-be-processed data from the on-chip cache module based on the scheduled descriptor information, and output the to-be-processed data; The external large-capacity cache particle is used to temporarily store data corresponding to the descriptor information in the DMA queue.

2. The system according to claim 1, characterized in that The queue number generating module is also used to compare the length of each queue with the length threshold corresponding to the queue. When the length of the queue is equal to the length threshold, the state of the queue is set to a congested state. When the first data sent to the congested state is received from the data receiving module, the descriptor information of the first data is added to the DMA queue.

3. The system according to claim 2, characterized in that The system also includes a DMA; The DMA is used to transmit the received data whose destination port is DMA; The DMA is further used to send first data to an external large-capacity cache particle, wherein the first data is data sent to a target queue, and the target queue is a queue in a congested state.

4. The system according to claim 3, characterized in that The queue number generating module is further used to update the storage enable in the descriptor information of the first data to temporary storage, and add the destination port as DMA in the descriptor information of the first data.

5. The system according to claim 3, characterized in that The system also includes a CPU; The CPU is used to determine the storage space of the on-chip cache module, and after detecting that the storage space of the target queue is released, obtain the second data corresponding to the target queue from the external large-capacity cache particles, and send the second data to the data receiving module, wherein the on-chip cache module includes different storage spaces, and the different storage spaces are used to store data corresponding to the descriptor information in queues other than the DMA queue.

6. The system according to claim 5, characterized in that The data receiving module sends the second data to the queue number generating module, and the queue number generating module sends the descriptor information corresponding to the second data to the target queue.

7. The system according to claim 3, characterized in that The external large-capacity cache particles are also used to determine the storage quantity of data of different external queues in real time; The data receiving module is also used to receive new data. When the storage quantity of the target plug-in queue stored in the plug-in large-capacity cache particles is cleared and the queue length of the target queue is less than the length threshold, the descriptor information corresponding to the new data is sent to the target queue of the queue number generating module, and the congestion state of the target queue is updated to a non-congested state, wherein the target plug-in queue is consistent with the queue number of the target queue.

8. The system according to claim 1, characterized in that The data output module is specifically used to: receive the to-be-processed descriptor information scheduled by the queue scheduling module, obtain the to-be-processed data from the on-chip cache module based on the to-be-processed descriptor information, determine the real destination port of the to-be-processed data based on the to-be-processed descriptor information, and send the to-be-processed data to the real destination port.

9. The system according to claim 1, characterized in that The external large-capacity cache particles include a double-rate synchronous dynamic random access memory or a quadruple-data-rate static random access memory.

10. A traffic processing method, characterized in that: The traffic is processed by the traffic processing system according to any one of claims 1 to 9.

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