A Development Method for Heterogeneous Integrated PDK Based on GaAs and FO-WLP Processes

Abstract

This invention discloses a development method for a heterogeneous integration PDK based on GaAs and FO-WLP processes, comprising: a preparation stage, including preparing development documents, design documents, and device model files for GaAs and FO-WLP processes; creating a heterogeneous integration PDK library; creating folders such as CDF, artwork, boot, DRC, and LVS for GaAs and FO-WLP processes; a development stage, writing a defs file to start the heterogeneous integration PDK; creating technical documents for GaAs and FO-WLP; creating symbol, CDF parameter, callback, artwork, DRC, and LVS files for GaAs and FO-WLP process devices; and a verification and testing stage, including CDF & callback verification, artwork verification, model file verification, and DRC and LVS verification. This invention can efficiently complete the development of heterogeneous integration process PDKs under the ADS tool, comprehensively solves some of the current technical problems in heterogeneous integration PDK development, achieves seamless integration of process data and design environment, shortens the production cycle, and plays an important role in promoting heterogeneous integrated circuit design research.

Description

Technical Field

[0001] This invention belongs to the field of PDK development, specifically relating to a development method for a heterogeneous integrated PDK based on GaAs and FO-WLP processes. Background Technology

[0002] In recent years, with the increasing demand for miniaturized, high-density, diversified functions, high performance, and low cost of electronic systems, heterogeneous integration technology has become one of the important research directions in electronic technology, enabling collaborative design across different processes, materials, and factories.

[0003] With the rapid development of information technology, the semiconductor industry has given rise to many high-performance semiconductor materials. III-V compound semiconductor materials, represented by GaAs and GaN, possess significant characteristics such as wide bandgap, high electron mobility, high thermal conductivity, and low noise, exhibiting superior high-frequency device performance and meeting the ever-increasing performance requirements of integrated circuits. However, due to the limitations of single semiconductor materials, it is difficult to meet the demands of highly information-based equipment. To fully leverage the advantages of various materials, structures, and devices, III-V compound semiconductors such as GaAs can be fan-out wafer-level packaging (FO-WLP). FO-WLP is a three-dimensional heterogeneous integration technology that offers significant advantages in package size, product performance, packaging cost, and packaging efficiency. Furthermore, it can integrate chips with different functions, significantly improving product performance.

[0004] To support the collaborative design of circuits using different processes, improve the efficiency of heterogeneous integrated circuit design, and avoid unnecessary duplicate tape-outs, designers urgently need a universal and accurate heterogeneous integration process design kit (PDK). The PDK is a crucial bridge between integrated circuit design and wafer foundries, containing a complete set of process documents and basic device libraries, and ensuring compliance with foundry design rule checks (DRC) and layout versus schematic checks (LVS). However, currently, there is no standardized heterogeneous integration PDK development scheme. To further advance heterogeneous integrated circuit design research, this paper proposes a development method for a heterogeneous integration PDK based on GaAs and FO-WLP processes. Summary of the Invention

[0005] This invention discloses a method for developing a heterogeneous integrated circuit PDK based on GaAs and FO-WLP processes using the ADS tool. This method achieves heterogeneous integration through the integration of information from both processes, realizing seamless integration of process data and the design environment, improving the design efficiency of heterogeneous integrated circuits, and shortening the production cycle. Considering that the design and subsequent foundry manufacturing of heterogeneous integrated circuits using GaAs and resin-based FO-WLP processes mainly involve FO-WLP based on GaAs process devices or circuits, this invention integrates FO-WLP process information on the basis of building a GaAs process PDK to realize the development of a heterogeneous integrated circuit PDK.

[0006] This invention provides a method for developing a heterogeneous integrated PDK based on GaAs and FO-WLP technology, comprising the following steps:

[0007] S1. Preparation Phase:

[0008] Obtain the process information files for GaAs and FO-WLP respectively. The process information files include: technical document development documents, device list development documents for GaAs and FO-WLP, graphic symbol development documents for circuit schematic design, CDF parameter development documents for describing device attributes, callback function development documents, layout development documents for device artwork development, bitmap file development documents, device model files for schematic simulation, and design manuals for design rule checking DRC files and layout comparison schematic LVS files.

[0009] Create a heterogeneous integration PDK library; create a main directory in the heterogeneous integration PDK library to store the basic components of the heterogeneous integration PDK; create folders in the basic components according to the GaAs and FO-WLP process information files; use the folders to classify and store the source files of the GaAs and FO-WLP process information files to facilitate the maintenance of source files of different process devices; the source files are source code files developed using the AEL language based on the GaAs and FO-WLP process information files.

[0010] The folders include: GaAs and FO-WLP CDF parameter folders, GaAs and FO-WLP artwork folders, GaAs and FO-WLP bitmap folders, model folders, DRC folders, and LVS folders; boot files and pallete files also need to be created in the basic components; thus obtaining an empty heterogeneous integration PDK.

[0011] S2, Development Phase:

[0012] S2-1: In the main directory created in step S1, create the lib.defs file and the for_editing_pdk.defs file, and write code to call the PDK device library into the ADS tool software; the PDK device library is a file used to store heterogeneous integrated PDK device units;

[0013] S2-2: Load the hollow heterogeneous integration PDK from S1 into the ADS tool software, and configure the path parameters of the heterogeneous integration PDK as follows to obtain the incomplete heterogeneous integration PDK:

[0014] The path parameters include: model file path, boot file path, DRC file path, and LVS file path.

[0015] Set the model file path to the path of the model folder created in S1.

[0016] Set the boot file path to the path of the boot folder created in step S1.

[0017] Set the DRC file path to the path of the DRC folder created in step S1.

[0018] Set the LVS file path to the path of the LVS folder created in step S1.

[0019] S2-3: Based on the technical documents developed in S1, create technical documents for GaAs and FO-WLP processes respectively in the incomplete heterogeneous integration PDK obtained in step S2-2; the technical documents are process documents used for layout design and physical verification, including: layer definition file, layer display file, layermap file, and substrate information file.

[0020] S2-4: Based on the device list development document of GaAs and FO-WLP in S1, create each device unit in the incomplete heterogeneous integration PDK obtained in step S2-2;

[0021] S2-5: Based on the graphic symbol development document for circuit schematic design in S1, create the symbol for each device in the ADS tool software;

[0022] S2-6: In the boot file of S1, write code to configure the parameter path of the heterogeneous integration PDK as described below:

[0023] The parameter paths of the heterogeneous integrated PDK include: GaAs CDF parameter file path, GaAs artwork parameter file path, FO-WLP CDF parameter file path, and FO-WLP artwork parameter file path.

[0024] Set the GaAs CDF parameter file path to the path of the GaAs CDF folder created in step S1.

[0025] Set the GaAs artwork parameter file path to the path of the GaAs artwork folder created in step S1.

[0026] Set the FO-WLP CDF parameter file path to the path of the FOWLP CDF folder created in step S1.

[0027] Set the path of the FO-WLP artwork parameter file to the path of the FOWLPartwork folder created in S1;

[0028] S2-7: Develop a document based on the CDF parameters used to describe device properties in S1.

[0029] Under the path of the GaAs CDF and FO-WLP CDF folders created in S2-6, use AEL language to develop CDF parameter files to describe the parameter attributes of GaAs and FO-WLP process devices;

[0030] S2-8: According to the development documentation of the Callback function in S1,

[0031] In the corresponding CDF parameter file in S2-7, the Callback function is developed using the AEL language to meet the requirements of the development document for the Callback function in S1.

[0032] S2-9: Based on the device model file used for schematic simulation in S1.

[0033] Obtain the path of the model folder created in step S1, and under the path of the model folder, convert the model files of GaAs and FO-WLP process devices into netlist files that can be read by the ADS tool software;

[0034] S2-10: Develop the layout document for device artwork development based on the information in S1.

[0035] Under the GaAs artwork parameter file path and FO-WLP artwork folder path set in steps S2-6, the layout of GaAs and FO-WLP process devices is developed using the AEL language;

[0036] S2-11: A design manual developed based on the design rule check DRC file and layout comparison schematic LVS file in S1.

[0037] Obtain the path of the DRC folder created in step S1, and under the path of the DRC folder, write the GaAs and FO-WLP process DRC files according to the design manual described in S1;

[0038] S2-12: A design manual developed based on the design rule check DRC file and layout comparison schematic LVS file in S1.

[0039] Obtain the path of the LVS folder created in step S1, and under the path of the LVS folder, write the GaAs and FO-WLP process LVS files according to the design manual described in S1;

[0040] S2-13: According to the development documentation of the bitmap file in S1.

[0041] Obtain the path of the bitmap folder created in step S1. Under the path of the bitmap folder, use the ADS tool software to draw the bitmap file of each device in the device list development document of GaAs and FO-WLP in step S1.

[0042] S2-14: Obtain the path of the pallete file created in step S1. Under the path of the pallete file, use AEL language to write code to load the bitmap file of each device drawn in step S2-13; and obtain the completed heterogeneous integration PDK.

[0043] S3, Verification Testing Phase:

[0044] S3-1: In the ADS tool software, load the heterogeneous integrated PDK obtained in step S2-14 using either the lib.defs file or the for_editing_pdk.defs file developed in step S2-1; in read-only mode, load the heterogeneous integrated PDK using the lib.defs file; in editable mode, load the heterogeneous integrated PDK using the for_editing_pdk.defs file.

[0045] The circuit is built using the required verification test device and Process Include device, and simulation is performed. The simulation results are then checked to see if they meet the simulation requirements. If they do not meet the requirements, the model file is checked to see if it is correctly converted into a netlist file that can be read by ADS. The process is then returned to step S2-9. If the process meets the requirements, the process proceeds to step S3-2.

[0046] S3-2: In the ADS Layout View, build a test layout example, read the GaAs and FO-WLP process DRC files in S2-11, perform DRC verification tests, and determine whether it meets the requirements of the design manual for design rule checking DRC files and layout comparison schematic LVS files as described in S1. If it does not meet the requirements, return to step S2-11; if it does meet the requirements, proceed to step S3-3.

[0047] S3-3: Simultaneously build identical layout and schematic cases in ADS Layout View and Schematic View, read the GaAs and FO-WLP process LVS files from step S2-12, perform LVS verification tests, and determine whether they meet the design manual requirements for design rule checking DRC files and layout comparison schematic LVS file development described in S1. If they do not meet the requirements, return to step S2-12.

[0048] Preferably, in S2-11, the GaAs and FO-WLP process DRC files are developed according to the following steps:

[0049] Obtain the path to the DRC folder created in step S1. Under this path, create four DRC files: GaAs_rule, FOWLP_rule, All_rule, and setrule. The GaAs_rule and FOWLP_rule files are used to write DRCs for GaAs and FO-WLP processes, respectively. The All_rule file simultaneously calls the written GaAs and FO-WLP process DRCs, allowing for simultaneous checking using DRC files from both GaAs and FO-WLP processes. The setrule file is used to call the developed GaAs and FO-WLP process DRC files in the PDK. This satisfies the designer's need to select one or more process DRCs for checking when using DRCs.

[0050] Preferably, in S2-12, the GaAs and FO-WLP process LVS files are developed according to the following steps:

[0051] Obtain the path to the LVS folder created in step S1. Under the path of the LVS folder, create four LVS files: kit_lvs, lvs_cb, initialize_lvs_job, and setrule. The kit_lvs file is used for layer operations to identify device information from the layout. The layers include: Device Layer, Pin Layer, and Artwork Layer. The lvs_cb file is used to define functions to identify the parameter information contained in the Artwork Layer. The initialize_lvs_job file is used to define user-defined identification functions for LVS, such as short-circuiting microstrip line devices in DeviceRecognition mode. The setrule file is used to call the developed GaAs and FO-WLP process LVS files in the PDK.

[0052] Preferably, after step S3-3, the following steps are also included:

[0053] S4: Write user manuals for the heterogeneous integration PDK, DRC, and LVS.

[0054] The development method for heterogeneous integration PDK based on GaAs and FO-WLP processes using the ADS tool provided in this invention comprehensively solves some of the technical problems currently encountered in the development of heterogeneous integration PDKs. The heterogeneous integration PDK development method adopted in this invention is not only applicable to GaAs and FO-WLP process integration, but also to integration using any different processes. With the successful development and implementation of heterogeneous integration PDKs, circuit researchers can be freed from complex and difficult tasks, and design will become more efficient. It is believed that the heterogeneous integration PDK development method of this invention will play an important role in advancing research on heterogeneous integrated circuit design. Attached Figure Description

[0055] The accompanying drawings are provided to further illustrate the invention and, together with the embodiments thereof, are used to explain the invention, but do not constitute a limitation thereof. In the drawings:

[0056] Figure 1 This is a flowchart of the heterogeneous integration PDK development process of this invention;

[0057] Figure 2 This is a directory structure diagram of the heterogeneous integration PDK of the present invention. Detailed Implementation

[0058] First, some terms used in this application will be explained as follows:

[0059] PDK: Process Design Kit

[0060] Symbol: Graphical symbols used in circuit schematic design

[0061] CDF: Component Description Format

[0062] Callback: Device parameter call function

[0063] artwork: layout file

[0064] Technical File: A process document used for layout design and physical verification.

[0065] DRC: Design Rule Check Document

[0066] LVS: Layout Versus Schematic

[0067] FO-WLP: Fan-out Wafer Level Packaging

[0068] boot: Used to load AEL files

[0069] pallete: Device list tray file

[0070] bitmap: A graphical file in the device list tray.

[0071] This invention provides a method for developing a heterogeneous integrated PDK based on GaAs and FO-WLP technology, comprising the following steps:

[0072] S1. Preparation Phase:

[0073] Obtain the process information files for GaAs and FO-WLP respectively. The process information files include: technical document development documents, device list development documents for GaAs and FO-WLP, graphic symbol development documents for circuit schematic design, CDF parameter development documents for describing device attributes, callback function development documents, layout development documents for device artwork development, bitmap file development documents, device model files for schematic simulation, and design manuals for design rule checking DRC files and layout comparison schematic LVS files.

[0074] Create a heterogeneous integration PDK library; create a main directory in the heterogeneous integration PDK library to store the basic components of the heterogeneous integration PDK, and further create folders in the basic components to classify and store the source files of the GaAs and FO-WLP process information files. The source files are source code files developed using the AEL language based on the GaAs and FO-WLP process information files.

[0075] The folder is created based on the GaAs and FO-WLP process information files, including: GaAs and FO-WLP CDF parameter folder, GaAs and FO-WLP artwork folder, GaAs and FO-WLP bitmap folder, model folder, DRC folder, and LVS folder; boot file and pallete file also need to be created in the basic components; resulting in an empty heterogeneous integration PDK.

[0076] S2, Development Phase:

[0077] S2-1: In the main directory created in step S1, create the lib.defs file and the for_editing_pdk.defs file, and write code to call the PDK device library into the ADS tool software; the PDK device library is a file used to store heterogeneous integrated PDK device units;

[0078] S2-2: Load the hollow heterogeneous integration PDK from S1 into the ADS tool software, and configure the path parameters of the heterogeneous integration PDK as follows:

[0079] The path parameters include: model file path, boot file path, DRC file path, and LVS file path.

[0080] Set the model file path to the path of the model folder created in S1.

[0081] Set the boot file path to the path of the boot folder created in step S1.

[0082] Set the DRC file path to the path of the DRC folder created in step S1.

[0083] Set the LVS file path to the path of the LVS folder created in step S1.

[0084] Among them, "model file path" is an attribute parameter of the PDK product obtained by the method in this case; "model folder path" is the path of the model folder created in the previous S1 step; similarly, "boot file path", "DRC file path", and "LVS file path" are also attribute parameters of the PDK product obtained by the method in this case.

[0085] S2-3: Based on the technical documents developed in S1, load the incomplete heterogeneous integration PDK into the ADS tool software in step S2-2 to create technical documents for GaAs and FO-WLP processes respectively; both include Layer definition files, Layer display files, layermap files, substrate information files, etc. During the development of the heterogeneous integration PDK technical documents, it is important to ensure that the Layer definitions in the GaAs and FO-WLP technical documents are not duplicated. If the LayerNumber is duplicated, communication with the foundry is necessary to ensure that the process information input during PDK development is consistent with the foundry's requirements. The defined GaAs and FO-WLP technical documents need to be called simultaneously in the lib.defs file and the for_editing_pdk.defs file mentioned in S2-1 to import the technical documents into the heterogeneous integration PDK.

[0086] S2-4: Based on the device list development document of GaAs and FO-WLP in S1, load it into the incomplete heterogeneous integration PDK in the ADS tool software in step S2-2 to create each device unit;

[0087] S2-5: Based on the graphic symbol development document for circuit schematic design in S1, create the symbol of the device in the heterogeneous integrated PDK device unit in step S2-4; draw the symbol of the device, which can be drawn according to a certain size ratio using lines and the corresponding pins of the device; or it can be directly obtained from the existing symbols in the ADS software;

[0088] S2-6: In the boot file of S1, write code to configure the parameter path of the heterogeneous integration PDK as described below:

[0089] The parameter paths of the heterogeneous integrated PDK include: GaAs CDF parameter file path, GaAs artwork parameter file path, FO-WLP CDF parameter file path, and FO-WLP artwork parameter file path.

[0090] Set the GaAs CDF parameter file path to the path of the GaAs CDF folder created in step S1.

[0091] Set the GaAs artwork parameter file path to the path of the GaAs artwork folder created in step S1.

[0092] Set the FO-WLP CDF parameter file path to the path of the FOWLP CDF folder created in step S1.

[0093] Set the path of the FO-WLP artwork parameter file to the path of the FOWLPartwork folder created in S1;

[0094] S2-7: Develop a document based on the CDF parameters used to describe device properties in S1.

[0095] Under the paths of the GaAs CDF and FO-WLP CDF folders created in S2-6, use AEL

[0096] The language development yielded CDF parameter files used to describe the parameter properties of GaAs and FO-WLP process devices;

[0097] S2-8: According to the development documentation of the Callback function in S1,

[0098] In the corresponding CDF parameter file in S2-7, the Callback function is developed using the AEL language to meet the requirements of the development document for the Callback function in S1.

[0099] S2-9: Based on the device model file used for schematic simulation in S1.

[0100] Obtain the path of the model folder created in step S1, and under the path of the model folder, convert the model files of GaAs and FO-WLP process devices into netlist files that can be read by the ADS tool software;

[0101] S2-10: Develop the layout document for device artwork development based on the information in S1.

[0102] Under the GaAs artwork parameter file path and FO-WLP artwork folder path set in steps S2-6, the layout of GaAs and FO-WLP process devices is developed using the AEL language;

[0103] S2-11: A design manual developed based on the design rule check DRC file and layout comparison schematic LVS file in S1.

[0104] Obtain the path of the DRC folder created in step S1, and under the path of the DRC folder, write the GaAs and FO-WLP process DRC files according to the design manual described in S1;

[0105] S2-12: A design manual developed based on the design rule check DRC file and layout comparison schematic LVS file in S1.

[0106] Obtain the path of the LVS folder created in step S1, and under the path of the LVS folder, write the GaAs and FO-WLP process LVS files according to the design manual described in S1;

[0107] S2-13: According to the development documentation of the bitmap file in S1.

[0108] Obtain the path of the bitmap folder created in step S1. Under the path of the bitmap folder, use the ADS tool software to draw the bitmap file of each device in the device list development document of GaAs and FO-WLP in step S1.

[0109] S2-14: Obtain the path of the pallete file created in S1. Under the path of the pallete file, use AEL language to write code to load the bitmap file of each device in the device list development document of GaAs and FO-WLP drawn in S1 in S2-13; and obtain the developed heterogeneous integration PDK.

[0110] S3, Verification Testing Phase:

[0111] S3-1: In the ADS tool software, load the lib.defs file or for_editing_pdk.defs file developed in step S2-14 to complete the heterogeneous integration PDK. Load the lib.defs file in read-only mode and load the for_editing_pdk.defs file in editable mode.

[0112] The circuit is built using the required verification test device and Process Include device, and simulation is performed. The simulation results are then checked to see if they meet the simulation requirements. If they do not meet the requirements, the model file is checked to see if it is correctly converted into a netlist file that can be read by ADS. The process is then returned to step S2-9. If the process meets the requirements, the process proceeds to step S3-2.

[0113] S3-2: In the ADS Layout View, build a test layout example, read the GaAs and FO-WLP process DRC files in S2-11, perform DRC verification tests, and determine whether it meets the requirements of the design manual for design rule checking DRC files and layout comparison schematic LVS files as described in S1. If it does not meet the requirements, return to step S2-11; if it does meet the requirements, proceed to step S3-3.

[0114] S3-3: Simultaneously build identical layout and schematic cases in ADS Layout View and Schematic View, read the GaAs and FO-WLP process LVS files from step S2-12, perform LVS verification tests, and determine whether they meet the design manual requirements for design rule checking DRC files and layout comparison schematic LVS file development described in S1. If they do not meet the requirements, return to step S2-12.

[0115] S4: Write user manuals for the heterogeneous integration PDK, DRC, and LVS.

[0116] The above description represents a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Modifications, substitutions, and improvements that can be easily conceived by those skilled in the art within the scope of the technology disclosed in the present invention should all be covered within the scope of protection of the present invention.

Claims

1. A method for developing a PDK based on GaAs and FO-WLP heterogeneous integration process, comprising the following steps: S1, preparation stage: Obtain GaAs and FO-WLP process information files, respectively, including: technical document development documents, device list development documents of GaAs and FO-WLP, graphic symbol symbol development documents for circuit schematic design, CDF parameter development documents for describing device properties, Callback callback function development documents, layout development documents for device artwork development, bitmap file development documents, device model files for schematic simulation, and design manual for developing design rule check DRC files and layout versus schematic LVS files; Create a heterogeneous integration PDK library; create a main directory in the heterogeneous integration PDK library to store the basic components of the heterogeneous integration PDK, create folders in the basic components according to the GaAs and FO-WLP process information files, and store source files of the GaAs and FO-WLP process information files in the folders, which are source code files developed by using AEL language according to the GaAs and FO-WLP process information files; The folders include: GaAs and FO-WLP CDF parameter folders, GaAs and FO-WLP artwork folders, GaAs and FO-WLP bitmap folders, model folders, DRC folders, and LVS folders; boot folders and pallete folders also need to be created in the basic components; and an empty heterogeneous integration PDK is obtained; S2, development stage: S2-1: In the main directory created in step S1, create lib.defs file and for_editing_pdk.defs file, and write code to call PDK device library into ADS tool software for use; the PDK device library is a file for storing heterogeneous integration PDK device units; S2-2: Load the empty heterogeneous integration PDK in step S1 in the ADS tool software, configure the path parameters of the heterogeneous integration PDK as follows to obtain a heterogeneous integration PDK that has not been completed: The path parameters include: model file path, boot file path, DRC file path, LVS file path, Set the model file path to the path of the model folder created in step S1, Set the boot file path to the path of the boot folder created in step S1, Set the DRC file path to the path of the DRC folder created in step S1, Set the LVS file path to the path of the LVS folder created in step S1, S2-3: According to the technical document development document in S1, create GaAs and FO-WLP process technical documents in the heterogeneous integration PDK obtained in step S2-2, which have not been completed; the technical documents are used for layout design and physical verification, including: Layer definition file, Layer display file, layermap file, substrate information file; S2-4: According to the device list development document of GaAs and FO-WLP in S1, create each device unit in the heterogeneous integration PDK obtained in step S2-2; S2-5: According to the symbol development document for circuit schematic design in S1, create the symbol of each device unit in the ADS tool software; S2-6: Write code to configure the parameter path of the heterogeneous integration PDK according to the boot file in S1 by the following method: The parameter path of the heterogeneous integration PDK includes: GaAs CDF parameter file path, GaAs artwork parameter file path, FO-WLP CDF parameter file path, FO-WLP artwork parameter file path, Set the GaAs CDF parameter file path to the path of the CDF parameter folder of GaAs created in S1, Set the GaAs artwork parameter file path to the path of the GaAs artwork folder created in S1, Set the FO-WLP CDF parameter file path to the path of the CDF parameter folder of FO-WLP created in S1, Set the FO-WLP artwork parameter file path to the path of the FO-WLP artwork folder created in S1; S2-7: According to the CDF parameter development document for describing device properties in S1, Develop CDF parameter files for describing the parameter properties of GaAs and FO-WLP process devices by using AEL language in the path of the GaAs CDF and FO-WLP CDF folders created in S2-6; S2-8: According to the development document of Callback function in S1, Develop the corresponding functions of Callback by using AEL language in the corresponding CDF parameter files in S2-7 to meet the requirements of the development document of Callback function in S1; S2-9: According to the device model file for schematic simulation in S1, Get the path of the model folder created in step S1, and convert the model files of GaAs and FO-WLP process devices into netlist files that can be read by the ADS tool software in the path of the model folder; S2-10: According to the layout development document for device artwork development in S1, In the step S2-6, the GaAs artwork parameter file path and the FO-WLP artwork parameter file path are set, and AEL language is used to develop the artwork of GaAs and FO-WLP process devices; S2-11: According to the design manual developed in the S1 for design rule check DRC file and layout versus schematic LVS file, Obtain the path of the DRC folder created in step S1, and develop GaAs and FO-WLP process DRC files according to the design manual in S1 under the path of the DRC folder; S2-12: According to the design manual developed in the S1 for design rule check DRC file and layout versus schematic LVS file, Obtain the path of the LVS folder created in step S1, and develop GaAs and FO-WLP process LVS files according to the design manual in S1 under the path of the LVS folder; S2-13: According to the development document of the bitmap file in the S1, Obtain the path of the bitmap folder created in step S1, and draw the bitmap file of each device in the development document of the device list of GaAs and FO-WLP in step S1 under the bitmap folder using ADS tool software; S2-14: Obtain the pallete folder created in the step S1, and write code to load the bitmap file of each device drawn in step S2-13 under the pallete folder by AEL language; Get the developed heterogeneous integrated PDK.

2. The method of claim 1, wherein the GaAs and FO-WLP process based heterogeneous integration PDK development method is characterized by, In the S2-11, the GaAs and FO-WLP process DRC files are developed according to the following steps: Obtain the path of the DRC folder created in step S1, and develop GaAs and FO-WLP process DRC files according to the design manual in S1 under the path of the DRC folder; 3. The method of claim 2, wherein the method is based on a GaAs and FO-WLP process heterogeneous integration PDK development method, characterized in that, In the S2-12, the GaAs and FO-WLP process LVS files are developed according to the following steps: The path of the LVS folder created in the acquisition step S1 is acquired, and four LVS files, i.e., a kit_lvs file, an lvs_cb file, an initialize_lvs_job file and a setrule file, are created under the path of the LVS folder; the kit_lvs file is used for layer operation and device information identification from a layout, and the layers include a device identification layer Device Layer, a device pin identification layer Pin Layer and a device parameter related identification layer Artwork Layer; the lvs_cb file is used for defining functions to identify parameter information contained in the device parameter related identification layer Artwork Layer; the initialize_lvs_job file is used for defining identification functions customized by a user of LVS; and the setrule file is used for calling the developed GaAs and FO-WLP process LVS files in a PDK.

4. The method of claim 1, wherein the method is based on a GaAs and FO-WLP process heterogeneous integration PDK development method, characterized in that, After the S2, the following steps are further included: S3, a verification test phase: S3-1: in the ADS tool software, the developed heterogeneous integration PDK obtained in the step S2-14 is loaded through any one of the lib.defs file and the for_editing_pdk.defs file developed in the step S2-1; the heterogeneous integration PDK is loaded through the lib.defs file in a read-only mode, and the heterogeneous integration PDK is loaded through the for_editing_pdk.defs file in an editable mode; a device requiring verification test and a Process Include device are called to build a circuit, simulation is performed, and it is judged whether the simulation result meets simulation requirements; if not, it is checked whether the model file converted into a netlist file readable by ADS is correct, and the step S2-9 is returned; if yes, the step S3-2 is entered; S3-2: in the ADS Layout View, a layout case is built and tested, the GaAs and FO-WLP process DRC files in the S2-11 are read, DRC verification test is performed, and it is judged whether the requirements of the design manual developed in the step S1 for the design rule check DRC file and the layout comparison schematic LVS file are met; if not, the step S2-11 is returned; if yes, the step S3-3 is entered; S3-3: in the ADS Layout View and the Schematic View, the same layout and schematic case are built, the GaAs and FO-WLP process LVS files in the step S2-12 are read, LVS verification test is performed, and it is judged whether the requirements of the design manual developed in the step S1 for the design rule check DRC file and the layout comparison schematic LVS file are met; if not, the step S2-12 is returned.

5. The method of claim 4, wherein the GaAs and FO-WLP process based heterogeneous integration PDK development method is characterized by, After the S3-3, the following steps are further included: S4: Write the Heterogeneous Integration PDK User Guide, DRC User Guide, LVS User Guide.

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