Storage device and method of operating the same

Abstract

A memory device and an operating method thereof are disclosed. The memory device can include a memory bank including a plurality of memory blocks each divided into a normal area and a row hammer area; a command control circuit adapted to perform an access operation on the normal area in response to an activation command; an internal command generation circuit adapted to generate an internal command in response to a precharge command; a target address generation circuit adapted to save a count of combinations of logical levels of a received address in the row hammer area by performing an access operation on the row hammer area in response to the internal command, and set an address corresponding to the count as a target address when the count satisfies a preset condition; and a refresh control circuit adapted to control an intelligent refresh operation on the target address.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0140262, filed on October 20, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The various embodiments relate to semiconductor circuits, and more specifically, to a storage device for performing smart refresh operations and a storage system including the storage device. Background Technology

[0004] Semiconductor memory devices comprise multiple memory cells for storing data. Each memory cell may include a capacitor and a transistor. Data is stored by charging or discharging the capacitor, and the amount of charge stored in the capacitor should always remain constant. However, the amount of charge stored in the capacitor may change due to various effects, including voltage differences with external circuitry. When the amount of charge stored in the capacitor changes, the data stored in the capacitor changes and may therefore be lost. Some semiconductor memory devices perform refresh operations to prevent such data loss.

[0005] Even during refresh operations, the increased integration in these devices may not guarantee the ability to prevent data loss in all situations. For example, increased integration reduces the distance between memory cells and the distance between word lines coupled to those cells. This reduced distance between word lines can allow interference between adjacent word lines. This, in turn, can make it difficult to retain the data stored in the memory cells coupled to those word lines. Therefore, the likelihood of data loss increases. Summary of the Invention

[0006] Various embodiments relate to a storage device and a storage system including the same, the storage device further including a storage area for storing input count information about combinations of logic levels for an address, and performing an intelligent refresh operation to refresh word lines adjacent to the most frequently enabled word line based on the result obtained by counting all combinations of logic levels for the address.

[0007] The technical problems to be solved by this disclosure are not limited to those described above, and those skilled in the art can clearly understand other unmentioned technical problems through the following description.

[0008] In one embodiment, a storage device may include: a storage body comprising a plurality of storage blocks, each storage block being divided into a normal region and a row hammer region; a command control circuit adapted to perform an access operation on the normal region in response to an activation command; an internal command generation circuit adapted to generate an internal command in response to a precharge command; a target address generation circuit adapted to store a count of each logic level combination of a received address in the row hammer region by performing an access operation on the row hammer region in response to the internal command, and to set the address corresponding to the count as a target address when the count meets a preset condition; and a refresh control circuit adapted to control an intelligent refresh operation on the target address.

[0009] In one embodiment, a method of operating a storage device includes a first storage bank and a second storage bank. The first storage bank has multiple storage blocks each divided into a first normal region and a first row hammer region, and the second storage bank has multiple storage blocks each divided into a second normal region and a second row hammer region. The method may include: performing an access operation on the first normal region and the second normal region according to a storage bank interleaving method, wherein the active region of the first storage bank partially overlaps with the precharge region of the second storage bank, and the active region of the second storage bank partially overlaps with the precharge region of the first storage bank; generating an internal command in response to a precharge command corresponding to the precharge region of the first storage bank or the second storage bank in a row hammer enable region; storing a count of each logic level combination of a received address in the first row hammer region or the second row hammer region by performing an access operation on the first row hammer region or the second row hammer region in response to the internal command; setting the address corresponding to the count as a target address when the count meets a preset condition; and performing a smart refresh operation on the target address.

[0010] In one embodiment, a storage device may include: a storage bank including a plurality of storage blocks, each storage block including a normal region and a row hammer region; a command control circuit adapted to perform an access operation on the normal region in response to an activation command; a target address generation circuit adapted to: determine a count of each logic level combination of one or more access addresses among a plurality of addresses in the storage bank in response to a precharge command, store the count value in the row hammer region, and determine the access address with the highest count value among the access addresses as the target address; and a refresh control circuit adapted to refresh one or more word lines among a plurality of word lines in the storage bank that are adjacent to the word line corresponding to the target address.

[0011] According to this embodiment, the storage device may additionally include a row hammer region for storing input count information about logic level combinations of an address, and performing an intelligent refresh operation to refresh the word line adjacent to the most frequently enabled word line based on the result obtained by counting all logic level combinations of the address. Through this operation, the storage device can accurately count the input counts of all logic level combinations of the address and refresh the most frequently enabled word line and its adjacent word lines, thereby minimizing interference between word lines.

[0012] Furthermore, the storage device can perform access operations on the normal region during the active interval and on the row hammer region during the precharge interval. This operation can minimize the increase in operation time during the active interval by adding the row hammer region. Attached Figure Description

[0013] Figure 1 An embodiment of the storage device is shown.

[0014] Figure 2 An implementation of the internal command generation circuit is shown.

[0015] Figure 3 An implementation of the storage unit is shown.

[0016] Figure 4 An implementation of the target address generation circuit is shown.

[0017] Figure 5 An implementation method for operating a storage device is shown.

[0018] Figure 6 An embodiment of the storage device is shown.

[0019] Figure 7 An implementation of the storage unit is shown.

[0020] Figure 8 An implementation method for operating a storage device is shown. Detailed Implementation

[0021] Embodiments of this disclosure are described below with reference to the accompanying drawings. However, the elements and features of this disclosure may be configured or arranged in different ways to form other embodiments, which may be variations of any disclosed embodiment.

[0022] In this disclosure, references to various features (e.g., elements, structures, modules, components, steps, operations, characteristics, etc.) included in terms such as “one embodiment,” “example embodiment,” “implementation,” “another embodiment,” “some embodiments,” “various embodiments,” “other embodiments,” “alternative embodiments,” etc., are intended to indicate that any such feature is included in one or more embodiments of this disclosure, but may necessarily or may not be combined in the same embodiment.

[0023] In this disclosure, the terms “comprising,” “including,” and “having” are open-ended. As used in the appended claims, these terms indicate the presence of a stated element and do not exclude the presence or addition of one or more other elements. The terms in the claims do not exclude the inclusion of additional components (e.g., interface units, circuitry, etc.).

[0024] In this disclosure, various units, circuits, or other components may be described or declared as "configured to" perform one or more tasks. In such a context, "configured to" is used to indicate a structure by indicating that a block / unit / circuit / component includes a structure (e.g., a circuit) that performs one or more tasks during operation. Thus, it can be said that a block / unit / circuit / component is configured to perform a task even when the specified block / unit / circuit / component is currently inoperable (e.g., not turned on or activated). Blocks / units / circuits / components used with the term "configured to" include hardware, such as circuits, memory storing program instructions executable to perform the operation, etc. Furthermore, "configured to" may include general structures (e.g., general-purpose circuits) manipulated by software and / or firmware (e.g., an FPGA or a general-purpose processor running software) to operate in a manner capable of performing the relevant tasks. "Configured to" may also include adjusting manufacturing processes (e.g., semiconductor manufacturing facilities) to manufacture means (e.g., integrated circuits) that implement or perform one or more tasks.

[0025] As used in this disclosure, the terms “circuit” or “logic” refer to all of the following: (a) implementations of hardware circuitry only (such as implementations of analog and / or digital circuitry only), and (b) combinations of circuitry and software (and / or firmware), such as (if applicable): (i) combinations of processors or (ii) portions of processor / software (including digital signal processors), software, and memory that work together to enable a device such as a mobile phone or server to perform various functions, and (c) circuitry, such as a microprocessor or a portion of a microprocessor, that requires software or firmware for operation, even if the software or firmware is not physically present. This definition of “circuit” or “logic” applies to all uses of the term in this application, including its use in any claim. As a further example, as used in this application, the terms “circuit” or “logic” also cover implementations of processors (or processors) or portions of processors and their accompanying software and / or firmware. For example, and where applicable to certain claim elements, the terms “circuit” or “logic” also cover integrated circuits for storage devices.

[0026] As used herein, the terms “first,” “second,” “third,” etc., serve as labels for nouns following these terms and do not imply any type of ordering (e.g., spatial, temporal, logical, etc.). The terms “first” and “second” do not necessarily mean that the first value must precede the second value. Furthermore, although terms may be used herein to identify various elements, these elements are not limited by these terms. These terms are used to distinguish one element from another that has the same or similar name. For example, a first circuit can be distinguished from a second circuit.

[0027] Furthermore, the term "based on" is used to describe one or more factors that influence the determination. This term does not exclude other factors that may influence the determination. That is, the determination may be based solely on these factors or at least partially on them. For example, the phrase "A is determined based on B." In this case, B is a factor influencing the determination of A, but such usage does not exclude the possibility that the determination of A is also based on C. In other cases, A may be determined solely based on B.

[0028] In this document, a data item, data entry, or data term can be a sequence of bits. For example, a data item may include a file, a portion of a file, a page in memory, an object in an object-oriented program, a digital message, a digitally scanned image, a portion of a video or audio signal, metadata, or the content of any other entity that can be represented by a sequence of bits. According to one embodiment, a data item may include discrete objects. According to another embodiment, a data item may include information units within a transmission packet between two different components.

[0029] Figure 1This is a diagram illustrating an embodiment of a storage device 1, which may include an internal command generation circuit 11, a target address generation circuit 12, a refresh control circuit 13, a command control circuit 14, and a storage body 20.

[0030] The storage bank 20 may include multiple storage blocks 21 and 22, each including normal areas (NM AREA) 211 and 221 and row hammer areas (RH AREA) 212 and 222. In one embodiment, the storage bank 20 may include a first storage block 21 and a second storage block 22. For reference, Figure 1 The illustration shows that memory bank 20 includes two memory blocks 21 and 22. However, this is only one embodiment. In another embodiment, memory bank 20 may include a greater number of memory blocks. The following description will be based on the assumption that memory bank 20 includes two memory blocks 21 and 22.

[0031] The first storage block 21 and the second storage block 22 may each include normal regions 211 and 221 and row hammer regions 212 and 222.

[0032] The first storage block 21 and the second storage block 22 may each include normal (NM) regions 211 and 221 and row hammer (RH) regions 212 and 222.

[0033] Normal regions 211 and 221 can store normal data.

[0034] The hammer regions 212 and 222 can store the count RCN of each logic level combination of the address ADD<1:N> input to the memory bank 20.

[0035] The internal command generation circuit 11 can receive a precharge command PCG from an external device (e.g., a memory controller). Furthermore, the internal command generation circuit 11 can receive a row hammer enable signal FEN, which is selected for enable by the mode register set (MRS).

[0036] The internal command generation circuit 11 can generate internal activation command IACT, internal read command IRD, internal write command IWT and internal precharge command IPCG based on the precharge command PCG and the hammer enable signal FEN.

[0037] When the hammer enable signal FEN is activated (hammer enable state), the internal command generation circuit 11 can generate an internal activation command IACT in response to the precharge command PCG input after the activation command ACT.

[0038] After a predetermined time has elapsed, the internal command generation circuit 11 can generate an internal precharge command IPCG. If the hammer enable signal FEN is not activated (hammer disabled state), the internal command generation circuit 11 may not generate a signal (regardless of whether the precharge command PCG is input). The internal command generation circuit 11 can enable the internal activation command IACT in response to the precharge command PCG during a preset time period, and then sequentially generate an internal read command IRD and an internal write command IWT within the activation range of the internal activation command IACT. It can also generate the internal precharge command IPCG in response to the disabled internal activation command IACT.

[0039] Command control circuit 14 can receive activation command ACT, read command RD, write command WT, and precharge command PCG from an external device (e.g., a memory controller). Furthermore, command control circuit 14 can receive a row hammer enable signal FEN, which is selected for enable by the mode register set (MRS). Additionally, command control circuit 14 can receive an internal precharge command IPCG from internal command generation circuit 11.

[0040] Command control circuit 14 can perform access operations on normal regions 211 and 221 of memory bank 20 in response to activation command ACT. Command control circuit 14 can activate memory bank 20 in response to activation command ACT, and read / write normal data to / from normal regions 211 and 221 of memory bank 20 in response to read command RD and write command WT. When the row hammer enable signal FEN is enabled, command control circuit 14 can precharge memory bank 20 in response to internal precharge command IPCG.

[0041] For reference, storage device 1 may include a mode register set (MRS) for setting its operating status information. Here, the mode register set (MRS) may set the value of an internal signal (e.g., a row hammer enable signal FEN) used in storage device 1 in response to an external command input from an external device (e.g., a memory controller).

[0042] Furthermore, in the above description, the operation of the internal command generation circuit 11 and the command control circuit 14 is controlled in response to the hammer enable signal FEN. However, according to an embodiment, the internal command generation circuit 11 and the command control circuit 14 can be configured to perform operations corresponding to the enable state of the hammer enable signal FEN without receiving the hammer enable signal FEN. For example, unlike the figures, the internal command generation circuit 11 can operate by receiving only the precharge command PCG without receiving the hammer enable signal FEN. Furthermore, the command control circuit 14 can operate by receiving only the activation command ACT, the read command RD, the write command WT, and the internal precharge command IPCG without receiving the hammer enable signal FEN and the precharge command PCG.

[0043] Additionally, when the hammer enable signal FEN is disabled, the command control circuit 14 can precharge the memory bank 20 in response to the precharge command PCG. The command control circuit 14 can control the operation of normal regions 211 and 221 of the memory bank 20 (e.g., activation operation, read / write operation, and precharge operation) by generating a normal region control signal NM_CON in response to the activation command ACT, read command RD, write command WT, precharge command PCG, internal precharge command IPCG, and hammer enable signal FEN.

[0044] The target address generation circuit 12 can perform an access operation on the row hammer regions 212 and 222 of the memory bank 20 in response to the internal activation command IACT. When the internal activation command IACT is activated, the target address generation circuit 12 can read / write the count RCN of each logic level combination of address ADD<1:N> to / from the row hammer regions 212 and 222 of the memory bank 20 in response to the internal read command IRD and the internal write command IWT. The target address generation circuit 12 can perform a precharge operation on the row hammer regions 212 and 222 of the memory bank 20 in response to the internal precharge command IPCG.

[0045] Since the internal activation command IACT is generated in response to the precharge command PCG input after the activation command ACT, the access operations to normal regions 211 and 221 performed by the command control circuit 14 and the access operations to the hammer regions 212 and 222 performed by the target address generation circuit 12 can be performed in non-overlapping operation periods. Therefore, the access operations to normal regions 211 and 221 (performed by the command control circuit 14 in response to the activation command ACT) are completed at the time when the precharge command PCG is input. Therefore, the access operations to hammer regions 212 and 222 (performed by the target address generation circuit in response to the internal activation command IACT generated by the precharge command) can be performed after the access operations to normal regions 211 and 221 (performed by the command control circuit 14) have been completed.

[0046] In one embodiment, the target address generation circuit 12 can perform an access operation on the row hammer regions 212 and 222 of the memory bank 20 in response to the internal activation command IACT. Additionally, the target address generation circuit 12 can store the count RCN of each logic level combination of the address ADD<1:N> in the row hammer regions 212 and 222 of the memory bank 20.

[0047] When the count RCN stored in the row hammer regions 212 and 222 of the memory bank 20 meets the preset conditions, the target address generation circuit 12 can set the address corresponding to the count RCN as the target address TGA<1:N>.

[0048] When the internal activation command IACT applied from the internal command generation circuit 11 is enabled, the target address generation circuit 12 can perform an internal read operation on the row hammer regions 212 and 222 in response to the internal read command IRD, and can perform an internal write operation on the row hammer regions 212 and 222 in response to the internal write command IWT.

[0049] The target address generation circuit 12 can read the count RCN of each logic level combination of address ADD<1:N> stored in the row hammer regions 212 and 222. In this case, the target address generation circuit 12 can perform an internal read operation on the row hammer regions 212 and 222 in response to an internal read command IRD received from the internal command generation circuit 11. The target address generation circuit 12 can increment the read count RCN by incrementing the count and store the incremented count RCN in the row hammer regions 212 and 222 by performing an internal write operation on the row hammer regions 212 and 222 in response to an internal write command IWT received from the internal command generation circuit 11.

[0050] The target address generation circuit 12 can receive the address ADD<1:N> from an external device (e.g., a memory controller). The address ADD<1:N> can include N bits, where N can be a natural number greater than or equal to 2. Therefore, the logic level combination of the address ADD<1:N> can indicate the combination of logic levels of the N bits contained in the address ADD<1:N>.

[0051] The target address generation circuit 12 can generate a count RCN of each logic level combination of address ADD<1:N> during an internal read operation, and then store the count RCN in row hammer regions 212 and 222 during an internal write operation.

[0052] In one implementation, the target address generation circuit 12 can generate a count RCN "3" during an internal read operation by counting the number of times an address with a first logic level combination is received. Then, during an internal write operation, the target address generation circuit 12 can store the generated count RCN in row hammer regions 212 and 222 such that the value (in the count RCN stored in row hammer regions 212 and 222) corresponding to the address with the first logic level combination becomes "3".

[0053] In another embodiment, the target address generation circuit 12 can generate a count RCN "7" during an internal read operation by counting the number of times an address with a second logic level combination is received. Then, during an internal write operation, the target address generation circuit 12 can store the generated count RCN in row hammer regions 212 and 222, such that the value corresponding to the address with the second logic level combination (in the count RCN stored in row hammer regions 212 and 222) becomes "7".

[0054] The operation performed by the target address generation circuit 12 during an internal read operation to generate a count RCN for each logic level combination of address ADD<1:N> can indicate the operation of reading the count RCN of each logic level combination of address ADD<1:N> stored in row hammer regions 212 and 222 into the target address generation circuit 12 during the internal read operation. The read count RCN can then be updated by incrementing the count. Therefore, the count RCN transferred from the target address generation circuit 12 to the row hammer regions 212 and 222 during an internal write operation can indicate the updated count RCN by incrementing the count RCN read during the internal read operation. In other words, the target address generation circuit 12 can read the count RCN of each logic level combination of address ADD<1:N> (such as stored in row hammer regions 212 and 222) during an internal read operation, update the read count RCN by incrementing the count, and store the updated count RCN in row hammer regions 212 and 222 during an internal write operation.

[0055] In one implementation, the target address generation circuit 12 can read a count RCN with the value "3" (stored in row hammer regions 212 and 222 in response to an address having a first logic level combination) during an internal read operation. The target address generation circuit 12 can then update the read count RCN to a count RCN with the value "4" by incrementing the count, and store the updated count RCN in row hammer regions 212 and 222 during an internal write operation, such that the value (in the count RCN stored in row hammer regions 212 and 222) corresponding to the address having the first logic level combination becomes "4".

[0056] In another embodiment, the target address generation circuit 12 can read a count RCN with the value "7" (stored in row hammer regions 212 and 222 in response to an address having the second logic level combination) during an internal read operation. The target address generation circuit 12 can then update the read count RCN to a count RCN with the value "8" by incrementing the count, and store the updated count RCN in row hammer regions 212 and 222 during an internal write operation, such that the value corresponding to the address having the second logic level combination (in the count RCN stored in row hammer regions 212 and 222) becomes "8".

[0057] In another embodiment, even when a count RCN with an initial value of "0" is stored in row hammer regions 212 and 222 in response to an address having a third logic level combination, the target address generation circuit 12 can read the count RCN during an internal read operation, update the read count RCN to a count RCN with a value of "1" by incrementing the count, and store the updated count RCN in row hammer regions 212 and 222 during an internal write operation. These operations can be performed such that the value in the count RCN stored in row hammer regions 212 and 222 corresponding to the address having the third logic level combination becomes "1".

[0058] When the count RCN of each logic level combination of address ADD<1:N> (such as those stored in hammer regions 212 and 222) meets the preset conditions, the target address generation circuit 12 can set the address ADD<1:N> corresponding to the count RCN as the target address TGA<1:N>.

[0059] In one embodiment, the target address generation circuit 12 can select the count with the largest (highest) value from the counts RCN of the various logic level combinations of the address ADD<1:N> stored in the row hammer regions 212 and 222, and then set the address ADD<1:N> corresponding to the selected count as the target address TGA<1:N>. Here, the count RCN that satisfies the preset condition can be the count with the largest (highest) value among the counts RCN of the various logic level combinations of the address ADD<1:N> stored in the row hammer regions 212 and 222.

[0060] The target address generation circuit 12 can output the target address TGA<1:N> stored therein to the memory bank 20 in response to the smart refresh signal SR received from the refresh control circuit 13. For example, when the refresh control circuit 13 generates the smart refresh signal SR to perform a smart refresh operation, the target address generation circuit 12 can output the target address TGA<1:N> to the memory bank 20 to perform a smart refresh operation on the target address TGA<1:N>.

[0061] The smart refresh operation may include refreshing one or more word lines among the multiple word lines WL1, WL2, WL3, ... included in the memory bank 20 that are adjacent to the word line corresponding to the target address TGA<1:N>. In one embodiment, when the word line corresponding to the target address TGA<1:N> among the multiple word lines WL1, WL2, WL3, ... included in the memory bank 20 is the J-th word line, during the smart refresh operation on the target address TGA<1:N>, not only the J-th word line can be selected and refreshed, but also the (J+1)-th and / or (J-1)-th word lines adjacent to it can be selected and refreshed. Here, J is a natural number equal to or greater than 1.

[0062] The target address generation circuit 12 can perform an internal write operation after performing a smart refresh operation, thereby resetting the count corresponding to the target address TGA<1:N> in the count RCN of each logic level combination of address ADD<1:N> stored in the row hammer regions 212 and 222.

[0063] The refresh control circuit 13 can receive refresh commands REF from an external device (e.g., a memory controller).

[0064] The refresh control circuit 13 can generate an intelligent refresh signal SR and an internal refresh signal IR based on the refresh command REF.

[0065] The refresh control circuit 13 can generate a smart refresh signal SR in a form corresponding to the conditions for performing a smart refresh operation. This smart refresh signal SR is enabled when a refresh command REF is input. The refresh control circuit 13 can generate the smart refresh signal SR and transmit the generated smart refresh signal SR to the memory bank 20 and the target address generation circuit 12, thereby controlling the smart refresh operation on the target address TGA<1:N>.

[0066] The refresh control circuit 13 can generate an internal refresh signal IR in a form corresponding to the conditions for performing a self-refresh operation, which is enabled when a refresh command REF is input. The refresh control circuit 13 can generate the internal refresh signal IR to perform a self-refresh operation.

[0067] The target address generation circuit 12 can initialize all counts RCN stored in the row hammer regions 212 and 222 of the memory bank 20 in response to the initialization signal INIT input during the power-on period and startup operation of the memory device 1. Each bit of the initialized count RCN can have a logic low level "0".

[0068] The target address generation circuit 12 can generate a row hammer control signal RH_CON in response to the internal activation command IACT, internal precharge command IPCG, internal read command IRD, internal write command IWT and initialization signal INIT, and can control the operation of the row hammer regions 212 and 222 of the memory bank 20, such as activation operation, precharge operation, internal read operation, internal write operation and initialization operation.

[0069] In one embodiment, the count RCN described in the above embodiments may include a predetermined number of bits. For example, the count RCN may include six bits.

[0070] Figure 2 It is used to describe Figure 1A diagram illustrating an embodiment of the internal command generation circuit 11 in a component of a disclosed storage device.

[0071] Reference Figure 2 The internal command generation circuit 11 may include a first generation circuit 111 and a second generation circuit 112.

[0072] The first generation circuit 111 can enable the internal activation command IACT for a preset time tDELAY in response to the precharge command PCG. The first generation circuit 111 can also enable the internal activation command IACT for a preset time in response to the precharge command PCG input when the hammer enable signal FEN is enabled. When the hammer enable signal FEN is disabled, the first generation circuit 111 can keep the internal activation command IACT disabled regardless of whether the precharge command PCG is input.

[0073] The second generation circuit 112 can receive the internal activation command IACT and sequentially generate the internal read command IRD, the internal write command IWT, and the internal precharge command IPCG. The second generation circuit 112 can sequentially generate the internal read command IRD and the internal write command IWT within the activation range of the internal activation command IACT, and can generate the internal precharge command IPCG in response to the disabled internal activation command IACT.

[0074] Figure 3 It is used to describe Figure 1 A diagram illustrating an embodiment of the storage unit 20 in the components of the storage device disclosed herein.

[0075] Reference Figure 3 The storage block 20 may include a first storage block 21 and a second storage block 22.

[0076] Row region 23 can be located on either the left or right side of storage body 20. Figure 3 An example is shown where row region 23 is located on the left side of memory bank 20. Furthermore, column region 24 can be located on either the top or bottom side of memory bank 20. Figure 3 An example is shown where column region 24 is located on the lower side of storage body 20. Furthermore, cross region 25 may be located between row region 23 and column region 24.

[0077] The memory bank 20 may include multiple memory cells MC coupled between multiple word lines WL1, WL2, WL3, ... and multiple bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11 and BL12.

[0078] The first and second memory blocks 21 and 22 included in memory bank 20 can share multiple word lines WL1, WL2, WL3, ... that are driven simultaneously. For example, multiple word lines WL1, WL2, WL3, ... can be driven simultaneously by word line drivers located in row area 23.

[0079] In this embodiment, the first memory block 21 and the second memory block 22 share multiple word lines WL1, WL2, WL3, ... and the case where multiple word lines WL1, WL2, WL3, ... are driven simultaneously is taken as an example. However, this is only one embodiment. In one embodiment, the multiple word lines corresponding to the first memory block 21 and the multiple word lines corresponding to the second memory block 22 can be driven independently. For example, a sub-word line driver may also be included between the first and second memory blocks 21 and 22. Through the sub-word line driver, the multiple word lines corresponding to the first memory block 21 and the multiple word lines corresponding to the second memory block 22 can be shared and driven, or they can be driven independently.

[0080] The bit lines BL1, BL2, BL3, BL4, BL5 and BL6 corresponding to the first storage block 21 and the bit lines BL7, BL8, BL9, BL10, BL11 and BL12 corresponding to the second storage block 22 can be physically separated from each other.

[0081] The memory cells MC coupled between some bit lines BL1 and BL2 (in the bit lines BL1, BL2, BL3, BL4, BL5 and BL6) and word lines WL1, WL2, WL3, ... included in the first memory block 21, and some bit lines BL7 and BL8 (in the bit lines BL7, BL8, BL9, BL10, BL11 and BL12) and word lines WL1, WL2, WL3, ... included in the second memory block 22, can be used as row hammer regions 212 and 222.

[0082] The memory cells MC coupled between the other bit lines BL3, BL4, BL5 and BL6 (in the first memory block 21) that do not overlap with bit lines BL1 and BL2 and the multiple word lines WL1, WL2, WL3, ... and the memory cells MC coupled between the other bit lines BL9, BL10, BL11 and BL12 (in the second memory block 22) that do not overlap with bit lines BL7 and BL8 and the multiple word lines WL1, WL2, WL3, ... can be used as normal regions 211 and 221.

[0083] Bit lines BL3, BL4, BL5 and BL6 / BL9, BL10, BL11 and BL12 included in normal regions 211 and 221, and bit lines BL1 and BL2 / BL7 and BL8 included in row hammer regions 212 and 222, can be coupled to column region 24 via their shared segment line SIO.

[0084] In one embodiment, column region 24 may include data input / output circuitry configured to output data transmitted via segment line SIO to a destination outside the storage device 1 (e.g., a memory controller), or to transmit data received from a source outside the storage device 1 to segment line SIO.

[0085] When an internal read operation is performed in response to an internal read command IRD generated by the internal command generation circuit 11, the target address generation circuit 12 can (via segment line SIO) read the count RCN of each logic level combination of the address ADD<1:N> stored in the memory cells MC between multiple word lines WL1, WL2, WL3, ... and bit lines BL1 and BL2 / BL7 and BL8 corresponding to the row hammer regions 212 and 222. For example, the target address generation circuit 12 can perform an internal read operation via segment line SIO to read the count RCN stored in the first selected memory cell in the memory cells MC included in the row hammer regions 212 and 222, which is coupled to the word line corresponding to the input address.

[0086] When an internal write operation is performed in response to an internal write command IWT generated by the internal command generation circuit 11, the target address generation circuit 12 can update the count RCN of each logic level combination read by the internal read operation through an ascending count. Then, the target address generation circuit 12 can write the updated count RCN to the memory cell MC coupled between multiple word lines WL1, WL2, WL3, ... and the bit lines BL1 and BL2 / BL7 and BL8 corresponding to the row hammer regions 212 and 222 via a segmented line SIO. For example, the target address generation circuit 12 can perform an internal write operation that updates the count RCN read by the internal read operation through an ascending count, transmits the updated count RCN to a first selected memory cell coupled to a word line (corresponding to the input address) in the memory cell MC included in the row hammer regions 212 and 222 via a segmented line SIO, and stores the transmitted count RCN in the first selected memory cell.

[0087] During a normal read operation performed in response to the read command RD, the command control circuit 14 can read normal data from the memory cell MC coupled between word lines WL1, WL2, WL3, ... and bit lines BL3, BL4, BL5 and BL6 / BL9, BL10, BL11 and BL12 corresponding to normal regions 211 and 221, and can transmit the read normal data to the data output circuitry included in column region 24 via segment line SIO. For example, the command control circuit 14 can perform a normal read operation by reading normal data from a second selected memory cell (in the memory cell MC included in normal regions 211 and 221) coupled to the word line corresponding to the input address, and transmitting the read normal data to the data output circuitry included in column region 24 via segment line SIO.

[0088] During a normal write operation performed in response to the write command WT, the command control circuit 14 can write normal data (such as data received from the data input circuitry included in column region 24 via segment line SIO) to memory cells MC coupled between word lines WL1, WL2, WL3, ... and bit lines BL3, BL4, BL5 and BL6 / BL9, BL10, BL11 and BL12 corresponding to normal regions 211 and 221. For example, the command control circuit 14 can perform a normal write operation to store normal data (such as data received from the data input circuitry included in column region 24 via segment line SIO) into a second selected memory cell in memory cell MC included in normal regions 211 and 221 coupled to a word line corresponding to the input address.

[0089] Figure 4 It is used to describe Figure 1 A diagram illustrating an embodiment of the target address generation circuit 12 in the components of the disclosed storage device.

[0090] Reference Figure 4 The target address generation circuit 12 may include a region control circuit 41, a storage circuit 42, and a target address output circuit 44.

[0091] The area control circuit 41 can read the count RCN corresponding to the input address by performing an internal read operation on the row hammer areas 212 and 222 corresponding to the input address. This operation can be performed in response to the internal read command IRD if the internal activation command IACT is enabled. The area control circuit 41 can update the count RCN by incrementing the count (e.g., by performing an internal read operation on the row hammer areas 212 and 222) and can store the updated count RCN in the row hammer areas 212 and 222 corresponding to the input address by performing an internal write operation on the row hammer areas 212 and 222. This operation can be performed in response to the internal write command IWT if the internal activation command IACT is enabled.

[0092] In one implementation, the region control circuit 41 may, in response to an internal read command IRD received from the internal command generation circuit 11, read the count RCN corresponding to the input address by performing an internal read operation on row hammer regions 212 and 222. The input address may be an address having any combination of logic level combinations of addresses ADD<1:N> input to the storage device 1. The input address may be input to the memory bank 20 to select any one of a plurality of word lines.

[0093] Therefore, the region control circuit 41 can perform an internal read operation via segment line SIO to read the count RCN stored in the memory cell MC between any word line corresponding to the input address among word lines WL1, WL2, WL3, ... and bit lines BL1 and BL2 / BL7 and BL8 corresponding to row hammer regions 212 and 222. This operation can be performed in response to an internal read command IRD received from the internal command generation circuit 11.

[0094] The area control circuit 41 can update the count RCN, which is read through an internal read operation and corresponds to the input address, by incrementing the count.

[0095] Therefore, the region control circuit 41 can perform an internal write operation that stores the count RCN (updated by ascending count) in a memory cell MC between any one of the word lines corresponding to the input address and the bit lines BL1 and BL2 / BL7 and BL8 corresponding to the row hammer regions 212 and 222. This operation can be performed in response to an internal write command IWT received from the internal command generation circuit 11.

[0096] The region control circuit 41 can reset the count RCN stored in the memory cell MC between any word line corresponding to the input address and the bit lines BL1 and BL2 / BL7 and BL8 corresponding to the row hammer regions 212 and 222. This operation can be performed in response to the reset signal RST.

[0097] The region control circuit 41 can initialize the count RCN stored in all memory cells MC coupled between word lines WL1, WL2, WL3, ... and bit lines BL1 and BL2 / BL7 and BL8 corresponding to row hammer regions 212 and 222. This operation can be performed in response to the initialization signal INIT. Each bit of the initialized count RCN can have a logic low level "0".

[0098] The storage circuit 42 can store the storage count SELN. When the count RCN (updated by the area control circuit 41 through an incremental counting operation) meets a preset condition, the storage circuit 42 can store the updated count RCN (meeting the preset condition) as the storage count SELN. The storage circuit 42 can reset the stored storage count SELN in response to the reset signal RST.

[0099] When the update count RCN generated by the region control circuit 41 during the activation operation of the memory bank 20 is greater than the save count SELN stored in the save circuit 42, the save circuit 42 can store the update count RCN therein as the save count SELN and generate a flag signal FLG. The save circuit 42 can reset the save count SELN stored therein in response to the reset signal RST.

[0100] The storage circuit 42 can compare the value of the stored storage count SELN with the value of the updated count RCN generated by the area control circuit 41 in response to the updated count RCN. When the comparison result indicates that the value of the updated count RCN generated by the area control circuit 41 is greater than the value of the stored storage count SELN stored in the storage circuit 42, the storage circuit 42 can store the updated count RCN generated by the area control circuit 41 as a new stored storage count SELN. When the comparison result indicates that the value of the updated count RCN generated by the area control circuit 41 is less than or equal to the value of the stored storage count SELN stored in the storage circuit 42, the storage circuit 42 can retain the stored storage count SELN. Therefore, the stored storage count SELN stored in the storage circuit 42 can have the same value as the maximum value among all the counts RCN stored in the hammer regions 212 and 222.

[0101] The storage circuit 42 can reset the value of the stored storage count SELN in response to the reset signal RST. In one embodiment, all bits of the reset storage count SELN can be logic low level "0".

[0102] When the value of the update count RCN generated by the area control circuit 41 is greater than the value of the save count SELN stored in the save circuit 42, the save circuit 42 may generate a flag signal FLG. When the value of the update count RCN generated by the area control circuit 41 is less than or equal to the value of the save count SELN stored in the save circuit 42, the save circuit 42 may not generate a flag signal FLG.

[0103] The target address output circuit 44 can save the input address as the target address TGA<1:N> in response to the flag signal FLG generated by the save circuit 42. The target address output circuit 44 can output the target address TGA<1:N> to the memory bank 20 during a smart refresh operation. The target address output circuit 44 can generate a reset signal RST after the smart refresh operation is performed.

[0104] When the flag signal FLG is generated by the storage circuit 42, it indicates that the update count RCN generated by the area control circuit 41 is stored as the new storage count SELN. Therefore, the input address at the time when the flag signal FLG is generated can be the input address corresponding to the maximum count among all counts RCN already stored in the hammer regions 212 and 222 before that corresponding time point. Therefore, the target address TGA<1:N> stored in the target address output circuit 44 can be the address corresponding to the maximum count among all counts RCN stored in the hammer regions 212 and 222.

[0105] The target address output circuit 44 can output the target address TGA<1:N> stored therein to the memory bank 20 in response to the smart refresh signal SR received from the refresh control circuit 13 and corresponding to the smart refresh operation. Therefore, the refresh control circuit 13 can generate the smart refresh signal SR and transmit it to the memory bank 20 and the target address generation circuit 12, such that a smart refresh operation is performed on the target address TGA<1:N> corresponding to the largest count among all counts RCN stored in the row hammer regions 212 and 222.

[0106] The target address output circuit 44 can generate a reset signal RST after the smart refresh operation is executed. The target address output circuit 44 can generate the reset signal RST after receiving the smart refresh signal SR corresponding to the smart refresh operation from the refresh control circuit 13. The reset signal RST is enabled when the smart refresh operation is completed.

[0107] Figure 5 It is used to describe according to one implementation method Figure 1 A diagram illustrating the operation of the storage device. In this embodiment, the activation command ACT and the precharge command PCG for the storage unit 20 can be entered alternately and repeatedly.

[0108] Furthermore, the operation of this implementation can be based on the following assumption: the hammer enable signal FEN is kept enabled to a logic high level.

[0109] Command control circuit 14 can enable word line enable signal WL_EN to logic high and disable bit line equalizer signal BL_EQ to logic low in response to the input of the first activation command ACT, thereby activating memory bank 20 (1). The word line enable signal WL_EN and the bit line equalizer signal BL_EQ can be generated by command control circuit 14 to control the operation of memory bank 20.

[0110] By enabling the word line enable signal WL_EN, the command control circuit 14 can activate any one of the multiple word lines WL1, WL2, WL3, ... included in the memory bank 20 that corresponds to the input address. The command control circuit 14 can disable the bit line equalization signal BL_EQ to a logic low level to disable equalization operations on the bit lines BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11, and BL12 coupled to any one of the word lines corresponding to the activated input address. As a result, the current state can be changed to a state where sensing amplification is possible.

[0111] Additionally, the command control circuit 14 can perform access operations on normal regions 211 and 221 until the first precharge command PCG is input after the first activation command ACT is input.

[0112] The internal command generation circuit 11 can activate the internal activation command IACT to a logic high level (2) in response to the input of the first precharge command PCG, and then maintain the activation state of the internal activation command IACT for a preset time tDELAY. For example, the internal command generation circuit 11 can activate the internal activation command IACT at a first time point tA, and then deactivate the internal activation command IACT at a second time point tB after the preset time tDELAY has elapsed. The target address generation circuit 12 can perform an access operation on the row hammer regions 212 and 222 in response to the activated internal activation command IACT.

[0113] If the row hammer enable signal FEN is deactivated to a logic low level, the internal command generation circuit 11 may not activate the internal activation command IACT. Since the internal activation command IACT is not activated, the command control circuit 14 can, in response to the input of the precharge command PCG, change the word line enable signal WL_EN to a logic low level and activate the bit line equalizer signal BL_EQ to a logic high level. As a result, the memory bank 20 can be precharged.

[0114] However, due to Figure 5The hammer enable signal FEN is activated to a logic high level, thus the internal command generation circuit 11 can activate the internal activation command IACT during a preset time tDELAY. The command control circuit 14 can, in response to the input of the precharge command PCG, change the word line enable signal WL_EN to a logic low level and activate the bit line equalizer signal BL_EQ to a logic high level. As a result, the operation for precharging the memory bank 20 can be delayed during the preset time tDELAY during which the internal activation command IACT remains active.

[0115] The internal command generation circuit 11 can sequentially generate an internal read command IRD and an internal write command IWT (3) during the period when the internal activation command IACT remains active. The target address generation circuit 12 can perform internal read and internal write operations on row hammer regions 212 and 222 in response to the sequentially generated internal read command IRD and internal write command IWT.

[0116] The internal command generation circuit 11 can generate an internal precharge command IPCG (4) in response to the deactivation of the internal activation command IACT. The command control circuit 14 can precharge the memory bank 20 (5) in response to the generated internal precharge command IPCG. The command control circuit 14 can change the word line enable signal WL_EN to logic low and activate the bit line equalizer signal BL_EQ to logic high in response to the generated internal precharge command IPCG. As a result, the memory bank 20 can be precharged (5).

[0117] As described above, the internal command generation circuit 11 can activate the internal activation command IACT for a preset time tDELAY in response to the input of the precharge command PCG after the activation command ACT, and then generate the internal precharge command IPCG. At this time, the command control circuit 14 can precharge the memory bank 20 in response to the internal precharge command IPCG instead of the precharge command PCG. Therefore, the time point at which the command control circuit 14 precharges the memory bank 20 in response to the internal precharge command IPCG can be delayed by a preset time tDELAY from the time point at which the command control circuit 14 precharges the memory bank 20 in response to the precharge command PCG.

[0118] Figure 6 This is a diagram illustrating an embodiment of a storage device 1 that may include a first storage bank 50, a second storage bank 60, an internal command generation circuit 81, a target address generation circuit 82, a refresh control circuit 83, and a command control circuit 84.

[0119] The first storage block 50 may include a first storage block 51 and a second storage block 52, each of which includes a first normal region (NM AREA1_1 and NM AREA1_2) 511 and 521 and a first row hammer region (RH AREA1_1 and RH AREA1_2) 512 and 522.

[0120] The second storage block 60 may include a third storage block 61 and a fourth storage block 62, each of which includes a second normal region (NM AREA2_1 and NM AREA2_2) 611 and 621 and a second row hammer region (RH AREA2_1 and RH AREA2_2) 612 and 622.

[0121] Storage device 1 may include more than two storage units. Furthermore, each of storage units 50 and 60 may include, for example, [missing information - likely a specific type of storage unit]. Figure 6 More storage blocks are shown. For ease of description, the following description will be based on the assumption that the first storage bank 50 and the second storage bank 60 are included in the storage device 1, the first storage block 51 and the second storage block 52 are included in the first storage bank 50, and the third storage block 61 and the fourth storage block 62 are included in the second storage bank 60.

[0122] The first normal regions 511 and 521 and the second normal regions 611 and 621 can be areas used to store normal data.

[0123] The first row hammer regions 512 and 522 can store the count RCN of each logic level combination of the address ADD<1:N> input to the first memory bank 50.

[0124] The second row hammer regions 612 and 622 can store the count RCN of each logic level combination of the address ADD<1:N> input to the second memory bank 60.

[0125] although Figure 1 The disclosed storage device 1 includes a storage unit 20, but Figure 6 The storage device 1 disclosed herein may include two storage banks 50 and 60. For example, Figure 6 Each of the two storage cells 50 and 60 included in the disclosed storage device 1 can have the same as... Figure 1 The storage device 1 disclosed herein includes a storage cell 20 of the same shape. In one embodiment, in... Figure 6 The first storage unit 50 included in the disclosed storage device 1 can perform operations with... Figure 1 The storage device 1 disclosed herein includes a storage unit 20 that operates in the same manner. Furthermore, Figure 6 The second storage unit 60 included in the storage device 1 disclosed herein can also perform operations with... Figure 1The storage device 1 disclosed herein includes a storage unit 20 that operates in the same manner.

[0126] therefore, Figure 6 The configuration and operation of the internal command generation circuit 81 disclosed herein can correspond to Figure 1 and Figure 2 Those in it. Therefore, Figure 6 The configuration and operation of the target address generation circuit 82 disclosed in the paper can be referred to Figure 1 and Figure 4 To describe those that are publicly available.

[0127] However, Figure 6 The first and second memory cells 50 and 60 shown can operate according to a memory cell interleaving method, wherein the active region and the precharge region partially overlap each other. When the first and second memory cells 50 and 60 operate according to the memory cell interleaving method, according to an embodiment, the active region of the first memory cell 50 and the precharge region of the second memory cell 60 can partially overlap each other, and the active region of the second memory cell 60 and the precharge region of the first memory cell 50 can partially overlap each other.

[0128] Since the first and second memory banks 50 and 60 operate according to a memory bank interleaving method, the activation command ACT and precharge command PCG (applied from an external device (e.g., a memory controller) to memory device 1 and corresponding to the first memory bank 50) can correspond to the activation and precharge intervals of the first memory bank 50. Similarly, the activation command ACT and precharge command PCG (applied from an external device (e.g., a memory controller) to memory device 1 and corresponding to the second memory bank 60) can correspond to the activation and precharge intervals of the second memory bank 60.

[0129] Command control circuit 84 can perform access operations on first normal regions 511 and 521 in response to the activation command ACT corresponding to the first memory bank 50. Command control circuit 84 can enter the activation range corresponding to the first memory bank 50 by activating the first memory bank 50 in response to the activation command ACT corresponding to the first memory bank 50. Command control circuit 84 can read / write normal data from / to the first normal regions 511 and 521 included in the first memory bank 50 in response to the read command RD and the write command WT in the activation range corresponding to the first memory bank 50. When the row hammer enable signal FEN is deactivated (e.g., in an inactive state), command control circuit 84 can precharge the first memory bank 50 in response to the precharge command PCG corresponding to the first memory bank 50. Command control circuit 84 can precharge the first memory bank 50 in response to the internal precharge command IPCG, which is generated by internal command generation circuit 81 in response to the precharge command PCG corresponding to the first memory bank 50. This can occur when the hammer enable signal FEN is activated.

[0130] Command control circuit 84 can perform access operations on second normal regions 611 and 621 in response to the activation command ACT corresponding to the second memory bank 60. Command control circuit 84 can enter the activation range corresponding to the second memory bank 60 by activating the second memory bank 60 in response to the activation command ACT corresponding to the second memory bank 60. Command control circuit 84 can read / write normal data from / to the second normal regions 611 and 621 included in the second memory bank 60 in response to the read command RD and the write command WT in the activation range corresponding to the second memory bank 60. When the row hammer enable signal FEN is deactivated (e.g., in an inactive state), command control circuit 84 can precharge the second memory bank 60 in response to the precharge command PCG corresponding to the second memory bank 60. Command control circuit 84 can precharge the second memory bank 60 in response to the internal precharge command IPCG, which is generated by internal command generation circuit 81 in response to the precharge command PCG corresponding to the second memory bank 60. This can occur when the hammer enable signal FEN is activated.

[0131] Command control circuit 84 can generate normal region control signal NM_CON in response to activation command ACT, read command RD, write command WT, precharge command PCG, internal precharge command IPCG and line hammer enable signal FEN, thereby controlling the operation (e.g. activation operation, read / write operation and precharge operation) of the first normal regions 511 and 521 included in the first memory bank 50 and the second normal regions 611 and 621 included in the second memory bank 60.

[0132] The target address generation circuit 82 can perform access operations on the first row hammer regions 512 and 522 included in the first memory bank 50. This access operation can be performed in response to an internal activation command IACT, which is generated by the internal command generation circuit 81 in response to a precharge command PCG corresponding to the first memory bank 50. The target address generation circuit 82 can also perform access operations on the second row hammer regions 612 and 622 included in the second memory bank 60. This access operation can be performed in response to an internal activation command IACT, which is generated by the internal command generation circuit 81 in response to a precharge command PCG corresponding to the second memory bank 60. The target address generation circuit 82 can generate a row hammer control signal RH_CON in response to an internal activation command IACT, an internal precharge command IPCG, an internal read command IRD, an internal write command IWT, and an initialization signal INIT, thereby controlling the operation (e.g., activation operation, precharge operation, internal read operation, internal write operation, and initialization operation) on the first row hammer regions 512 and 522 included in the first memory bank 50 and the second row hammer regions 612 and 622 included in the second memory bank 60.

[0133] Figure 7 It is used to describe Figure 6 The diagram illustrates an embodiment of storage units 50 and 60 in the components of the storage device disclosed herein.

[0134] Reference Figure 7 The first storage bank 50 may include a first storage block 51 and a second storage block 52. The second storage bank 60 may include a third storage block 61 and a fourth storage block 62.

[0135] The first row region ROW AREA1 53 can be located on either the right or left side of the first memory bank 50. As an example, Figure 7 The first row region 53 is shown to be located on the left side of the first memory cell 50. Furthermore, the first column region COLUMN AREA 154 can be located on either the top or bottom side of the first memory cell 50. As an example, Figure 7 The first column area 54 is shown to be located on the lower side of the first storage unit 50. Furthermore, the first cross area 55 may be located between the first row area 53 and the first column area 54.

[0136] The second row region ROW AREA2 63 can be located on either the right or left side of the second memory bank 60. As an example, Figure 7 The second row region 63 is shown to be located on the left side of the second memory bank 60. Furthermore, the second column region COLUMN AREA264 can be located on either the top or bottom side of the second memory bank 60. As an example, Figure 7 The second column region 64 is shown to be located below the second storage unit 60. Furthermore, the second cross area 65 may be located between the second row region 63 and the second column region 64.

[0137] As an example, Figure 7 The diagram shows the first memory bank 50 located to the left of the second memory bank 60. However, this is only one embodiment. In one embodiment, the first memory bank 50 may be located to the right of the second memory bank 60.

[0138] The first memory bank 50 may include multiple memory cells MC coupled between multiple word lines WL1, WL2, WL3... and multiple bit lines BL11, BL12, BL13, BL14, BL15 and BL16.

[0139] The second memory bank 60 may include multiple memory cells MC coupled between word lines WLA, WLB, WLC... and multiple bit lines BL21, BL22, BL23, BL24, BL25 and BL26.

[0140] The first and second memory blocks 51 and 52 included in the first memory bank 50 can share word lines WL1, WL2, WL3, ... which are driven simultaneously. For example, word lines WL1, WL2, WL3, ... can be driven simultaneously by word line drivers located in the first row area 53.

[0141] The third and fourth memory blocks 61 and 62 included in the second memory bank 60 can share multiple word lines WLA, WLB, WLC, ... that are driven simultaneously. For example, word lines WLA, WLB, WLC, ... can be driven simultaneously by word line drivers located in the second row area 63.

[0142] In this embodiment, the first storage block 51 and the second storage block 52 share word lines WL1, WL2, WL3, ... and drive these word lines simultaneously. Furthermore, the third storage block 61 and the fourth storage block 62 share word lines WLA, WLB, WLC, ... and drive these word lines simultaneously.

[0143] In one embodiment, multiple word lines corresponding to the first memory block 51, the second memory block 52, the third memory block 61, and the fourth memory block 62 can be driven independently. For example, sub-word line drivers can be included between the first and second memory blocks 51 and 52, and between the third and fourth memory blocks 61 and 62. Through these sub-word line drivers, the multiple word lines corresponding to the first memory block 51 and the multiple word lines corresponding to the second memory block 52 can be shared and driven or driven independently, and the multiple word lines corresponding to the third memory block 61 and the multiple word lines corresponding to the fourth memory block 62 can be shared and driven or driven independently.

[0144] Bit lines BL11, BL12, and BL13 corresponding to the first memory block 51 and bit lines BL14, BL15, and BL16 corresponding to the second memory block 52 can be physically separated from each other. Bit lines BL21, BL22, and BL23 corresponding to the third memory block 61 and bit lines BL24, BL25, and BL26 corresponding to the fourth memory block 62 can be physically separated from each other.

[0145] The memory cell MC, which is coupled between bit line BL11 and word lines WL1, WL2, WL3, ... in the bit lines BL11, BL12, and BL13 included in the first memory block 51, and the memory cell MC, which is coupled between bit line BL14 and word lines WL1, WL2, WL3, ... in the bit lines BL14, BL15, and BL16 included in the second memory block 52, can be used as the first row hammer regions 512 and 522.

[0146] The memory cell MC, which is coupled between bit line BL21 and word lines WLA, WLB, WLC, ... in the bit lines BL21, BL22 and BL23 included in the third memory block 61, and the memory cell MC, which is coupled between bit line BL24 and word lines WLA, WLB, WLC, ... in the multiple bit lines BL24, BL25 and BL26 included in the fourth memory block 62, can be used as the second row hammer regions 612 and 622.

[0147] The memory cells MC coupled between other bit lines BL12 and BL13 (which do not overlap with bit line BL11 in the plurality of bit lines BL11, BL12 and BL13 included in the first memory block 51) and word lines WL1, WL2, WL3, ... and the memory cells MC coupled between other bit lines BL15 and BL16 (which do not overlap with bit line BL14 in the plurality of bit lines BL14, BL15 and BL16 included in the second memory block 52) and word lines WL1, WL2, WL3, ... can be used as the first normal regions 511 and 521.

[0148] The memory cells MC coupled between other bit lines BL22 and BL23 (which do not overlap with bit line BL21 in the plurality of bit lines BL21, BL22 and BL23 included in the third memory block 61) and word lines WLA, WLB, WLC, ... and the memory cells MC coupled between other bit lines BL25 and BL26 (which do not overlap with bit line BL24 in the plurality of bit lines BL24, BL25 and BL26 included in the fourth memory block 62) and word lines WLA, WLB, WLC, ... can be used as second normal regions 611 and 621.

[0149] Bit lines BL12 and BL13 / BL15 and BL16 included in the first normal regions 511 and 521, and bit lines BL11 / BL14 included in the first row hammer regions 512 and 522, can be coupled to the first column region 54 via the first segment line SIO1 shared by them.

[0150] Bit lines BL22 and BL23 / BL25 and BL26 included in the second normal regions 611 and 621, and bit lines BL21 / BL24 included in the second row hammer regions 612 and 622, can be coupled to the second column region 64 via the second segment line SIO2 shared by them.

[0151] The first segment line SIO1 and the second segment line SIO2 can be physically separated from each other.

[0152] The first column region 54 may include data input / output circuitry configured to output data transmitted via the first segment line SIO1 to a destination outside the storage device 1 (e.g., a memory controller) or to transmit data received from a source outside the storage device 1 to the first segment line SIO1. Similarly, the second column region 64 may include data input / output circuitry configured to output data transmitted via the second segment line SIO2 to a destination outside the storage device 1 (e.g., a memory controller) or to transmit data received from a source outside the storage device 1 to the second segment line SIO2.

[0153] When the internal command generation circuit 81 generates an internal read command IRD corresponding to the first memory bank 50 to perform an internal read operation on the first memory bank 50, the target address generation circuit 82 can (via the first segment line SIO1) read the count RCN of each logic level combination of the address ADD<1:N>. These count RCNs can be stored in memory cells MC coupled between word lines WL1, WL2, WL3, ... and bit lines BL11 and BL14 corresponding to the first row hammer regions 512 and 522. For example, the target address generation circuit 82 can perform an internal read operation by reading the count RCN stored in the first selected memory cell coupled to the word line corresponding to the input address in the memory cells MC included in the first row hammer regions 512 and 522 via the first segment line SIO1.

[0154] When the internal command generation circuit 81 generates an internal write command IWT corresponding to the first memory bank 50 to perform an internal write operation on the first memory bank 50, the target address generation circuit 82 can update the count RCN of each logic level combination by ascending count (read by the internal read operation). Then, the target address generation circuit 82 can write the updated count RCN to the memory cell MC coupled between word lines WL1, WL2, WL3, ... and bit lines BL11 and BL14 corresponding to the first row hammer regions 512 and 522 (via the first segment line SIO1). For example, the target address generation circuit 82 can perform an internal write operation by updating the count RCN (read by the internal read operation) by ascending count and then (via the first segment line SIO1) transmitting the updated count RCN to the first selected memory cell in the memory cell MC included in the first row hammer regions 512 and 522, coupled to the word line corresponding to the input address.

[0155] Command control circuit 84 can read normal data from memory cells MC coupled between word lines WL1, WL2, WL3, ... and bit lines BL12 and BL13 / BL15 and BL16 corresponding to the first normal regions 511 and 521, and can transmit the read normal data to the data output circuit included in the first column region 54 via the first segment line SIO1 during a normal read operation on the first memory bank 50. A normal read operation can be performed in response to a read command RD corresponding to the first memory bank 50. For example, command control circuit 84 can perform a normal read operation to read normal data from a second selected memory cell in the memory cell MC included in the first normal regions 511 and 521, coupled to the word line corresponding to the input address. Then, command control circuit 84 can transmit the read data to the data output circuit included in the first column region 54 via the first segment line SIO1.

[0156] Command control circuitry 84 can write normal data (received via the first segment line SIO1 from the data input circuitry included in the first column region 54) to memory cells MC coupled between word lines WL1, WL2, WL3, ... and bit lines BL12 and BL13 / BL15 and BL16 corresponding to the first normal regions 511 and 521 during a normal write operation on the first memory bank 50. A normal write operation can be performed in response to a write command WT corresponding to the first memory bank 50. For example, command control circuitry 84 can perform a normal write operation to save normal data (received via the first segment line SIO1 from the data input circuitry included in the first column region 54) to a second selected memory cell in memory cell MC included in the first normal regions 511 and 521, coupled to a word line corresponding to the input address.

[0157] When the internal command generation circuit 81 generates an internal read command IRD corresponding to the second memory bank 60 to perform an internal read operation on the second memory bank 60, the target address generation circuit 82 can (via the second segment line SIO2) read the count RCN of each logic level combination of the address ADD<1:N>. These count RCNs can be stored in memory cells MC coupled between word lines WLA, WLB, WLC, ... and bit lines BL21 and BL24 corresponding to the second row hammer regions 612 and 622. For example, the target address generation circuit 82 can perform an internal read operation by reading the count RCN stored in a second selected memory cell coupled to the word line corresponding to the input address in the memory cells MC included in the second row hammer regions 612 and 622 via the second segment line SIO2.

[0158] When the internal command generation circuit 81 generates an internal write command IWT corresponding to the second memory bank 60 to perform an internal write operation on the second memory bank 60, the target address generation circuit 82 can update the count RCN of each logic level combination by ascending count (read through the internal read operation). Then, the target address generation circuit 82 can write the updated count RCN to the memory cell MC coupled between word lines WLA, WLB, WLC, ... and bit lines BL21 and BL24 corresponding to the second row hammer regions 612 and 622 (via the second segment line SIO2). For example, the target address generation circuit 82 can perform an internal write operation by updating the count RCN (read through the internal read operation) by ascending count, transmitting the updated count RCN (via the second segment line SIO2) to a second selected memory cell in the memory cell MC included in the second row hammer regions 612 and 622, coupled to the word line corresponding to the input address, and then storing the transmitted count RCN in the second selected memory cell.

[0159] Command control circuit 84 can read normal data from memory cell MC coupled between word lines WLA, WLB, WLC, ... and bit lines BL22 and BL23 / BL25 and BL26 corresponding to the second normal regions 611 and 621. Then, during a normal read operation on the second memory bank 60, command control circuit 84 can transmit the read normal data to the data output circuit included in the second column region 64 via the second segment line SIO2. A normal read operation can be performed in response to a read command RD corresponding to the second memory bank 60. For example, command control circuit 84 can perform a normal read operation by reading normal data from a second selected memory cell MC included in the second normal regions 611 and 621, coupled to a word line corresponding to the input address, and transmitting the read data to the data output circuit included in the second column region 64 via the second segment line SIO2.

[0160] Command control circuitry 84 can write normal data (received via the second segment line SIO2 from the data input circuitry included in the second column region 64) to memory cells MC coupled between word lines WLA, WLB, WLC, ... and bit lines BL22 and BL23 / BL25 and BL26 corresponding to the second normal regions 611 and 621 during a normal write operation to the second memory bank 60. A normal write operation can be performed in response to a write command WT corresponding to the second memory bank 60. For example, command control circuitry 84 can perform a normal write operation to save normal data (received via the second segment line SIO2 from the data input circuitry included in the second column region 64) to a second selected memory cell MC included in the second normal regions 611 and 621, coupled to a word line corresponding to the input address.

[0161] Figure 8 It is used to describe the operation Figure 6 The implementation of the storage device, particularly how the first storage bank 50 and the second storage bank 60 are based on Figure 6 A diagram illustrating the operation of the memory interleaving method.

[0162] In this embodiment, the time period from the time point tC when the first activation command ACT is input to the time point tD when the first precharge command PCG is input can be the activation interval 1 on the first memory 50. ST BANK ACTIVE SECTION.

[0163] Furthermore, the time interval from the time point tF when the second activation command ACT is input to the time point tH when the second precharge command PCG is input can be the activation interval 2 on the second memory bank 60. ND BANK ACTIVE SECTION.

[0164] During operation, the storage device can enter the precharge interval 1 of the first storage cell 50 in response to the input of the first precharge command PCG. ST BANK PRECHARGE SECTION. At this point, refer to... Figure 5 Description: The storage device has entered the pre-charge interval 1 of the first storage cell 50. ST In the case of BANK PRECHARGE SECTION, when an access operation is performed on the first row hammer regions 512 and 522 included in the first memory bank 50 ST During BANK FCC OPERATION, the precharge operation on the first memory bank 50 may not be completed even at the time tF when the second activation command ACT is input. For example, the time when the precharge operation on the first memory bank 50 is completed (e.g., the precharge interval 1 on the first memory bank 50) may be missed. ST The end time tG of BANKPRECHARGE SECTION can be later than the time tF when the second activation command ACT is entered.

[0165] Since the first and second memory banks 50 and 60 included in a storage device 1 operate according to a memory bank interleaving method, the storage device can enter the activation region of the second memory bank 60 before the pre-charge operation of the first memory bank 50 is completed. Then, access operations can be performed on the second normal regions 611 and 621 included in the second memory bank 60. Therefore, the pre-charge region 1 of the first memory bank 50... ST BANK PRECHARGE SECTION and the active section 2 of the second memory bank 60 ND BANK ACTIVE SECTION can overlap.

[0166] Similarly, since the first and second memory banks 50 and 60 included in a storage device 1 operate according to a memory bank interleaving method, the storage device can enter the active region of the first memory bank 50 before the pre-charge operation of the second memory bank 60 is completed. Then, access operations can be performed on the first normal regions 511 and 521 included in the first memory bank 50. Therefore, the pre-charge region 2 of the second memory bank 60... ND BANK PRECHARGE SECTION and the active section 1 of the first memory bank 50 ST BANK ACTIVE SECTION can overlap.

[0167] In summary, since the storage device has entered the pre-charge interval 1 of the first storage cell 50... STIn the case of BANKPRECHARGE SECTION, an access operation is performed on the first row hammer regions 512 and 522 included in the first memory bank 50. ST BANK FCC OPERATION, therefore the precharge interval 1 of the first memory bank 50 ST The BANK PRECHARGESECTION can be delayed by a preset time tDELAY. During the precharge interval 1 of the first storage unit 50... ST BANK PRECHARGESECTION and the activation zone 2 of the second memory bank 60 ND When the BANK ACTIVE SECTIONs overlap (because the first and second storage banks 50 and 60 included in a storage device 1 can operate according to the storage bank interleaving method), this phenomenon can be covered as if it had not occurred.

[0168] Similarly, since the storage device has entered the pre-charge zone 2 of the second storage cell 60 ND In the case of BANKPRECHARGE SECTION, an access operation is performed on the second row hammer regions 612 and 622 included in the second memory bank 60. ND BANK FCC OPERATION, therefore the precharge zone 2 of the second memory bank 60 ND The BANK PRECHARGESECTION can be delayed by a preset time tDELAY. This occurs during the pre-charge interval 2 of the second storage unit 60. ND BANK PRECHARGESECTION and the active region 1 of the first memory bank 50 ST When the BANK ACTIVE SECTIONs overlap (because the first and second storage banks 50 and 60 included in a storage device 1 can operate according to the storage bank interleaving method), this phenomenon can be covered as if it had not occurred.

[0169] Although various embodiments have been described for illustrative purposes, it will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention as defined by the appended claims. Embodiments can be combined to form other embodiments.

Claims

1. A storage device, comprising: The storage unit comprises multiple storage blocks, each of which is divided into a normal area and a row hammer area; Command control circuitry adapted to perform access operations on the normal area in response to an activation command; Internal command generation circuitry, suitable for generating internal commands in response to precharge commands; The target address generation circuit is adapted to store a count of each logic level combination of the received address in the row hammer area by performing an access operation on the row hammer area in response to the internal command, and to set the address corresponding to the count as the target address when the count meets a preset condition. as well as The refresh control circuit is suitable for controlling the intelligent refresh operation on the target address.

2. The storage device according to claim 1, wherein, The internal command generation circuit generates an internal activation command in response to the precharge command, and generates an internal precharge command in the internal command after a preset time.

3. The storage device according to claim 2, wherein, The command control circuit activates the memory in response to the activation command and precharges the memory in response to the internal precharge command.

4. The storage device according to claim 2, wherein, The internal command generation circuit includes: A first generation circuit is adapted to enable the internal activation command during the preset time in response to the precharge command; and The second generation circuit is adapted to sequentially generate an internal read command and an internal write command within the activation range of the internal activation command, and to generate the internal precharge command in response to a prohibited internal activation command.

5. The storage device according to claim 4, wherein, The target address generation circuit includes: A region control circuit is adapted to: increase a count read by performing an internal read operation on a row hammer region corresponding to an input address, the count being incremented by an incrementing count in response to the internal read command; and store the incremented count in the row hammer region corresponding to the input address by performing an internal write operation in response to the internal write command. A storage circuit is adapted to: compare the incremented count with a stored count; when the incremented count is greater than the stored count, store the incremented count by replacing the stored count with the incremented count and generating a flag signal; and reset the stored count in response to a reset signal; and A target address output circuit is adapted to: store the input address as the target address in response to a generated flag signal, output the target address to the memory during the smart refresh operation, and generate the reset signal after the smart refresh operation is performed.

6. The storage device according to claim 5, wherein, The bit lines included in the normal region and the bit lines included in the hammer region share the same segment line.

7. The storage device according to claim 6, wherein, The area control circuit: During the internal read operation, the count stored in the first selected memory cell, coupled to the word line corresponding to the input address, is read through the segmented line from the first memory cell included in the row hammer region. During the internal write operation, the incremented count is written to the first selected memory cell via the segment line, and In response to the reset signal, the count stored in the target memory cell, which is coupled to the word line corresponding to the target address, in the first memory cell is reset.

8. The storage device according to claim 7, wherein, The command control circuit: Reading first data from a second selected memory cell in the second memory cell included in the normal region, coupled to a word line corresponding to the input address, and outputting the read first data through the segment line during a normal read operation, and During a normal write operation, the second data received through the segment line is written to the second selected storage cell.

9. The storage device according to claim 1, wherein, The intelligent refresh operation includes refreshing one or more word lines in the memory that are arranged adjacent to the word line corresponding to the target address.

10. A method of operating a storage device, the storage device comprising a first storage bank and a second storage bank: the first storage bank having a plurality of storage blocks each divided into a first normal region and a first row hammer region, and the second storage bank having a plurality of storage blocks each divided into a second normal region and a second row hammer region, the method comprising: Access operations are performed on the first normal region and the second normal region according to the memory interleaving method, wherein the active region of the first memory partially overlaps with the precharge region of the second memory, and the active region of the second memory partially overlaps with the precharge region of the first memory. During the hammer-enabled interval, an internal command is generated in response to a precharge command corresponding to the precharge interval of the first memory or the second memory. In response to the internal command, the system performs an access operation on the first row hammer region or the second row hammer region to store a count of each logic level combination of the received address in the first row hammer region or the second row hammer region, and sets the address corresponding to the count as the target address when the count meets a preset condition. as well as Perform a smart refresh operation on the target address.

11. The method of claim 10, further comprising: An internal precharge command is generated after a preset time elapsed from the time point when the internal activation command in the internal command is generated.

12. The method of claim 11, further comprising: During the hammer-enabled interval, the first memory bank or the second memory bank is activated in response to the activation command, and In response to the internal precharge command, the first memory cell or the second memory cell is precharged.

13. The method according to claim 11, wherein, Generating the internal activation command includes: enabling the internal activation command for the preset time in response to the precharge command.

14. The method according to claim 13, wherein, Generating the internal precharge command includes: generating the internal precharge command in response to a disabled internal activation command.

15. The method of claim 14, further comprising: Within the activation range of the internal activation command, internal read commands and internal write commands are generated sequentially.

16. The method according to claim 15, wherein, Setting the address corresponding to the count to the target address includes: The count read by performing an internal read operation on the first or second row hammer region corresponding to the input address is increased by being incremented in response to the internal read command, and the increased count is stored in the first or second row hammer region corresponding to the input address by performing an internal write operation in response to the internal write command. The incremented count is compared with the stored count. When the incremented count is greater than the stored count, the incremented count is saved by replacing the stored count with the incremented count and generating a flag signal. The stored count is also reset in response to a reset signal. In response to the generated flag signal, the input address is stored as the target address, and the target address is output to the first memory bank or the second memory bank during the smart refresh operation; and The reset signal is generated after the smart refresh operation is performed.

17. The method of claim 16, wherein: The bit lines included in the first normal region and the bit lines included in the first hammer region share a first segment line, and the bit lines included in the second normal region and the bit lines included in the second hammer region share a second segment line. Storing the increased count in the first hammer area or the second hammer area includes: During the internal read operation, the count stored in the first selected memory cell, which is coupled to the word line corresponding to the input address, is read through the first segment line or the second segment line from the first memory cell included in the first row hammer region or the second memory cell included in the second row hammer region. During the internal write operation, the increased count is written to the first selected memory cell via the first segment line or the second segment line; and In response to the reset signal, the count stored in the target storage cell, which is coupled to the word line corresponding to the target address, in the first storage cell or the second storage cell is reset.

18. The method of claim 17, further comprising: Read first data from a second selected memory cell in the third memory cell included in the first normal region or the fourth memory cell included in the second normal region, coupled to a word line corresponding to the input address, and output the read first data through the first segment line or the second segment line during normal read operation; as well as During a normal write operation, the second data received via the first segment line or the second segment line is written to the second selected storage cell.

19. The method of claim 10, further comprising: During the hammer-prohibition interval, in response to a precharge command corresponding to the precharge interval of the first memory or the second memory, the first memory or the second memory is precharged.

20. The method of claim 10, wherein, The intelligent refresh operation includes refreshing one or more word lines in each of the first and second memory banks that are arranged adjacent to the word line corresponding to the target address.

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