Semiconductor memory device and method of operating a semiconductor memory device

Abstract

Semiconductor memory devices and methods of operating semiconductor memory devices are provided. The semiconductor memory devices include an array of memory cells and a plurality of data input / output (I / O) pins. The plurality of data I / O pins are configured to receive write data to be stored in the array of memory cells or output read data stored in the array of memory cells. The semiconductor memory devices are configured to perform a burst operation in which a single set of data including a plurality of data bits is input or output through the plurality of data I / O pins based on a single command received from an external memory controller. A number of the plurality of data I / O pins corresponds to an integer that is not a power of two. A burst length representing a unit of the burst operation corresponds to an integer that is not a power of two.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2021-0140424, filed on October 20, 2021, with the Korean Intellectual Property Office (KIPO), and Korean Patent Application No. 10-2022-0040041, filed on March 31, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The example embodiments generally relate to semiconductor integrated circuits, and more specifically to semiconductor memory devices and methods of operating semiconductor memory devices. Background Technology

[0003] Semiconductor memory devices can be classified into non-volatile memory devices (such as flash memory) and volatile memory devices (such as dynamic random access memory (DRAM)). The high-speed operation and cost-effectiveness of volatile memory devices make their use as system memory feasible.

[0004] Recently, the integration and capacity of semiconductor memory devices have been increasing, as have data transfer rates. Consequently, the total number of bits transferred for each memory access can increase, and additional input / output (I / O) pins or lines, along with corresponding module / board signal traces and connector pins, may be required. However, the additional I / O pins can increase the overall cost of the memory device. Therefore, techniques for sending more bits without excessively increasing the number of I / O pins have been investigated. Summary of the Invention

[0005] Without excessively increasing costs, at least one example embodiment of this disclosure provides a semiconductor memory device capable of improving or enhancing bandwidth and signal integrity characteristics.

[0006] At least one exemplary embodiment of this disclosure provides a method of operating a semiconductor memory device.

[0007] According to an example embodiment, a semiconductor memory device includes a memory cell array and a plurality of data input / output (I / O) pins. The plurality of data I / O pins are configured to receive write data to be stored in the memory cell array or to output read data stored in the memory cell array. The semiconductor memory device is configured to perform burst operations, in which a single dataset comprising multiple data bits is input or output through the plurality of data I / O pins based on a single command received from an external memory controller. The number of the plurality of data I / O pins corresponds to an integer not a power of two. The burst length, representing a unit of the burst operation, corresponds to an integer not a power of two.

[0008] According to an example embodiment, a method of operating a semiconductor memory device includes receiving a write command or a read command. The method includes at least one of the following operations: a data write operation in which write data is stored in a memory cell array; or a data read operation in which read data stored in the memory cell array is retrieved from the memory cell array, wherein the steps performed are based on the write command or the read command. During the data write operation, the write data is received through a plurality of data input / output (I / O) pins. During the data read operation, the read data is output through the plurality of data input / output (I / O) pins. The operations of receiving write data and / or outputting read data are performed based on burst operations, in which a single dataset comprising a plurality of data bits is input or output through the plurality of data I / O pins based on a single command received from an external memory controller. The number of the plurality of data I / O pins corresponds to an integer not a power of two. The burst length, representing a unit of the burst operation, corresponds to an integer not a power of two.

[0009] According to an example embodiment, a semiconductor memory device includes a memory cell array, a plurality of data input / output (I / O) pins, a data processing path, and a clock divider. The plurality of data I / O pins are configured to receive write data to be stored in the memory cell array or to output read data stored in the memory cell array. The data processing path is between the memory cell array and the plurality of data I / O pins. The clock divider is configured to generate a second command clock signal based on a first command clock signal. A write operation to store data in the memory cell array is performed based on a write command, or a read operation to retrieve data stored in the memory cell array from the memory cell array is performed based on a read command. The operations of receiving write data and / or outputting read data are performed based on burst operations, in which a single dataset including multiple data bits is input or output through the plurality of data I / O pins based on a single command received from an external memory controller. The number of the plurality of data I / O pins corresponds to an integer not a power of two. The burst length, representing a unit of a burst operation, corresponds to an integer not a power of two and an integer multiple of three. The plurality of data bits in the single dataset includes first data bits corresponding to written or read data. The number of first data bits corresponds to an integer that is a power of two. The memory cell array, data processing path, and the plurality of data I / O pins are configured to operate based on a data clock signal and a second command clock signal. The division ratio of the clock divider corresponds to an integer that is not a power of two and is an integer that is a multiple of three.

[0010] In the semiconductor memory device and the method of operating the semiconductor memory device according to the example embodiment, both the burst length and the number of data I / O pins can be implemented as integers that are not powers of two. Even if both the burst length and the number of data I / O pins correspond to integers that are not powers of two, the actual data to be written or read can be implemented as multiple pieces of information (e.g., data bits) corresponding to integers that are powers of two. Additionally, supplementary data required to write or read the actual data, or dummy data to be discarded, can also be included in the single dataset. Therefore, the semiconductor memory device can have improved or enhanced bandwidth and signal integrity characteristics without excessively increasing cost. Attached Figure Description

[0011] The illustrative, non-limiting exemplary embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0012] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0013] Figure 2 This is a diagram used to describe a burst operation performed in a semiconductor memory device according to an example embodiment.

[0014] Figure 3 This is a block diagram illustrating a memory system including a semiconductor memory device according to an example embodiment.

[0015] Figure 4 It is shown Figure 1 A block diagram of an example semiconductor memory device.

[0016] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C , Figure 10 and Figure 11 This is a diagram used to illustrate the operation of a semiconductor memory device according to an example embodiment.

[0017] Figure 12 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0018] Figure 13 It is shown Figure 12 A block diagram of an example semiconductor memory device.

[0019] Figure 14 , Figure 15A , Figure 15B , Figure 16A and Figure 16B This is a diagram used to illustrate the operation of a semiconductor memory device according to an example embodiment.

[0020] Figure 17 and Figure 18 This is a flowchart illustrating a method of operating a semiconductor memory device according to an example embodiment.

[0021] Figure 19 This is a block diagram illustrating an example of a memory module that can be used in a memory system according to an example embodiment.

[0022] Figure 20 This is a block diagram illustrating an example memory system according to an example embodiment.

[0023] Figure 21 This is a block diagram illustrating an electronic system including a memory module according to an example embodiment. Detailed Implementation

[0024] Various exemplary embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are illustrated. However, this disclosure may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Throughout this application, the same reference numerals denote the same elements.

[0025] Figure 1 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0026] Reference Figure 1 The semiconductor memory device 100 includes a memory cell array 110, a data processing path 120, and multiple data input / output (I / O) pins 130.

[0027] The memory cell array 110 stores data. For example, the memory cell array 110 may include multiple memory cells for storing data.

[0028] In some example embodiments, the semiconductor memory device 100 may be a volatile memory device. For example, the semiconductor memory device 100 may be dynamic random access memory (DRAM), and the memory cell array 110 may include a plurality of dynamic memory cells.

[0029] Multiple data I / O pins 130 (e.g., multiple data I / O pins DQ) receive write data WDAT to be stored in memory cell array 110, or output read data RDAT stored in (and obtained from) memory cell array 110. For example, the pins may be contact pads or contact pins, but the example embodiment is not limited thereto.

[0030] The data processing path 120 can be set or located between the memory cell array 110 and multiple data I / O pins 130, and can perform data processing for storing write data WDAT in the memory cell array 110 or for outputting read data RDAT.

[0031] The memory cell array 110, data processing path 120, and multiple data I / O pins 130 can operate based on the data clock signal WCK.

[0032] Semiconductor memory device 100 can perform data write operations or data read operations. For example, when a write command is received from outside the semiconductor memory device 100 (e.g., from an external memory controller), the semiconductor memory device 100 can perform a write operation to store data WDAT in the memory cell array 110 based on the write command, and during the data write operation, the write data WDAT can be received through multiple data I / O pins 130. When a read command is received from outside, the semiconductor memory device 100 can perform a read operation to obtain data RDAT stored in the memory cell array 110 based on the read command, and during the data read operation, the read data RDAT can be output through multiple data I / O pins 130.

[0033] The semiconductor memory device 100 can perform burst operations based on a single command received from an external source (e.g., from an external memory controller), in which a single dataset DS comprising multiple data bits is input or output through multiple data I / O pins 130.

[0034] The operations of receiving write data WDAT during a data write operation and outputting read data RDAT during a data read operation can be performed based on burst operations. For example, a single dataset DS may include write data WDAT or read data RDAT. For example, based on a single write command, a single dataset DS including write data WDAT can be input through multiple data I / O pins 130. For example, based on a single read command, a single dataset DS including read data RDAT can be output through multiple data I / O pins 130.

[0035] In the semiconductor memory device 100 according to the example embodiment, the number (or quantity) of a plurality of data I / O pins 130 may correspond to an integer that is not a power of two (e.g., an integer other than a power of two), and the burst length representing a unit of burst operation may correspond to an integer that is not a power of two, which will be referred to Figure 2 Described.

[0036] Figure 2 This is a diagram used to describe a burst operation performed in a semiconductor memory device according to an example embodiment.

[0037] Reference Figure 2 An example of a single dataset DS being input or output via multiple data I / O pins DQ based on a single command during a burst operation is shown.

[0038] Burst operation means sequentially increasing and / or decreasing the value from the memory controller (e.g., Figure 3The memory controller 20 in the memory provides the initial address of the semiconductor memory device to write large amounts of data into the semiconductor memory device (e.g., Figure 1 In and / or from a semiconductor memory device (e.g., semiconductor memory device 100) and / or from a semiconductor memory device (e.g., Figure 1 The semiconductor memory device 100 performs operations that read large amounts of data. The basic unit of a burst operation can be represented as the burst length BL.

[0039] Figure 2 An example is shown with multiple data I / O pins DQ, including the first data I / O pin to the (m+1)th data I / O pins DQ0, DQ1, ..., DQm (e.g., (m+1) data I / O pins, where m is a natural number greater than or equal to two). Additionally, Figure 2 An example is shown where the burst length BL is (n+1), where n is a natural number greater than or equal to four.

[0040] A single dataset DS may include multiple data bits BL0, BL1, BL2, BL3, ..., BLn. The total number of data bits BL0 to BLn may correspond to a value obtained by multiplying the number of data I / O pins DQ0 to DQm by the burst length BL (e.g., (m+1)×(n+1)), and may represent a unit of information based on a single command being sent at once (e.g., input or output).

[0041] During burst operations, data bits BL0 to BLn can be sequentially input or output via data I / O pins DQ0 to DQm based on the data clock signal WCK. For example, (m+1) data bits BL0 can be simultaneously input or output via (m+1) data I / O pins DQ0 to DQm. Next, (m+1) data bits BL1 can be simultaneously input or output via (m+1) data I / O pins DQ0 to DQm. Following this, (m+1) data bits BL2 can be simultaneously input or output via (m+1) data I / O pins DQ0 to DQm. Subsequently, (m+1) data bits BL3 can be simultaneously input or output via (m+1) data I / O pins DQ0 to DQm. Finally, (m+1) data bits BLn can be simultaneously input or output via (m+1) data I / O pins DQ0 to DQm. As a result, the (n+1) data bits BL0 to BLn corresponding to the burst length BL can be sequentially input or output through a data I / O pin (e.g., through data I / O pin DQ0).

[0042] In the semiconductor memory device 100 according to the example embodiment, the number of data I / O pins DQ0 to DQm (e.g., (m+1)) may correspond to an integer that is not a power of two. Additionally, the burst length BL (e.g., (n+1)) may correspond to an integer that is not a power of two. For example, at least one of the number of data I / O pins DQ0 to DQm and the burst length BL may correspond to an integer that is a multiple of three.

[0043] For reference Figure 1 As described, a single dataset DS may include write data WDAT or read data RDAT. In this case, multiple data bits BL0 to BLn included in a single dataset DS may include a first data bit corresponding to write data WDAT or read data RDAT. For example, the first data bit may represent the actual data that will be written or read (e.g., user data, etc.). For example, the number of first data bits may correspond to a power of two (i.e., 2). N , where N is a positive integer.

[0044] In some example embodiments, a single dataset DS may also include additional data associated with or related to the written data WDAT or the read data RDAT. In this case, the multiple data bits BL0 to BLn included in a single dataset DS may also include second data bits in addition to the first data bits, and the second data bits may correspond to the additional data. For example, the additional data may include at least one of the following: Data Bus Inversion (DBI) information required to write or read actual data, error correction code (ECC) information (e.g., parity bit), and metadata, but the example embodiments are not limited thereto. For example, the number of second data bits may correspond to an integer as a power of two.

[0045] In other example embodiments, a single dataset DS may also include dummy data that is independent of (or unrelated to) the written data WDAT or the read data RDAT. In this case, the multiple data bits BL0 to BLn included in the single dataset DS may also include second data bits in addition to the first data bits, and the second data bits may correspond to dummy data. For example, dummy data may represent data that is discarded when not used to write or read actual data. For example, the number of second data bits may correspond to an integer that is a power of two.

[0046] In some example embodiments, even if both the number of the first data bits and the number of the second data bits correspond to integers that are powers of two, the number of multiple data bits BL0 to BLn, including the first data bits and the second data bits (e.g., (m+1)×(n+1)), may correspond to integers that are not powers of two.

[0047] Conventionally, in order to send multiple messages (e.g., data bits) corresponding to an integer power of two during a burst operation, all or at least one of the burst length and the number of data I / O pins is implemented to correspond to an integer power of two. For example, 2 x Each data bit is implemented by setting the burst length and the number of data I / O pins to 2. y and 2 z It is transmitted once based on a single command, where each of x, y, and z is a natural number and x = y + z.

[0048] To increase or enhance the bandwidth of a semiconductor memory device, increasing the burst length or the number of data I / O pins may be necessary. However, if the conventional approach described above is used, difficulties arise in implementation because all or at least one of the burst length and the number of data I / O pins must be implemented as integers corresponding to powers of two. For example, doubling the burst length can lead to a problem where signal integrity characteristics are severely degraded or worsened due to the lack of a data window. Doubling the number of data I / O pins can also result in an excessive increase in manufacturing costs.

[0049] In the semiconductor memory device 100 according to the example embodiment, both the burst length and the number of data I / O pins can be implemented as integers that are not powers of two. Even if both the burst length and the number of data I / O pins correspond to integers that are not powers of two, the actual data to be written or read can be implemented as multiple pieces of information (e.g., data bits) corresponding to integers that are powers of two. In addition, additional data required to write or read the actual data or dummy data to be discarded can also be included in a single dataset DS. Therefore, the semiconductor memory device 100 can have improved or enhanced bandwidth and signal integrity characteristics without excessively increasing cost.

[0050] For example, even if the burst length and the number of data I / O pins do not correspond to 2 respectively y and 2 z The result is obtained by multiplying the burst length by the number of data I / O pins, which is equal to 2. x The corresponding value can also be implemented, making 2 x Information (e.g., data bits) is sent. For another example, 2 bits are sent if necessary. x Information can be conveyed by discarding some bits. Optionally, when the total is 2... x When the +a information is sent along with additional data including DBI information, ECC information, and / or metadata, even if the burst length and the number of data I / O pins do not correspond to 2 respectively. y and 2 zThe result is obtained by multiplying the burst length by the number of data I / O pins, which is equal to 2. x The value corresponding to +a can also be achieved, where a is a natural number.

[0051] Figure 3 This is a block diagram illustrating a memory system including a semiconductor memory device according to an example embodiment.

[0052] Reference Figure 3 The memory system 10 includes a memory controller 20 and a semiconductor memory device 40. The memory system 10 may also include multiple signal lines 30 that electrically connect the memory controller 20 and the semiconductor memory device 40.

[0053] The semiconductor memory device 40 is controlled by the memory controller 20. For example, based on a request from a host device (not shown), the memory controller 20 may store data (e.g., write or program) in the semiconductor memory device 40, or may retrieve data from the semiconductor memory device 40 (e.g., read or sense).

[0054] Multiple signal lines 30 may include control lines, command lines, address lines, data input / output (I / O) lines, and power lines. The memory controller 20 can send commands (CMD), addresses (ADDR), and control signals (CTRL) to the semiconductor memory device 40 via the command lines, address lines, and control lines; can exchange data (DAT) with the semiconductor memory device 40 via the data I / O lines; and can send the power supply voltage (PWR) to the semiconductor memory device 40 via the power lines. Although Figure 3 Not shown, but the multiple signal lines 30 may also include a DQS line for transmitting a data strobe signal (DQS) signal.

[0055] Semiconductor memory device 40 may be a semiconductor memory device according to an example embodiment. For example, as shown in reference... Figure 1 and Figure 2 As described, the semiconductor memory device 40 includes data I / O pins, the number of which corresponds to an integer not a power of two, and the data I / O pins can be connected to data I / O lines to receive or output data DAT. The data DAT may include a dataset for performing burst operations, and the burst length of the dataset may correspond to an integer not a power of two.

[0056] In some example embodiments, at least a portion or all of the signal lines 30 may be referred to as a channel. The term "channel" as used herein may refer to a signal line that includes data I / O lines for transmitting data DAT. However, example embodiments are not limited thereto, and a channel may also include command lines for transmitting command CMD and / or address lines for transmitting address ADDR.

[0057] Figure 4 It is shown Figure 1 A block diagram of an example semiconductor memory device.

[0058] Reference Figure 4 The semiconductor memory device 200 may include control logic circuitry 210, address register 220, memory bank control logic circuitry 230, row address multiplexer (RA MUX) 240, refresh counter 245, column address (CA) latch 250, row decoder 260, column decoder 270, memory cell array 300, sense amplifier unit 285, input / output (I / O) gating circuitry 290, data I / O buffer 295, and / or data I / O pins 299. For example, the semiconductor memory device 200 may be DRAM.

[0059] The memory cell array 300 may include first memory arrays 310 to eighth memory arrays 380 (e.g., first memory arrays to eighth memory arrays 310, 320, 330, 340, 350, 360, 370, and 380). The row decoder 260 may include first memory cell row decoders 260a to 260h respectively connected to the first memory arrays 310 to 380. The column decoder 270 may include first memory cell column decoders 270a to 270h respectively connected to the first memory arrays 310 to 380. The sense amplifier unit 285 may include first memory cell sense amplifiers 285a to 285h respectively connected to the first memory arrays 310 to 380.

[0060] The first memory arrays 310 to 380, the first memory row decoders 260a to 260h, the first memory column decoders 270a to 270h, and the first memory sense amplifiers 285a to 285h can form the first to eighth memory arrays. Each of the first memory arrays 310 to 380 may include multiple word lines WL, multiple bit lines BTL, and multiple memory cells MC formed at the intersections of the word lines WL and the bit lines BTL.

[0061] Although Figure 4 A semiconductor memory device 200 including eight memory cells is shown, but the semiconductor memory device 200 may include any number of memory cells; for example, one, two, four, eight, sixteen, or thirty-two memory cells, or any number between one and thirty-two.

[0062] Address register 220 can be accessed from the memory controller (e.g., Figure 3The memory controller 20 receives an address ADDR that includes the bank address BANK_ADDR, the row address ROW_ADDR, and the column address COL_ADDR. The address register 220 can provide the received bank address BANK_ADDR to the bank control logic circuit 230, provide the received row address ROW_ADDR to the row address multiplexer 240, and provide the received column address COL_ADDR to the column address latch 250.

[0063] The memory bank control logic circuit 230 can generate a memory bank control signal in response to the memory bank address BANK_ADDR. One of the first memory bank row decoders 260a to the eighth memory bank row decoder 260h corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal, and one of the first memory bank column decoders 270a to the eighth memory bank column decoder 270h corresponding to the memory bank address BANK_ADDR can be activated in response to the memory bank control signal.

[0064] The row address multiplexer 240 can receive the row address ROW_ADDR from the address register 220 and the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 can selectively output either the row address ROW_ADDR or the refresh row address REF_ADDR as a row address RA. The row address RA output from the row address multiplexer 240 can be applied to the first memory bank row decoders 260a to the eighth memory bank row decoders 260h.

[0065] The activated bank row decoders in the first bank row decoder 260a to the eighth bank row decoder 260h can decode the row address RA output from the row address multiplexer 240 and can activate the word line WL corresponding to the row address RA. For example, the activated bank row decoder can generate a word line drive voltage and apply the word line drive voltage to the word line WL corresponding to the row address RA.

[0066] Column address latch 250 may receive column address COL_ADDR from address register 220 and may temporarily store the received column address COL_ADDR. In some example embodiments, in burst mode performing burst operations, column address latch 250 may generate a column address that is incremented from the received column address COL_ADDR. Column address latch 250 may apply the temporarily stored or generated column address to first bank column decoders 270a to eighth bank column decoders 270h.

[0067] The active memory bank column decoder among the first memory bank column decoders 270a to the eighth memory bank column decoder 270h can decode the column address COL_ADDR output from the column address latch 250, and can control the I / O gate circuit 290 to output data corresponding to the column address COL_ADDR.

[0068] I / O gate circuit 290 may include a circuit system for gate input / output data. I / O gate circuit 290 may also include a read data latch for storing data output from the first memory array 310 to the eighth memory array 380, and may also include a write controller for writing data to the first memory array 310 to the eighth memory array 380.

[0069] Data DAT read from one of the first memory arrays 310 to the eighth memory array 380 can be sensed by a sense amplifier connected to that memory array from which the data DAT will be read, and can be stored in a read data latch. The data DAT stored in the read data latch can be provided to the memory controller via data I / O buffer 295 and data I / O pin 299.

[0070] Data DAT to be written to one of the first memory arrays 310 to the eighth memory arrays 380 can be provided from the memory controller via data I / O buffer 295 and data I / O pin 299. The received data DAT can be provided to I / O gate circuit 290, and I / O gate circuit 290 can write the data DAT to a subpage of a target page in a memory array via a write driver.

[0071] In a write operation of the semiconductor memory device 200, the data I / O buffer 295 can receive data DAT from the memory controller and provide the received data DAT to the I / O gate circuit 290. In a read operation of the semiconductor memory device 200, the data DAT can be provided from the I / O gate circuit 290 to the memory controller.

[0072] Control logic circuitry 210 can control the operation of semiconductor memory device 200. For example, control logic circuitry 210 can generate control signals for semiconductor memory device 200 to perform write and / or read operations. Control logic circuitry 210 may include command decoder 211 for decoding command CMD received from memory controller and mode register 212 for setting the operating mode of semiconductor memory device 200. In some example embodiments, the operations described herein as being performed by control logic circuitry 210 may be performed by processing circuitry system. For example, command decoder 211 can generate control signals corresponding to command CMD by decoding write enable signals, row address strobe signals, column address strobe signals, chip select signals, etc.

[0073] Memory cell array 300 can correspond to Figure 1 The memory cell array 110 in the middle. The sense amplifier unit 285, I / O gate circuit 290, and data I / O buffer 295, etc., can correspond to... Figure 1 Data processing path 120. Data I / O pin 299 can correspond to Figure 1 Multiple data I / O pins 130 are present in the memory cell array 300. The data I / O buffer 295 and data I / O pins 299 can operate based on a data clock signal WCK. Although not shown in detail, the sense amplifier unit 285, I / O gate circuit 290, etc., can also operate based on the data clock signal WCK. For example, the data clock signal WCK can be received from the memory controller or can be generated internally in the semiconductor memory device 200.

[0074] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9A , Figure 9B , Figure 9C , Figure 10 and Figure 11 This is a diagram used to illustrate the operation of a semiconductor memory device according to an example embodiment.

[0075] Reference Figure 5 An example of a sudden operation is shown. Figure 5 In the example, multiple commands CMD1, CMD2, and CMD3 can be received consecutively or sequentially, and therefore multiple datasets DS1, DS2, and DS3 corresponding to the multiple commands CMD1 to CMD3 can be received consecutively or sequentially. Additionally, tCCD can represent the minimum time interval required between two consecutive commands.

[0076] For example, when multiple commands CMD1 to CMD3 are write commands, multiple datasets DS1 to DS3, including the data to be written, can be continuously input through multiple data I / O pins, and the data write operation can be executed based on the write command and the written data. Similarly, when multiple commands CMD1 to CMD3 are read commands, a data read operation can be executed based on the read command to obtain the read data, and multiple datasets DS1 to DS3, including the read data, can be continuously output through multiple data I / O pins.

[0077] Reference Figure 6 The burst length and the number of data I / O pins are both implemented as integers corresponding to powers of two, and a conventional (or existing) example is shown. For example, Figure 6 Showing based on a single command (e.g., Figure 5 The command CMD1 in the command is a single dataset that is input or output (e.g., Figure 5 Examples of datasets (DS1) in the dataset.

[0078] exist Figure 6 In the example, the burst length can be 2 4 =16, the number of data I / O pins DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6 and DQ7 can be 2 3 =8, therefore a single dataset can include 16 × 8 = 128 data bits BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11, BL12, BL13, BL14, and BL15. Additionally, a Data Mask Inversion (DMI) I / O pin for additional information can be additionally formed, and a single dataset can also include 16 DBI bits DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, and DBI15 received via the DMI I / O pin. For example, see reference... Figure 2 As described, a single dataset may also include additional data associated with the written data WDAT or the read data RDAT, and the DBI bits DBI0 to DBI15 may correspond to the DBI information included in the additional data.

[0079] Therefore, in Figure 6 In the example, a single dataset sent based on a single command may include a total of 144 (128+16) bits transmitted through a total of 9 (=8+1) I / O pins.

[0080] In addition, Figure 6In the example, data bits BL0 to BL15 and DBI bits DBI0 to DBI15 can be input or output based on the data clock signal WCKc, and the data transmission operation can be performed based on a four-times data rate (QDR) scheme, in which four bits are sent during a time period (or cycle) tCKc of the data clock signal WCKc. Therefore, the four time periods of the data clock signal WCKc can be repeated within tCCD (e.g., tCCD = 4 × tCKc), and a burst length of 16 can be achieved.

[0081] In the standard low-power double data rate 5 (LPDDR5) standard, burst operations use Figure 6 The two datasets shown are used in this implementation. In this case, the burst length is 16, the number of data I / O pins is 16, and a total of 256 data bits are transmitted. Additionally, 32 DBI bits are transmitted through two DMI I / O pins. Therefore, a total of 288 bits can be transmitted in a single burst operation through a total of 18 I / O pins. For example, when tCCD is approximately 1.88 nanoseconds (ns), the time period tCKc of the data clock signal WCKc can be approximately 470 picoseconds (ps), and the time required to transmit one bit (e.g., one unit interval (UI)) can be approximately 118 ps.

[0082] Reference Figure 7 The burst length and the number of data I / O pins are both implemented as integers corresponding to powers of two, as shown in a conventional (or existing) example. Additionally, Figure 7 Showing with Figure 6 Compared to an example where the bandwidth is doubled. (And) Figure 6 The example is the same. Figure 7 This shows an example of a single dataset being input or output based on a single command.

[0083] exist Figure 7 In the example, the burst length can be 2 5 =32, the number of data I / O pins DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6 and DQ7 can be 2. 3=8, therefore a single dataset can include 32×8=256 data bits BL0, BL1, BL2, BL3, BL4, BL5, BL6, BL7, BL8, BL9, BL10, BL11, BL12, BL13, BL14, BL15, BL16, BL17, BL18, BL19, BL20, BL21, BL22, BL23, BL24, BL25, BL26, BL27, BL28, BL29, BL30 and BL31. Additionally, a DMI I / O pin for additional information can be additionally formed, and a single dataset may also include 32 DBI bits (DBI0, DBI1, DBI2, DBI3, DBI4, DBI5, DBI6, DBI7, DBI8, DBI9, DBI10, DBI11, DBI12, DBI13, DBI14, DBI15, DBI16, DBI17, DBI18, DBI19, DBI20, DBI21, DBI22, DBI23, DBI24, DBI25, DBI26, DBI27, DBI28, DBI29, DBI30, and DBI31) received via the DMI I / O pin. For example, DBI bits DBI0 to DBI31 may correspond to references. Figure 2 Describes the DBI information.

[0084] Therefore, in Figure 7 In the example, a single dataset sent based on a single command may include a total of 288 (256+32) bits transmitted through a total of 9 (=8+1) I / O pins.

[0085] In addition, Figure 7 In the example, data bits BL0 to BL31 and DBI bits DBI0 to DBI31 can be input or output based on the data clock signal WCKr, and the data transmission operation can be performed based on a QDR scheme, in which four bits are sent during a period tCKr of the data clock signal WCKr. Therefore, eight periods of the data clock signal WCKr can be repeated within tCCD (e.g., tCCD = 8 × tCKr), and a burst length of 32 can be achieved.

[0086] In the recently discussed next-generation standard, Low Power Double Data Rate 6 (LPDDR6), there is a problem with burst operation. Figure 7The two datasets shown are implemented with the consideration of doubling the bandwidth compared to the LPDDR5 standard. In this case, the burst length is 32, the number of data I / O pins is 16, and a total of 512 data bits are transmitted. Additionally, 64 DBI bits are transmitted through two DMI I / O pins. Therefore, a total of 576 bits can be transmitted in a single burst operation through a total of 18 I / O pins. As a result, in Figure 7 In the example, with Figure 6 Compared to the previous example, the burst length can be doubled (16→32), the number of bits included in a single dataset can be doubled (144→288), and therefore the bandwidth can be doubled. However, in Figure 7 In the example, with Figure 6 Compared to the previous example, the time period tCKr of the data clock signal WCKr can be reduced to approximately half. For example, when tCCD equals approximately 1.88 ns, compared to... Figure 6 Compared to the previous example, the time period tCKr of the data clock signal WCKr can be reduced to approximately 235 ps, and the time required to send one bit can be reduced to approximately 59 ps (e.g., 1 UI = 59 ps). As a result, in Figure 7 In the example, with Figure 6 Compared to other examples, this can lead to serious degradation or deterioration of signal integrity characteristics.

[0087] Although not shown in detail, it is possible to double the bandwidth by doubling the number of I / O pins. However, in this case, the manufacturing cost could increase excessively.

[0088] Reference Figure 8 An example is shown where, according to the example embodiment, both the burst length and the number of data I / O pins are implemented as integers that are not powers of two. Additionally, Figure 8 Showing with Figure 6 Compared to examples where bandwidth is doubled. For example, both the burst length and the number of data I / O pins can be implemented as integers corresponding to multiples of three. Figure 6 and Figure 7 The example is the same. Figure 8 This shows an example of a single dataset being input or output based on a single command.

[0089] exist Figure 8 In the example, the burst length can be 24 (=3×2) 3 The number of data I / O pins DQ0, DQ1, DQ2, DQ3, DQ4, DQ5, DQ6, DQ7, DQ8, DQ9, DQ10, and DQ11 can be 12 (=3×2). 2In this scenario, a single dataset based on a single command sent can comprise a total of 288 (=24×12) bits BL0 to BL31 and DBI0 to DBI31 transmitted via a total of 12 I / O pins. In other words, in Figure 8 In the example, with Figure 7 Compared to the previous example, the same number of bits can be sent.

[0090] In addition, Figure 8 In the example, data bits BL0 to BL31 and DBI bits DBI0 to DBI31 can be input or output based on the data clock signal WCK, and the data transmission operation can be performed based on a QDR scheme, in which four bits are sent during a period tCK of the data clock signal WCK. Therefore, six periods of the data clock signal WCK can be repeated within tCCD (e.g., tCCD = 6 × tCK), and a burst length of 24 can be achieved.

[0091] exist Figure 8 In the example, with Figure 6 Compared to the previous example, the burst length can be increased by approximately 1.5 times (16→24), the number of I / O pins can be increased by approximately 1.33 times (9→12), and the number of bits included in a single dataset can be doubled (144→288), thus doubling the bandwidth. Additionally, in Figure 8 In the example, with Figure 6 Compared to the previous example, the time period tCK of the data clock signal WCK can be reduced to about 2 / 3. For example, when tCCD is equal to about 1.88ns, compared to... Figure 6 Compared to the previous example, the data clock signal WCK's duration tCK can be reduced to approximately 313 ps, and the time required to send one bit can be reduced to approximately 78 ps (e.g., 1 UI = 78 ps). As a result, in Figure 8 In the example, with Figure 7 Compared to previous examples, the bandwidth of semiconductor memory devices can be effectively increased without excessive degradation of signal integrity characteristics (e.g., while ensuring signal integrity characteristics). Furthermore, in Figure 8 In the example, with Figure 6 Compared to previous examples, the number of I / O pins can be increased without excessive increase (e.g., by about 1.33 times), so the bandwidth of the semiconductor memory device can be effectively increased without excessive cost increase (e.g., with minimal cost increase).

[0092] exist Figure 8 In the example, with Figure 7Compared to the example, data bits BL24, BL25, BL26, BL27, BL28, BL29, BL30, and BL31, and DBI bits DBI24, DBI25, DBI26, DBI27, DBI28, DBI29, DBI30, and DBI31 can be arranged, assigned, and / or mapped to correspond to data I / O pins DQ9, DQ10, and DQ11. Figure 7 and Figure 8 In the diagram, data bits BL24 to BL31 and DBI bits DBI24 to DBI31 whose arrangement, allocation, and / or mapping have been altered are indicated by shaded lines. Additionally, in... Figure 8 In the example, with Figure 7 Compared to the previous example, the data clock signal WCK's duration tCK can be increased by approximately 1.33 times, and the number of I / O pins can be increased by approximately 1.33 times. Therefore, based on Figure 8 The example described above (where both the burst length and the number of data I / O pins are implemented as integers that are not powers of two (e.g., integers that are multiples of three)) is more suitable for the LPDDR6 standard.

[0093] In some example embodiments, data bits BL0 to BL31 may be related to a reference. Figure 2 The description refers to the first data bit corresponding to the write data WDAT or read data RDAT, and the DBI bits DBI0 to DBI31 can be the reference. Figure 2 The second data bit corresponds to the additional data described. As mentioned above, even if the burst length is implemented to correspond to an integer that is not a power of two (e.g., 24) and the number of data I / O pins is implemented to correspond to an integer that is not a power of two (e.g., 12), the number of the first data bits may correspond to an integer that is a power of two (e.g., 256) and the number of the second data bits may correspond to an integer that is a power of two (e.g., 32). However, the sum of the number of the first data bits and the second data bits may correspond to an integer that is not a power of two (e.g., 288).

[0094] Reference Figure 9A , Figure 9B and Figure 9C An example is shown in which both the burst length and the number of data I / O pins, according to the example embodiment, are implemented as integers that are not powers of two.

[0095] Apart from Figure 8 The DBI bits DBI0 to DBI31 in the code are changed. Figure 9A , Figure 9B and Figure 9C Examples can be compared with Figure 8 The examples are basically the same. With Figure 8 Duplicate descriptions will be omitted.

[0096] exist Figure 9A In the example, Figure 8 The DBI bits DBI0 to DBI31 can be changed to ECC bits ECC0, ECC1, ECC2, ECC3, ECC4, ECC5, ECC6, ECC7, ECC8, ECC9, ECC10, ECC11, ECC12, ECC13, ECC14, ECC15, ECC16, ECC17, ECC18, ECC19, ECC20, ECC21, ECC22, ECC23, ECC24, ECC25, ECC26, ECC27, ECC28, ECC29, ECC30, and ECC31. In other words, as shown in the reference... Figure 2 As described, a single dataset may include additional data associated with the written data WDAT or the read data RDAT. The additional data may include ECC information, and the ECC bits ECC0 to ECC31 may correspond to the ECC information (e.g., parity bits).

[0097] exist Figure 9B In the example, Figure 8 The DBI bits DBI0 to DBI31 can be changed to the metadata bits MET0, MET1, MET2, MET3, MET4, MET5, MET6, MET7, MET8, MET9, MET10, MET11, MET12, MET13, MET14, MET15, MET16, MET17, MET18, MET19, MET20, MET21, MET22, MET23, MET24, MET25, MET26, MET27, MET28, MET29, MET30, and MET31. In other words, as shown in the reference... Figure 2 As described, a single dataset may include additional data associated with written data WDAT or read data RDAT, the additional data may include metadata, and the meta bits MET0 to MET31 may correspond to the metadata.

[0098] exist Figure 9C In the example, Figure 8 The DBI bits DBI0 to DBI31 can be changed to dummy bits DUM0, DUM1, DUM2, DUM3, DUM4, DUM5, DUM6, DUM7, DUM8, DUM9, DUM10, DUM11, DUM12, DUM13, DUM14, DUM15, DUM16, DUM17, DUM18, DUM19, DUM20, DUM21, DUM22, DUM23, DUM24, DUM25, DUM26, DUM27, DUM28, DUM29, DUM30, and DUM31. In other words, as shown in the reference... Figure 2As described, a single dataset may include dummy data that is not related to the written data WDAT or the read data RDAT and is not used and is discarded during data write / read operations, and dummy bits DUM0 to DUM31 may correspond to the dummy data.

[0099] Figure 10 This illustrates a regular example where both the burst length and the number of data I / O pins are implemented as integers corresponding to powers of two. Figure 11 An example is shown in which both the burst length and the number of data I / O pins, according to an example embodiment, are implemented as integers that are not powers of two.

[0100] Figure 10 Examples can be compared with Figure 7 The examples are basically the same. Except for some changes in the arrangement of the bits, Figure 11 Examples can be compared with Figure 8 The examples are basically the same. With Figure 7 and Figure 8 Duplicate descriptions will be omitted.

[0101] exist Figure 11 In the example, with Figure 10 Compared to the examples, data bits BL3, BL7, BL11, BL15, BL19, BL23, BL27, and BL31, and DBI bits DBI3, DBI7, DBI11, DBI15, DBI19, DBI23, DBI27, and DBI31 can be arranged, assigned, and / or mapped to correspond to data I / O pins DQ9, DQ10, and DQ11. Figure 10 and Figure 11 In this embodiment, the data bits BL3, BL7, BL11, BL15, BL19, BL23, BL27, and BL31, whose arrangement, allocation, and / or mapping are altered, and the DBI bits DBI3, DBI7, DBI11, DBI15, DBI19, DBI23, DBI27, and DBI31, are indicated by shaded lines. In other embodiments, these shaded bits may be arranged, allocated, and / or mapped to correspond to three different data I / O pins (i.e., not data I / O pins DQ9, DQ10, and DQ11).

[0102] However, the example embodiments are not limited thereto, and the bits whose arrangement, allocation and / or mapping are changed may be determined differently according to the example embodiments.

[0103] Figure 12 This is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0104] Reference Figure 12The semiconductor memory device 102 includes a memory cell array 110, a data processing path 120, and multiple data I / O pins 130. The semiconductor memory device 102 may also include a clock divider 140.

[0105] In addition to the semiconductor memory device 102 including a clock divider 140, the semiconductor memory device 102 can be connected to... Figure 1 The semiconductor memory device 100 is basically the same. (And...) Figure 1 Duplicate descriptions will be omitted.

[0106] The clock divider 140 can generate a second command clock signal TCLK based on the first command clock signal CLK. For example, the second command clock signal TCLK can be generated by dividing the first command clock signal CLK.

[0107] The memory cell array 110, data processing path 120, and multiple data I / O pins 130 can be operated based on the data clock signal WCK and the second command clock signal TCLK.

[0108] In some example embodiments, the division ratio of clock divider 140 (e.g., a value obtained by dividing the duration of the second command clock signal TCLK by the duration of the first command clock signal CLK) may correspond to an integer that is not a power of two. For example, the division ratio of clock divider 140 may correspond to an integer that is a multiple of three. However, the example embodiments are not limited to this, and the division ratio of clock divider 140 may correspond to any integer.

[0109] Figure 13 It is shown Figure 12 A block diagram of an example semiconductor memory device.

[0110] Reference Figure 13 The semiconductor memory device 202 may include control logic circuitry 210, address register 220, memory bank control logic circuitry 230, row address multiplexer 240, refresh counter 245, column address latch 250, row decoder 260, column decoder 270, memory cell array 300, sense amplifier unit 285, I / O gating circuitry 290, data I / O buffer 295, and / or data I / O pins 299. The semiconductor memory device 202 may also include a clock divider 205.

[0111] In addition to the semiconductor memory device 202 also including a clock divider 205, the semiconductor memory device 202 can be connected to... Figure 4 The semiconductor memory device 200 is basically the same. (And...) Figure 4 Duplicate descriptions will be omitted.

[0112] Clock divider 205 can correspond to Figure 12 Clock divider 140 is included. Clock divider 205 can generate a second command clock signal TCLK based on a first command clock signal CLK. Control logic circuitry 210 and address register 220 can operate based on the second command clock signal TCLK. For example, the first command clock signal CLK can be received from the memory controller or can be generated internally in the semiconductor memory device 202.

[0113] Figure 14 , Figure 15A , Figure 15B , Figure 16A and Figure 16B This is a diagram used to illustrate the operation of a semiconductor memory device according to an example embodiment.

[0114] Reference Figure 14 Examples of the data clock signal WCKc, the command clock signal CLKc, and the internal signals SIG1, SIG2, and SIG3 generated based on the data clock signal WCKc and the command clock signal CLKc are shown. For example, Figure 14 The signals in the data can be used to determine burst length, the number of data I / O pins, and single data sets, such as... Figure 6 The example shown is a typical implementation.

[0115] Reference Figure 15A Examples of the data clock signal WCK, the first command clock signal CLK, the second command clock signal TCLK, and the internal signals SIG1, SIG2, and SIG3 generated based on the data clock signal WCK, the first command clock signal CLK, and the second command clock signal TCLK are shown. For example, Figure 15A The signals in the data can be used to determine the burst length, the number of data I / O pins, and the single data set, depending on factors such as... Figure 8 In the example implemented by the example embodiment shown, for example, the value obtained by dividing the period of the second command clock signal TCLK by the period of the first command clock signal CLK (e.g., the division ratio of clock divider 140) can be three. In other words, clock divider 140 can be a 3:1 clock divider.

[0116] Reference Figure 15B Examples of the data clock signal WCK, the first command clock signal CLK, the second command clock signals TCLK1 and TCLK2, and the internal signals SIG1, SIG2, and SIG3 generated based on the data clock signal WCK, the first command clock signal CLK, and the second command clock signals TCLK1 and TCLK2 are shown. For example, Figure 15B The signals in the data can be used to determine the burst length, the number of data I / O pins, and the single data set, depending on factors such as... Figure 8In the example implemented by the example embodiment shown, for example, the value obtained by dividing the time periods of the second command clock signals TCLK1 and TCLK2 by the time period of the first command clock signal CLK (e.g., the division ratio of the clock divider 140) can be six.

[0117] Figure 15A and Figure 15B The internal signals SIG1 to SIG3 can be used with Figure 14 The internal signals SIG1 to SIG3 are essentially the same. In other words, although... Figure 14 Common examples and Figure 15A and Figure 15B The example implementation operates based on data clock signals WCKc and WCK with different time periods and command clock signals CLKc, TCLK, TCLK1, and TCLK2 with different time periods, but the same internal signals SIG1, SIG2, and SIG3 can be used by... Figure 14 Common examples and Figure 15A and Figure 15B Example embodiments are generated. Therefore, Figure 14 Common examples and Figure 15A and Figure 15B The example embodiments can be implemented using the same internal circuitry (e.g., circuitry included in the data processing path). Furthermore, these examples can be easily implemented even when performing combined operations, if desired.

[0118] In some example embodiments, the value obtained by dividing the time periods of the second command clock signals TCLK, TCLK1, and TCLK2 by the time period of the data clock signal WCK may correspond to an integer that is not a power of two. For example, the value obtained by dividing the time period of the second command clock signal TCLK by the time period of the data clock signal WCK may correspond to an integer that is a multiple of three (e.g., 6). For example, the value obtained by dividing the time periods of the second command clock signals TCLK1 and TCLK2 by the time period of the data clock signal WCK may correspond to an integer that is a multiple of three (e.g., 12).

[0119] In some example embodiments, the value obtained by dividing the duration of the first command clock signal CLK by the duration of the data clock signal WCK can correspond to an integer as a power of two (e.g., 2).

[0120] Reference Figure 16A Data read operation uses Figure 15A An example of the signals executed is shown. During a data read operation, the internal signals CSL, FRP, PDL, LTC, and EXT, as shown, can be generated. In one example, the internal signal EXT may include EXIT0 and EXIT1.

[0121] Reference Figure 16B Data write operations use Figure 15A An example of the signals being executed is shown. During a data write operation, the internal signals PWY, PCLKWC, and PWT / PDT, as shown, can be generated.

[0122] Figure 17 and Figure 18 This is a flowchart illustrating a method of operating a semiconductor memory device according to an example embodiment.

[0123] Reference Figure 1 and Figure 17 The method of operating a semiconductor memory device according to an example embodiment is performed by a semiconductor memory device 100 including a memory cell array 110 and a plurality of data I / O pins 130.

[0124] In the method of operating a semiconductor memory device according to an example embodiment, a write command or a read command is received (step S100). Based on the write command or read command, a write operation of data WDAT stored in the memory cell array 110 or a read operation of data RDAT stored in the memory cell array 110 being retrieved from the memory cell array is performed (step S200).

[0125] During a data write operation, the write data WDAT can be received via multiple data I / O pins 130. During a data read operation, the read data RDAT can be output via multiple data I / O pins 130. The operations of receiving the write data WDAT and outputting the read data RDAT can be performed based on burst operations, in which a single dataset DS comprising multiple data bits is input or output via multiple data I / O pins 130 based on a single command received from an external source.

[0126] The number of multiple data I / O pins 130 can correspond to an integer that is not a power of two, and the burst length representing the unit of burst operation can also correspond to an integer that is not a power of two. For example, see reference Figure 2 As described, at least one of the number of data I / O pins DQ0 to DQm and the burst length BL can correspond to an integer that is a multiple of three.

[0127] Reference Figure 12 and Figure 18 The method of operating the semiconductor memory device according to the example embodiment is performed by the semiconductor memory device 102, which includes a memory cell array 110, a plurality of data I / O pins 130 and a clock divider 140.

[0128] In the method of operating a semiconductor memory device according to an example embodiment, step S100 may be combined with... Figure 17 Step S100 is essentially the same. The second command clock signal TCLK can be generated by dividing the first command clock signal CLK (step S300). For example, the value obtained by dividing the time period of the second command clock signal TCLK by the time period of the first command clock signal CLK can correspond to an integer that is not a power of two. For example, the value obtained by dividing the time period of the second command clock signal TCLK by the time period of the first command clock signal CLK can correspond to an integer that is a multiple of three.

[0129] Based on a write command or a read command, a write operation is performed whereby data WDAT is written to memory cell array 110 or data is read from memory cell array 110 whereby data RDAT is retrieved from memory cell array 110 (step S200a). Except for the operations of receiving write data WDAT and outputting read data RDAT, which can also be performed based on the second command clock signal TCLK, step S200a can be similar to... Figure 17 Step S200 in the process.

[0130] As those skilled in the art will understand, the inventive concept can be embodied in a system, method, computer program product, and / or a computer program product embodied on one or more computer-readable media having computer-readable program code embodied thereon. The computer-readable program code can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing apparatus. The computer-readable medium can be a computer-readable signal medium or a computer-readable storage medium. A computer-readable storage medium can be any tangible medium that can contain or store a program used by or in conjunction with an instruction execution system, apparatus, or device. For example, a computer-readable medium can be a non-transitory computer-readable medium.

[0131] Figure 19 This is a block diagram illustrating an example of a memory module that can be used in a memory system according to an example embodiment.

[0132] Reference Figure 19The memory module 500 may include a buffer chip 590 (e.g., a register clock driver (RCD)) disposed in or mounted on the circuit board 501, multiple semiconductor memory devices 601a, 601b, 601c, 601d, 601e, 602a, 602b, 602c, 602d, 602e, 603a, 603b, 603c, 603d, 604a, 604b, 604c and 604d, module resistor units 560 and 570, a serial presence detection (SPD) chip 580 and / or a power management integrated circuit (PMIC) 585.

[0133] Buffer chip 590 can be used in memory controllers (e.g., Figure 3 The memory controller 20 controls semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, 604a to 604d, and PMIC 585. For example, buffer chip 590 can receive address ADDR, command CMD, and data DAT from the memory controller.

[0134] SPD chip 580 may be a programmable read-only memory (PROM) (e.g., electrically erasable PROM (EEPROM)). SPD chip 580 may include initial information and / or device information DI of memory module 500. In some example embodiments, SPD chip 580 may include initial information and / or device information DI of memory module 500 (such as module form, module configuration, storage capacity, module type, and / or execution environment, etc.).

[0135] When the memory system including memory module 500 is started, the memory controller can read device information DI from SPD chip 580 and identify memory module 500 based on device information DI. The memory controller can control memory module 500 based on device information DI from SPD chip 580. For example, the memory controller can identify the type of semiconductor memory device included in memory module 500 based on device information DI from SPD chip 580.

[0136] Here, the circuit board 501, serving as a printed circuit board (PCB), extends between a first edge portion 503 and a second edge portion 505 in a second direction D2 perpendicular to the first direction D1. The first edge portion 503 and the second edge portion 505 extend in the first direction D1. A buffer chip 590 is located at the center of the circuit board 501. Multiple memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d can be arranged in multiple rows between the buffer chip 590 and the first edge portion 503 and between the buffer chip 590 and the second edge portion 505. In some example embodiments, the operations described herein as being performed by the buffer chip 590 can be performed by a processing circuitry system.

[0137] In this example, semiconductor memory devices 601a to 601e and 602a to 602e may be arranged along multiple rows between buffer chip 590 and the first edge portion 503. Semiconductor memory devices 603a to 603d and 604a to 604d may be arranged along multiple rows between buffer chip 590 and the second edge portion 505. Semiconductor memory devices 601a to 601d, 602a to 602d, 603a to 603d and 604a to 604d may be referred to as data chips storing actual data, and semiconductor memory devices 601e and 602e may be referred to as parity chips storing ECC information (e.g., parity bits).

[0138] Buffer chip 590 can provide command / address signals (e.g., CA) to semiconductor memory devices 601a to 601e via command / address transmission line 561, and can provide command / address signals to semiconductor memory devices 602a to 602e via command / address transmission line 563. Additionally, buffer chip 590 can provide command / address signals to semiconductor memory devices 603a to 603d via command / address transmission line 571, and can provide command / address signals to semiconductor memory devices 604a to 604d via command / address transmission line 573.

[0139] Command / address transmission lines 561 and 563 may be jointly connected to module resistor unit 560 located adjacent to the first edge portion 503, and command / address transmission lines 571 and 573 may be jointly connected to module resistor unit 570 located adjacent to the second edge portion 505. Each of module resistor units 560 and 570 may include a terminal resistor Rtt / 2 connected to the terminal voltage Vtt.

[0140] For example, each or at least one of the plurality of semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d and 604a to 604d may be a DRAM device or may include a DRAM device.

[0141] The SPD chip 580 may be adjacent to the buffer chip 590, and the PMIC 585 may be located between the semiconductor memory device 603d and the second edge portion 505. The PMIC 585 may generate a power supply voltage VDD based on the input voltage VIN, and may provide the power supply voltage VDD to the semiconductor memory devices 601a to 601e, 602a to 602e, 603a to 603d, and 604a to 604d.

[0142] Figure 20 This is a block diagram illustrating an example memory system according to an example embodiment.

[0143] Reference Figure 20 The memory system 800 may include a memory controller 810 and / or memory modules 820 and 830. For example, the memory system 800 may have quad-rank memory modules. According to an example embodiment, although two memory modules are depicted in... Figure 20 However, more or fewer memory modules may be included in the memory system 800.

[0144] Memory controller 810 controls memory modules 820 and / or 830 to execute commands supplied from a processor and / or a host. Memory controller 810 may be implemented using a processing circuitry system (e.g., a processor) and / or may be implemented using a host, application processor (AP), or system-on-a-chip (SoC). For signal integrity, the source end may be implemented using a resistor RTT on bus 840 of memory controller 810. Resistor RTT may be connected to the power supply voltage VDDQ. Memory controller 810 may include a transmitter 811 that can send signals to at least one of memory modules 820 and / or 830, and a receiver 813 that can receive signals from at least one of memory modules 820 and / or 830.

[0145] Memory modules 820 and 830 may be referred to as a first memory module 820 and a second memory module 830. The first memory module 820 and the second memory module 830 can be connected to a memory controller 810 via a bus 840. Each of the first memory module 820 and the second memory module 830 may correspond to... Figure 19 The memory module 500. The first memory module 820 may include memory rows RK1 and RK2, and the second memory module 830 may include memory rows RK3 and RK4.

[0146] Figure 21 This is a block diagram illustrating an electronic system including a memory module according to an example embodiment.

[0147] Reference Figure 21 The electronic system 900 may include an application processor (AP) 910, a connectivity module 920, a user interface 930, a non-volatile memory (NVM) device 940, a memory module (MM) 950 (such as a dual in-line memory module (DIMM)), and / or a power supply 960. For example, the electronic system 900 may be a mobile system.

[0148] Application processor 910 may include memory controller (MCT) 911. Application processor 910 can execute applications (such as at least one of web browsers, game applications, video players, etc.). Connectivity module 920 can perform wired and / or wireless communication with external devices.

[0149] The memory module 950 can store data and / or operations processed by the application processor 910 as working memory. The memory module 950 may include multiple memory devices (MDs) 951, 952, 953, ..., 95q (where q is a positive integer greater than 3) and / or a buffer chip (RCD) 961. The memory module 950 may be... Figure 19 The memory module 500.

[0150] Non-volatile memory device 940 may store a startup image for booting electronic system 900. User interface 930 may include at least one input device (such as a keyboard, touch screen, etc.) and at least one output device (such as a speaker, display device, etc.). Power supply 960 may provide operating voltage to electronic system 900.

[0151] Electronic system 900 or its components can be mounted using various types of packages.

[0152] The inventive concept can be applied to a wide range of electronic devices and systems, including semiconductor memory systems. For example, the inventive concept can be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smartphones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, camcorders, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, automobiles, and the like.

[0153] The foregoing is illustrative of exemplary embodiments and should not be construed as limiting the exemplary embodiments. Although some exemplary embodiments have been described, those skilled in the art will readily understand that many modifications are possible in the exemplary embodiments without substantially departing from the novelty and advantages of the exemplary embodiments. Therefore, all such modifications are intended to be included within the scope of the exemplary embodiments as defined in the claims. It should therefore be understood that the foregoing is illustrative of various exemplary embodiments and should not be construed as limiting the specific exemplary embodiments disclosed, and modifications to the disclosed exemplary embodiments, as well as other exemplary embodiments, are intended to be included within the scope of the appended claims.

Claims

1. A semiconductor memory device comprising: an array of memory cells; and a plurality of data input / output pins configured to receive write data to be stored in the array of memory cells or output read data stored in the array of memory cells, wherein, in a burst operation performed by the semiconductor memory device, a single set of data including a plurality of data bits is inputted or outputted through the plurality of data input / output pins based on a single command received from an external memory controller, a number of the plurality of data input / output pins corresponds to an integer that is not a power of two, and a burst length representing a unit of the burst operation corresponds to an integer that is not a power of two, wherein the semiconductor memory device further comprises a clock divider configured to generate a second command clock signal based on a first command clock signal, wherein the array of memory cells and the plurality of data input / output pins are configured to operate based on the second command clock signal and a data clock signal, and wherein a value obtained by dividing a period of the second command clock signal by a period of the data clock signal corresponds to an integer that is not a power of two.

2. The semiconductor memory device of claim 1, wherein, the single set of data includes write data or read data, the plurality of data bits in the single set of data includes first data bits corresponding to the write data or the read data, and a number of the first data bits corresponds to an integer that is a power of two.

3. The semiconductor memory device of claim 2, wherein, the single set of data further includes additional data associated with the write data or the read data, and the plurality of data bits in the single set of data further includes second data bits other than the first data bits, the second data bits corresponding to the additional data.

4. The semiconductor memory device according to claim 3, wherein, a number of the second data bits corresponds to an integer that is a power of two.

5. The semiconductor memory device of claim 3, wherein, a number of the plurality of data bits including the first data bits and the second data bits corresponds to an integer that is not a power of two.

6. The semiconductor memory device of claim 3, wherein, the additional data includes at least one of data bus inversion information, error correction code information, and metadata.

7. The semiconductor memory device of claim 2, wherein, the single set of data further includes dummy data that is not associated with the write data or the read data, and the plurality of data bits in the single set of data further includes second data bits other than the first data bits, the second data bits corresponding to the dummy data.

8. The semiconductor memory device of claim 1, wherein, the burst length corresponds to an integer that is a multiple of three.

9. The semiconductor memory device of claim 1, wherein, a division ratio of the clock divider corresponds to an integer that is not a power of two.

10. The semiconductor memory device of claim 9, wherein, the division ratio of the clock divider corresponds to an integer that is a multiple of three.

11. The semiconductor memory device of claim 1, wherein, a value obtained by dividing a period of the second command clock signal by a period of the data clock signal corresponds to an integer that is a multiple of three.

12. The semiconductor memory device of claim 1, wherein, a value obtained by dividing a period of the first command clock signal by a period of the data clock signal corresponds to an integer that is a power of two.

13. The semiconductor memory device of claim 1, further comprising: a data processing path between the array of memory cells and the plurality of data input / output pins, and wherein the data processing path is configured to operate based on the second command clock signal and a data clock signal.

14. The semiconductor memory device of claim 1, wherein, The burst length is twenty-four, the number of the plurality of data input / output pins is twelve, and the number of the plurality of data bits in the single data set is two hundred eighty-eight.

15. A method of operating a semiconductor memory device, the method comprising: receiving a write command or a read command; and performing at least one of: a data write operation in which write data is stored in an array of memory cells included in the semiconductor memory device; and a data read operation in which read data stored in the array of memory cells is fetched from the array of memory cells, wherein the performed step is based on the write command or the read command, wherein during the data write operation, the write data is received through a plurality of data input / output pins included in the semiconductor memory device, during the data read operation, the read data is output through the plurality of data input / output pins, the operation of receiving the write data and / or the operation of outputting the read data is performed based on a burst operation in which a single data set including a plurality of data bits is inputted or outputted through the plurality of data input / output pins based on a single command received from an external memory controller, the number of the plurality of data input / output pins corresponds to an integer that is not a power of two, and a burst length representing a unit of the burst operation corresponds to an integer that is not a power of two, wherein the method further comprises generating the second command clock signal by dividing a first command clock signal, wherein the operation of receiving the write data and / or the operation of outputting the read data is performed based on the second command clock signal and a data clock signal, and wherein a value obtained by dividing a period of the second command clock signal by a period of the data clock signal corresponds to an integer that is not a power of two.

16. A semiconductor memory device comprising: an array of memory cells; a plurality of data input / output pins configured to receive write data to be stored in the array of memory cells or to output read data stored in the array of memory cells; a data processing path between the array of memory cells and the plurality of data input / output pins; and a clock divider configured to generate a second command clock signal based on a first command clock signal, wherein a data write operation in which write data is stored in the array of memory cells is performed based on a write command, or a data read operation in which read data stored in the array of memory cells is fetched from the array of memory cells is performed based on a read command, the operation of receiving the write data and / or the operation of outputting the read data is performed based on a burst operation in which a single data set including a plurality of data bits is inputted or outputted through the plurality of data input / output pins based on a single command received from an external memory controller, the number of the plurality of data input / output pins corresponds to an integer that is not a power of two, ​ a burst length representing a unit of burst operation corresponds to an integer that is not a power of two and corresponds to an integer that is a multiple of three, the plurality of data bits in the single data set includes a first data bit corresponding to write data or read data, a number of the first data bits corresponds to an integer that is a power of two, the memory cell array, the data processing path, and the plurality of data input / output pins are configured to operate based on a data clock signal and a second command clock signal, a division ratio of the clock divider corresponds to an integer that is not a power of two and corresponds to an integer that is a multiple of three, and a value obtained by dividing a period of the second command clock signal by a period of the data clock signal corresponds to an integer that is not a power of two and corresponds to an integer that is a multiple of three.

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