Test structure

Abstract

A test structure comprises: a substrate; a plurality of adjacent sample units on the substrate, each of the plurality of sample units comprising a sample to be tested and a first wiring structure; a plurality of wiring units on the substrate, each of the wiring units comprising a second wiring structure, the second wiring structure being connected to the sample to be tested or the first wiring structure of two adjacent sample units. The test structure can be formed by unit stitching of the sample units and the wiring units according to design rules, so as to realize conversion of the structure into a large number of repeatable testable circuits.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to testing structures. Background Technology

[0002] In semiconductor manufacturing processes, back-end processes are typically used to connect transistors within a cell and to lay out and route the circuitry between cells, including metals and conductive plugs. Defects in back-end processes have two main impacts on circuits: one is that a broken structure in the design becomes short-circuited, caused by defects that connect previously unconnected metals. The other is that a connected structure in the design becomes broken, caused by missing metal during processing or a lack of contact between conductive plugs and metal. Therefore, understanding the quality of back-end processes is crucial in semiconductor manufacturing; reducing defects in the process can effectively improve yield and reduce costs.

[0003] In existing technologies, various defect-prone structures need to be implemented through layout design. Further research into the probability of a particular structure generating defects requires extensive replication of that structure and measurement of its open-circuit or short-circuit states using circuitry. Traditional layout design necessitates a holistic consideration of the arrangement of samples with a specific structure and the layout of its wiring.

[0004] However, in the above methods, due to the large variety of defects and the complexity of the surrounding environment, it is very difficult to transform these structures into testable structures through wiring layout. It requires a high degree of reliance on design experience. At the same time, since the overall arrangement of the samples and the layout of their wiring need to be considered, the above methods have low design efficiency. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a test structure that only requires designing potential defect structures within a single sample unit. The test structure is formed by assembling sample units, wiring units, and filler units according to design rules, thus transforming the structure into a large number of repeatable testable circuits. Furthermore, because the wiring units and sample units are separate, the environment of the structure can be reproduced well and is not affected by interference from the test circuitry.

[0006] To solve the above-mentioned technical problems, the present invention provides a test structure, comprising: a substrate; a plurality of adjacent sample units located on the substrate, each of the plurality of sample units including a sample to be tested and a first wiring structure; and a plurality of wiring units located on the substrate, each of the wiring units including a second wiring structure, wherein the second wiring structure is connected to the sample to be tested or the first wiring structure of two adjacent sample units.

[0007] Optionally, the types of the plurality of sample units include: a first sample type and a second sample type; the types of the plurality of wiring units include: a first wiring type corresponding to the first sample type and a second wiring type corresponding to the second sample type.

[0008] Optionally, when the sample unit is of the first sample type, the first wiring structure includes: two power conductive layers, two third conductive layers located on the same layer as the power conductive layers, and two fourth conductive layers located on the power conductive layers, wherein the power conductive layers are arranged along a second direction, the third conductive layers are arranged along a first direction, and each third conductive layer is connected to the sample under test through one fourth conductive layer; the sample under test includes an input terminal and an output terminal, and each fourth conductive layer has a conductive plug between the input terminal of the sample under test, the output terminal of the sample under test, and the third conductive layer.

[0009] Optionally, when the sample unit is of the second sample type, the first wiring structure includes: two power conductive layers and two fourth conductive layers located on the power conductive layers, wherein the two power conductive layers are arranged along a second direction, and each power conductive layer is connected to the sample under test through one fourth conductive layer; the sample under test includes an input terminal and an output terminal, and each fourth conductive layer has a conductive plug between the input terminal of the sample under test, between the output terminal of the sample under test, and between the power conductive layers.

[0010] Optionally, when the wiring unit type is the first wiring type, the second wiring structure includes: three power conductive layers, two third conductive layers located on the same layer as the power conductive layers, and one fourth conductive layer located on the power conductive layers, wherein the power conductive layers are arranged along a second direction, the third conductive layers are arranged along a second direction, each third conductive layer is located between two power conductive layers in the second direction, and each third conductive layer is connected through the fourth conductive layer; a conductive plug is provided between each third conductive layer and the fourth conductive layer.

[0011] Optionally, when the wiring unit is of the second wiring type, the second wiring structure includes: three power conductive layers and one fourth conductive layer located on the power conductive layers, wherein the power conductive layers are arranged along a second direction; the first power conductive layer and the third power conductive layer along the second direction are connected through the fourth conductive layer; and conductive plugs are provided between the first power conductive layer and the fourth conductive layer along the second direction, and between the third power conductive layer and the fourth conductive layer along the second direction.

[0012] Optionally, when the sample unit is of the first sample type, the sample units are arranged in an N×M array. The connection method between the sample units and between the sample units and the wiring unit includes: the second power conductive layer in the sample unit of the nth row along the second direction coincides with the first power conductive layer in the sample unit of the (n+1)th row along the second direction, where n is a natural number greater than or equal to 1 and less than N; adjacent third conductive layers in adjacent sample units in the same row are connected; adjacent power conductive layers in adjacent sample units in the same row are connected; the sample units and wiring units are arranged along the first direction, the Mth sample unit in the (2i-1)th row and the Mth sample unit in the 2ith row are connected by a wiring unit, and the first sample unit in the 2ith row and the first sample unit in the (2i+1)th row are connected by a wiring unit, where i is a natural number greater than or equal to 1 and less than N / 2; adjacent third conductive layers in adjacent sample units and wiring units in the same row are connected; adjacent power conductive layers in adjacent sample units and wiring units in the same row are connected.

[0013] Optionally, when the sample unit is of the second sample type, the sample units are arranged in an N×M array, and the spacing between two adjacent rows of sample units is the spacing between two power conductive layers in the sample unit; the connection method between the sample units and between the sample unit and the wiring unit includes: connecting adjacent power conductive layers in adjacent sample units in the same row; the sample units and wiring units are arranged along a first direction, and the first sample unit in the i-th row and the first sample unit in the i+1-th row are connected through a wiring unit; the M-th sample unit in the i-th row and the M-th sample unit in the i+1-th row are electrically connected through a wiring unit, where i is a natural number greater than or equal to 1 and less than N; and connecting adjacent power conductive layers in adjacent sample units and wiring units in the same row.

[0014] Optionally, the test structure further includes: a plurality of filling units located on the substrate, wherein the filling units fill the gaps in the arrangement according to the shape of the sample unit and the wiring unit; the filling unit includes two power conductive layers, which are arranged along a second direction.

[0015] Optionally, the spacing between each power conductive layer in the sample unit, the wiring unit, and the filling unit is the same.

[0016] Optionally, the length of the sample to be tested is 1 micrometer to 10 micrometers, and the width of the sample to be tested is 1 micrometer to 10 micrometers.

[0017] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0018] The present invention provides a test structure comprising several adjacent sample units on a substrate, each sample unit including a sample under test and a first wiring structure; and several wiring units on the substrate, each wiring unit including a second wiring structure, the second wiring structure being connected to the sample under test or the first wiring structure of two adjacent sample units. The present invention is simple in design and convenient in layout and wiring. It only requires designing possible defect structures in a single sample unit, and the test structure can be formed by splicing sample units and wiring units according to design rules, thereby transforming the structure into a large number of repeatable testable circuits. Furthermore, since the wiring units and sample units are separate, the structural environment can be reproduced well and is not affected by interference from the test lines. In addition, since the present invention forms a layout structure through unit splicing, the present invention has strong applicability; as long as it conforms to the standard digital cell architecture, the test structure of the present invention can be used for defect testing. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a test structure;

[0020] Figure 2 This is a schematic diagram of another test structure;

[0021] Figure 3 This is a schematic diagram of a test structure according to an embodiment of the present invention;

[0022] Figure 4 This is a schematic diagram of the structure of a first sample type in one embodiment of the present invention;

[0023] Figure 5 This is a schematic diagram of the structure of the first wiring type in one embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the structure of the filling unit in one embodiment of the present invention;

[0025] Figure 7 This is a schematic diagram of a test structure according to another embodiment of the present invention;

[0026] Figure 8 This is a schematic diagram of the structure of the second sample type in another embodiment of the present invention;

[0027] Figure 9 This is a schematic diagram of the structure of the second wiring type in another embodiment of the present invention;

[0028] Figure 10 This is a schematic diagram of the structure of the filling unit in another embodiment of the present invention. Detailed Implementation

[0029] As described in the background section, due to the wide variety of defects and the complexity of the surrounding environment, transforming these structures into testable structures through wiring layout is extremely difficult and requires a high degree of reliance on design experience. Furthermore, because the overall arrangement of the samples and the layout of their wiring need to be considered, the above methods are inefficient. A detailed explanation follows with reference to the accompanying drawings.

[0030] Figure 1 This is a schematic diagram of a test structure. Several test samples 100 are designed as short-circuit samples. These test samples 100 are connected in series via several third conductive layers 103 and power conductive layers 101 and 102. Each of the third conductive layers 103 and the test samples 100, power conductive layers 101, and power conductive layers 102 has a conductive plug 104. The test method for this embodiment includes: connecting a first pad 105 to the power conductive layer 101 and a second pad 106 to the power conductive layer 102; applying a first voltage to the first pad 105 and a second voltage to the second pad 106, wherein the first voltage is greater than the second voltage; and determining whether an open-circuit defect exists in the test samples 100 by testing the current on the first pad 105. If the current is 0 amperes, it indicates that at least one of the test samples 100 is open-circuited; if the current is greater than 0 amperes, it indicates that none of the test samples 100 are open-circuited.

[0031] Figure 2 This is a schematic diagram of another test structure. Several test samples 200 are designed as open-circuit samples; the test samples 200 are connected in parallel via several third conductive layers 203 and power conductive layers 201 and 202; each of the third conductive layers 203 and the test samples 200, power conductive layers 201 and 202 has a conductive plug 204. The test method for the test structure described in this embodiment includes: connecting a first pad 205 to the power conductive layer 201, connecting a second pad 206 to the power conductive layer 202, applying a first voltage to the first pad 205, and applying a second voltage to the second pad 206, wherein the first voltage is greater than the second voltage; by testing the current on the first pad 205, it is determined whether there is a short-circuit defect among the test samples 200; if the current is greater than 0 amperes, it indicates that at least one of the test samples 200 is short-circuited; if the current is 0 amperes, it indicates that none of the test samples 200 are short-circuited.

[0032] The test structure requires overall consideration of the arrangement of the samples under test and the layout of its wiring, resulting in low design efficiency as each sample needs to be designed, laid out, and wired individually. Furthermore, due to the wide variety of defects and the complexity of the surrounding environment, transforming these structures into testable structures through wiring layout is extremely difficult and requires a high degree of reliance on design experience.

[0033] To address the aforementioned technical problems, embodiments of the present invention provide a test structure, comprising: a plurality of adjacent sample units located on a substrate, each of the plurality of sample units including a sample to be tested and a first wiring structure; and a plurality of wiring units located on the substrate, each of the wiring units including a second wiring structure, the second wiring structure being connected to the sample to be tested or the first wiring structure of two adjacent sample units. The technical solution of the present invention is simple in design and convenient in layout and wiring. It only requires designing the possible defect structure in a single sample unit, and the test structure can be formed by splicing the sample units and wiring units according to design rules, thereby transforming the structure into a large number of repeatable testable circuits. Furthermore, since the wiring units and sample units are separate, the environment of the structure can be reproduced well and is not affected by interference or influence from the test circuitry. In addition, since the present invention forms a layout structure through unit splicing, the present invention has strong applicability; as long as it conforms to the standard digital cell architecture, the test structure of the present invention can be used for defect testing.

[0034] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figure 3 This is a schematic diagram of a test structure according to an embodiment of the present invention.

[0036] Please refer to Figure 3 A substrate; a plurality of adjacent sample units 310 located on the substrate, each of the plurality of sample units 310 including a sample to be tested 300 and a first wiring structure; a plurality of wiring units 320 located on the substrate, each of the wiring units 320 including a second wiring structure, the second wiring structure being connected to the sample to be tested 300 or the first wiring structure of two adjacent sample units.

[0037] In this embodiment, the type of the plurality of sample units 310 is a first sample type, and the type of the wiring unit 320 is a first wiring type corresponding to the first sample type.

[0038] In this embodiment, the length of the sample unit 310 is 1 micrometer to 10 micrometers, and the width of the sample unit 310 is 1 micrometer to 10 micrometers; the length of the wiring unit 310 is 1 micrometer to 10 micrometers, and the width of the wiring unit 310 is 1 micrometer to 10 micrometers; the length of the sample to be tested 300 is 1 micrometer to 10 micrometers, and the width of the sample to be tested 300 is 1 micrometer to 10 micrometers.

[0039] The function of the wiring unit is to connect the two sample units to form a test circuit.

[0040] Figure 4 This is a schematic diagram of the structure of a first sample type in one embodiment of the present invention.

[0041] Please refer to Figure 4 Each of the plurality of sample units 310 includes a sample to be tested 300 and a first wiring structure. The first wiring structure includes: two power conductive layers 301, two third conductive layers 302 located on the same layer as the power conductive layers 301, and two fourth conductive layers 303 located on the power conductive layers 301. The power conductive layers 301 are arranged along a second direction Y, and the third conductive layers 302 are arranged along a first direction X. Each third conductive layer 302 is connected to the sample to be tested 300 through one fourth conductive layer 303. The sample to be tested 300 includes an input terminal and an output terminal. Each fourth conductive layer 303 has a conductive plug 304 between itself and the input terminal of the sample to be tested 300, between itself and the output terminal of the sample to be tested 300, and between itself and each third conductive layer 302. There is a spacing 'a' between each power conductive layer 301.

[0042] In this embodiment, the test sample 300 is designed as a short-circuit sample.

[0043] The power conductive layer 301 serves as power wiring to simulate a real chip environment and conform to digital cell design rules. Two different power supply voltages can be applied to the two power conductive layers 301 respectively.

[0044] In this embodiment, the width of the power conductive layer 301 is 40 nanometers to 500 nanometers, and the length of the power conductive layer 301 is 2 micrometers to 12 micrometers. The spacing 'a' between each power conductive layer 301 is 100 nanometers to 10 micrometers.

[0045] The third conductive layer 302 is a metal wiring layer used to connect the pad, the adjacent sample unit 310, or the adjacent wiring unit 320.

[0046] The function of the fourth conductive layer 303 is to connect the input and output terminals of the sample to be tested 300 to the third conductive layer 302.

[0047] In this embodiment, the width of the fourth conductive layer 303 is 20 nanometers to 500 nanometers, and the length of the fourth conductive layer 303 is 100 nanometers to 100 micrometers.

[0048] In this embodiment, the length and width of the conductive plug 304 are both 20 nanometers to 100 nanometers.

[0049] Figure 5 This is a schematic diagram of the structure of the first wiring type in one embodiment of the present invention.

[0050] Please refer to Figure 5 Each of the wiring units 320 includes a second wiring structure, which includes: three power conductive layers 301, two third conductive layers 302 located on the same layer as the power conductive layers 301, and one fourth conductive layer 303 located on the power conductive layers 301. The power conductive layers 301 are arranged along a second direction Y, and the third conductive layers 302 are also arranged along the second direction Y. Each third conductive layer 302 is located between two power conductive layers 301 in the second direction Y, and each third conductive layer 302 is connected through the fourth conductive layer 303. A conductive plug 304 is provided between each third conductive layer 302 and the fourth conductive layer 303. A spacing 'a' is provided between each power conductive layer 301.

[0051] The function of the wiring unit 320 is to connect two sample units 310 in two adjacent rows. Therefore, the spacing a of each power conductive layer 301 in the wiring unit 320 is the same as the spacing a of each power conductive layer 301 in the sample unit 310.

[0052] The power conductive layer 301 serves as power wiring to simulate a real chip environment and conform to digital cell design rules. Two different power supply voltages can be applied to the two power conductive layers 301 respectively.

[0053] In this embodiment, the width of the power conductive layer 301 is 40 nanometers to 500 nanometers, and the length of the power conductive layer 301 is 2 micrometers to 12 micrometers. The spacing 'a' between each power conductive layer 301 is 100 nanometers to 10 micrometers.

[0054] The third conductive layer 302 is a metal wiring layer used to connect adjacent sample units 310.

[0055] The function of the fourth conductive layer 303 is to connect the two third conductive layers 302 in the wiring unit.

[0056] In this embodiment, the width of the fourth conductive layer 303 is 20 nanometers to 500 nanometers, and the length of the fourth conductive layer 303 is 100 nanometers to 100 micrometers.

[0057] In this embodiment, the length and width of the conductive plug 304 are both 20 nanometers to 100 nanometers.

[0058] Please continue to refer to this. Figure 3 The sample units 310 are arranged in an N×M array. The connection method between the sample units 310 and between the sample units 310 and the wiring unit 320 includes: the second power conductive layer 301 along the second direction Y in the sample unit of the nth row coincides with the first power conductive layer 301 along the second direction in the sample unit of the (n+1)th row, where n is a natural number greater than or equal to 1 and less than N; adjacent third conductive layers 302 in adjacent sample units 310 in the same row are connected; adjacent power conductive layers 301 in adjacent sample units 310 in the same row are connected; the sample units Sample units 310 and 320 are arranged along the first direction X. The Mth sample unit 310 in the (2i-1)th row and the Mth sample unit 310 in the 2ith row are connected by a wiring unit 320. The first sample unit 310 in the 2ith row and the first sample unit 310 in the 2i+1th row are connected by a wiring unit 320, where i is a natural number greater than or equal to 1 and less than N / 2. Adjacent sample units 310 in the same row and adjacent third conductive layers 302 in the wiring unit 320 are connected. Adjacent sample units 310 in the same row and adjacent power conductive layers 301 in the wiring unit 320 are connected.

[0059] Please continue to refer to this. Figure 3 The test structure in this embodiment also includes: a plurality of filling units 330 located on the substrate, which fill the gaps in the arrangement of the sample unit 310 and the wiring unit 320 according to the shape of the arrangement.

[0060] Figure 6 This is a schematic diagram of the structure of the filling unit in one embodiment of the present invention.

[0061] Please refer to Figure 6 The filling unit 330 includes two power conductive layers 301, which are arranged along a second direction Y. Each power conductive layer 301 has a spacing a between it.

[0062] The purpose of the filling unit 330 is to conform to the design rules of digital units.

[0063] The power conductive layer 301 serves as power wiring to simulate a real chip environment and conform to digital cell design rules. Two different power supply voltages can be applied to the two power conductive layers 301 respectively.

[0064] In this embodiment, the width of the power conductive layer 301 is 40 nanometers to 500 nanometers, and the length of the power conductive layer 301 is 2 micrometers to 12 micrometers. The spacing 'a' between each power conductive layer 301 is 100 nanometers to 10 micrometers.

[0065] In order to comply with the design rules of digital units, the spacing between each power conductive layer 310 in the sample unit 310, the wiring unit 320 and the filling unit 330 is the same.

[0066] Please continue to refer to this. Figure 3 The testing method for the test structure described in this embodiment includes: connecting a first pad 315 to the third conductive layer 302 in the first sample unit 310 of the first row, and connecting a second pad 316 to the third conductive layer 302 in the Mth sample unit 310 of the Nth row; applying a first voltage to the first pad 315 and a second voltage to the second pad 316, wherein the first voltage is greater than the second voltage; and determining whether there is an open circuit defect in the plurality of test samples 300 by testing the current on the first pad 315. If the current is 0 amperes, it indicates that at least one of the plurality of test samples 300 is open-circuited; if the current is greater than 0 amperes, it indicates that none of the plurality of test samples 300 is open-circuited.

[0067] It should be noted that the first pad 315 and the second pad 316 are formed only when the test structure is tested, and are not included in the layout design of the test structure. The first pad 315 and the second pad 316 serve as voltage application terminals and test terminals.

[0068] The test structure of this embodiment is simple in design and convenient in layout and wiring. Only the test sample 300 in a single sample unit 310 needs to be designed as a short-circuit sample. The test structure can be formed by splicing the sample unit 310, wiring unit 320, and fill unit 330 according to the design rules, thereby transforming the structure into a large number of repeatable testable circuits. Furthermore, since the wiring unit 320 and the sample unit 310 are separate, the environment of the structure can be reproduced well and will not be affected by interference from the test lines. In addition, since the test structure of this embodiment is formed by splicing units to form a layout structure, the test structure has strong applicability. As long as it conforms to the standard digital cell architecture, the test structure can be used for defect testing.

[0069] Figure 7This is a schematic diagram of a test structure according to another embodiment of the present invention.

[0070] Please refer to Figure 7 A substrate; a plurality of adjacent sample units 410 located on the substrate, each of the plurality of sample units 410 including a sample to be tested 400 and a first wiring structure; a plurality of wiring units 420 located on the substrate, each of the wiring units 420 including a second wiring structure, the second wiring structure being connected to the sample to be tested 400 or the first wiring structure of two adjacent sample units.

[0071] In this embodiment, the type of the plurality of sample units 410 is a second sample type, and the type of the wiring unit 420 is a second wiring type corresponding to the second sample type.

[0072] In this embodiment, the length of the sample unit 410 is 1 micrometer to 10 micrometers, and the width of the sample unit 410 is 1 micrometer to 10 micrometers; the length of the wiring unit 410 is 1 micrometer to 10 micrometers, and the width of the wiring unit 410 is 1 micrometer to 10 micrometers; the length of the sample to be tested 400 is 1 micrometer to 10 micrometers, and the width of the sample to be tested 400 is 1 micrometer to 10 micrometers.

[0073] The function of the wiring unit is to connect the two sample units to form a test circuit.

[0074] Figure 8 This is a schematic diagram of the structure of the second sample type in another embodiment of the present invention.

[0075] Please refer to Figure 8 Each of the plurality of sample units 410 includes a sample to be tested 400 and a first wiring structure. The first wiring structure includes: two power conductive layers 401 and two fourth conductive layers 403 located on the power conductive layers 401. The two power conductive layers 401 are arranged along a second direction Y, and each power conductive layer 401 is connected to the sample to be tested 400 through one fourth conductive layer 403. The sample to be tested 400 includes an input terminal and an output terminal. Each fourth conductive layer 403 has a conductive plug 404 between itself and the input terminal of the sample to be tested 400, between itself and the output terminal of the sample to be tested 400, and between itself and each power conductive layer 401. There is a spacing 'a' between each power conductive layer 401.

[0076] In this embodiment, the sample to be tested 400 is designed as an open-circuit sample.

[0077] The power conductive layer 401 serves as power wiring to simulate a real chip environment and conform to digital cell design rules. Two different power supply voltages can be applied to the two power conductive layers 401 respectively.

[0078] In this embodiment, the width of the power conductive layer 401 is 40 nanometers to 500 nanometers, and the length of the power conductive layer 401 is 2 micrometers to 12 micrometers. The spacing 'a' between each power conductive layer 401 is 100 nanometers to 10 micrometers.

[0079] The function of the fourth conductive layer 403 is to connect the input and output terminals of the sample under test 400 to the power conductive layer 401.

[0080] In this embodiment, the width of the fourth conductive layer 403 is 20 nanometers to 500 nanometers, and the length of the fourth conductive layer 403 is 100 nanometers to 100 micrometers.

[0081] In this embodiment, the length and width of the conductive plug 404 are both 20 nanometers to 100 nanometers.

[0082] Figure 9 This is a schematic diagram of the structure of the second wiring type in another embodiment of the present invention.

[0083] Please refer to Figure 9 Each of the wiring units 420 includes a second wiring structure, which includes: three power conductive layers 401 and one fourth conductive layer 403 located on the power conductive layers 401. The power conductive layers 401 are arranged along a second direction Y. The first power conductive layer 401 and the third power conductive layer 401 along the second direction Y are connected through the fourth conductive layer 403. Conductive plugs 404 are provided between the first power conductive layer 401 and the fourth conductive layer 403 along the second direction Y, and between the third power conductive layer 401 and the fourth conductive layer 403 along the second direction Y. A spacing 'a' is provided between each of the power conductive layers 401.

[0084] The function of the wiring unit 420 is to connect two sample units 410 in two adjacent rows. Therefore, the spacing a of each power conductive layer 401 in the wiring unit 420 is the same as the spacing a of each power conductive layer 401 in the sample unit 410.

[0085] The power conductive layer 401 serves as power wiring to simulate a real chip environment and conform to digital cell design rules. Two different power supply voltages can be applied to the two power conductive layers 401 respectively.

[0086] In this embodiment, the width of the power conductive layer 401 is 40 nanometers to 500 nanometers, and the length of the power conductive layer 401 is 2 micrometers to 12 micrometers. The spacing 'a' between each power conductive layer 401 is 100 nanometers to 10 micrometers.

[0087] The function of the fourth conductive layer 403 is to connect the first power conductive layer 401 along the second direction Y and the third power conductive layer 401 along the second direction Y in the wiring unit 420.

[0088] In this embodiment, the width of the fourth conductive layer 403 is 20 nanometers to 500 nanometers, and the length of the fourth conductive layer 403 is 100 nanometers to 100 micrometers.

[0089] In this embodiment, the length and width of the conductive plug 404 are both 20 nanometers to 100 nanometers.

[0090] Please continue to refer to this. Figure 7 The sample units 410 are arranged in an N×M array, and the spacing between two adjacent rows of sample units 410 is the spacing a between the two power conductive layers 401 in the sample unit 410. The connection method between the sample units 410 and between the sample units 410 and the wiring unit 420 includes: adjacent power conductive layers 401 in adjacent sample units 410 in the same row are connected; the sample units 410 and the wiring unit 420 are arranged along the first direction X, and the first sample unit 410 in the i-th row and the first sample unit 410 in the (i+1)-th row are connected through a wiring unit 420; the M-th sample unit 410 in the i-th row and the M-th sample unit 410 in the (i+1)-th row are electrically connected through a wiring unit 420, where i is a natural number greater than or equal to 1 and less than N; adjacent sample units 410 and adjacent power conductive layers 401 in the wiring unit 420 in the same row are connected.

[0091] Please continue to refer to this. Figure 7 The test structure in this embodiment also includes: a plurality of filling units 430 located on the substrate, which fill the gaps in the arrangement of the sample unit 410 and the wiring unit 420 according to the shape of the arrangement.

[0092] Figure 10 This is a schematic diagram of the structure of the filling unit in another embodiment of the present invention.

[0093] Please refer to Figure 10 The filling unit 430 includes two power conductive layers 401, which are arranged along a second direction Y. Each power conductive layer 401 has a spacing a between it.

[0094] The purpose of the filling unit 430 is to conform to the design rules of digital units.

[0095] The power conductive layer 401 serves as power wiring to simulate a real chip environment and conform to digital cell design rules. Two different power supply voltages can be applied to the two power conductive layers 401 respectively.

[0096] In this embodiment, the width of the power conductive layer 401 is 40 nanometers to 500 nanometers, and the length of the power conductive layer 401 is 2 micrometers to 12 micrometers. The spacing 'a' between each power conductive layer 401 is 100 nanometers to 10 micrometers.

[0097] In order to comply with the design rules of digital units, the spacing between each power conductive layer 410 in the sample unit 410, the wiring unit 420 and the filling unit 430 is the same.

[0098] Please continue to refer to this. Figure 7 The testing method for the test structure described in this embodiment includes: connecting a first pad 415 to the first power conductive layer 401 along the second direction Y, and connecting a second pad 416 to the last power conductive layer 401 along the second direction Y; applying a first voltage to the first pad 415 and a second voltage to the second pad 416, wherein the first voltage is greater than the second voltage; determining whether there is a short-circuit defect among the plurality of test samples 400 by testing the current on the first pad 415; if the current is greater than 0 amperes, it indicates that at least one of the plurality of test samples 400 is short-circuited; if the current is 0 amperes, it indicates that none of the plurality of test samples 400 is short-circuited.

[0099] It should be noted that the first pad 415 and the second pad 416 are formed only when the test structure is tested, and are not included in the layout design of the test structure. The first pad 415 and the second pad 416 serve as voltage application terminals and test terminals.

[0100] The test structure of this embodiment is simple in design and convenient in layout and wiring. It only requires that the test sample 400 in a single sample unit 410 be designed as an open-circuit sample. The test structure can be formed by splicing the sample unit 410, wiring unit 420, and fill unit 430 according to the design rules, thereby transforming the structure into a large number of repeatable testable circuits. Furthermore, since the wiring unit 420 and the sample unit 410 are separate, the environment of the structure can be reproduced well and is not affected by interference from the test circuitry. In addition, since the test structure of this embodiment is formed by splicing units to form a layout structure, the test structure has strong applicability. As long as it conforms to the standard digital cell architecture, the test structure can be used for defect testing.

[0101] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A test structure, characterized in that, include: Substrate; A plurality of adjacent sample units located on the substrate, each of the plurality of sample units including a sample to be tested and a first wiring structure; A plurality of wiring units located on the substrate, each wiring unit including a second wiring structure, the second wiring structure being connected to the test sample or the first wiring structure of two adjacent sample units; The type of the plurality of sample units is the first sample type; The first wiring structure includes: two power conductive layers, two third conductive layers located on the same layer as the power conductive layers, and two fourth conductive layers located on the power conductive layers. The power conductive layers are arranged along a second direction, and the third conductive layers are arranged along a first direction. Each third conductive layer is connected to the sample under test through one fourth conductive layer. The sample under test includes an input terminal and an output terminal. Each fourth conductive layer has a conductive plug between itself and the input terminal of the sample under test, between itself and the output terminal of the sample under test, and between itself and each third conductive layer.

2. The test structure as described in claim 1, characterized in that, The test structure further includes: a plurality of filling units located on the substrate, which fill the gaps in the arrangement of the sample unit and the wiring unit according to the shape of the arrangement; the filling unit includes two power conductive layers, which are arranged along the second direction.

3. The test structure as described in claim 2, characterized in that, The spacing between each power conductive layer in the sample unit, the wiring unit, and the filling unit is the same.

4. The test structure as described in claim 1, characterized in that, The length of the sample to be tested is 1 micrometer to 10 micrometers, and the width of the sample to be tested is 1 micrometer to 10 micrometers.

5. A test structure, characterized in that, include: Substrate; A plurality of adjacent sample units located on the substrate, each of the plurality of sample units including a sample to be tested and a first wiring structure; A plurality of wiring units located on the substrate, each wiring unit including a second wiring structure, the second wiring structure being connected to the test sample or the first wiring structure of two adjacent sample units; The type of the plurality of sample units is the second sample type; The first wiring structure includes: two power conductive layers and two fourth conductive layers located on the power conductive layers, wherein the two power conductive layers are arranged along a second direction, and each power conductive layer is connected to the sample under test through one fourth conductive layer; the sample under test includes an input terminal and an output terminal, and each fourth conductive layer has a conductive plug between the input terminal of the sample under test, between the output terminal of the sample under test, and between the power conductive layers.

6. The test structure as described in claim 5, characterized in that, The test structure further includes: a plurality of filling units located on the substrate, which fill the gaps in the arrangement of the sample unit and the wiring unit according to the shape of the arrangement; the filling unit includes two power conductive layers, which are arranged along the second direction.

7. The test structure as described in claim 6, characterized in that, The spacing between each power conductive layer in the sample unit, the wiring unit, and the filling unit is the same.

8. The test structure as described in claim 5, characterized in that, The length of the sample to be tested is 1 micrometer to 10 micrometers, and the width of the sample to be tested is 1 micrometer to 10 micrometers.

9. A test structure, characterized in that, include: Substrate; A plurality of adjacent sample units located on the substrate, each of the plurality of sample units including a sample to be tested and a first wiring structure; A plurality of wiring units located on the substrate, each wiring unit including a second wiring structure, the second wiring structure being connected to the test sample or the first wiring structure of two adjacent sample units; The type of the plurality of sample units is the first sample type; The types of the plurality of wiring units include: a first wiring type corresponding to the first sample type; The second wiring structure includes: three power conductive layers, two third conductive layers located on the same layer as the power conductive layers, and one fourth conductive layer located on the power conductive layers. The power conductive layers are arranged along a second direction, the third conductive layers are arranged along a second direction, each third conductive layer is located between two power conductive layers in the second direction, and each third conductive layer is connected through the fourth conductive layer. A conductive plug is provided between each third conductive layer and the fourth conductive layer.

10. The test structure as described in claim 9, characterized in that, The test structure further includes: a plurality of filling units located on the substrate, which fill the gaps in the arrangement of the sample unit and the wiring unit according to the shape of the arrangement; the filling unit includes two power conductive layers, which are arranged along the second direction.

11. The test structure as described in claim 10, characterized in that, The spacing between each power conductive layer in the sample unit, the wiring unit, and the filling unit is the same.

12. The test structure as described in claim 9, characterized in that, The length of the sample to be tested is 1 micrometer to 10 micrometers, and the width of the sample to be tested is 1 micrometer to 10 micrometers.

13. A test structure, characterized in that, include: Substrate; A plurality of adjacent sample units located on the substrate, each of the plurality of sample units including a sample to be tested and a first wiring structure; A plurality of wiring units located on the substrate, each wiring unit including a second wiring structure, the second wiring structure being connected to the test sample or the first wiring structure of two adjacent sample units; The type of the plurality of sample units is the second sample type; The type of the plurality of wiring units is the second wiring type corresponding to the second sample type; The second wiring structure includes: three power conductive layers and one fourth conductive layer located on the power conductive layers, wherein the power conductive layers are arranged along a second direction; the first power conductive layer and the third power conductive layer along the second direction are connected through the fourth conductive layer; and conductive plugs are provided between the first power conductive layer and the fourth conductive layer along the second direction, and between the third power conductive layer and the fourth conductive layer along the second direction.

14. The test structure as described in claim 13, characterized in that, The test structure further includes: a plurality of filling units located on the substrate, which fill the gaps in the arrangement of the sample unit and the wiring unit according to the shape of the arrangement; the filling unit includes two power conductive layers, which are arranged along the second direction.

15. The test structure as described in claim 14, characterized in that, The spacing between each power conductive layer in the sample unit, the wiring unit, and the filling unit is the same.

16. The test structure as described in claim 13, characterized in that, The length of the sample to be tested is 1 micrometer to 10 micrometers, and the width of the sample to be tested is 1 micrometer to 10 micrometers.

17. A test structure, characterized in that, include: Substrate; A plurality of adjacent sample units located on the substrate, each of the plurality of sample units including a sample to be tested and a first wiring structure; A plurality of wiring units located on the substrate, each wiring unit including a second wiring structure, the second wiring structure being connected to the test sample or the first wiring structure of two adjacent sample units; The type of the plurality of sample units is the first sample type; The sample units are arranged in an N×M array. The connection methods between the sample units and between the sample units and the wiring units include: the second power conductive layer in the sample unit in the nth row along the second direction coincides with the first power conductive layer in the sample unit in the (n+1)th row along the second direction, where n is a natural number greater than or equal to 1 and less than N; adjacent third conductive layers in adjacent sample units in the same row are connected; adjacent power conductive layers in adjacent sample units in the same row are connected; the sample units and wiring units are arranged along the first direction, the Mth sample unit in the (2i-1)th row and the Mth sample unit in the 2ith row are connected by a wiring unit, and the first sample unit in the 2ith row and the first sample unit in the (2i+1)th row are connected by a wiring unit, where i is a natural number greater than or equal to 1 and less than N / 2; adjacent third conductive layers in adjacent sample units and wiring units in the same row are connected; adjacent power conductive layers in adjacent sample units and wiring units in the same row are connected.

18. The test structure as described in claim 17, characterized in that, The test structure further includes: a plurality of filling units located on the substrate, which fill the gaps in the arrangement of the sample unit and the wiring unit according to the shape of the arrangement; the filling unit includes two power conductive layers, which are arranged along the second direction.

19. The test structure as described in claim 18, characterized in that, The spacing between each power conductive layer in the sample unit, the wiring unit, and the filling unit is the same.

20. The test structure as described in claim 17, characterized in that, The length of the sample to be tested is 1 micrometer to 10 micrometers, and the width of the sample to be tested is 1 micrometer to 10 micrometers.

21. A test structure, characterized in that, include: Substrate; A plurality of adjacent sample units located on the substrate, each of the plurality of sample units including a sample to be tested and a first wiring structure; A plurality of wiring units located on the substrate, each wiring unit including a second wiring structure, the second wiring structure being connected to the test sample or the first wiring structure of two adjacent sample units; The type of the plurality of sample units is the second sample type; The sample units are arranged in an N×M array, and the spacing between two adjacent rows of sample units is the spacing between the two power conductive layers in the sample unit. The connection methods between the sample units and between the sample unit and the wiring unit include: connecting adjacent power conductive layers in adjacent sample units in the same row; The sample units and wiring units are arranged along a first direction. The first sample unit in the i-th row and the first sample unit in the (i+1)-th row are connected by a wiring unit. The M-th sample unit in the i-th row and the M-th sample unit in the (i+1)-th row are electrically connected by a wiring unit, where i is a natural number greater than or equal to 1 and less than N. Adjacent power conductive layers in adjacent sample units and wiring units in the same row are connected.

22. The test structure as described in claim 21, characterized in that, The test structure further includes: a plurality of filling units located on the substrate, which fill the gaps in the arrangement of the sample unit and the wiring unit according to the shape of the arrangement; the filling unit includes two power conductive layers, which are arranged along the second direction.

23. The test structure as described in claim 22, characterized in that, The spacing between each power conductive layer in the sample unit, the wiring unit, and the filling unit is the same.

24. The test structure as described in claim 21, characterized in that, The length of the sample to be tested is 1 micrometer to 10 micrometers, and the width of the sample to be tested is 1 micrometer to 10 micrometers.

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