Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the method comprising: forming a substrate comprising a first region and a plurality of second regions, the substrate having a plurality of initial fins separated from each other; forming a first isolation layer and a first mask layer on the first isolation layer, the first isolation layer and the first mask layer exposing the plurality of initial fins of the plurality of second regions; after forming the first mask layer, etching the plurality of initial fins on the plurality of second regions to form a plurality of intermediate fins, taking the first mask layer as a mask; performing ion implantation on the plurality of intermediate fins on the plurality of second regions and the substrate to form a modified region; removing the modified region to form a plurality of fins, and after removing the modified region, the surface of the plurality of second regions has a plurality of protrusions and a plurality of recesses alternately, the surface of the plurality of second regions is lower than the surface of the first region, or the highest part of the surface of the plurality of second regions is flush with the surface of the first region; and forming a second isolation layer on the surface of the plurality of second regions after removing the modified region. Thus, the performance and reliability of the semiconductor structure are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In semiconductor manufacturing, as the feature size of integrated circuits continues to decrease, the channel length of MOSFETs is also correspondingly shortened. However, as the device channel length is shortened, the distance between the source and the drain of the device is also shortened, resulting in poor control of the gate over the channel and more prone to short channel effects (SCE).

[0003] FinFETs have outstanding performance in suppressing short channel effects. The gate of a FinFET can control the fin from at least two sides, and thus the control of the gate over the channel is stronger than that of a planar MOSFET, which can well suppress short channel effects.

[0004] However, the performance of the semiconductor structure in the prior art still needs to be improved. SUMMARY

[0005] The present application solves the technical problem of providing a semiconductor structure and a forming method thereof to improve the performance and reliability of the semiconductor structure.

[0006] To solve the above technical problem, the technical solution of the present application provides a semiconductor structure, comprising: a substrate, the substrate comprising a first region and a plurality of second regions, the surface of the second region having a plurality of protrusions and a plurality of recesses alternately, and the surface of the second region being lower than the surface of the first region, or the highest part of the surface of the second region being flush with the surface of the first region; a plurality of fins on the first region, the spacing between the plurality of fins being uniform; a first isolation layer on the first region; and a second isolation layer on the surface of the plurality of second regions.

[0007] Optionally, the surface of the first isolation layer and the surface of the second isolation layer are higher than the surface of the plurality of fins.

[0008] Optionally, the plurality of protrusions and the plurality of recesses alternately constitute a continuous wavy surface.

[0009] Optionally, in a first direction, the minimum spacing between the surface of the first region and the surface of the second region is above 3 nanometers, and the first direction is parallel to a direction perpendicular to the surface of the first region.

[0010] Optionally, the spacing between the highest part and the lowest part of the surface of the second region in a first direction is above 50 angstroms, and the first direction is parallel to a direction perpendicular to the surface of the first region.

[0011] Correspondingly, the technical scheme of the present application also provides a forming method of a semiconductor structure, comprising: forming a substrate, the substrate having a plurality of initial fins separated from each other, the spacing between the plurality of initial fins being uniform, the substrate comprising a first region and a plurality of second regions, and the plurality of initial fins being located on the first region and the plurality of second regions; forming a first isolation layer on the surface of the first region and the surface of the plurality of initial fins on the first region, and a first mask layer on the first isolation layer, the first isolation layer and the first mask layer exposing the plurality of initial fins of the plurality of second regions; after the first mask layer is formed, taking the first mask layer as a mask, etching the plurality of initial fins on the plurality of second regions to form a plurality of intermediate fins, the top surface of the intermediate fins on the plurality of second regions being higher than the surface of the substrate and lower than the top surface of the intermediate fins on the first region; performing ion implantation on the intermediate fins on the plurality of second regions and the substrate to form a modified region in the intermediate fins on the plurality of second regions and the substrate; etching the modified region until the modified region is removed to form a plurality of fins, and after the modified region is removed, the surface of the plurality of second regions has a plurality of protrusions and a plurality of recesses alternately, the surface of the plurality of second regions being lower than the surface of the first region, or the highest part of the surface of the plurality of second regions being flush with the surface of the first region; after the modified region is removed, forming a second isolation layer on the surface of the plurality of second regions.

[0012] Optionally, the method for forming the first isolation layer and the first mask layer comprises: forming an initial first isolation layer on the surface of the first region, the surface of the plurality of second regions and the surface of the plurality of initial fins; forming a first mask layer on the surface of the initial first isolation layer, the first mask layer exposing the surface of the initial first isolation layer on the plurality of second regions; taking the first mask layer as a mask, etching the initial first isolation layer on the plurality of second regions until the initial first isolation layer on the plurality of second regions is removed to form the first isolation layer.

[0013] Optionally, the process for forming the initial first isolation layer comprises a flowable chemical vapor deposition process.

[0014] Optionally, the plurality of protrusions and the plurality of recesses alternately on the surface of the plurality of second regions form a continuous wavy surface.

[0015] Optionally, the material of the substrate and the plurality of initial fins comprises silicon, and the process parameters for performing ion implantation on the intermediate fins on the plurality of second regions and the substrate comprise: the implanted ions comprising arsenic ions or boron ions.

[0016] Optionally, the process for etching the modified region comprises a wet etching process.

[0017] Optionally, the etchant used in the wet etching process comprises hydrofluoric acid, nitric acid and acetic acid, and the ratio among the hydrofluoric acid, the nitric acid and the acetic acid is 1:1:2.

[0018] Optionally, the first isolation layer surface and the second isolation layer surface are higher than the fin surfaces.

[0019] Optionally, the process of forming the second isolation layer comprises a flowable chemical vapor deposition process.

[0020] Optionally, the substrate and the initial fins are formed by a self-aligned double patterning process or a self-aligned multiple patterning process.

[0021] Compared with the prior art, the technical scheme of the embodiment of the present application has the following beneficial effects:

[0022] In the method for forming a semiconductor structure provided by the technical scheme, the intermediate fins are formed, ion implantation is performed on the intermediate fins on the second regions and the substrate to form modified regions, and the modified regions are etched until the intermediate fins and the substrate of the modified regions are removed, so that the surface height of the substrate of each second region is better controlled, and the surface of the second region with alternating protrusions and recesses can be formed, thereby not only reducing the stress on the fins to reduce defects such as bending, merging and breaking of the fins, but also reducing the risk of leakage and short circuit. Therefore, the performance and reliability of the semiconductor structure are improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] Figures 1 to 3 is a structural schematic diagram of a semiconductor structure formation process;

[0024] Figures 4 to 11 is a structural schematic diagram corresponding to each step in the method for forming a semiconductor structure according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] As described in the background, the performance and reliability of the existing semiconductor structure still need to be improved. Now, a semiconductor structure formation process is described and analyzed.

[0026] Figures 1 to 3 is a structural schematic diagram of a semiconductor structure formation process.

[0027] Please refer to Figure 1 A substrate 100 is provided, and the substrate 100 has a plurality of initial fins 110 which are separate from each other, and the substrate 100 comprises a plurality of regions A.

[0028] Please refer to Figure 2 A photoresist layer 120 is formed on the substrate 100 and the surfaces of the fins 110, and the photoresist layer 120 exposes the plurality of regions A.

[0029] Please continue to refer to Figure 2Erosion of the initial fin 110 in the plurality of regions A with the photoetching mask layer 120 as a mask to form a plurality of fins 111.

[0030] Please refer to Figure 3 After forming the plurality of fins 111, a flowable chemical vapor deposition process is used to form an isolation layer 130 on the surface of the substrate 100 and the fins 111.

[0031] However, in the above method, since the size of each region A is different, the initial fin 110 in the plurality of regions of different sizes is removed, and the fins 111 with different densities are formed on each region of the substrate 100, which causes the material of the isolation layer 130 to easily generate stress on the fins 111 during the material filling process of the isolation layer 130 after the formation of the fins 111, so that each fin 111 is prone to bending, merging, breaking and other defects. Therefore, the performance and reliability of the semiconductor structure are poor.

[0032] To solve the above technical problems, the technical scheme of the present application provides a semiconductor structure and a forming method thereof. Since a plurality of intermediate fins are formed, and ion implantation is performed on the intermediate fins in the plurality of second regions and the substrate to form a modified region, and the modified region is etched until the intermediate fins and the substrate in the modified region are removed, the surface height of each second region substrate is better controlled, and a second region surface with alternating plurality of protrusions and plurality of recesses can be formed, thereby not only reducing the stress on the plurality of fins to reduce the bending, merging, breaking and other defects of the plurality of fins, but also reducing the risk of leakage and short circuit. Therefore, the performance and reliability of the semiconductor structure are improved.

[0033] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0034] Figures 4 to 11 is a structure diagram corresponding to each step in the forming method of the semiconductor structure of an embodiment of the present application.

[0035] First, a substrate is formed, the substrate has a plurality of initial fins which are mutually separated, the spacing between the plurality of initial fins is uniform, the substrate includes a first region and a plurality of second regions, and the plurality of initial fins are located on the first region and the plurality of second regions.

[0036] In this embodiment, a self-aligned multiple patterning process (SAQP, Self-Aligned Quadruple Patterning) is used to form the substrate and the plurality of initial fins.

[0037] In some other embodiments, the substrate and the initial fin portions are formed by using a self-aligned double patterning process (SADP).

[0038] For the specific steps of forming the substrate and the initial fin portions by using a self-aligned multiple patterning process, please refer to Figures 4 to 5 .

[0039] For the specific steps of forming the substrate and the initial fin portions by using a self-aligned multiple patterning process, please refer to Figure 4 .

[0040] In the embodiment, the material of the initial substrate 200 includes a semiconductor material. Specifically, the material of the initial substrate 200 includes silicon.

[0041] In other embodiments, the material of the initial substrate includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0042] For the specific steps of forming the substrate and the initial fin portions by using a self-aligned multiple patterning process, please refer to Figure 4 .

[0043] The fin mask material layer 210 is used to transfer the pattern of the initial fin portions formed subsequently.

[0044] In the embodiment, the fin mask material layer 210 is a multi-layer composite material layer.

[0045] Specifically, the material of the fin mask material layer 210 includes a hard mask material such as silicon nitride.

[0046] In other embodiments, the fin mask material layer is a single material layer.

[0047] For the specific steps of forming the substrate and the initial fin portions by using a self-aligned multiple patterning process, please refer to Figure 4 .

[0048] In the embodiment, the method for forming the second core structures 221 comprises: forming a second core structure material layer (not shown) on the surface of the fin mask material layer 210; forming a first core structure material layer (not shown) on the second core structure material layer; forming a fin photoetching layer (not shown) on the first core structure material layer, and the fin photoetching layer exposes part of the first core structure material layer; taking the fin photoetching layer as a mask, etching the first core structure material layer until the surface of the second core structure material layer is exposed, and forming a plurality of first core structures (not shown) which are separated from each other; forming a first sidewall material layer (not shown) on the exposed surface of the second core structure material layer and the surface of the first core structures; taking an anisotropic etching process to etch the first sidewall material layer until the second core structure material layer is exposed, and forming a plurality of first sidewalls (not shown) on the sidewalls of the first core structures; after forming the plurality of first sidewalls, removing the plurality of first core structures; after removing the plurality of first core structures, taking the plurality of first sidewalls as a mask, etching the second core structure material layer until the surface of the fin mask material layer 210 is exposed, and forming a plurality of second core structures 221 which are separated from each other.

[0049] In the embodiment, after forming the plurality of second core structures 221, the plurality of first sidewalls are removed.

[0050] Please continue to refer to Figure 4 A plurality of second sidewalls 220 are formed on the sidewall surfaces of the plurality of second core structures 221.

[0051] In the embodiment, the method for forming the second sidewalls 220 comprises: forming a second sidewall material layer (not shown) on the surface of the plurality of second sidewalls 220 and the exposed surface of the fin mask material layer 210; taking an anisotropic etching process to etch the second sidewall material layer until the top surface of the plurality of second core structures 221 and the surface of the fin mask material layer 210 are exposed.

[0052] In the embodiment, the process for forming the second sidewall material layer comprises at least one of a chemical vapor deposition process, a physical vapor deposition process and an atomic layer deposition process.

[0053] In the embodiment, the etching process for etching the second sidewall material layer comprises a plasma etching process.

[0054] In the embodiment, after forming the plurality of second sidewalls 220, the plurality of second core structures 221 are removed.

[0055] Please refer to Figure 5 and Figure 6 , Figure 5 is Figure 6 a schematic diagram of a cross-sectional structure along the X1-X2 direction,Figure 6 is Figure 5 a schematic view of the stereoscopic structure of the initial substrate 200, and a plurality of fin mask structures 211 are formed on the surface of the initial substrate 200.

[0056] Specifically, the method for forming the plurality of fin mask structures 211 includes: taking the plurality of second sidewalls 220 as a mask, etching the fin mask material layer 210 until the surface of the initial substrate 200 is exposed.

[0057] In the embodiment, the process for etching the fin mask material layer 210 includes at least one of a dry etching process and a wet etching process.

[0058] In the embodiment, after the plurality of fin mask structures 211 are formed, the plurality of second core structures 221 are removed.

[0059] Please continue to refer to Figure 5 and Figure 6 taking the plurality of fin mask structures 211 as a mask, etching the initial substrate 200 to form a substrate 201 and a plurality of initial fins 202 on the substrate 201.

[0060] In the embodiment, the material of the substrate 201 and the plurality of initial fins 202 includes a semiconductor material. Specifically, the material of the substrate 201 and the plurality of initial fins 202 includes silicon.

[0061] In other embodiments, the material of the substrate and the plurality of initial fins includes silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs, or InGaAsP, etc.

[0062] The substrate 201 includes a first region I and a plurality of second regions II.

[0063] The second region II is used for fin cutting (Fin Cut) of the initial fin 202 to form fins required by the integrated circuit design.

[0064] It should be noted that Figure 5 only one second region II is schematically shown in the above embodiment, but the number of the second regions II can also be two or more, and the area ranges of the second regions II can be the same or different. Specifically, the number and the area ranges of the second regions II are determined according to actual design requirements, and the number and the area ranges of the second regions II should not be regarded as features limiting the protection scope of the present application.

[0065] The intervals between the initial fins 202 are uniform, and the initial fins 202 are located on the first region I and the second regions II.

[0066] In the embodiment, the process of etching the initial substrate 200 includes at least one of a dry etching process and a wet etching process.

[0067] In addition, in the embodiment, the fin mask structures 211 are reserved in the subsequent processes of forming the first isolation layer, the fins, and the second isolation layer, so that the fins in the first region I are further protected in the subsequent etching processes, ion implantation processes, and the like through the fin mask structures 211, to improve the performance and reliability of the semiconductor structure.

[0068] Next, a first isolation layer and a first mask layer on the first isolation layer are formed on the surface of the first region I and the surfaces of the initial fins 202 in the first region I, and the first isolation layer and the first mask layer expose the initial fins 202 in the second regions II. For specific steps of forming the first isolation layer and the first mask layer, please refer to Figures 7 to 8 .

[0069] Please refer to Figure 7 An initial first isolation layer 230 is formed on the surface of the first region I, the surfaces of the second regions II, and the surfaces of the initial fins 202.

[0070] The initial first isolation layer 230 provides material for the subsequent formation of the first isolation layer.

[0071] In the embodiment, the material of the initial first isolation layer 230 includes a dielectric material, and the dielectric material includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0072] In the embodiment, the process of forming the initial first isolation layer 230 includes a flowable chemical vapor deposition process (FCVD). The flowable chemical vapor deposition process has better flowability and filling property, so that the material can be better filled between the adjacent initial fins 202, and the initial first isolation layer 230 with a smoother surface is formed.

[0073] Specifically, the method of forming the initial first isolation layer 230 in the embodiment includes: using the flowable chemical vapor deposition process to form an initial first isolation material layer (not shown) on the surface of the first region I, the surfaces of the second regions II, the surfaces of the initial fins 202, and the surfaces of the fin mask structures 211, and the surface of the initial first isolation material layer is higher than the surfaces of the fin mask structures 211; and planarizing the initial first isolation material layer until the top surfaces of the fin mask structures 211 are exposed, to form the initial first isolation layer 230.

[0074] The process of planarizing the initial first isolation material layer includes a chemical mechanical polishing process.

[0075] Please refer to Figure 8 A first mask layer 240 is formed on the surface of the initial first isolation layer 230 (as shown in Figure 7 The first mask layer 240 exposes the surface of the initial first isolation layer 230 in the second regions II.

[0076] In this embodiment, the method of forming the first mask layer 240 includes: forming a first mask material layer (not shown) on the surface of the initial first isolation layer 230; forming a photoresist pattern layer (not shown) on the surface of the first mask material layer, the photoresist pattern layer exposes the surface of the first mask material layer in the second regions II; etching the first mask material layer with the photoresist pattern layer as a mask until the surface of the initial first isolation layer 230 is exposed, thereby forming the first mask layer 240.

[0077] In this embodiment, an anti-reflective layer (ARC) is further formed on the surface of the first mask material layer before forming the photoresist pattern layer, so as to improve the accuracy of pattern transfer.

[0078] Specifically, the anti-reflective layer is a silicon-containing anti-reflective layer (Si-ARC).

[0079] In this embodiment, the first mask layer 240 is different from the material of the initial first isolation layer 230, so that in the subsequent etching process of forming the first isolation layer, the material of the initial first isolation layer 230 and the material of the first mask layer 240 have a large etching selectivity ratio.

[0080] Specifically, the material of the first mask layer 240 in this embodiment includes an organic substance.

[0081] Please refer to Figure 8 The initial first isolation layer 230 (as shown in Figure 7 ) in the second regions II is etched with the first mask layer 240 as a mask until the initial first isolation layer 230 in the second regions II is removed, thereby forming the first isolation layer 231.

[0082] In this embodiment, the process of etching the initial first isolation layer 230 in the second regions II includes at least one of a dry etching process and a wet etching process.

[0083] Since the first isolation layer 231 is formed after the initial fins 202 with uniform spacing are formed and before the fins are subsequently formed, the stress on the fins when filling the first isolation layer 231 with a material is reduced, thereby reducing defects such as bending, merging, and breaking of the fins, and improving the performance and reliability of the semiconductor structure.

[0084] Please continue to refer to Figure 8 After the first isolation layer 231 is formed, the initial fins 202 in the second region II are etched to form intermediate fins 203 using the first mask layer 240 as a mask.

[0085] The top surface of the intermediate fins 203 in the second region II is higher than the surface of the substrate 201 and lower than the top surface of the intermediate fins 203 in the first region I.

[0086] In this embodiment, the process of etching the initial fins 202 in the second region II includes at least one of a dry etching process and a wet etching process. In this embodiment, the initial fins 202 in the second region II are etched in situ.

[0087] In other embodiments, after the first mask layer is formed, the initial first isolation layer and the initial fins are etched simultaneously to form the first isolation layer and the intermediate fins using the first mask layer as a mask.

[0088] Please refer to Figure 9 The intermediate fins 203 in the second region II and the substrate 201 are subjected to ion implantation to form modified regions 204 in the intermediate fins 203 in the second region II and the substrate 201.

[0089] Since the ion implantation process can better control the implantation depth, the modified regions 204 formed by the ion implantation process can better control the depth of each modified region 204.

[0090] In addition, it should be understood that since the intermediate fins 203 in the second region II and the substrate 201 are subjected to ion implantation to form the modified regions 204, the depth of the modified regions 204 below the intermediate fins 203 is less than the depth of the modified regions 204 below the substrate 201 based on the height difference between the intermediate fins 203 and the substrate 201.

[0091] In this embodiment, the process parameters for ion implantation of the intermediate fins 203 in the second region II and the substrate 201 include that the implanted ions include arsenic ions or boron ions.

[0092] In this embodiment, after the modified regions 204 are formed, the first mask layer 240 is removed.

[0093] The process of removing the first mask layer 240 includes an ashing process.

[0094] In other embodiments, the first mask layer is removed simultaneously in the subsequent etching process of removing the modified regions.

[0095] Please refer to Figure 10 The modified regions 204 are etched until the modified regions 204 are removed, forming a plurality of fins 205. After the modified regions 204 are removed, the surface of the second regions II has a plurality of protrusions 201a and a plurality of recesses 201b alternately, and the surface of the second regions II is lower than the surface of the first regions I, or the highest part of the surface of the second regions II is flush with the surface of the first regions I.

[0096] Since a plurality of intermediate fins 203 are formed, the intermediate fins 203 and the substrate 201 in the second regions II are ion implanted to form modified regions 204, and the modified regions 204 are etched until the modified regions 204 are removed, the surface height of each second region II substrate 201 is better controlled, and the surface of the second regions II with a plurality of protrusions 201a and a plurality of recesses 201b alternately can be formed, thereby not only reducing the stress formed on the plurality of fins 205 to reduce defects such as bending, merging, and breaking of the plurality of fins 205, but also reducing the risk of leakage and short circuit. Therefore, the performance and reliability of the semiconductor structure are improved.

[0097] Specifically, since the depth of each modified region 204 is well controlled, after the modified regions 204 are etched and the intermediate fins 203 and the substrate 201 of the modified regions 204 are removed, on the one hand, the surface of each second region II substrate 201 can be within a suitable height range, thereby reducing the risk of leakage and short circuit. On the other hand, the height difference between the surfaces of each second region II substrate 201 is small, thereby reducing the stress formed on the plurality of fins 205 by the second isolation layer when the second isolation layer is subsequently formed, and further reducing defects such as bending, merging, and breaking of the plurality of fins 205.

[0098] Moreover, it is to be understood that, since the depth of the modification region 204 under the middle fin 203 is less than the depth under the substrate 201, after the modification region 204 is etched and removed, the surface of the second region II can have a plurality of protrusions 201a and a plurality of recesses 201b alternately. On this basis, on the one hand, when the second isolation layer is subsequently formed on the surface of the second region II, the surface of the second region II with a plurality of protrusions 201a and a plurality of recesses 201b alternately can enhance the support and restriction capability of the second isolation layer, thereby reducing the stress of the second isolation layer on the plurality of fins 205, and reducing the defects such as bending, merging, and breaking of the plurality of fins 205. On the other hand, the surface of the second region II with a plurality of protrusions 201a and a plurality of recesses 201b alternately increases the migration path of the carriers in the second region II, thereby reducing the leakage current in the substrate 201.

[0099] In summary, the defects such as bending, merging, and breaking of the plurality of fins 205 are reduced, and the risk of leakage and short circuit of the semiconductor structure is reduced. Thus, the performance and reliability of the semiconductor structure are improved.

[0100] In addition, since the modification region 204 is formed and etched to form the plurality of fins 205, in the process of etching the modification region 204, the etching selectivity between the material of the substrate 201 and the material of the modification region 204 can be large, thereby increasing the process window.

[0101] Preferably, the surface of the second region II is lower than the surface of the first region I, to further reduce the risk of leakage and improve the reliability of the semiconductor structure.

[0102] Preferably, in the first direction K, the minimum distance W1 between the surface of the first region I and the surface of the second region II is greater than 3 nanometers, and the first direction K is parallel to the direction perpendicular to the surface of the first region I.

[0103] If the minimum distance W1 is too small, it is not conducive to improve the risk of leakage and short circuit of the semiconductor structure. Therefore, by making the minimum distance W1 greater than 3 nanometers, the improvement effect on the risk of leakage and short circuit of the semiconductor structure can be further improved.

[0104] Preferably, the distance W2 between the highest point and the lowest point of the surface of the second region II in the first direction K is greater than 50 angstroms.

[0105] If the distance W2 is too small, it is not conducive to increase the migration path of the carriers in the second region II. Therefore, by making the distance W2 greater than 50 angstroms, the migration path of the carriers in the second region II can be further increased, thereby further improving the improvement effect on the risk of leakage and short circuit of the semiconductor structure.

[0106] In the embodiment, the second region II surface alternately comprises a plurality of protrusions 201a and a plurality of recesses 201b, forming a continuous wavy surface. Thus, the uniformity of stress distribution is further improved, so as to further reduce the risk of bending, merging, breaking and other defects of the plurality of fin portions 205.

[0107] Specifically, the first isolation layer 231 in the embodiment is higher than the surface of the plurality of fin portions 205. Thus, the plurality of fin portions 205 can be better protected, and meanwhile, the insulation between devices is further improved, so as to further reduce the risk of leakage and short circuit of the semiconductor structure.

[0108] The process of etching the modified region 204 comprises at least one of a wet etching process and a dry etching process.

[0109] Preferably, the wet etching process is used to etch the modified region 204. Since the wet etching process is anisotropic and can generally provide a higher etching selectivity, the modified region 204 can be better removed (reducing the residue of the modified region 204) and the damage to the substrate 201 of the non-modified region 204 caused by the etching process is reduced by using the wet etching process to etch the modified region 204. Thus, the performance and reliability of the semiconductor structure are further improved.

[0110] In the embodiment, the etchant used in the wet etching process comprises hydrofluoric acid, nitric acid and acetic acid, and the ratio of the hydrofluoric acid, the nitric acid and the acetic acid is 1:1:2. Thus, a larger etching selectivity can be achieved for the material of the modified region 204 (silicon doped with arsenic ions or boron ions) and the material of the non-modified region 204 (silicon), so as to remove the modified region 204.

[0111] Please refer to Figure 11 After the modified region 204 is removed, a second isolation layer 250 is formed on the surface of the plurality of second regions II.

[0112] In the embodiment, the process of forming the second isolation layer 250 comprises a flowable chemical vapor deposition process. The flowable chemical vapor deposition process has better flowability and filling property, so that the material of the second isolation layer 250 can be better filled on the concave-convex surface of the second region II, and the second isolation layer 250 with a smoother surface is formed.

[0113] Specifically, the method for forming the second isolation layer 250 in the embodiment includes: forming a second isolation material layer (not shown) on the surface of the first isolation layer 231 and the surface of the second region II by using a flowable chemical vapor deposition process, the surface of the second isolation material layer being higher than the surface of the first isolation layer 231; and planarizing the second isolation material layer until the surface of the first isolation layer 231 and the top surface of the fin mask structure 211 are exposed, thereby forming the second isolation layer 250.

[0114] The planarization of the second isolation material layer includes a chemical mechanical polishing process.

[0115] In the embodiment, the surface of the second isolation layer 250 is higher than the surface of the fin 205. Thus, the insulation between devices is further improved, thereby further reducing the risk of leakage and short circuit of the semiconductor structure.

[0116] Correspondingly, the embodiment of the present application further provides a semiconductor structure formed by the above method, please continue to refer to Figure 11 , which comprises: a substrate 201, the substrate 201 comprising a first region I and a plurality of second regions II, the surface of the second region II having a plurality of protrusions 201a and a plurality of recesses 201b alternately, and the surface of the second region II being lower than the surface of the first region I or the highest part of the surface of the second region II being flush with the surface of the first region I; a plurality of fins 205 on the first region I, the spacing between the fins 205 being uniform; a first isolation layer 231 on the first region I; and a second isolation layer 250 on the surface of the second region II.

[0117] In the embodiment, the material of the substrate 201 and the plurality of initial fins 202 comprises a semiconductor material. Specifically, the material of the substrate 201 and the plurality of initial fins 202 comprises silicon.

[0118] In other embodiments, the material of the substrate and the plurality of initial fins comprises silicon carbide, silicon germanium, a multi-element semiconductor material composed of group III-V elements, silicon-on-insulator (SOI) or germanium-on-insulator (GOI), etc. The multi-element semiconductor material composed of group III-V elements includes InP, GaAs, GaP, InAs, InSb, InGaAs or InGaAsP, etc.

[0119] Preferably, the surface of the second region II is lower than the surface of the first region I.

[0120] Preferably, in the first direction K, the minimum spacing W1 between the surface of the first region I and the surface of the second region II is greater than 3 nanometers, and the first direction K is parallel to the direction perpendicular to the surface of the first region I.

[0121] Preferably, the distance W2 between the highest and lowest points of the second region II surface in the first direction K is more than 50 angstroms.

[0122] In this embodiment, the alternating protrusions 201a and recesses 201b on the surface of the second region II constitute a continuous wavy surface.

[0123] In this embodiment, the surface of the first isolation layer 231 is higher than the surface of the plurality of fins 205.

[0124] In this embodiment, the surface of the second isolation layer 250 is higher than the surface of a plurality of fins 205.

[0125] In this embodiment, the material of the first isolation layer 231 includes a dielectric material, which includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride.

[0126] In this embodiment, the material of the second isolation layer 250 includes a dielectric material, which includes at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonate, silicon carbonitride, and silicon carbonitride.

[0127] In this embodiment, the semiconductor structure further includes a fin mask structure 211 located on the top surface of the fin 205. The fin mask structure 211 is also located within the first isolation layer 231, and the first isolation layer 231 exposes the top surface of the fin mask structure 211.

[0128] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method of forming a semiconductor structure, characterized by, The method comprises the following steps: forming a substrate, the substrate having a plurality of initial fins separated from each other, the spacing between the initial fins being uniform, the substrate comprising a first region and a plurality of second regions, and the initial fins being located on the first region and the plurality of second regions; forming a first isolation layer on the surface of the first region and the surface of the initial fins on the first region, and a first mask layer on the first isolation layer, the first isolation layer and the first mask layer exposing the initial fins on the plurality of second regions; after the first mask layer is formed, etching the initial fins on the plurality of second regions to form a plurality of intermediate fins by using the first mask layer as a mask, the intermediate fins on the plurality of second regions having a top surface higher than the surface of the substrate and lower than the top surface of the intermediate fins on the first region; performing ion implantation on the intermediate fins on the plurality of second regions and the substrate to form a modified region in the intermediate fins on the plurality of second regions and the substrate; etching the modified region until the modified region is removed to form a plurality of fins, and after the modified region is removed, the surface of the plurality of second regions has a plurality of protrusions and a plurality of recesses alternately arranged, the surface of the plurality of second regions being lower than the surface of the first region, or the highest part of the surface of the plurality of second regions being flush with the surface of the first region; forming a second isolation layer on the surface of the plurality of second regions after the modified region is removed.

2. The method of forming a semiconductor structure of claim 1, wherein The method for forming the first isolation layer and the first mask layer comprises the following steps: forming an initial first isolation layer on the surface of the first region, the surface of the plurality of second regions and the surface of the initial fins; forming a first mask layer on the surface of the initial first isolation layer, the first mask layer exposing the surface of the initial first isolation layer on the plurality of second regions; and etching the initial first isolation layer on the plurality of second regions by using the first mask layer as a mask until the initial first isolation layer on the plurality of second regions is removed to form the first isolation layer.

3. The method of forming a semiconductor structure of claim 2, wherein, The process for forming the initial first isolation layer comprises a flowable chemical vapor deposition process.

4. The method of forming a semiconductor structure of claim 1, wherein, The plurality of protrusions and the plurality of recesses alternately arranged on the surface of the plurality of second regions form a continuous wavy surface.

5. The method of forming a semiconductor structure of claim 1, wherein, The material of the substrate and the initial fins comprises silicon, and the process parameters for performing ion implantation on the intermediate fins on the plurality of second regions and the substrate comprise that the implanted ions comprise arsenic ions or boron ions.

6. The method of forming a semiconductor structure of claim 1, wherein, The process for etching the modified region comprises a wet etching process.

7. The method of forming a semiconductor structure of claim 6, wherein, The etchant used in the wet etching process comprises hydrofluoric acid, nitric acid and acetic acid, and the ratio among the hydrofluoric acid, the nitric acid and the acetic acid is 1:1:

2.

8. The method of forming a semiconductor structure of claim 1, wherein, The surface of the first isolation layer and the surface of the second isolation layer are higher than the surface of the plurality of fins.

9. The method of forming a semiconductor structure of claim 1, wherein, The process for forming the second isolation layer comprises a flowable chemical vapor deposition process.

10. The method of forming a semiconductor structure of claim 1, wherein, The substrate and the initial fins are formed by using a self-aligned double patterning process or a self-aligned multiple patterning process.

11. A semiconductor structure, characterized by The semiconductor structure is formed by using the method for forming a semiconductor structure according to any one of claims 1 to 10, and the semiconductor structure comprises: a substrate comprising a first region and a plurality of second regions, the surface of the plurality of second regions having a plurality of protrusions and a plurality of recesses alternately arranged, and the surface of the plurality of second regions being lower than the surface of the first region or the highest part of the surface of the plurality of second regions being flush with the surface of the first region; a plurality of fins on the first region, the spacing between the fins being uniform. a first isolation layer on the first region; a second isolation layer on the surfaces of the second regions.

12. The semiconductor structure of claim 11, wherein, the surfaces of the first isolation layer and the surfaces of the second isolation layer are higher than the surfaces of the fins.

13. The semiconductor structure of claim 11, wherein, the alternating protrusions and recesses form a continuous wavy surface.

14. The semiconductor structure of claim 11, wherein, in a first direction parallel to a direction normal to the surfaces of the first regions, the minimum distance between the surfaces of the first regions and the surfaces of the second regions is more than 3 nm.

15. The semiconductor structure of claim 11, wherein, in a first direction parallel to a direction normal to the surfaces of the first regions, the distance between the highest points and the lowest points of the surfaces of the second regions is more than 50 angstroms.

Images