Power supply system and electronic device

Abstract

The present disclosure discloses a power supply system and an electronic device. The power supply system is used to supply power to a load, and includes a system board, a substrate, an output capacitor, a positive output lead area, a negative output lead area, and a power unit. The system board includes oppositely arranged first and second surfaces, and the load is arranged on the first surface. The substrate includes oppositely arranged first and second surfaces, and the first surface of the substrate is located between the second surface of the system board and the second surface of the substrate. The output capacitor is attached to the second surface of the system board. The positive output lead area and the negative output lead area are arranged on the first surface of the substrate, connected to the second surface of the system board, and electrically connected to the output capacitor through wiring in the system board. The power unit is arranged on the second surface of the substrate and electrically connected to the positive output lead area and the negative output lead area through wiring in the substrate.

Description

Technical Field

[0001] This disclosure relates to the field of power electronics technology, and in particular to a power supply system and electronic equipment. Background Technology

[0002] The core of data processing lies in various types of processor chips, such as Central Processing Units (CPUs), Graphics Processing Units (GPUs), Field-Programmable Gate Arrays (FPGAs), and ASICs. The power supply system is extremely important for the performance of these processor chips; a stable supply voltage can effectively improve their performance. Therefore, the steady-state and dynamic performance of the power supply units that power the processor chips is crucial. In the power supply system, the connection impedance between the power supply units and the processor chips is relatively high, directly affecting the power supply performance of the processor chips, resulting in poorer processor chip performance and consequently, poor overall power supply performance.

[0003] Therefore, it is necessary to develop a power supply system to solve the problems faced by existing technologies. Summary of the Invention

[0004] The purpose of this disclosure is to provide a power supply system and electronic equipment that have the advantage of better power supply efficiency.

[0005] To achieve the above objectives, one embodiment of this disclosure provides a power supply system for supplying power to a load. The power supply system includes a system board, a substrate, at least one output capacitor, at least one positive output conductive area, at least one negative output conductive area, and at least one power unit. The system board includes a first surface and a second surface disposed opposite to each other, with the load disposed on the first surface. The substrate includes a first surface and a second surface disposed opposite to each other, with the first surface of the substrate located between the second surface of the system board and the second surface of the substrate. At least one output capacitor is surface-mounted on the second surface of the system board. At least one positive output conductive area is disposed on the first surface of the substrate and connected to the second surface of the system board, and electrically connected to one end of the output capacitor via wiring within the system board. At least one negative output conductive area is disposed on the first surface of the substrate and connected to the second surface of the system board, and electrically connected to the other end of the output capacitor via wiring within the system board. At least one power unit is disposed on the second surface of the substrate and electrically connected to at least one positive output conductive area and at least one negative output conductive area via wiring within the substrate.

[0006] Another embodiment of this disclosure provides an electronic device that includes a load and the aforementioned power supply system for supplying power to the load. Attached Figure Description

[0007] Figure 1 This is a cross-sectional structural diagram of the power supply system according to the first embodiment of this disclosure.

[0008] Figure 2 for Figure 1 The diagram shows the exploded structure of the power supply system.

[0009] Figure 3A and Figure 3B for Figure 1 The diagram shows the structure of the power supply system substrate from two different perspectives.

[0010] Figure 3C for Figure 1 A schematic diagram of another embodiment of the power supply system substrate shown.

[0011] Figure 3D for Figure 1 A schematic diagram of another embodiment of the power supply system substrate shown.

[0012] Figure 3E for Figure 1 A schematic diagram of another embodiment of the power supply system substrate shown.

[0013] Figure 3F for Figure 1 A schematic diagram of another embodiment of the power supply system substrate shown.

[0014] Figure 3G for Figure 1 A schematic diagram of another embodiment of the power supply system substrate shown.

[0015] Figure 4 for Figure 1 The equivalent circuit diagram of the power supply system is shown.

[0016] Figure 5 for Figure 1 The diagram shows the structure of the power supply system's substrate and the electronic components mounted on the substrate.

[0017] Figure 6 for Figure 1 A schematic diagram of another embodiment of the power supply system substrate shown.

[0018] Figure 7 for Figure 1 The top view of the second side of the power supply system substrate shown.

[0019] Figure 8 for Figure 1 The power supply system shown is illustrated by a cross-sectional view of the connection holes.

[0020] Figure 9 This is a cross-sectional structural diagram of the power supply system according to the second embodiment of this disclosure.

[0021] Figure 10This is a cross-sectional structural diagram of the power supply system according to the third embodiment of this disclosure.

[0022] Figure 11 for Figure 10 The diagram shows the exploded structure of the power supply system.

[0023] Figure 12 This is a cross-sectional structural diagram of the power supply system according to the fourth embodiment of this disclosure.

[0024] Figure 13 for Figure 1 A schematic diagram showing the installation positions of various conductive areas of the power supply system in another embodiment.

[0025] Figure 14 for Figure 13 The diagram shows the polarity relationship between the positive output conducting region and the adjacent output capacitor.

[0026] Figure 15 for Figure 13 A schematic diagram showing the polarity relationship of another embodiment of the positive output conducting region and the adjacent output capacitor.

[0027] Figure 16 This is a schematic diagram of the second side of the substrate of the power supply system according to the fifth embodiment of this disclosure.

[0028] Figure 17 for Figure 16 An enlarged schematic diagram of the first embodiment of the power unit pads of the power supply system shown.

[0029] Figure 18 for Figure 16 An enlarged schematic diagram of a second embodiment of the power unit pads of the power supply system shown.

[0030] Figure 19 for Figure 16 An enlarged schematic diagram of the third embodiment of the power unit pads of the power supply system shown.

[0031] Figure label:

[0032] 1, 1a, 1b, 1c: Power supply system

[0033] Vin: Input voltage

[0034] RL: Load

[0035] Cin: Input capacitance

[0036] Q1, Q2: Switching elements

[0037] L: Inductance

[0038] Co: Output capacitor

[0039] Vin+: Positive input terminal

[0040] Vin-: Negative input terminal

[0041] Vout+: Positive output terminal

[0042] Vout-: Negative output terminal

[0043] 2: System board

[0044] 21: The first side of the system board

[0045] 22: The second side of the system board

[0046] 3, 3a, 3': Substrate

[0047] 31: The first surface of the substrate

[0048] 32: The second side of the substrate

[0049] 331: First receiving slot

[0050] 331a: Second receiving slot

[0051] 331b: Third receiving slot

[0052] 331c: Fourth Reception Slot

[0053] 332: Connecting hole

[0054] 333: Copper Pillar

[0055] 334: Conductive Structure

[0056] 34: First sidewall of the substrate

[0057] 35: Second sidewall of the substrate

[0058] 36: The third sidewall of the substrate

[0059] 37: The fourth sidewall of the substrate

[0060] 381: Controller pads

[0061] 382: Capacitor pads

[0062] 39, 39a: Power unit pads

[0063] 391: Signal pin

[0064] 392: Input pin

[0065] 393: Output pin

[0066] 394: Ground pin

[0067] 395: First sidewall of the power unit pad

[0068] 396: Second sidewall of the power unit pad

[0069] 397: Third sidewall of the power unit pad

[0070] 398: Fourth sidewall of the power unit pad

[0071] O: Center point

[0072] 4: Output capacitor

[0073] 51: Positive Output Conductor Area

[0074] 511: Sub-positive output conductive area

[0075] 52: Negative output conduction area

[0076] 521: Sub-negative output conduction area

[0077] 53: Positive Input Conduction Area

[0078] 531: Sub-positive input guide area

[0079] 54: Negative Input Conductor Area

[0080] 541: Sub-negative input conduction area

[0081] 6: Power Unit

[0082] 601: Positive output pin of the power unit

[0083] 602: Negative output pin of the power unit

[0084] 61: First row

[0085] 62: Second row

[0086] 63: Third row

[0087] 64: Fourth row

[0088] 7: Controller Detailed Implementation

[0089] Some typical embodiments embodying the features and advantages of this disclosure will be described in detail in the following description. It should be understood that this disclosure can be varied in different implementations without departing from the scope of this disclosure, and the descriptions and drawings therein are for illustrative purposes only and not for limiting the scope of this disclosure.

[0090] Please see Figures 1 to 4 ,in Figure 1 This is a cross-sectional structural diagram of the power supply system according to the first embodiment of this disclosure. Figure 2 for Figure 1 The diagram shown is an exploded view of the power supply system. Figure 3A and Figure 3B for Figure 1 The diagram shows the structure of the power supply system's substrate from two different perspectives. Figure 4 for Figure 1 The equivalent circuit diagram of the power supply system shown is as follows. Figure 4 The circuit diagram shown is only schematic of a single-phase power unit. In a real power supply system, the power unit may contain multiple phases. Figure 4 The circuit within the dashed box shown is connected in parallel to output the power required by the load RL. Of course, one power unit can correspond to two or more phases connected in parallel within the dashed box; this is not a limitation. The power supply system 1 in this embodiment is used to receive and convert the input voltage Vin to supply power to the load RL, where the load RL is a processor chip, such as a Central Processing Unit (CPU), Graphics Processing Unit (GPU), Tensor Processing Unit (TPU), Network Processing Unit (NPU), Field Programmable Gate Array (FPGA), or Application Specific Integrated Circuit (ASIC). Figure 1 The power supply system 1 shown may include one or more power units, and may form multiple Figure 4 The circuit structure shown in the diagram involves multiple power units connected in parallel to supply power to the load RL. The following description uses a power supply system 1 composed of a single-phase power unit as an example. Figure 4As shown, power supply system 1 includes an input capacitor Cin, two switching elements Q1 and Q2, an inductor L, and an output capacitor Co. The two switching elements Q1 and Q2 and the inductor L constitute the power unit 6 of power supply system 1 to convert the electrical energy provided by the input voltage Vin. The power unit 6 of power supply system 1 can be a BUCK circuit or an LLC circuit. The input capacitor Cin is connected to the input voltage Vin to receive the electrical energy provided by the input voltage Vin, and the two ends of the input capacitor Cin are respectively connected to the positive input terminal Vin+ and the negative input terminal Vin- of power supply system 1. The two switching elements Q1 and Q2 are connected in series, and the circuit branch formed by the two switching elements Q1 and Q2 in series is connected in parallel with the input capacitor Cin. The first end of the inductor L is connected to the midpoint of the two switching elements Q1 and Q2, and the second end of the inductor L is connected to the output capacitor Co. The two ends of the output capacitor Co are respectively connected to the positive output terminal Vout+ and the negative output terminal Vout- of power supply system 1, and the output capacitor Co is connected in parallel with the load RL. The negative input terminal Vin- and the negative output terminal Vout- of power supply system 1 are short-circuited.

[0091] like Figures 1 to 3B As shown, the physical structure of the power supply system 1 in this embodiment includes a system board 2, a base plate 3, multiple output capacitors 4, multiple positive output conductive areas 51, multiple negative output conductive areas 52, multiple positive input conductive areas 53, multiple negative input conductive areas 54, and multiple power units 6. First, as... Figure 1 and Figure 2 As shown, system board 2 includes a first surface 21 and a second surface 22, which are arranged opposite to each other, wherein the load RL is disposed on the first surface 21 of system board 2. Figure 2 , Figure 3A and Figure 3BAs shown, substrate 3 includes a first surface 31, a second surface 32, a plurality of first receiving grooves 331, a first sidewall 34, a second sidewall 35, a third sidewall 36, and a fourth sidewall 37. The first surface 31 and the second surface 32 of substrate 3 are disposed opposite to each other. The first surface 31 of substrate 3 is attached to the second surface 22 of system board 2, such that the first surface 31 of substrate 3 is located between the second surface 22 of system board 2 and the second surface 32 of substrate 3. The position of substrate 3 on system board 2 corresponds to the position of load RL on system board 2. The plurality of first receiving grooves 331 are formed by the indentation of the first surface 31 of substrate 3. When the first surface 31 of substrate 3 is attached to the second surface 21 of system board 2, each first receiving groove 331 and the second surface 22 of system board 2 define a closed receiving space. Each first receiving groove 331 may be, but is not limited to, manufactured by milling. The first sidewall 34, the second sidewall 35, the third sidewall 36 and the fourth sidewall 37 of the substrate 3 are all located between the first surface 31 and the second surface 32 of the substrate 3, wherein the first sidewall 34 and the second sidewall 35 are arranged opposite to each other, and the third sidewall 36 and the fourth sidewall 37 are arranged opposite to each other and located between the first sidewall 34 and the second sidewall 35.

[0092] like Figure 1 As shown, each output capacitor 4 is used to form as follows: Figure 4 The corresponding power supply system 1 shows an output capacitor Co, and the output capacitor 4 is surface-mounted to the second side 22 of the system board 2 using a soldering process, and is electrically connected to the load RL via wiring in the system board 2. Each output capacitor 4 is housed in a corresponding first receiving slot 331 on the substrate 3, and the volume of each first receiving slot 331 is larger than the volume of the corresponding output capacitor 4. There is a gap between the wall of each first receiving slot 331 and the corresponding output capacitor 4, so that the output capacitor 4 does not contact the wall of the corresponding first receiving slot 331, thereby improving the stability of the output capacitor 4 mounted on the system board 2.

[0093] Each positive output conductive area 51 is used to construct Figure 4 The positive output terminal Vout+ of the power supply system 1 shown is arranged sequentially on the first surface 31 of the substrate 3 and connected to the second surface 22 of the system board 2 when the first surface 31 of the substrate 3 is attached to it. Each positive output conductive area 51 extends in the same direction as the first sidewall 34 of the substrate 3 towards the second sidewall 35, and is electrically connected to one end of the corresponding output capacitor 4 via wiring within the system board 2. Multiple positive output conductive areas 51 are interconnected via wiring within the substrate 3 to form the overall positive output terminal Vout+ of the power supply system 1. Each negative output conductive area 52 is used to form... Figure 4The negative output terminal Vout- in the power supply system 1 shown is arranged sequentially on the first surface 31 of the substrate 3 and connected to the second surface 22 of the system board 2 when the first surface 31 of the substrate 3 is attached to the second surface 22 of the system board 2. Each negative output conductive area 52 extends in the same direction as the first sidewall 34 of the substrate 3 towards the second sidewall 35, and is electrically connected to the other end of the corresponding output capacitor 4 via wiring within the system board 2. Multiple negative output conductive areas 52 are interconnected via wiring within the substrate 3 to form the overall negative output terminal Vout- of the power supply system 1. Figure 3A and Figure 3B As shown, the multiple negative output conducting areas 52 and the multiple positive output conducting areas 51 are staggered, meaning that there is a corresponding positive output conducting area 51 between every two adjacent negative output conducting areas 52, and a corresponding negative output conducting area 52 between every two adjacent positive output conducting areas 51. In this embodiment, each first receiving slot 331 is located between the corresponding positive output conducting area 51 and the corresponding negative output conducting area 52, such that the output capacitor 4 located in the corresponding first receiving slot 331 is located between the corresponding positive output conducting area 51 and the corresponding negative output conducting area 52.

[0094] In the above embodiments, such as Figure 2 As shown, the power unit 6 includes at least one positive output pin 601 and at least one negative output pin 602. The positive output pin 601 of the power unit 6 is electrically connected to the positive output conductive area 51 via wiring in the substrate 3, and is electrically connected to one end of the output capacitor Co via wiring in the system board 2; the negative output pin 602 of the power unit 6 is electrically connected to the negative output conductive area 52 via wiring in the substrate 3, and is electrically connected to the other end of the output capacitor Co via wiring in the system board 2.

[0095] Another possible pin arrangement, such as Figure 3C As shown, since the current in the positive output conducting region 51 is larger than that in the negative output conducting region 52, the size of the positive output conducting region 51 is set to be wider, or it can be set as two positive output conducting regions 51 side by side, forming an arrangement of positive output conducting region 51, positive output conducting region 51, negative output conducting region 52, positive output conducting region 51, positive output conducting region 51, negative output conducting region 52, positive output conducting region 51, positive output conducting region 51, and negative output conducting region 52, that is, there are two corresponding positive output conducting regions 51 between every two adjacent negative output conducting regions 52. For the side-by-side positive output conducting regions 51, a green strip can be used to block them on a very wide positive output conducting region 51, such as... Figure 3C As shown by the dotted line, it can also be set as two independent positive output conductive areas 51. Such a setting is beneficial for venting during the soldering process between the substrate and the system board, and reduces the proportion of voids.

[0096] In addition to the pin arrangement, the pin layout can also be as follows: Figure 3C Besides the arrangement shown, other arrangements are also possible, such as... Figure 3D As shown, each pair of adjacent positive output conductive areas 51 is connected to two corresponding negative output conductive areas 52, forming an arrangement of positive output conductive area 51, negative output conductive area 52, negative output conductive area 52, positive output conductive area 51, negative output conductive area 52, and negative output conductive area 52. In other embodiments, each pair of adjacent positive output conductive areas 51 is connected to a corresponding negative output conductive area 52, and the number of negative output conductive areas 52 can be greater than two. Figure 3E As shown, each pair of adjacent first receiving slots 331 contains two positive output conductive areas 51 or two negative output conductive areas 52, forming an arrangement of positive output conductive area 51, positive output conductive area 51, negative output conductive area 52, negative output conductive area 52, positive output conductive area 51, positive output conductive area 51, negative output conductive area 52, and negative output conductive area 52. Figure 3F As shown, each pair of adjacent first receiving slots 331 contains multiple positive output conductive areas 51 or multiple negative output conductive areas 52. By dividing large pads into smaller pads, the venting path during the soldering process can be increased, making the soldering more stable and reducing the void ratio. It is worth noting that in these embodiments, the number of positive output conductive areas 51 and negative output conductive areas 52 at each location can be other values, such as more than two.

[0097] The second side 22 of the system board 2, used for connection to the substrate 3, can have pads arranged in a structure identical to those of the substrate 3. Similarly, the first side 21, used for connection to the load RL, can also have pads arranged in a structure identical to those of the load RL. Alternatively, to achieve better current sharing from the power unit to the load, the second side 22 of the system board 2 can also have the same pad arrangement as the first side 21 of the system board 2. That is, the pad arrangements of the first side 21, the second side 22 of the system board 2, and the first side 31 of the substrate 3 are completely identical. Depending on the actual manufacturing process, the relative positions of the substrate 3 and the system board 2 may be offset. The effective welding area must be at least 50% larger than the pad area to ensure welding reliability and current flow requirements.

[0098] Please continue to refer to this. Figures 3D-3F It can be seen that the polarity of the output conducting areas on both sides of each output capacitor 4 is different. Along the first direction S1, there are two output conducting areas between every two adjacent output capacitors 4, and the polarity of the two output conducting areas is the same. Figure 3G As shown, along the first direction S1, there can also be three output conducting regions between every two adjacent output capacitors 4, wherein the polarities of the output conducting regions adjacent to the two adjacent output capacitors 4 are different. Figure 3F As shown, along the second direction S2, the electrodes on the same side of adjacent output capacitors 4 are identical. This embodiment, by setting multiple output conductive areas, greatly improves the current-carrying capacity, further enhancing the power supply efficiency of the power module 6. Figure 3F Taking the first column of capacitors on the far left as an example, each capacitor has two end faces. The same side of output capacitor 4 refers to the side face corresponding to the same end face of output capacitor 4 along the second direction array, for example... Figure 3F The output capacitor 4 is located to the left or right. It is worth noting that in this embodiment, the first direction S1 is the arrangement direction of the first receiving slot 331, such as the horizontal direction, and the second direction S2 is the extension direction of the first receiving slot 331, such as the vertical direction. The second direction S2 is perpendicular to the first direction S1.

[0099] Each positive input conductor 53 is used to construct Figure 4 The positive input terminal Vin+ in the power supply system 1 shown is as follows: Figure 2 , Figure 3A and Figure 3B As shown, in this embodiment, there are two positive input conductive areas 53. The two positive input conductive areas 53 are disposed on the first surface 31 of the substrate 3 and are adjacent to the first sidewall 34 and the second sidewall 35 of the substrate 3, respectively. A plurality of positive output conductive areas 51 and a plurality of negative output conductive areas 52 are respectively located between the two positive input conductive areas 53. The two positive input conductive areas 53 are interconnected through wiring in the substrate 3 to form the positive input terminal Vin+ of the power supply system 1.

[0100] Each negative input conduction area 54 is used to construct Figure 4 The negative input terminal Vin- in the power supply system 1 shown is as follows: Figure 2 , Figure 3A and Figure 3BAs shown, in this embodiment, there are two negative input conductive areas 54. The two negative input conductive areas 54 are disposed on the first surface 31 of the substrate 3 and are adjacent to the third sidewall 36 and the fourth sidewall 37 of the substrate 3, respectively. Multiple positive output conductive areas 51 and multiple negative output conductive areas 52 are respectively located between the two negative input conductive areas 54. The two negative input conductive areas 54 are interconnected via wiring within the substrate 3 to form the negative input terminal Vin- of the power supply system 1. In some embodiments, since the negative input terminal Vin- and the negative output terminal Vout- of the power supply system 1 are short-circuited, the positions of the negative input conductive areas 54 constituting the negative input terminal Vin- and the negative output conductive areas 52 constituting the negative output terminal Vout- of the power supply system 1 can be interchanged. In this embodiment, the positive output conductive area 51, the negative output conductive area 52, the positive input conductive area 53, and the negative input conductive area 54 may be, but are not limited to, constructed by solder mask defined pads (SMD) or non-solder mask defined pads (NSMD).

[0101] like Figure 1 and Figure 2 As shown, multiple power units 6 are disposed on the second surface 32 of the substrate 3. Each power unit 6 is electrically connected to the corresponding positive output conducting area 51, negative output conducting area 52, positive input conducting area 53 and negative input conducting area 54 via wiring in the substrate 3.

[0102] As can be seen from the above, in this embodiment, the output capacitor 4 of the power supply system 1 is surface-mounted on the second surface 22 of the system board 2, and the load RL is disposed on the first surface 21 of the system board 2. This makes the connection path between the output capacitor 4 and the load RL very short, that is, the connection path between the output capacitor 4 and the load RL is only the wiring inside the system board 2 connecting the output capacitor 4 and the load RL. This also makes the connection impedance between the output capacitor 4 and the load RL low, thereby improving the power supply performance of the power unit 6. Therefore, the overall performance of the power supply system 1 in this embodiment is also improved. In addition, since each output capacitor 4 is disposed in the corresponding first receiving slot 331 on the substrate 3, and the output capacitor 4 is located between the corresponding positive output conducting area 51 and the corresponding negative output conducting area 52, it means that... Figure 4 The current on the output capacitor Co shown can flow evenly to the positive output terminal Vout+ and the negative output terminal Vout-, resulting in a significant current sharing effect between the positive output conductive area 51 constituting the positive output terminal Vout+ and the negative output conductive area 52 constituting the negative output terminal Vout-. Finally, since the output capacitors Co are all mounted on the system board 2 using conventional surface mount technology, the process is simple and reliable.

[0103] Please see Figure 5and cooperate Figure 2 and Figure 3A ,in Figure 5 for Figure 1 The diagram shows a schematic of the power supply system substrate and the electronic components disposed on the substrate. In this embodiment, the power supply system 1 further includes a controller 7 disposed on the second surface 32 of the substrate 3, adjacent to a portion of the power units 6, and further adjacent to the connection between the first sidewall 34 and the third sidewall 36 of the substrate 3. The controller 7 is electrically connected to multiple power units 6 via wiring within the substrate 3. The controller 7 is used to control the operating state of switching elements (not shown) within the power units 6. As can be seen from the above, in this embodiment, both the controller 7 and the power units 6 of the power supply system 1 are disposed on the second surface 32 of the substrate 3. Therefore, no additional connecting lines are required between the controller 7 and the power units 6, which significantly reduces the connection impedance between the controller 7 and the power units 6 and also reduces the time for the control signal output by the controller 7 to be transmitted to the power units 6, thereby maintaining the stability of the output voltage of the power supply system 1. Furthermore, since the controller 7 is disposed on the second surface 32 of the substrate 3, the number of electronic components on the system board 2 can be reduced, thus reducing the area of ​​the system board 2.

[0104] Please continue reading. Figure 5 In this embodiment, there are twelve power units 6, and the twelve power units 6 are arranged in three rows, namely the first row 61, the second row 62 and the third row 63. The first row 61, the second row 62 and the third row 63 are arranged in sequence, and the arrangement direction between the first row 61, the second row 62 and the third row 63 is the same as the direction from the fourth sidewall 37 of the substrate 3 toward the third sidewall 36. Each row of the first row 61, the second row 62 and the third row 63 contains four power units 6.

[0105] In some embodiments, the power unit 6 can... Figure 4The two switching elements Q1 and Q2 and the inductor L shown are packaged into a single structure. A portion of the input capacitor Cin in the power supply system can be integrated into this single structure, while another portion of the input capacitor Cin is disposed on the second side of the substrate. Multiple input capacitors Cin are disposed on the second side 32 of the substrate 3, and are sequentially arranged between the first sidewall 34 and the second sidewall 35 of the substrate 3. These multiple input capacitors Cin are interleaved with multiple power units 6. As can be seen from the above, in this embodiment, both the power units 6 and the input capacitors Cin of the power supply system 1 are disposed on the second side 32 of the substrate 3. Therefore, no additional connecting lines are needed between the power units 6 and the input capacitors Cin, significantly reducing the connection impedance between them. The voltage on the input capacitors Cin is less prone to attenuation, and voltage fluctuations are less likely to affect the power units 6 after being filtered by the input capacitors Cin. Therefore, the input voltage of the power units 6 is more stable. Furthermore, since the input capacitors Cin are disposed on the second side 32 of the substrate 3, the number of electronic components on the system board 2 can be reduced, further shrinking the area of ​​the system board 2. In other embodiments, to reduce the size of the power unit 6, all the input capacitors Cin can be located on the second side of the substrate, with only the input capacitor Cin located on the second side of the substrate. Figure 4 The two switching elements Q1 and Q2 shown, along with the inductor L, are packaged as a single, integral structure, instead of integrating the input capacitor Cin inside the power unit 6.

[0106] In some embodiments, to improve the power supply performance of the power unit 6, the number of output capacitors 4 needs to be significantly increased, and the number of receiving slots on the substrate also needs to be increased accordingly to accommodate the corresponding number of output capacitors 4. Please refer to [link to relevant documentation]. Figure 6 and cooperate Figure 1 ,in Figure 6 for Figure 1 A schematic diagram of another embodiment of the power supply system substrate is shown. (See diagram below.) Figure 6 As shown, in this embodiment, the substrate 3a includes not only the first receiving groove 331, but also a plurality of second receiving grooves 331a, a plurality of third receiving grooves 331b, and a plurality of fourth receiving grooves 331c. The plurality of second receiving grooves 331a are formed by the indentation of the first surface 31 of the substrate 3a and penetrate through the third sidewall 36 and the fourth sidewall 37 of the substrate 3a. Some of the second receiving grooves 331a are located between the positive output conducting area 51 and the positive input conducting area 53, and other parts of the second receiving grooves 331a are located between the negative output conducting area 52 and the positive input conducting area 53. The plurality of second receiving grooves 331a are used to accommodate the additional output capacitor 4.

[0107] Multiple third receiving slots 331b are formed by the recess of the first surface 31 of the substrate 3a and extend through the third sidewall 36 and the fourth sidewall 37 of the substrate 3a. A portion of the third receiving slots 331b divides the positive output conducting area 51 into multiple sub-positive output conducting areas 511, for example, two. The two sub-positive output conducting areas 511 of each positive output conducting area 51 are arranged sequentially and spaced apart, with the arrangement direction of the two sub-positive output conducting areas 511 being the same as the direction from the first sidewall 34 of the substrate 3 towards the second sidewall 35. Another portion of the third receiving slots 331b divides the negative output conducting area 52 into multiple sub-negative output conducting areas 521, for example, two. The two sub-negative output conducting areas 521 of each negative output conducting area 52 are arranged sequentially and spaced apart, with the arrangement direction of the two sub-negative output conducting areas 521 being the same as the direction from the first sidewall 34 of the substrate 3 towards the second sidewall 35. The multiple third receiving slots 331b are used to accommodate additional output capacitors 4. The third receiving groove 331b in the other part divides the negative input conducting area 54 into multiple sub-negative input conducting areas 541, such as two. The two sub-negative input conducting areas 541 of each negative input conducting area 54 are arranged sequentially and spaced apart. The arrangement direction of the two sub-negative input conducting areas 541 is the same as the direction of the first sidewall 34 of the substrate 3 toward the second sidewall 35. The multiple third receiving grooves 331b are used to accommodate the additional output capacitor 4.

[0108] Multiple fourth receiving slots 331c are formed by the recess of the first surface 31 of the substrate 3a. Each fourth receiving slot 331c is connected to the corresponding first receiving slot 331. The fourth receiving slots 331c divide the positive input conducting area 53 into multiple sub-positive input conducting areas 531, such as four. The four sub-positive input conducting areas 531 of each positive input conducting area 53 are arranged sequentially and spaced apart. The arrangement direction of the four sub-positive input conducting areas 531 is the same as the direction from the third sidewall 36 of the substrate 3 toward the fourth sidewall 37. The multiple fourth receiving slots 331c are used to accommodate additional output capacitors 4.

[0109] Please see Figure 7 and cooperate Figure 1 and Figure 2 ,in Figure 7 for Figure 1 The top view of the second side of the power supply system substrate shown. Figure 7 As shown, the second surface 32 of the substrate 3 includes a controller pad 381, a plurality of input capacitor pads 382, ​​and a plurality of power unit pads 39. The controller pad 381 is adjacent to the connection between the first sidewall 34 and the third sidewall 36 of the substrate 3, and is used for the controller 7 to be disposed, for example, by soldering, so that the controller 7 is disposed on the second surface 32 and electrically coupled to the substrate 3 via the controller pad 381, and the control signal output by the controller 7 can be transmitted to the wiring in the substrate 3 via the controller pad 381.

[0110] The multiple power unit pads 39 on the substrate 3 form three rows, and the positions of the three rows formed by the multiple power unit pads 39 on the substrate 3 correspond to the positions of the three rows on the substrate 3 where the power units 6 are disposed. Figure 7 The first row 61, the second row 62, and the third row 63 represent the three rows formed by the multiple power unit pads 39 on the substrate 3, and the arrangement of the three rows will not be described again here. Each power unit pad 39 is used for the corresponding power unit 6 to be set by, for example, soldering, so that the power unit 6 is set on the second surface 32 and electrically coupled to the substrate 3 through the corresponding power unit pad 39, and the electrical energy output by the power unit 6 can be transferred to the wiring in the substrate 3 through the power unit pad 39.

[0111] In this embodiment, each power unit pad 39 includes a plurality of signal pins 391. Each signal pin 391 is electrically coupled to the controller 7 via wiring within the substrate 3. When a power unit 6 is disposed on a corresponding power unit pad 39, the control signal output by the controller 7 is transmitted to the power unit 6 via the corresponding signal pin 391. The plurality of signal pins 391 of each power unit pad 39 are disposed on one of the four sides of the corresponding power unit pad 39 that is relatively far from the center point O of the substrate 3. Figure 7For example, the center point O of the substrate 3 is preset to be the center position of the three rows formed by the multiple power unit pads 39 on the substrate 3. In this embodiment, the center point O of the substrate 3 is located between the second power unit 6 and the third power unit 6 in the second row 62. The signal pins 391 of the four power unit pads 39 in the first row 61 are all located on the side of the corresponding power unit pad 39 that is relatively far from the center point O of the substrate 3, that is, on the side of the four sides of the power unit pad 39 that is adjacent to the fourth sidewall 37 of the substrate 3. The signal pins 391 of the two power unit pads 39 adjacent to the first sidewall 34 of the substrate 3 in the second row 62 are all located on the side of the corresponding power unit pad 39 that is relatively far from the center point O of the substrate 3, that is, on the side of the four sides of the power unit pad 39 that is adjacent to the first sidewall 34 of the substrate 3. In the second row 62, the signal pins 391 of the two power unit pads 39 adjacent to the second sidewall 35 of the substrate 3 are all located on the side of the corresponding power unit pad 39 that is relatively far from the center point O of the substrate 3, that is, on the side of the four sides of the power unit pad 39 that is adjacent to the second sidewall 35 of the substrate 3. In the third row 63, the signal pins 391 of the four power unit pads 39 are all located on the side of the corresponding power unit pad 39 that is relatively far from the center point O of the substrate 3, that is, on the side of the four sides of the power unit pad 39 that is adjacent to the third sidewall 36 of the substrate 3. The arrangement of the signal pins 391 of the power unit pads 39 allows for a more flexible wiring arrangement within the substrate 3.

[0112] Of course, each power unit pad 39 also includes more types of pins, such as input pin 392, output pin 393, and ground pin 394. The signal pin 391, input pin 392, output pin 393, and ground pin 394 can be, but are not limited to, constructed using solder mask-defined (SMD) or non-solder mask-defined (NSMD) pads. The configuration of the input pin 392, output pin 393, and ground pin 394 will be described in detail later.

[0113] Multiple input capacitor pads 382 are sequentially arranged in four rows between the third sidewall 36 and the fourth sidewall 37 of the substrate 3. The four rows of input capacitor pads 381 are staggered with the three rows of power unit pads 39, meaning that there is a corresponding row of power unit pads 39 between every two adjacent rows of input capacitor pads 381. The multiple input capacitor pads 382 in each row are arranged sequentially and are oriented in the same direction as the first sidewall 34 of the substrate 3 towards the second sidewall 35. Each input capacitor pad 382 is in contact with the corresponding input capacitor Cin, so that the input capacitor Cin is electrically coupled to the substrate 3 through the corresponding input capacitor pad 382 to transfer electrical energy between the substrate 3 and the input capacitor Cin.

[0114] In some embodiments, the interconnection between the various conductive areas located on the first surface 31 of the substrate 3 and the various pins of the power unit pads 39 located on the second surface 32 of the substrate 3 can be achieved in various ways, such as by providing connection holes in the substrate 3 for electrical connection. Please refer to [link to relevant documentation]. Figure 8 and cooperate Figure 1 , Figure 2 and Figure 7 ,in Figure 8 for Figure 1 The power supply system shown is illustrated with a cross-sectional view of the connection holes. (See diagram below.) Figure 8As shown, the substrate 3 also includes a plurality of connection holes 332. Each connection hole 332 penetrates through the first surface 31 and the second surface 32 of the substrate 3. Each connection hole 332 can be a through-hole structure or a blind buried hole structure with conductive function. The position of one end of the connection hole 332 corresponds to the input terminal pin 392, output terminal pin 393 or ground pin 394 of the power unit pad 39. The position of the other end of the connection hole 332 corresponds to the positive input conductive area 53, the positive output conductive area 51, the negative output conductive area 52 or the negative input conductive area 54. The input terminal pin 392 of each power unit pad 39 is connected to the positive input conductive area 53 through the corresponding connection hole 332. The positive input terminal of the power unit 6 receives electrical energy from the system board 2 through the input terminal pin 392 of the power unit pad 39 on the substrate 3, the corresponding connection hole 332 and the positive input conductive area 53. Each power unit pad 39's output pin 393 is connected to the positive output conductive area 51 via a corresponding connection hole 332. The positive output power of the power unit 6 is transmitted to the system board 2 via the output pin 393 of the power unit pad 39 on the substrate 3, the corresponding connection hole 332, and the positive output conductive area 51. Each power unit pad 39's ground pin 394 is connected to the negative output conductive area 52 or the negative input conductive area 54 via a corresponding connection hole 332. The negative output power of the power unit 6 is transmitted to the system board 2 via the ground pin 394 of the power unit pad 39 on the substrate 3, the corresponding connection hole 332, and the negative output conductive area 52. The negative input power of the power unit 6 is transmitted to the system board 2 via the ground pin 394 of the power unit pad 39 on the substrate 3, the corresponding connection hole 332, and the negative input conductive area 54. Figure 8 The example only shows that the output pin 393 is connected to the positive output conductive area 51 via the corresponding connection hole 332, and the ground pin 394 of the power unit pad 39 is connected to the negative output conductive area 52 via the corresponding connection hole 332. The input pin 392 is connected to the positive input conductive area 53 via the corresponding connection hole 332, and the ground pin 394 is connected to the negative input conductive area 54 via the corresponding connection hole 332. They can also be connected in a similar way, and will not be described in detail here. As can be seen from the above, since the substrate 3 is located between the power unit 6 and the system board 2, the input power received on the system board 2 can be directly transmitted to the power unit 6 through the connection hole 332 in the substrate 3. The power unit 6 converts the input power and then transmits it to the system board 2 through the connection hole 332 in the substrate 3. Since the output capacitor 4 is directly attached to the second surface 22 of the system board 2, the converted power received by the system board 2 can be directly transmitted to the output capacitor 4 and the load RL through the wiring in the system board 2. Therefore, it can be seen that the arrangement of the power supply system 1 disclosed herein makes the connection path between the output capacitor 4 and the load RL shorter, thereby significantly reducing the transmission impedance between the output capacitor 4 and the load RL.

[0115] To prevent the substrate 3 from bending when the first surface 31 of the substrate 3 is milled to form the first receiving groove 331, which would affect the welding between the substrate 3 and the system board 2, in some embodiments, the original substrate (hereinafter referred to as the original substrate 3) before the first receiving groove 331 is formed can be optimized. For example, the wiring layer density adjacent to the first surface 31 of the original substrate 3 can be increased, and the wiring layer density adjacent to the second surface 32 of the original substrate 3 can be decreased. This results in lower stress in the portion of the original substrate 3 near the four sidewalls, and higher stress in the other portion of the original substrate 3 near the center, causing pre-bending of the original substrate 3. When the first surface 31 of the original substrate 3 is milled to form the first receiving groove 331 to form the substrate 3, the stress at the center of the substrate 3 can be released to ensure the flatness of the substrate 3. In other embodiments, when the first surface 31 of the substrate 3 is provided with a first receiving groove 331 by milling, the second surface 32 of the substrate 3 is also provided with an additional groove by milling or drilling, so that the stress release degree of the first surface 31 and the second surface 32 of the substrate 3 is the same, so as to ensure the flatness of the substrate 3.

[0116] Please see Figure 9 This is a cross-sectional structural diagram of the power supply system according to the second embodiment of this disclosure. The power supply system 1a of this embodiment is similar to... Figure 1 The power supply system 1 shown is, compared to Figure 1The power supply system 1 shown is connected between the conductive area and the pins corresponding to the power unit pad 39 via a connection hole. The power supply system 1a of this embodiment includes a plurality of copper pillars 333. Each copper pillar 333 is embedded in the substrate 3. The position of one end of the copper pillar 333 corresponds to the input pin 392, output pin 393 or ground pin 394 of the power unit pad 39. The position of the other end of the copper pillar 333 corresponds to the positive input conductive area 53, the positive output conductive area 51, the negative output conductive area 52 or the negative input conductive area 54. The input pin 392 of each power unit pad 39 is connected to the positive input conductive area 53 via the corresponding copper pillar 333. The output pin 393 of each power unit pad 39 is connected to the positive output conductive area 51 via the corresponding copper pillar 333. The ground pin 394 of each power unit pad 39 is connected to the negative output conductive area 52 or the negative input conductive area 54 via the corresponding copper pillar 333. Therefore, the power supply system 1a of this embodiment can meet the current requirements between the corresponding conductive area on the first surface 31 of the substrate 3 and the pin corresponding to the power unit pad 39 on the second surface 32 of the substrate 3. When the current between the corresponding conductive area on the first surface 31 of the substrate 3 and the pin corresponding to the power unit pad 39 on the second surface 32 of the substrate 3 is large, the effective conductive area that the copper pillar 333 can achieve is large, which makes the current transmission more stable. In addition, since the substrate 3 is located between the system board 2 and the power unit 6, the heat generated by the power unit 6 can be conducted to the system board 2 through the copper pillar 333 in the substrate 3, and dissipated through the heat sink (not shown) on the system board 2.

[0117] Please see Figure 10 and Figure 11 ,in Figure 10 This is a cross-sectional structural diagram of the power supply system according to the third embodiment of this disclosure. Figure 11 for Figure 10 The diagram shows the exploded structure of the power supply system. The power supply system 1b in this embodiment is similar to... Figure 1 The power supply system 1 shown is, compared to Figure 1The first surface 31 of the substrate 3 of the power supply system 1 shown is directly attached to the second surface 22 of the system board 2, and a first receiving groove 331 is formed on the first surface 31 of the substrate 3 by milling. In this embodiment, the first surface 31 of the substrate 3 of the power supply system 1b is spaced apart from the second surface 22 of the system board 2, and the power supply system 1b also includes a plurality of conductive structures 334. Each conductive structure 334 is composed of conductive pillars. Each conductive structure 334 can be an integrally formed structure or a segmented structure composed of multiple components. One end of each conductive structure 334 is connected to the second surface 22 of the system board 2, and the other end of each conductive structure 334 is connected to the corresponding conductive area among the positive output conductive area 51, negative output conductive area 52, positive input conductive area 53 or negative input conductive area 54 on the first surface 31 of the substrate 3. Furthermore, a first receiving groove 331 is defined between each conductive structure 334, an adjacent conductive structure 334, the first surface 31 of the substrate 3, and the second surface 22 of the system board 2. Each first receiving groove 331 is used to accommodate the corresponding output capacitor 4. In some embodiments, the two ends of each conductive structure 334 used for welding can be wavy surfaces to achieve the effect of venting gas. Of course, the formation method and placement of the conductive structure 334 are not limited, and will not be elaborated here. As can be seen from the above, since the output capacitor 4 is located between the substrate 3 and the system board 2, and the output capacitor 4 is directly surface-mounted on the second surface 22 of the system board 2, the electrical energy transmitted by the power unit 6 is sequentially transmitted to the system board 2 via the substrate 3 and the conductive structure 334, and then transmitted to the output capacitor 4 and the load RL via the wiring in the system board 2.

[0118] In some embodiments, the conductive structure 334 can be configured not only as conductive pillars but also as solder balls, and its formation can be a ball grid array (BGA) package, such as... Figure 12 As shown, Figure 12 This is a cross-sectional structural diagram of the power supply system according to the fourth embodiment of this disclosure. To avoid potential solder ball collapse, high-temperature core solder balls can be used to form the conductive structure 334, such as a copper core or a high-melting-point solder core. In some embodiments, to simultaneously address solder ball collapse and cost considerations, high-temperature core solder balls are provided at the four corners of the first surface 31 of the substrate 3, while conventional solder balls are provided at the remaining positions on the first surface 31 of the substrate 3. This utilizes the solder balls at the four corners of the substrate 3 to control the collapse of solder balls at the remaining positions on the substrate 3, thereby improving the process yield of the power supply system 1c of this embodiment. Furthermore, since the power supply system 1b of the previous embodiment and the power supply system 1c of this embodiment directly connect the substrate 3 and the system board 2 using the conductive structure 334 without requiring additional processing on the substrate 3, the flatness of the power supply system 1b of the previous embodiment and the power supply system 1c of this embodiment is relatively high.

[0119] In some embodiments, the positions of the plurality of positive output conducting regions 51 and the plurality of negative output conducting regions 52 disposed on the first surface 31 of the substrate 3 are not limited to those of other embodiments. Figure 2 , Figure 3A The settings are shown in the image, but can be adjusted as needed. Please refer to [link / reference]. Figure 13 and Figure 14 ,in Figure 13 for Figure 1 The diagram shows the installation positions of various conductive areas of the power supply system according to another embodiment. Figure 14 for Figure 13 The diagram shows the polarity relationship between the positive output conducting region and the adjacent output capacitor. (See diagram for example.) Figure 13 As shown, in this embodiment, the substrate 3b has a plurality of positive output conductive areas 51 and a plurality of negative output conductive areas 52 arranged alternately, with a corresponding negative output conductive area 52 between every two positive output conductive areas 51, and a corresponding positive output conductive area 51 between every two negative output conductive areas 52. Each output capacitor 4 is disposed between two adjacent conductive areas, for example, between a corresponding positive output conductive area 51 and a corresponding negative output conductive area 52. Figure 13 As shown, in this embodiment, the positive output conducting region 51 and the negative output conducting region 52, which are connected to the output capacitor 4, are arranged alternately along the first direction S1 and also alternately along the second direction S2, which is perpendicular to the first direction S1. Current flows from the positive output conducting region 51 through the output capacitor 4 to the negative output conducting region 52 to form an output circuit. Along the first direction, the current directions of adjacent output circuits are opposite, which partially cancels out the parasitic inductance of the adjacent output circuits, further improving the efficiency of the power supply system. Along the second direction, the current directions of adjacent output circuits are also opposite, which also partially cancels out the parasitic inductance of the adjacent output circuits, further improving the efficiency of the power supply system.

[0120] Figure 14 The polarity of the pins of the output capacitor 4 is illustrated using the positive output conductive area 51 and the adjacent output capacitor 4 as an example. Figure 14 One pin on the output capacitor 4 is labeled Vo, indicating that it is electrically connected to the positive output terminal Vout+. Figure 14 The other pin on the output capacitor 4 is marked GND, indicating that it is electrically connected to the negative output terminal Vout-, as shown below. Figure 14 As shown, according to Figure 13 In this configuration, the polarity of the pins adjacent to the positive output conductive area 51 in the two pins of each output capacitor 4 is the same as the polarity of the positive output conductive area 51. Similarly, the polarity of the pins of the negative output conductive area 52 and the adjacent output capacitor 4 is also similar. Figure 14That is, the polarity of the pins adjacent to the negative output conductive area 52 in each of the two pins of each output capacitor 4 is the same as the polarity of the negative output conductive area 52, which will not be elaborated further here. Due to the polarity characteristics of the pins of the output capacitor 4, if the conductive structure connected to the positive output conductive area 51 and the conductive structure connected to the negative output conductive area 52 accidentally become interconnected, a short circuit will not occur. In this embodiment, the shape of each positive output conductive area 51 and the shape of each negative output conductive area 52 are circular, which makes the area occupied by the positive output conductive area 51 and the negative output conductive area 52 on the first surface 31 of the substrate 3 smaller. Therefore, under the premise that the area of ​​the first surface 31 of the substrate 3 is fixed, the number of output capacitors 4 can be increased. Since multiple output capacitors 4 are connected in parallel, the equivalent series resistance of the increased number of output capacitors 4 decreases, thereby improving the stability of the output voltage of the power supply system.

[0121] In other embodiments, the shape of each positive output conduction region 51 is not limited to... Figure 14 The circle shown, as Figure 15 As shown, where Figure 15 for Figure 13 A schematic diagram showing the polarity relationship of another embodiment of the positive output conducting region and the adjacent output capacitor. (See diagram below.) Figure 15 As shown, each positive output conducting region 51 is square in shape. Compared to a circular positive output conducting region 51, the area of ​​each positive output conducting region 51 is increased, resulting in a smaller current density flowing through the positive output conducting region 51. Of course, the shape of each negative output conducting region 52 can also be square, which will not be elaborated here.

[0122] In some embodiments, the controller pad 381, the plurality of input capacitor pads 382, ​​and the plurality of power unit pads 39 on the second surface 32 of the substrate 3 are not limited to Figure 7 The arrangement shown. Please refer to [link / reference]. Figure 16 and Figure 17 ,in Figure 16 This is a schematic diagram of the second side of the substrate of the power supply system according to the fifth embodiment of this disclosure. Figure 17 for Figure 16 This is an enlarged schematic diagram of a first embodiment of the power unit pads of the power supply system shown. The second surface 32 of the substrate 3c in this embodiment is similar to... Figure 7 The second surface 32 of the substrate 3 shown includes a controller pad 381, multiple input capacitor pads 382, ​​and multiple power unit pads 39. Compared to Figure 7The arrangement of the multiple power unit pads 39 shown forms three rows. In this embodiment, the arrangement of the multiple power unit pads 39 forms four rows, namely the first row 61, the second row 62, the third row 63, and the fourth row 64. Of course, the multiple power units 6 connected to the multiple power unit pads 39 are also arranged in four rows, which will not be described in detail here.

[0123] In this embodiment, each power unit pad 39 includes a plurality of signal pins 391, wherein the plurality of signal pins 391 of each power unit pad 39 are disposed on one of the four sides of the corresponding power unit pad 39 that is relatively far from the center point O of the substrate 3, such as... Figure 16 As shown, the center point O of the substrate 3 is located at the center between the second power unit 6 of the second row 62, the third power unit 6 of the second row 62, the second power unit 6 of the third row 63, and the third power unit 6 of the third row 63. The signal pins 391 of the two power unit pads 39 in the first row 61 are located on the side of the corresponding power unit pad 39 that is relatively far from the center point O of the substrate 3, that is, on the side of the four sides of the power unit pad 39 that is adjacent to the fourth sidewall 37 of the substrate 3. The signal pins 391 of the two power unit pads 39 in the second row 62 that are respectively adjacent to the first sidewall 34 and the second sidewall 35 of the substrate 3 are respectively located on the side of the corresponding power unit pad 39 that is relatively far from the center point O of the substrate 3, that is, on the side of the four sides of the power unit pad 39 that is adjacent to the first sidewall 34 and the second sidewall 35 of the substrate 3. In the second row 62, the signal pins 391 of the two power unit pads 39 adjacent to the center point O of the substrate 3 are both located on the side of the corresponding power unit pad 39 adjacent to the fourth sidewall 37 of the substrate 3. In the third row 63, the signal pins 391 of the two power unit pads 39 adjacent to the first sidewall 34 and the second sidewall 35 of the substrate 3 are respectively located on the side of the four sides of the corresponding power unit pad 39 that is relatively far from the center point O of the substrate 3, that is, respectively located on the side of the four sides of the corresponding power unit pad 39 adjacent to the first sidewall 34 and the second sidewall 35 of the substrate 3. In the third row 63, the signal pins 391 of the two power unit pads 39 adjacent to the center point O of the substrate 3 are both located on the side of the corresponding power unit pad 39 adjacent to the third sidewall 36 of the substrate 3. The signal pins 391 of the two power unit pads 39 in the fourth row 64 are located on the side of the corresponding power unit pad 39 that is relatively far from the center point O of the substrate 3, that is, on the side of the corresponding power unit pad 39 that is adjacent to the third sidewall 36 of the substrate 3.

[0124] The above-described configuration shortens the path distance between the power unit 6 connected to the power unit pad 39 and the controller 7 connected to the controller pad 381, and reduces the signal delay of the control signal of the power unit 6. Furthermore, in this embodiment, each input capacitor pad 382 is adjacent to the signal pin 391 of the corresponding power unit pad 39, thus reducing the path distance between the input capacitor Cin connected to the input capacitor pad 382 and the power unit 6 connected to the power unit pad 39. In addition, considering the above-described pad configuration, the path distance between the power unit 6 connected to the second surface 32 of the substrate 3 and the load RL connected to the first surface 31 of the substrate 3 is also shortened, reducing the impedance between the power unit 6 and the load RL and improving the current sharing of the power unit 6. In this embodiment, each power unit 6 can be a one-phase, two-phase, or multi-phase BUCK circuit. If the power unit 6 is a multi-phase circuit, the power density of each power unit 6 can be significantly increased, allowing for a lower required number of power units 6 in the power supply system to provide the electrical energy required by the load RL.

[0125] like Figure 17As shown, each power unit pad 39 has a first sidewall 395, a second sidewall 396, a third sidewall 397, and a fourth sidewall 398. The first sidewall 395 and the second sidewall 396 of the power unit pad 39 are arranged opposite to each other, and the third sidewall 397 and the fourth sidewall 398 of the power unit pad 39 are arranged opposite to each other and located between the first sidewall 395 and the second sidewall 396. In addition to multiple signal pins 391, each power unit pad 39 also has multiple input pins 392, multiple output pins 393, and multiple ground pins 394. Multiple signal pins 391 are adjacent to the first sidewall 395 of the power unit pad 39 and arranged sequentially. Multiple output pins 393 are located at the center of the power unit pad 39. Multiple input pins 392 and multiple ground pins 394 are arranged sequentially around the multiple output pins 393. Some of the input pins 392 are adjacent to the third sidewall 397 of the power unit pad 39. The fourth sidewall 398 of the power unit pad 39 has an additional portion of the input pins 392 located between the signal pin 391 and the output pin 393. A portion of the ground pins 394 are adjacent to the third sidewall 397 of the power unit pad 39, a portion of the ground pins 394 are adjacent to the second sidewall 396 of the power unit pad 39, and the remaining portion of the ground pins 394 are adjacent to the fourth sidewall 398 of the power unit pad 39. In this embodiment, the connection holes in the substrate 3 connected to the various pins can be blind vias to reduce the spacing between the multiple connection holes, thereby increasing the number of connection holes in the substrate 3 to achieve higher current flow capability.

[0126] In other embodiments, the placement of the various pins on the power unit pads is not limited to... Figure 17 As shown, please refer to Figure 18 , it is Figure 16This is an enlarged schematic diagram of a second embodiment of the power unit pad of the power supply system shown. In this embodiment, multiple signal pins 391 of the power unit pad 39a are adjacent to the first sidewall 395 of the power unit pad 39 and arranged sequentially; multiple ground pins 394 are adjacent to the second sidewall 396 of the power unit pad 39 and arranged sequentially; multiple input pins 392 are arranged sequentially and located between the multiple signal pins 391 and the multiple output pins 393; and multiple output pins 393 are arranged sequentially and located between the multiple input pins 392 and the multiple ground pins 394. Because the current flowing through the output pins 393 is relatively large, in some embodiments, the range of the output pins 393 is increased to meet the actual needs of the circuit, resulting in the output pins 393 possibly protruding beyond the third sidewall 397 and the fourth sidewall 398 of the power unit pad 39. Figure 19 As shown, it is Figure 16 The diagram shows an enlarged view of the third embodiment of the power unit pad of the power supply system. In order to connect the output pins 393 protruding from the third sidewall 397 and the fourth sidewall 398 of the power unit pad 39, a greater number of connection holes 332 can be provided on the substrate 3 to connect the output pins 393 protruding from the third sidewall 397 and the fourth sidewall 398 of the power unit pad 39. The above arrangement can achieve a higher current flow capacity.

[0127] Embodiments of this disclosure also provide an electronic device comprising a load RL and power supply systems 1, 1a, 1b and 1c of the foregoing embodiments, wherein power supply systems 1, 1a, 1b and 1c are used to supply power to the load RL.

[0128] In summary, this disclosure provides a power supply system and electronic device, wherein the output capacitor of the power supply system is surface-mounted on the second side of the system board, and the load is disposed on the first side of the system board. This results in a very short connection path between the output capacitor and the load, i.e., the connection path between the output capacitor and the load is only the wiring within the system board connecting the output capacitor and the load. Consequently, the connection impedance between the output capacitor and the load is also low, thereby improving the power supply performance of the power unit. Therefore, the overall performance of the power supply system of this disclosure is also improved. Furthermore, since each output capacitor is disposed in a corresponding receiving slot on the substrate, and the output capacitor is located between the corresponding positive output conducting area and the corresponding negative output conducting area, the current on the output capacitor can flow evenly to the positive output terminal and the negative output terminal. This makes the current sharing effect between the positive output conducting area constituting the positive output terminal and the negative output conducting area constituting the negative output terminal very significant.

Claims

1. A power supply system, characterized in that, The power supply system is used to supply power to a load, and the power supply system includes: A system board includes a first surface and a second surface disposed opposite to each other, wherein the load is disposed on the first surface; A substrate includes a first surface and a second surface disposed opposite to each other, wherein the first surface of the substrate is located between the second surface of the system board and the second surface of the substrate; At least one output capacitor is surface-mounted on the second side of the system board; At least one positive output conducting area is disposed on the first side of the substrate and connected to the second side of the system board, and is electrically connected to one end of the at least one output capacitor via wiring in the system board; At least one negative output conducting area is disposed on the first side of the substrate and connected to the second side of the system board, and is electrically connected to the other end of the at least one output capacitor via wiring in the system board. as well as At least one power unit is disposed on the second side of the substrate and is electrically connected to the at least one positive output conducting area and the at least one negative output conducting area via wiring in the substrate.

2. The power supply system as described in claim 1, characterized in that, At least one of the power units includes at least one positive output pin and at least one negative output pin, wherein the at least one positive output pin is electrically connected to the at least one positive output conductive area through wiring in the substrate, and the at least one negative output pin is electrically connected to the at least one negative output conductive area through wiring in the substrate.

3. The power supply system as described in claim 1, characterized in that, The at least one positive output conducting area is a plurality of positive output conducting areas, the at least one negative output conducting area is a plurality of negative output conducting areas, and the plurality of positive output conducting areas and the plurality of negative output conducting areas are arranged alternately. There is a corresponding negative output conducting area between every two positive output conducting areas, and there is a corresponding positive output conducting area between every two negative output conducting areas, wherein each output capacitor is disposed between the corresponding positive output conducting area and the corresponding negative output conducting area.

4. The power supply system as described in claim 1, characterized in that, The at least one positive output conducting region is a plurality of positive output conducting regions, and the at least one negative output conducting region is a plurality of negative output conducting regions, wherein there are two corresponding positive output conducting regions between every two adjacent negative output conducting regions.

5. The power supply system as described in claim 1, characterized in that, The at least one positive output conducting region is a plurality of positive output conducting regions, and the at least one negative output conducting region is a plurality of negative output conducting regions, wherein there are at least two corresponding negative output conducting regions between two adjacent positive output conducting regions.

6. The power supply system as described in claim 1, characterized in that, The at least one positive output conducting region is a plurality of positive output conducting regions, the at least one negative output conducting region is a plurality of negative output conducting regions, and at least two conducting regions are provided between two adjacent output capacitors along the first direction, and the polarity of the at least two conducting regions is the same.

7. The power supply system as described in claim 1, characterized in that, The at least one positive output conducting region is a plurality of positive output conducting regions, the at least one negative output conducting region is a plurality of negative output conducting regions, and at least three conducting regions are provided between two adjacent output capacitors along the first direction, and the polarity of the conducting regions adjacent to the two output capacitors is different.

8. The power supply system as described in claim 1, characterized in that, The at least one positive output conducting region is a plurality of positive output conducting regions, the at least one negative output conducting region is a plurality of negative output conducting regions, and there are two output capacitors adjacent to each other along the second direction. The conducting regions located on the same side of the two output capacitors and adjacent to the two output capacitors have the same polarity.

9. The power supply system as described in claim 1, characterized in that, The at least one positive output conducting region is a plurality of positive output conducting regions, the at least one negative output conducting region is a plurality of negative output conducting regions, and there are two output capacitors adjacent to each other along the second direction. The polarities of the conducting regions located on the same side of the two output capacitors and adjacent to the two output capacitors are different.

10. The power supply system as described in claim 1, characterized in that, The second side of the system board has multiple pads with the same pad structure as the first side of the substrate; The first side of the system board has a plurality of pads with the same pad structure as the load, or the first side of the system board has a plurality of pads with the same pad structure as the second side of the system board.

11. The power supply system as described in claim 1, characterized in that, The first surface of the substrate is attached to the second surface of the system board. The substrate also includes at least one first receiving groove, which is formed by the indentation of the first surface of the substrate. Each of the first receiving grooves is disposed between the corresponding positive output conducting area and the corresponding negative output conducting area to accommodate the corresponding output capacitor. Each of the output capacitors is located between the corresponding positive output conducting area and the corresponding negative output conducting area.

12. The power supply system as described in claim 11, characterized in that, The volume of each of the first receiving slots is greater than the volume of the corresponding output capacitor.

13. The power supply system as described in claim 1, characterized in that, The power supply system also includes two positive input conductive areas and two negative input conductive areas. The two positive input conductive areas are disposed on the first surface of the substrate and electrically connected to the corresponding power unit via wiring in the substrate. The two positive input conductive areas are respectively adjacent to a first sidewall and a second sidewall of the substrate. The at least one positive output conductive area and the at least one negative output conductive area are respectively located between the two positive input conductive areas. The two negative input conductive areas are disposed on the first surface of the substrate and electrically connected to the corresponding power unit via wiring in the substrate. The two negative input conductive areas are respectively adjacent to a third sidewall and a fourth sidewall of the substrate. The at least one positive output conductive area and the at least one negative output conductive area are respectively located between the two negative input conductive areas.

14. The power supply system as described in claim 13, characterized in that, The first surface of the substrate includes a plurality of second receiving grooves and a plurality of third receiving grooves. The plurality of second receiving grooves penetrate the third sidewall and the fourth sidewall of the substrate. A portion of the second receiving grooves is located between the at least one positive output conducting area and the corresponding positive input conducting area, and another portion of the second receiving grooves is located between the at least one negative output conducting area and the corresponding positive input conducting area. The plurality of third receiving grooves penetrate the third sidewall and the fourth sidewall of the substrate. A portion of the third receiving grooves divides each positive output conducting area into a plurality of sub-positive output conducting areas. The plurality of sub-positive output conducting areas are arranged sequentially and spaced apart. The arrangement direction of the plurality of sub-positive output conducting areas is the same as that of the first surface of the substrate. The third receiving groove, in the direction of the first sidewall facing the second sidewall, divides each negative output conducting area into multiple sub-negative output conducting areas. These multiple sub-negative output conducting areas are arranged sequentially and spaced apart. The arrangement direction of these multiple sub-negative output conducting areas is the same as the direction of the first sidewall facing the second sidewall of the substrate. The third receiving groove, in the direction of the first sidewall facing the second sidewall of the substrate, divides each negative input conducting area into multiple sub-negative input conducting areas. These multiple sub-negative input conducting areas are arranged sequentially and spaced apart. The arrangement direction of these multiple sub-negative input conducting areas is the same as the direction of the first sidewall facing the second sidewall of the substrate. The multiple second receiving grooves and the multiple third receiving grooves are respectively used to accommodate the corresponding output capacitors.

15. The power supply system as described in claim 14, characterized in that, The first surface of the substrate includes a plurality of fourth receiving slots, which divide each positive input conducting area into a plurality of sub-positive input conducting areas. The plurality of sub-positive input conducting areas are arranged sequentially and spaced apart. The arrangement direction of the plurality of sub-positive input conducting areas is the same as the direction of the third sidewall of the substrate toward the fourth sidewall. The plurality of fourth receiving slots are used to accommodate the corresponding output capacitors.

16. The power supply system as described in claim 1, characterized in that, The shape of each positive output conductive area and the shape of each negative output conductive area are respectively a circle or a square.

17. The power supply system as described in claim 1, characterized in that, The second surface of the substrate further includes a controller pad, a plurality of input capacitor pads, and at least one power unit pad. The controller pad is in contact with a controller of the power supply system so that the controller is electrically coupled to the substrate via the controller pad. Each input capacitor pad is in contact with an input capacitor of the power supply system so that the input capacitor is electrically coupled to the substrate via the corresponding input capacitor pad. The at least one power unit pad is in contact with the power unit so that the power unit is electrically coupled to the substrate via the corresponding power unit pad. Each power unit pad includes at least one signal pin, at least one input pin, at least one output pin, and at least one ground pin. The at least one signal pin is disposed on one of the four sides of the corresponding power unit pad away from a center point of the substrate.

18. The power supply system as described in claim 17, characterized in that, The power supply system further includes at least one positive input conductive area and at least one negative input conductive area. The substrate also includes a plurality of connection holes, each of which penetrates the first surface and the second surface of the substrate. The position of one end of each connection hole corresponds to the at least one input pin, the at least one output pin, or the at least one ground pin. The position of the other end of each connection hole corresponds to the at least one positive input conductive area, the at least one positive output conductive area, the at least one negative input conductive area, or the at least one negative output conductive area. The at least one input pin is connected to the at least one positive input conductive area via the corresponding connection hole, the at least one output pin is connected to the at least one positive output conductive area via the corresponding connection hole, and the at least one ground pin is connected to the at least one negative input conductive area or the at least one negative output conductive area via the corresponding connection hole.

19. The power supply system as described in claim 17, characterized in that, The power supply system further includes at least one positive input conductive area and at least one negative input conductive area. The substrate also includes a plurality of copper pillars, each copper pillar being embedded between the first surface and the second surface of the substrate. The position of one end of each copper pillar corresponds to the at least one input pin, the at least one output pin, or the at least one ground pin. The position of the other end of each copper pillar corresponds to the at least one positive input conductive area, the at least one positive output conductive area, the at least one negative input conductive area, or the at least one negative output conductive area. The at least one input pin is connected to the at least one positive input conductive area via the corresponding copper pillar, the at least one output pin is connected to the at least one positive output conductive area via the corresponding copper pillar, and the at least one ground pin is connected to the at least one negative input conductive area or the at least one negative output conductive area via the corresponding copper pillar.

20. The power supply system as described in claim 17, characterized in that, Each power unit pad includes a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall, wherein the first sidewall is disposed opposite to the second sidewall, the third sidewall is disposed opposite to the fourth sidewall and located between the first sidewall and the second sidewall, wherein at least one signal pin is a plurality of signal pins, at least one output pin is a plurality of output pins, at least one ground pin is a plurality of ground pins, and at least one input pin is a plurality of input pins, wherein the plurality of signal pins are adjacent to the first sidewall and arranged in an orderly manner, the plurality of output pins are disposed at the center of the power unit pad, the plurality of ground pins and the plurality of input pins are arranged sequentially around the plurality of output pins, and some of the plurality of input pins are located between the corresponding signal pin and the corresponding output pin.

21. The power supply system as described in claim 17, characterized in that, The power unit pad includes a first sidewall, a second sidewall, a third sidewall, and a fourth sidewall. The first sidewall is disposed opposite to the second sidewall, and the third sidewall is disposed opposite to the fourth sidewall and located between the first sidewall and the second sidewall. At least one signal pin is a plurality of signal pins, at least one output pin is a plurality of output pins, at least one ground pin is a plurality of ground pins, and at least one input pin is a plurality of input pins. The plurality of signal pins are adjacent to the first sidewall and arranged in an arrangement, the plurality of ground pins are adjacent to the second sidewall and arranged in an arrangement, the plurality of input pins are arranged and located between the plurality of signal pins and the plurality of output pins, and the plurality of output pins are arranged and located between the plurality of input pins and the plurality of ground pins.

22. The power supply system as described in claim 1, characterized in that, The power supply system also includes at least one positive input conductive area and at least one negative input conductive area. The power supply system includes multiple conductive structures, one end of each conductive structure is connected to the second surface of the system board, and the other end of each conductive structure is connected to the corresponding conductive area among the at least one positive input conductive area, the at least one positive output conductive area, the at least one negative input conductive area, or the at least one negative output conductive area. A receiving groove is defined between each conductive structure, an adjacent conductive structure, the first surface of the substrate, and the second surface of the system board. The receiving groove is used to accommodate the corresponding output capacitor.

23. The power supply system as described in claim 22, characterized in that, Each of these conductive structures consists of a conductive pillar or a solder ball.

24. The power supply system as described in claim 1, characterized in that, The power supply system also includes a controller disposed on the second side of the substrate and electrically connected to the at least one power unit via wiring in the substrate. The controller is used to control the operating state of at least one switching element in the corresponding power unit.

25. The power supply system as described in claim 1, characterized in that, The power supply system also includes an input capacitor, at least a portion of which is disposed on the second side of the substrate; The at least one power unit is a plurality of power units, and the plurality of power units are arranged in a plurality of rows. The plurality of rows are arranged sequentially, and each of the plurality of rows contains the same number of power units. The plurality of rows are spaced apart from at least a portion of the input capacitor.

26. The power supply system as described in claim 1, characterized in that, The power supply system also includes an input capacitor, and each power unit includes a switching element and an inductor, wherein the switching element and the inductor are packaged as a single integral structure. In this power supply system, part of the input capacitor is integrated into the at least one power unit.

27. The power supply system as described in claim 1, characterized in that, The load is a processor chip, which may include a CPU, GPU, TPU, or NPU.

28. An electronic device, characterized in that, The electronic device includes a load and a power supply system as described in any one of claims 1 to 27, wherein the power supply system is used to supply power to the load.

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