Current sensing circuit and corresponding DC-DC converter

Abstract

Embodiments of the present disclosure relate to current sensing circuitry and corresponding DC-DC converters. A power switch current sensing circuit includes matched first and second transistors having sources connected to first and second terminals of a power switch, respectively. A current mirror has a first node coupled to a drain of the first transistor and a second node coupled to a drain of the second transistor. The current mirror draws a current from the first node equal to a current flowing through the second transistor. Bias circuitry provides a same bias voltage to control terminals of the first and second transistors. An output resistance is coupled between the first node and a reference voltage node. A difference between a current flowing through the first transistor and a current drawn by the current mirror circuit from the first node flows through the output resistance. An output voltage generated at the first node is representative of a current flowing through the power switch.

Description

[0001] Priority requirements

[0002] This application claims priority to Italian Patent Application No. 102021000026927, filed on October 20, 2021, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This specification relates to current sensing circuits that can be used, for example, in DC-DC converters. Background Technology

[0004] The operation of certain DC-DC converters known in the art relies on current control algorithms (e.g., peak current control or valley current control). To implement the current control algorithm, current sensing circuitry is typically provided in the DC-DC converter to sense and reproduce the waveform of the current flowing through the converter's power switches.

[0005] like Figure 1 As shown, the current I flowing through the power switch of the converter SW It typically has a trapezoidal waveform (i.e., each current pulse includes a steep rising edge RE, a linear portion LP that can be increased or decreased, and a steep falling edge FE). Therefore, due to the high-frequency components of the current signal, accurate sensing of current I is possible. SW This can be challenging. In particular, if the current sensing circuit has a limited bandwidth, the current signal I... SW The edges RE and FE may be difficult to sense (e.g., track).

[0006] Certain current sensing circuits with wide bandwidth are known in the art. However, those solutions may be affected by one or more drawbacks, such as high quiescent current consumption, large silicon area occupation, and / or inability to sense bidirectional current (i.e., inability to sense both positive and negative currents in the same branch).

[0007] Therefore, there is a need in the art for an improved current sensing circuit with a wide bandwidth, the purpose of which is to mitigate (e.g., overcome) one or more drawbacks of known solutions. Summary of the Invention

[0008] One or more embodiments may relate to a circuit.

[0009] One or more embodiments may relate to a corresponding DC-DC converter.

[0010] In one or more embodiments, a first transistor has a source terminal configured to be selectively coupled to a first terminal of an electronic power transistor switch, and a second transistor has a source terminal configured to be selectively coupled to a second terminal of the electronic power transistor switch. The second transistor has the same dimensions as the first transistor. A current mirror circuit is coupled between a first node and a second node. The drain terminal of the first transistor is connected to the first node, and the drain terminal of the second transistor is connected to the second node. The current mirror circuit is configured to draw a current from the first node equal to the current flowing through the second transistor. A bias circuit is coupled to the first transistor and the second transistor and is configured to provide the same bias voltage to the control terminals of the first transistor and the second transistor. An output resistor is coupled between the first node and a reference voltage node such that the difference between the current flowing through the first transistor and the current drawn from the first node by the current mirror circuit flows through the output resistor and generates an output voltage signal at the first node indicating the current flowing through the electronic power transistor switch.

[0011] Therefore, one or more embodiments help to accurately sense the current flowing through a power switch with a wide bandwidth.

[0012] In one or more embodiments, the current generator circuit can be arranged to inject an offset current into the output resistor. This can thus generate a positive offset in the output voltage signal.

[0013] In one or more embodiments, a first switch and a first resistive element may be connected in series between the source terminal of the first transistor and the first terminal of the electronic power transistor switch. A second switch and a second resistive element may be connected in series between the source terminal of the second transistor and the second terminal of the electronic power transistor switch. The first switch may be controllable, closing in response to the electronic power transistor switch being turned on and opening in response to the electronic power transistor switch being de-turned on. The dimensions of the first switch, the second switch, the first resistive element, the second resistive element, and the current mirror circuit may be designed such that when the current flowing through the electronic power transistor switch is zero, the amount of current flowing through the first transistor and the second transistor is the same.

[0014] In one or more embodiments, when in the closed state, the first switch and the second switch may have the same conductivity; the first resistive element and the second resistive element may have the same resistance value; and the current mirror circuit may have a 1:1 mirror ratio.

[0015] In one or more embodiments, the resistance values ​​of the first resistive element and the second resistive element may be greater than the reciprocal of the transconductance values ​​of the first transistor and the second transistor, optionally at least 10 times greater, optionally at least 20 times greater.

[0016] In one or more embodiments, the bias circuit may include a third transistor arranged in a cross-diode (i.e., diode-connected) configuration and in series with a bias current generator. The bias circuit may include a third switch and a third resistive element arranged in series between the source terminal of the third transistor and a second terminal of an electronic power transistor switch. The control terminal of the third transistor may be coupled to the control terminals of the first transistor and the second transistor.

[0017] In one or more embodiments, the third transistor may have the same dimensions as the first transistor. When in the closed state, the first, second, and third switches may have the same conductivity. The first, second, and third resistive elements may have the same resistance value.

[0018] In one or more embodiments, a fourth switch may be arranged between the second terminal of the electronic power transistor switch and the node between the first switch and the first resistive element. The fourth switch may be controlled to close in response to the electronic power transistor switch being de-conducting and to open in response to the electronic power transistor switch being on.

[0019] In one or more embodiments, the current mirror circuit may include an enhancement-mode cascode current mirror circuit. A first mirror transistor may have a drain terminal coupled to a first node. A second mirror transistor may be arranged in series with the first mirror transistor and may have a drain terminal coupled to the source terminal of the first mirror transistor. A third mirror transistor may have a drain terminal coupled to a second node. A fourth mirror transistor may be arranged in series with the third mirror transistor and may have a drain terminal coupled to the source terminal of the third mirror transistor. The gate terminal of the first mirror transistor may be connected to the gate terminal of the third mirror transistor, the gate terminal of the second mirror transistor may be connected to the gate terminal of the fourth mirror transistor, and the gate terminal of the fourth mirror transistor may be connected to the second node.

[0020] In one or more embodiments, the enhanced cascode current mirror circuit may include a first mirror resistor series coupled to a second mirror transistor and a second mirror resistor series coupled to a fourth mirror transistor. The first and second mirror resistors may optionally have the same resistance value.

[0021] In one or more embodiments, the bias current generator may include a cascode current generator that includes a tracking transistor arranged in a trans-diode configuration and has a gate terminal connected to the gate terminals of a first mirror transistor and a third mirror transistor.

[0022] In one or more embodiments, the DC-DC converter may include an electronic power transistor switch disposed between the input node and the output node of the converter. A current sensing circuit according to one or more embodiments may be coupled to the electronic power transistor switch of the converter. Control circuitry of the converter may be configured to operate the electronic power transistor switch, coupling the source terminal of a first transistor to a first terminal of the electronic power transistor switch in response to the electronic power transistor switch being turned on, and decoupling the source terminal of the first transistor from the first terminal of the electronic power transistor switch in response to the electronic power transistor switch being de-turned on.

[0023] In one or more embodiments, the control circuit may also be configured to couple the source terminal of the first transistor to a second terminal of the electronic power transistor switch in response to the electronic power transistor switch being de-converted, and to decouple the source terminal of the first transistor from the second terminal of the electronic power transistor switch in response to the electronic power transistor switch being converted. Attached Figure Description

[0024] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, in which:

[0025] Figure 1 It is a timing diagram showing the waveform of the current flowing through the power switch of the DC-DC converter, and has been described above;

[0026] Figure 2 This is an exemplary circuit diagram of a DC-DC converter and a current sensing circuit configured to sense the current flowing through the high-side switch of the converter.

[0027] Figure 3 This is an exemplary circuit diagram of a DC-DC converter and a current sensing circuit configured to sense the current flowing through a low-side switch of the converter.

[0028] Figure 4 It represents the current waveform flowing through the power switch of the DC-DC converter and the current waveform generated by the DC-DC converter. Figure 2 or Figure 3 The timing diagram of the output signal generated by the current sensing circuit shown;

[0029] Figure 5 It is a timing diagram showing the waveform of the current flowing through the load of a DC-DC converter operating in continuous conduction mode (CCM);

[0030] Figure 6 This is an exemplary circuit diagram of a current sensing circuit configured to sense the current flowing through the high-side switch of a DC-DC converter.

[0031] Figure 7This is an exemplary circuit diagram showing the implementation details of the high-side current sensing circuit;

[0032] Figure 8 This is an exemplary circuit diagram of a current sensing circuit configured to sense the current flowing through the low-side switch of a DC-DC converter.

[0033] Figure 9 It represents the waveform of the current flowing through the power switch of the DC-DC converter, derived from... Figure 2 or Figure 3 The output signal generated by the current sensing circuit shown, and the signal generated by the current sensing circuit according to Figure 6 Timing diagram comparing the output signals generated by the -8 current sensing circuit; and

[0034] Figure 10 It represents the current waveform flowing through the power switch of a DC-DC converter operating in continuous conduction mode, by... Figure 2 or Figure 3 The output signal generated by the current sensing circuit shown and the signal generated by the current sensing circuit according to Figure 6 Timing diagram showing the comparison between the output signals generated by the current sensing circuit of -8. Detailed Implementation

[0035] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments described herein. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure certain aspects of the embodiments.

[0036] References to "an embodiment" or "an embodiment" within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment" that may appear at one or more points in this specification do not necessarily refer to the same embodiment. Furthermore, in one or more embodiments, a particular configuration, structure, or feature may be combined in any suitable manner.

[0037] The headings / references used herein are provided for convenience only and are not intended to limit the scope of protection or the scope of the embodiments.

[0038] In the accompanying drawings, unless the context otherwise requires, the same parts or elements are indicated by the same reference numerals / numbers, and for the sake of brevity, the corresponding descriptions will not be repeated.

[0039] Through the detailed description of the exemplary embodiments, one can first refer to Figure 2 , Figure 2This is an example of a DC-DC boost converter 10 and an associated current sensing circuit 20, which is configured to sense the current flowing through the high-side switch of the converter 10.

[0040] Converter 10 includes components configured to receive input DC voltage V IN The input node 102 of the converter 10 is used. An inductor L (e.g., an inductor) is arranged between the input node 102 and the intermediate node 104 of the converter 10. A high-side switch HS (e.g., a p-channel power MOS transistor) is arranged between the intermediate node 104 and the output node 106 of the converter 10. A low-side switch LS (e.g., an n-channel power MOS transistor) is arranged at the intermediate node 104 and provides a reference voltage V. GND (For example, 0V) between the reference or ground node 108 of converter 10. Current I HS The current I flows through the high-side switch HS. LS Flow through the low-side switch LS. Capacitor ( Figure 2 (Not visible in the image) can be coupled between output node 106 and reference node 108 to operate converter 10. The high-side switch HS and low-side switch LS are controlled by the control unit of converter 10 (…). Figure 2 (Not visible in the image) Control is performed according to a known control scheme, so that an output DC voltage V is generated at output node 106. OUT .

[0041] The current sensing circuit 20 relies on a replication-based architecture with a closed loop to sense the time-varying current I flowing through the high-side switch HS of the converter 10. HSThe waveform is described. Specifically, the current sensing circuit 20 includes a replica HSR of a high-side switch HS coupled between node 104 (e.g., at the drain terminal of the replica power MOS transistor HSR) and the inverting input of an operational amplifier 202, such as an error amplifier (e.g., at the source terminal of the replica transistor HSR). The replica switch HSR is controlled by the same control signal received by the high-side switch HS: the gate terminals of transistors HS and HSR can be coupled to each other. The non-inverting input of operational amplifier 202 is coupled downstream of the high-side switch HS (e.g., coupled to the source terminal of transistor HS). The output signal of operational amplifier 202 controls the conductivity of a first transistor M1, for example, which is coupled to the gate terminal of an n-channel MOS transistor M1. A first current mirror circuit is arranged between the replica switch HSR, the source terminal of transistor M1, and the reference node 108. Specifically, the first current mirror circuit includes an n-channel MOS transistor M2 and an n-channel MOS transistor M3. The n-channel MOS transistor M2 has a drain terminal coupled to the inverting input of the operational amplifier 202 and a source terminal coupled to the reference node 108. The n-channel MOS transistor M3 has a drain terminal coupled to the source terminal of transistor M1 and a source terminal coupled to the reference node 108. The gate terminals of transistors M2 and M3 are connected to each other and to the drain terminal of transistor M3, such that the current flowing through transistors M1 and M3 is mirrored to flow through transistor M2. The second current mirror circuit is arranged between the drain terminal of transistor M1, the output node 110 of the current sensing circuit 20, and the output node 106 of the converter 10. Specifically, the second current mirror circuit includes p-channel MOS transistors M4 and M5. P-channel MOS transistor M4 has a drain terminal coupled to the drain terminal of transistor M1 and a source terminal coupled to output node 106. P-channel MOS transistor M5 has a drain terminal coupled to output node 110 and a source terminal coupled to output node 106. The gate terminals of transistors M4 and M5 are connected to each other and to the drain terminal of transistor M4, such that the current flowing through transistors M1 and M4 is mirrored to flow through transistor M5. Resistive element R... S Coupled between the output node 110 and the reference node 108 of the current sensing circuit 20, so that current flows through transistor M5 and resistor R. S The current generates a voltage V at output node 110. SENSE It indicates the current I flowing through the high-side switch HS of converter 10. HS .

[0042] This can also be used as an introduction for reference. Figure 3 , Figure 3 This is a circuit diagram example of a DC-DC boost converter 10 and an associated current sensing circuit 30, which is configured to sense the current flowing through the low-side switch of the converter 10.

[0043] Converter 10 is basically the same as the reference Figure 2 The same components are described and include the same HS, LS, L and capacitors coupled to output node 106.

[0044] The current sensing circuit 30 relies on a replication-based architecture with a closed loop to sense the time-varying current I flowing through the low-side switch LS of the converter 10. LS The waveform. Specifically, the current sensing circuit 30 includes a replica LSR of the low-side switch LS, coupled between node 108 (e.g., at the source terminal of the replica power MOS transistor LSR) and the inverting input of an operational amplifier 302, such as an error amplifier (e.g., at the drain terminal of the replica transistor LSR). The replica switch LSR is controlled by the same control signal as the low-side switch LS: although only for illustrative purposes... Figure 3 While not visible in the diagram, the gate terminals of transistors LS and LSR can be coupled to each other. The non-inverting input of operational amplifier 302 is coupled upstream of the low-side switch LS (e.g., coupled to the drain terminal of transistor LS). The output signal of operational amplifier 302 controls the conductivity of the first transistor M1, for example, which is coupled to the gate terminal of the n-channel MOS transistor M1. The source terminal of transistor M1 is coupled to the inverting input of operational amplifier 302. A current mirror circuit including transistors M4 and M5 is arranged between the drain terminal of transistor M1, the output node 110 of current sensing circuit 30, and the output node 106 of converter 10, as shown in reference [reference missing]. Figure 2 As described above. Similarly, the resistive element R S Coupled between the output node 110 and the reference node 108 of the current sensing circuit 30, so that current flows through transistor M5 and resistor R S The current generates a voltage V at output node 110. SENSE It indicates the current I flowing through the low-side switch LS of converter 10. LS .

[0045] Figure 2 and Figure 3 The current sensing circuits 20 and 30 illustrated below may have one or more disadvantages discussed below.

[0046] The first drawback is that the bandwidth of such a current sensing circuit may be limited in order to provide the necessary closed-loop stability. This could lead to issues such as... Figure 4 The distortion of the sensed trapezoidal current waveform illustrated in the example. Figure 4 This illustrates the current (I) flowing through the high-side or low-side switch of converter 10. HS Or I LS The waveform of ) and the output signal V generated by the current sensing circuit 20 or 30 SENSEThe timing diagram shows the comparison between them. Due to bandwidth limitations, the output signal V... SENSE ( Figure 4 The solid line in the figure can be relative to the actual current waveform I. HS Or I LS ( Figure 4 The dashed lines in the image are essentially smoothed, resulting in poor accuracy in current sensing.

[0047] To increase the bandwidth of the current sensing circuit 20 or 30, the operational amplifier and the replica branch can be biased with a large current. However, this approach may lead to a second drawback: the high quiescent current consumption may not meet the design constraints of low-power DC-DC converters and / or efficiency requirements under light loads.

[0048] The third drawback is that the current sensing circuit 20 or 30 requires an operational amplifier, a duplicate switch (e.g., a duplicate transistor), and a duplicate branch, which results in a high silicon area footprint.

[0049] The fourth drawback is that the current sensing circuit 20 or 30 can only sense positive current flowing from node 104 to output node 106 (high-side sensing) or to reference node 108 (low-side sensing). It cannot sense reverse (negative) current flowing from output node 106 (high-side sensing) or from reference node 108 (low-side sensing) to node 104, resulting in accuracy loss for the DC-DC converter operating in forced continuous conduction mode (CCM), where current reversal occurs under light load. Figure 5 This illustrates the time period T. CK Undetected load current I in light load CCM LOAD A portion of the timing diagram: positive region 51 was correctly sensed, while negative region 52 was not sensed.

[0050] Therefore, one or more embodiments may provide different current sensing architectures (e.g., for applications in DC-DC converters) with the aim of mitigating one or more of the aforementioned disadvantages.

[0051] Figure 6 This is an exemplary circuit diagram of certain components of the DC-DC boost converter 10 (e.g., see the high-side switch HS arranged between nodes 104 and 106) and an associated current sensing circuit 60 configured to sense the current flowing through the high-side switch HS of the converter 10. Other components of the converter 10 (e.g., the low-side switch LS, the inductor L, and the output capacitor) can be substantially as shown in the reference diagram. Figure 2 The arrangement is as discussed, and is not included for ease of illustration only. Figure 6 As shown in the image.

[0052] The current sensing circuit 60 includes a sensing circuit 62 (e.g., the "core" of the sensing portion) and a biasing circuit 64 (e.g., a reference branch). The sensing circuit 62 is configured to sense the current I flowing through the high-side switch HS. HS And an indicator current I is generated at the corresponding output node 620. HS voltage signal V SENSE The bias circuit 64 is configured to generate a fixed bias voltage for the sensing circuit 62, as described below.

[0053] Sensing circuit 62 includes a first transistor P1 (e.g., a p-channel MOS transistor) having a source terminal selectively coupled to node 104 (e.g., coupled to the drain terminal of transistor HS). For example, sensing circuit 62 may include a first resistor R1 (e.g., a resistor) coupled between the source terminal of transistor P1 and a first terminal of switch SW1a. A second terminal of switch SW1a may be coupled to node 104. Additionally, sensing circuit 62 may include a second switch SW1b disposed between resistor R1 and output node 106, such that the source terminal of transistor P1 is selectively coupled to output node 106 (e.g., coupled to the source terminal of transistor HS).

[0054] Sensing circuit 62 includes a second transistor P2 (e.g., a p-channel MOS transistor) having a source terminal that can be coupled to output node 106 (e.g., coupled to the source terminal of transistor HS). For example, sensing circuit 62 may include a second resistor R2 (e.g., a resistor) coupled between the source terminal of transistor P2 and the first terminal of switch SW2. The second terminal of switch SW2 can be coupled to output node 106. The gate terminals of transistors P1 and P2 can be coupled to each other to receive the same bias voltage.

[0055] Sensing circuit 62 includes a current mirror circuit 66 disposed between the drain terminals of transistors P1 and P2 and reference node 108. Specifically, current mirror circuit 66 may include n-channel MOS transistors 662 and 664, the drain terminal of n-channel MOS transistor 662 being coupled to the drain terminal of transistor P1 (i.e., at node 620) and the source terminal being coupled to reference node 108, and the drain terminal of n-channel MOS transistor 664 being coupled to the drain terminal of transistor P2 and the source terminal being coupled to reference node 108. The gate terminals of transistors 662 and 664 are connected to each other and to the drain terminal of transistor 664 (e.g., to the drain terminal of transistor P2). It should also be noted that the current mirror described herein is a simple example of possible implementations, and any suitable current mirror architecture of any type can be implemented in current mirror circuit 66.

[0056] In one or more embodiments, the dimensions of switches SW1a, SW1b, SW2, resistors R1, R2, transistors P1, P22, and current mirror 66 are designed to match such that when no current flows through the high-side switch HS (e.g., because the high-side switch HS is open), the same amount of current flows in both branches of the sensing circuit 62 (i.e., the same current flows through transistors P1 and P2). For example, in one or more embodiments, switches SW1a, SW1b, and SW2 may be substantially equal and may have the same resistance value when closed; resistors R1 and R2 may be substantially equal and may have the same resistance value R. IN The current mirror 66 can have a 1:1 mirror factor. Alternatively, resistors R1 and R2 can be different (e.g., their resistance ratio is equal to N), and the current mirror 66 can have a 1:N mirror factor to compensate for the different values ​​of R1 and R2. Other combinations of the resistance values ​​of switches SW1a, SW1b, and SW2, as well as the resistance values ​​of resistors R1 and R2 and the mirror factor of the current mirror 66, are also possible, provided that the two branches of the sensing circuit 62 are matched such that transistor 662 is configured to draw a current from node 620 equal to the current flowing through transistor P2.

[0057] Additionally, the sensing circuit 62 includes an output resistor R coupled between node 620 and reference node 108. OUT (For example, a resistor). Therefore, the current generated by the difference between the current flowing through transistor P1 and the current absorbed by transistor 662 is forced to flow through resistor R. OUT And generate output signal V SENSE The sensing circuit 62 may additionally include a finely tuned current generator 68, which is coupled between the power rail (e.g., node 106) and node 620 and configured to generate current I. TRIM Injected into node 620 (and therefore through resistor R) OUT Therefore, the current generator 68 can output signal V. SENSE The offset voltage V is generated in OS =I TRIM 〃R OUT .

[0058] Bias circuit 64 is configured to generate a fixed bias voltage for the (gate) terminals of transistors P1 and P2. Specifically, bias circuit 64 may include a third transistor P3 (e.g., a p-channel MOS transistor) having a source terminal that can be coupled to output node 106 (e.g., coupled to the source terminal of transistor HS). For example, bias circuit 64 may include a third resistor R3 (e.g., a resistor) coupled between the source terminal of transistor P3 and a first terminal of switch SW3. A second terminal of switch SW3 may be coupled to output node 106. The gate terminal of transistor P3 may be coupled to the gate terminals of transistors P1 and P2 and to the drain terminal of transistor P3 (i.e., P3 may be configured as a trans-diode). Bias circuit 64 may include a current generator circuit 642 disposed between the drain terminal of transistor P3 and reference node 108. The current generator circuit 642 can be configured to set a fixed current I1 flowing through transistor P3, such that switch SW3, resistor R3, transistor P3, and circuit 642 are connected at output node 106 (where the voltage is fixed at V). OUT (at point) and reference node 108 (where the voltage is fixed at V) GND The series arrangement between transistors P1 and P2 generates the gate voltages (e.g., bias voltages) of transistors P1 and P2.

[0059] In such Figure 6 In one or more of the illustrated embodiments, resistor R3 can be substantially equal to resistors R1 and R2, and therefore can have a resistance value R. IN Switch SW3 can be substantially equal to switches SW1a and SW2, and can have the same resistance value when closed. In this configuration, when no current flows through the high-side switch HS, the current flowing through transistors P1 and P2 can be equal to I1. Alternatively, the dimensions of transistor P3 and resistor R3 can differ from those of transistors P1 and P2 and resistors R1 and R2. For example, when R3 > R1 and R3 > R2, the current flowing through transistors P1 and P2 can be higher than I1.

[0060] Switches SW1a and SW1b can be controlled by the control circuit of converter 10. Figure 6 The control circuit (not visible in the middle) also controls the operation of the high-side switch HS. Therefore, when the high-side switch HS is closed (e.g., on) and the current I... HS When current flows through switch SW1a, switch SW1a can be closed and switch SW1b can be opened, thereby generating a voltage drop V between node 104 and node 106. DS HSConversely, when the high-side switch HS is open (e.g., off), switch SW1a can be open while switch SW1b can be closed. Switches SW2 and SW3 can remain permanently closed so that the high-side switch HS is open (and a zero output signal V is correctly generated). SENSE =V OS The sensing circuit 62 is also powered at this time. The dimensions of switches SW2 and SW3 can be designed to improve the matching of the current flow lines (or branches) of transistors P1, P2, and P3.

[0061] In essence, the sensing circuit 62 operates as an equivalent differential input stage comprising a series arrangement of P1, R1 and P2, R2. The equivalent transconductance g seen from node 104... m EQ It can be calculated as g m EQ =(1 / g m P +R IN ) -1 , where g m P It is the transconductance of transistors P1 and P2, R IN These are the resistance values ​​of resistors R1 and R2. In one or more embodiments, the value R... IN It can be much greater than 1 / g m P (For example, through design) so that g m EQ ≈1 / R IN (For example, R) IN >10*1 / g m P Switches SW2 and SW3 can remain permanently closed (e.g., their control terminals can be open), providing good matching between the two branches of sensing circuit 62 and bias circuit 64. As a result of this good matching, when the voltage drop V across the high-side switch HS... DS HS When I is zero (i.e., when I is zero) HS When I = 0, the same current I UP The current flows through two branches of the sensing circuit 62. Depending on the embodiment, the current I... UP It can be equal to or different from the current I1.

[0062] Therefore, in one or more embodiments, when the high-side switch HS is in the on state, switch SW1a can be closed and switch SW1b can be open, causing current I... UP Flow through transistor P1, where I UP It can be calculated as follows:

[0063]

[0064] Therefore, at voltage V SENSE Depends on voltage V DS HS In this case, the output signal V at node 620 SENSE It can indicate the current I flowing through the high-side switch HS. HS :

[0065] V SENSE =I TRIM ·R OUT +(I UP -I1)·R OUT

[0066]

[0067] in:

[0068] V Os =I TRIM ·R OUT

[0069]

[0070] Therefore, the output voltage V SENSE It is a fine-tuning offset (V) OS Add a voltage V amplified by a constant gain G. DS HS The sum. Within the range where gain G is the ratio between two resistors of the same type, gain G can also be independent of process, rotation angle, and temperature variations.

[0071] When the high-side switch HS is in a non-conducting state (e.g., open), switch SW1a can be open and switch SW1b can be closed, causing current I... UP and output voltage V SENSE It can have the following values:

[0072] I UP =I1

[0073] V SENSE =I TRIM ·R OUT =V OS

[0074] In one or more embodiments, an offset voltage V is generated. OS The finely tuned current generator 68 provides dynamic settings for the output branch of the current mirror circuit 66, thus promoting the operation of the current mirror circuit 66 as a proper current mirror.

[0075] In addition, by appropriately setting the offset voltage V OSThe value, and one or more embodiments, can also sense the negative current in the high-side switch HS (i.e., the current flowing from node 106 to node 104). This is possible as long as the output voltage V... SENSE If the value is higher than the minimum voltage (e.g., a lower threshold) that allows the output branch of the current mirror circuit 66 to saturate (e.g., transistor 662 to saturate), then a negative current I can be executed. HS Correct sensing.

[0076] Figure 7 This is an exemplary circuit diagram showing possible implementation details of the current sensing circuit 60. Specifically, Figure 7 Details of the current mirror circuit 66 and the bias circuit 64 are illustrated.

[0077] like Figure 7 As shown, in one or more embodiments, the current mirror circuit 66 may include an enhanced (or improved) cascode current mirror. An n-channel MOS transistor 662a has a drain terminal coupled to the drain terminal of transistor P1 (i.e., at node 620) and a source terminal coupled to the drain terminal of another n-channel MOS transistor 662b. A resistor 666 (e.g., a resistor) is coupled between the source terminal of transistor 662b and reference node 108. An n-channel MOS transistor 664a has a drain terminal coupled to the drain terminal of transistor P2 and a source terminal coupled to the drain terminal of another n-channel MOS transistor 664b. A resistor 668 (e.g., a resistor) is coupled between the source terminal of transistor 664b and reference node 108. Resistors 666 and 668 may be equal. The gate terminals of transistors 662a and 664a are connected to each other. The gate terminals of transistors 662b and 664b are connected to each other and to the drain terminal of transistor 664a (i.e., to the drain terminal of transistor P2). Furthermore, the dimensions of the current mirror 66 and components P1, P2, R1, R2, SW1a, SW1b, and SW2 can be determined to provide two matched branches in the sensing circuit 62, such that the current mirror 66 is configured to draw a current from node 620 equal to the current flowing through transistor P2. The current mirror circuit 66 is implemented as follows: Figure 7 The illustrated enhanced cascode current mirror can help reduce the voltage V. SENSE The error of the current mirror and / or the output voltage V SENSE The dynamic ground extension. Additionally, resistors 666 and 668 used to degrade the current mirror can improve current mirror matching and further reduce the voltage V. SENSE The current mirror error is a function of .

[0078] like Figure 7As shown, in one or more embodiments, bias circuit 64 may include a common-source, common-gate bias circuit. Transistor 702 in a diode configuration (e.g., an n-channel MOS transistor) has a drain terminal and a gate terminal coupled to the gate terminals of transistors 662a and 664a. Resistor 704, matching (e.g., equal to) resistors 666 and 668, is coupled between the source terminal of transistor 702 and reference node 108. A common-source, common-gate current mirror is coupled to the drain terminal of transistor 702 to force current through transistor 702. Specifically, the common-source, common-gate current mirror includes a p-channel MOS transistor 706 having a drain terminal coupled to the drain terminal of transistor 702 and a source terminal coupled to the drain terminal of another p-channel MOS transistor 708. The source terminal of transistor 708 is coupled to a power supply voltage rail (e.g., node 106). The cascode current mirror includes a p-channel MOS transistor 710, which has a source terminal coupled to a power supply voltage rail and a drain terminal coupled to the source terminal of another p-channel MOS transistor 712. The gate terminals of transistors 708 and 710 are coupled to each other and to the drain terminal of transistor 710. The gate terminals of transistors 706 and 712 are coupled to each other and to the drain terminal of transistor 712. A cascode bias circuit can be configured to reduce mirroring error by setting the same drain-source voltage to transistors 708 and 710.

[0079] like Figure 7 As shown, the current generator circuit 714 is configured to generate current I IN The drain terminal of the n-channel transistor 716 in the trans-diode configuration is injected. The n-channel transistor 718 has a gate terminal coupled to the gate terminal of transistor 716 and is arranged in series with transistors 710 and 712, such that current I... IN Mirrored by transistors 710, 712, and 718, and then further mirrored by transistors 706 and 708. n-channel transistor 720 has a gate terminal coupled to the gate terminal of transistor 716 and is arranged in series with transistor P3, such that current I... IN The transistors 720 and P3 are mirrored. Additional n-channel transistors 722 and 724 can be series-coupled to transistors 718 and 720, respectively. Figure 7 In the configuration shown, the transistor 702, which is connected in series with the resistor 704, helps to track the rotation angle and temperature changes of the current mirror 66.

[0080] Those skilled in the art will understand that the references herein are discussed only by way of non-limiting examples. Figure 7 The specific arrangement of the disclosed bias circuit 64 is as long as it is one of many possible implementations of the bias circuit suitable for operating the current sensing circuit 60.

[0081] The above discussion Figure 6 and Figure 7 This is an example of one or more embodiments configured to sense the current flowing through the high-side switch HS of the DC-DC converter 10. Other embodiments may be configured to sense the current flowing through the low-side switch LS of the DC-DC converter 10 by employing a complementary architecture, such as... Figure 8 exemplified in .

[0082] Figure 8 This is an exemplary circuit diagram of certain components of the DC-DC boost converter 10 (e.g., see the low-side switch LS arranged between nodes 104 and 108 and the inductor L arranged between nodes 102 and 104) and an associated current sensing circuit 80 configured to sense the current flowing through the low-side switch LS of the converter 10. Other components of the converter 10 (e.g., the high-side switch HS and the output capacitor) can be substantially as shown in the reference diagram. Figure 2 The arrangement is as discussed, and is not included for ease of illustration only. Figure 8 As shown in the figure. Those skilled in the art will understand that, Figure 8 The circuit 80 in the example is basically the same as Figure 6 The circuit 60 in the example is complementary and operates according to the same principle; however, circuit 80 will be described below.

[0083] The current sensing circuit 80 includes a sensing circuit 82 (e.g., the "core" of the sensing portion) and a biasing circuit 84 (e.g., a reference branch). The sensing circuit 82 is configured to sense the current I flowing through the low-side switch LS. LS And an indicator current I is generated at the corresponding output node 820. LS voltage signal V SENSE The bias circuit 84 is configured to generate a fixed bias voltage for the sensing circuit 82, as described below.

[0084] Sensing circuit 82 includes a first transistor N1 (e.g., an n-channel MOS transistor) having a source terminal selectively coupled to node 104 (e.g., coupled to the drain terminal of transistor LS). For example, sensing circuit 82 may include a first resistor R1 (e.g., a resistor) coupled between the source terminal of transistor N1 and a first terminal of switch SW1a. A second terminal of switch SW1a may be coupled to node 104. Additionally, sensing circuit 82 may include a second switch SW1b disposed between resistor R1 and reference node 108, such that the source terminal of transistor N1 is selectively coupled to reference node 108 (e.g., coupled to the source terminal of transistor LS).

[0085] Sensing circuit 82 includes a second transistor N2 (e.g., an n-channel MOS transistor) having a source terminal that can be coupled to reference node 108 (e.g., coupled to the source terminal of transistor LS). For example, sensing circuit 82 may include a second resistor R2 (e.g., a resistor) coupled between the source terminal of transistor N2 and the first terminal of switch SW2. The second terminal of switch SW2 may be coupled to reference node 108. The gate terminals of transistors N1 and N2 may be coupled to each other to receive the same bias voltage.

[0086] Sensing circuit 82 includes a current mirror circuit 86 disposed between the drain terminals of transistors N1 and N2 and a power supply voltage node (e.g., node 106, or the chip input power supply node, or the regulated voltage generated therefrom). Specifically, current mirror circuit 86 may include p-channel MOS transistors 862 and 864, p-channel MOS transistor 862 having a drain terminal coupled to the drain terminal of transistor N1 (i.e., at node 820) and a source terminal coupled to the power supply voltage node, and p-channel MOS transistor 864 having a drain terminal coupled to the drain terminal of transistor N2 and a source terminal coupled to the power supply voltage node. The gate terminals of transistors 862 and 864 are connected to each other and to the drain terminal of transistor 864 (e.g., to the drain terminal of transistor N2). It should also be noted that the current mirror described herein is a simple example of possible implementations, and any suitable current mirror architecture of any type can be implemented in current mirror circuit 86.

[0087] As previously referenced Figure 6 In one or more embodiments, the dimensions of switches SW1a, SW1b, SW2, resistors R1, R2, transistors N1, N2, and current mirror 86 are determined to be matched such that when no current flows through the low-side switch LS (e.g., because the low-side switch LS is open), the same amount of current flows in both branches of the sensing circuit 82 (i.e., the same current flows through transistors N1 and N2). For example, in one or more embodiments, switches SW1a, SW1b, and SW2 may be substantially equal and may have the same resistance value when closed; resistors R1 and R2 may be substantially equal and may have the same resistance value R. INThe current mirror 86 can have a 1:1 mirror factor. Alternatively, resistors R1 and R2 can be different (e.g., their resistance ratio is equal to N) and the current mirror 86 can have a 1:N mirror factor to compensate for the different values ​​of R1 and R2. Other combinations of the resistance values ​​of switches SW1a, SW1b, and SW2, the resistance values ​​of resistors R1 and R2, and the resistance values ​​of the mirror factor of the current mirror 86 are also possible, provided that the two branches of the sensing circuit 82 are matched such that transistor 862 is configured to inject a current equal to the current flowing through transistor N2 into node 820.

[0088] Additionally, the sensing circuit 82 includes an output resistor R coupled between node 820 and reference node 108. OUT (For example, a resistor). Therefore, the current generated by the difference between the current injected by transistor 862 and the current flowing through transistor N1 is forced to flow through resistor R. OUT And generate output signal V SENSE The sensing circuit 82 may additionally include a finely tuned current generator 88, which is coupled between the power rail and node 820 and configured to generate current I. TRIM Injected into node 820 (and therefore through resistor R) OUT Therefore, the current generator 88 can output signal V. SENSE The offset voltage V is generated in OS =I TRIM 〃R OUT .

[0089] Bias circuit 84 is configured to generate a fixed bias voltage for the (gate) terminals of transistors N1 and N2. Specifically, bias circuit 84 may include a third transistor N3 (e.g., an n-channel MOS transistor) whose source terminal may be coupled to reference node 108 (e.g., coupled to the source terminal of transistor LS). For example, bias circuit 84 may include a third resistor R3 (e.g., a resistor) coupled between the source terminal of transistor N3 and the first terminal of switch SW3. The second terminal of switch SW3 may be coupled to reference node 108. The gate terminal of transistor N3 may be coupled to the gate terminals of transistors N1 and N2 and to the drain terminal of transistor N3 (i.e., N3 may be configured as a trans-diode). Bias circuit 84 may include a current generator circuit 842 disposed between the drain terminal of transistor N3 and a power supply voltage node. The current generator circuit 842 can be configured to set a fixed current I1 flowing through transistor N3, such that circuit 842, transistor N3, resistor R3, and switch SW3 are connected at the supply voltage node and reference node 108 (where the voltage is fixed at V). GND The series arrangement between the transistors generates the gate voltages (e.g., bias voltages) of transistors N1 and N2.

[0090] In such Figure 8 In one or more of the illustrated embodiments, resistor R3 can be substantially equal to resistors R1 and R2, and therefore can have a resistance value R. IN Switch SW3 can be substantially equal to switches SW1a and SW2, and can have the same resistance value when closed. In this configuration, when no current flows through the low-side switch LS, the current flowing through transistors N1 and N2 can be equal to I1. Alternatively, the dimensions of transistor N3 and resistor R3 can differ from those of transistors N1 and N2 and resistors R1 and R2. For example, when R3 > R1 and R3 > R2, the current flowing through transistors N1 and N2 can be higher than I1.

[0091] Switches SW1a and SW1b can be controlled by the control circuit of converter 10. Figure 7 (Not visible in the middle) This control circuit also controls the operation of the low-side switch LS. Therefore, when the low-side switch LS is closed (e.g., on) and the current I... LS When current flows through switch SW1a, switch SW1a can be closed and switch SW1b can be opened, thereby generating a voltage drop V between node 104 and node 108. DS LS Conversely, when the low-side switch LS is open (e.g., off), switch SW1a can be open and switch SW1b can be closed. Switches SW2 and SW3 can remain permanently closed so that the low-side switch LS is open (and a zero output signal V is correctly generated). SENSE =V OS The sensing circuit 82 is also powered at this time. The dimensions of switches SW2 and SW3 can be designed to improve the matching of the current flow lines (or branches) of transistors N1, N2, and N3.

[0092] In essence, the sensing circuit 82 operates as an equivalent differential input stage comprising a series arrangement of N1, R1 and N2, R2. The equivalent transconductance g seen from node 104... m EQ It can be calculated as g m EQ =(1 / g m N +R IN )-1, where g m N It is the transconductance of transistors N1 and N2, R IN These are the resistance values ​​of resistors R1 and R2. In one or more embodiments, the value R... IN It can be much greater than 1 / g m N (For example, through design) so that g m EQ ≈1 / R IN(For example, R) IN >10*1 / g m N Switches SW2 and SW3 can remain permanently closed (e.g., their control terminals can be open), providing good matching between the two branches of the sensing circuit 82 and the bias circuit 84. As a result of this good matching, when the voltage drop V across the low-side switch LS... DS LS When I is zero (i.e., when I is zero) LS When I = 0, the same current I DOWN The current flows through two branches of the sensing circuit 82. Depending on the embodiment, the current I... DOWN It can be equal to or different from the current I1.

[0093] Therefore, in one or more embodiments, when the low-side switch LS is in the on state, switch SW1a can be closed and switch SW1b can be open, causing current I... DOWN Flow through transistor N1, where I DOWN It can be calculated as:

[0094]

[0095] Therefore, at voltage V SENSE Depends on voltage V DS LS In this case, the output signal V at node 820 SENSE It can indicate the current I flowing through the low-side switch LS. LS :

[0096] V SENSE =I TRIM ·R OUT +(I1-I DOWN )·R OUT

[0097]

[0098] in:

[0099] V OS =I TRIM ·R OUT

[0100]

[0101] Therefore, the output voltage V SENSE It is a fine-tuning offset (V) OS Add a voltage V amplified by a constant gain G. DS LSThe sum. When the gain G is the ratio between two resistors of the same type, the gain G can also be independent of process, rotation angle and temperature variations.

[0102] When the low-voltage side switch LS is in a non-conducting state (e.g., open), switch SW1a can be opened and switch SW1b can be closed, allowing current I to flow. DOWN and output voltage V SENSE It can have the following values:

[0103] I DOWN =I1

[0104] V SENSE =I TRIM ·R OUT =V OS

[0105] In one or more embodiments, a generation offset voltage V is provided. OS The dynamic output of the branch of the current mirror circuit 86 is set by the fine-tuning current generator 88, thus promoting the operation of the current mirror circuit 86 as a proper current mirror.

[0106] In addition, by appropriately setting the offset voltage V OS The value of V, one or more embodiments can also sense the negative current in the low-side switch LS (i.e., the current flowing from node 108 to node 104). This is possible as long as the output voltage V SENSE If the value is higher than the minimum voltage (e.g., a lower threshold) that allows the output branch of the current mirror circuit 86 to saturate (e.g., transistor 862 to saturate), then a negative current I can be executed. LS Correct sensing.

[0107] Therefore, one or more embodiments illustrated herein rely on an open-loop current sensing structure that does not impose limitations on loop stability. As a result, the bandwidth of the current sensing circuit is not limited by design constraints and is limited, at least in the first approximation, by parasitic capacitance at the nodes (only).

[0108] One or more embodiments can advantageously provide an open-loop current sensing structure with a bandwidth unconstrained by design limitations, and a bandwidth greater than that achievable with known closed-loop structures. Tracking of the voltage drop (VDS) across the high-side switch HS and / or the low-side switch LS can be more accurate, thereby facilitating more accurate tracking of the waveform of the current flowing in the power switches of the DC-DC converter. Figure 9 It is the current I flowing through the (high-side or low-side) switch. SW Examples of waveforms (dashed lines), current sensed by a conventional closed-loop structure (dotted-dash lines), and current sensed by one or more embodiments disclosed herein (solid lines).

[0109] One or more embodiments can advantageously facilitate sensing current flowing in the power switch in both directions, and thus can prove accurate in the CCM under light load conditions where negative current needs to be sensed. Figure 10 The current I flowing through the switch (dashed line) (high-side or low-side) under specific conditions of CCM operation. SW For example Figure 2 -3 The current sensed by the closed-loop structure (dotted line) in Figure 3, and by Figure 6 Example of the waveform of the current sensed in one or more embodiments shown in Figure 8 (solid line).

[0110] One or more embodiments can advantageously operate at a lower bias current than that required by closed-loop structures known in the art, where large bandwidth can only be achieved by means of a significant bias current. Therefore, one or more embodiments can provide lower quiescent current consumption.

[0111] One or more embodiments may result in a lower silicon footprint compared to structures known in the art, provided they do not require dedicated error amplifier circuitry and replication branches.

[0112] It should be noted that one or more embodiments of the current sensing circuit disclosed herein are applicable not only to boost DC-DC converters, but generally to any DC-DC converter topology (e.g., boost, buck, buck-boost, etc.). More generally, it will be understood that one or more embodiments of the current sensing circuit are disclosed herein by way of non-limiting example only, referring to possible applications of the current sensing circuit in DC-DC converters. The current sensing circuit according to one or more embodiments can be applied to any application that must accurately sense time-varying current waveforms (e.g., Class D amplifiers or overcurrent protection circuits).

[0113] Additionally, it should be noted that one or more embodiments have been disclosed herein with reference to CMOS technology. It should be understood that one or more embodiments may alternatively rely on bipolar technology, such that any reference to the "source," "drain," and "gate" terminals of a "MOS" transistor can also be interpreted as the "emitter," "collector," and "base" terminals of a "BJT" transistor.

[0114] Without violating the basic principles and without departing from the scope of protection, the details and embodiments may vary significantly from what has been described by example only.

[0115] The claims form an integral part of the technical teachings provided herein regarding the embodiments.

[0116] The scope of protection is determined by the appended claims.

Claims

1. A current sensing circuit, comprising: The first transistor has a source terminal configured to be selectively coupled to a first terminal of an electronic power transistor switch via a first switch and a first resistor; The second transistor has a source terminal configured to be selectively coupled to a second terminal of the electronic power transistor switch via a second switch and a second resistor; The first transistor and the second transistor have the same dimensions; The first switch and the first resistor are coupled in series between the source terminal of the first transistor and the first terminal of the electronic power transistor switch; The second switch and the second resistor are coupled in series between the source terminal of the second transistor and the second terminal of the electronic power transistor switch; A current mirror circuit is coupled between a first node and a second node, wherein the drain terminal of the first transistor is connected to the first node and the drain terminal of the second transistor is connected to the second node, and the current mirror circuit is configured to absorb a current from the first node equal to the current flowing through the second transistor. A bias circuit, coupled to the first transistor and the second transistor, is configured to provide the same bias voltage to the control terminals of the first transistor and the second transistor; as well as An output resistor having a first terminal directly connected to the first node and a second terminal coupled to a reference voltage node; The output voltage signal at the first node indicates the current flowing through the electronic power transistor switch.

2. The current sensing circuit of claim 1, further comprising a current generator circuit configured to inject an offset current into the first node to generate a positive offset in the output voltage signal.

3. The current sensing circuit according to claim 1, wherein: The first switch can be controlled to close when the electronic power transistor switch is turned on, and to open when the electronic power transistor switch is not turned on; The dimensions of the first switch, the second switch, the first resistor, the second resistor, and the current mirror circuit are designed such that when the current flowing through the electronic power transistor switch is zero, the same amount of current flows through the first transistor and the second transistor.

4. The current sensing circuit according to claim 3, wherein: The first switch and the second switch have the same conductivity when they are in the closed state; The first resistor and the second resistor have the same resistance value; and The current mirror circuit has a 1:1 mirror ratio.

5. The current sensing circuit according to claim 3, wherein the same resistance value of the first resistor and the second resistor is a factor greater than the reciprocal of the same transconductance value of the first transistor and the second transistor.

6. The current sensing circuit according to claim 5, wherein the factor is at least 10.

7. The current sensing circuit according to claim 5, wherein the factor is at least 20.

8. The current sensing circuit according to claim 3, wherein the bias circuit comprises: The third transistor is in a cross-diode configuration and is arranged in series with the bias current generator; as well as A third switch and a third resistor are coupled in series between the source terminal of the third transistor and the second terminal of the electronic power transistor switch; and The control terminal of the third transistor is coupled to the control terminal of the first transistor and the control terminal of the second transistor.

9. The current sensing circuit according to claim 8, wherein: The third transistor has the same dimensions as the first transistor; The first switch, the second switch, and the third switch have the same conductivity when they are in the closed state. as well as The first resistor, the second resistor, and the third resistor have the same resistance value.

10. The current sensing circuit of claim 8, further comprising a fourth switch coupled between the second terminal of the electronic power transistor switch and a node between the first switch and the first resistor; The fourth switch is controlled to close when the electronic power transistor switch is not turned on, and to open when the electronic power transistor switch is turned on.

11. The current sensing circuit according to claim 8, wherein the current mirror circuit comprises: A first mirror transistor has a drain terminal coupled to the first node; The second mirror transistor is coupled in series to the first mirror transistor and has a drain terminal coupled to the source terminal of the first mirror transistor; The third mirror transistor has a drain terminal coupled to the second node; A fourth mirror transistor, connected in series to the third mirror transistor and having a drain terminal coupled to the source terminal of the third mirror transistor; The gate terminal of the first mirror transistor is connected to the gate terminal of the third mirror transistor, the gate terminal of the second mirror transistor is connected to the gate terminal of the fourth mirror transistor, and the gate terminal of the fourth mirror transistor is connected to the second node.

12. The current sensing circuit of claim 11, wherein the current mirror circuit further comprises a first mirror resistor connected in series to the second mirror transistor and a second mirror resistor connected in series to the fourth mirror transistor, the first mirror resistor and the second mirror resistor having the same resistance value.

13. The current sensing circuit of claim 11, wherein the bias current generator includes a cascode current generator, the cascode current generator including a tracking transistor arranged in a trans-diode configuration, and the cascode current generator having a gate terminal connected to the gate terminals of the first mirror transistor and the third mirror transistor.

14. The current sensing circuit of claim 1, further comprising a control circuit, the control circuit being configured to: Operate the electronic power transistor switch; In response to the electronic power transistor switch being turned on, the source terminal of the first transistor is coupled to the first terminal of the electronic power transistor switch; and In response to the electronic power transistor switch being de-energized, the source terminal of the first transistor is decoupled from the first terminal of the electronic power transistor switch.

15. The current sensing circuit of claim 14, wherein the control circuit is further configured to: In response to the electronic power transistor switch being de-energized, the source terminal of the first transistor is coupled to the second terminal of the electronic power transistor switch; and In response to the electronic power transistor switch being turned on, the source terminal of the first transistor is decoupled from the second terminal of the electronic power transistor switch.

16. A DC-DC converter, comprising: An electronic power transistor switch is coupled between the input node and the output node; The current sensing circuit according to claim 1 is coupled to the electronic power transistor switch; as well as The control circuit is configured as follows: Operate the electronic power transistor switch; In response to the electronic power transistor switch being turned on, the source terminal of the first transistor is coupled to the first terminal of the electronic power transistor switch through the first resistor; as well as In response to the electronic power transistor switch being de-energized, the source terminal of the first transistor is decoupled from the first terminal of the electronic power transistor switch.

17. The DC-DC converter of claim 16, wherein the control circuit is further configured to: In response to the electronic power transistor switch being de-conducted, the source terminal of the first transistor is coupled to the second terminal of the electronic power transistor switch via a first resistor; and In response to the electronic power transistor switch being turned on, the source terminal of the first transistor is decoupled from the second terminal of the electronic power transistor switch.

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