Sequence Detection Device and Sequence Detection Method

Abstract

The present invention provides a sequence detection device and a sequence detection method. The sequence detection device includes a decision feedback equalizer (DFE), a combinational circuit, a decision circuit, and a sequence detection circuit. The DFE is used to process symbol decision signals to generate a first equalized signal. The combinational circuit is used to combine a data signal and the first equalized signal to generate a sampling signal. The decision circuit is used to perform a hard decision on the sampling signal to generate a symbol decision signal. The sequence detection circuit is used to perform sequence detection on the data signal to generate and output a symbol sequence. For sequence detection, the sequence detection circuit selects branches for branch metric calculation at least according to the symbol decision signals. The present invention can reduce the computational complexity and power consumption of branch metric calculation by reducing the number of branches and only requiring a smaller number of branch metric calculations.

Description

Technical Field

[0001] The present invention relates to the field of data communication, and more particularly, to a sequence detection device using path - selective sequence detection and a related sequence detection method. Background Art

[0002] In high - speed data communication systems, existing filtering and equalization architectures may be insufficient to support challenging channels and next - generation Ethernet. For example, due to various factors such as noise, crosstalk, and inter - symbol interference (ISI), the detection of received signals in a data communication system is challenging. A typical feed - forward equalizer (FFE) can remove pre - cursor ISI and post - cursor ISI by using information from adjacent symbols. However, since a typical FFE does not use any noise - free estimated symbols (e.g., noise - free sliced symbols), a typical FFE may enhance noise other than ISI. A typical decision - feedback equalizer (DFE) can remove post - cursor ISI by using one or more noise - free estimated previous symbols (e.g., one or more noise - free sliced previous symbols). However, due to dependence on previous decisions, a typical DFE may cause error propagation. Maximum likelihood sequence detection (MLSD) is a commonly used technique in addition to traditional FFE and DFE, which utilizes and further removes ISI to handle noise. However, MLSD has a higher level of implementation complexity as well as a higher level of power consumption and memory consumption. Therefore, there is a need for an innovative low - complexity and power - saving MLSD in a sequence detector. Summary of the Invention

[0003] In view of this, the present invention provides a sequence detection device for path - selective sequence detection and a related sequence detection method.

[0004] According to a first aspect of the present invention, an exemplary sequence detection device is disclosed. The exemplary sequence detection device includes a decision feedback equalizer (DFE), a combining circuit, a decision circuit, and a sequence detection circuit. The DFE is configured to process a symbol decision signal to generate a first equalized signal. The combining circuit is configured to combine a data signal and the first equalized signal to produce a sampled signal. The decision circuit is used to perform a hard decision on the sampled signal to generate a symbol decision signal. The sequence detection circuit is used to perform sequence detection on the data signal to generate and output a symbol sequence, wherein, for sequence detection, the sequence detection circuit selects branches at least according to the symbol decision signal to perform branch metric calculation.

[0005] According to a second aspect of the present invention, an exemplary sequence detection method is disclosed. The exemplary sequence detection method includes: performing decision feedback equalization on a symbol decision signal to generate a first equalized signal; combining a data signal and the first equalized signal to produce a sampled signal; performing a hard decision on the sampled signal to generate a symbol decision signal; performing sequence detection on the data signal to generate and output a symbol sequence, wherein the sequence detection includes selecting branches at least according to the symbol decision signal to perform branch metric calculation.

[0006] The sequence detection device and related sequence detection method proposed by the present invention can reduce the computational complexity and power consumption of branch metric calculation by reducing the number of branches and only requiring a smaller number of branch metric calculations.

[0007] After reading the following detailed description of the preferred embodiments illustrated in the various figures, these and other objects of the present invention will no doubt become apparent to those of ordinary skill in the art. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention can be more fully understood by combining the accompanying drawings and reading the subsequent detailed description and embodiments, wherein:

[0009] Figure 1 is a schematic diagram illustrating a sequence detection device using path-selective maximum likelihood sequence detection (MLSD) according to an embodiment of the present invention.

[0010] Figure 2 is a schematic diagram illustrating a trellis generated by a first branch reduction step according to an embodiment of the present invention.

[0011] Figure 3 is a schematic diagram illustrating a trellis generated by a second branch reduction step according to an embodiment of the present invention.

[0012] Figure 4It is a schematic diagram illustrating a grid generated by a third branch reduction step according to an embodiment of the present invention.

[0013] Figure 5 It is a schematic diagram illustrating grids obtained by using all the first branch reduction steps, second branch reduction steps, and third branch reduction steps under different combinations of consecutive symbols {d k-1 , d k} in a 4-level PAM signaling and 1-tap DFE system.

[0014] Figure 6 It is a schematic diagram illustrating a grid generated by a fourth branch reduction step according to an embodiment of the present invention.

[0015] Figure 7 It is a schematic diagram illustrating grids obtained by using all the first branch reduction steps, second branch reduction steps, third branch reduction steps, and fourth branch reduction steps under different combinations of consecutive symbols {d k-1 , d k} in a 4-level PAM signaling and 1-tap DFE system.

[0016] Figure 8 It is a schematic diagram illustrating a sequence detection device using path selection MLSD with dynamic switching according to an embodiment of the present invention.

[0017] Figure 9 It is a schematic diagram illustrating the distribution of samples transmitted via an AWGN channel. Detailed Description

[0018] Certain terms are used in the specification and claims to refer to particular components. Those of ordinary skill in the art should understand that electronic device manufacturers may use different names to refer to the same component. The specification and claims do not use the difference in names as a way to distinguish components, but use the difference in functions of components as the basis for distinction. The term "comprising" mentioned throughout the specification and the following claims is an open-ended term and should be interpreted as "including but not limited to". In addition, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if it is described in the text that the first device is electrically connected to the second device, it means that the first device can be directly connected to the second device, or indirectly connected to the second device through other devices or connection means.

[0019] Figure 1FIG. 0 is a schematic diagram illustrating a sequence detection apparatus using path-selective maximum likelihood sequence detection (MLSD) according to an embodiment of the present invention. The sequence detection apparatus 100 may be part of a receiver in a data communication system. In this embodiment, the sequence detection apparatus 100 is a digital circuit, including a feed-forward equalizer (FFE) 102, a decision-feedback equalizer (DFE) 104, a sequence detection circuit 106, a combinational circuit 108, and a decision circuit 110. The FFE 102 may be implemented by an m-tap FFE having m multipliers 112, (m−1) single-symbol delay elements 114, and (m−1) adders 116, where m FFE coefficients f1-f m (m≥1) are respectively applied to the m multipliers 112. However, this is only for illustration and does not mean a limitation to the present invention. In fact, the FFE 102 may adopt any suitable FFE structure. That is, the present invention has no limitation on the FFE design. The FFE 102 is configured to process the received signal S_IN to generate an equalized signal S_FFE as a data signal to be processed by sequence detection (e.g., path-selective MLSD). For example, a pulse-amplitude modulation (PAM) signal is generated by a transmitter of a data communication system and sent through a channel to a receiver of the data communication system, and the received signal S_IN is a digital signal derived from the PAM signal. Taking 4-level PAM signaling as an example, there are four symbols {−3, −1, +1, +3}, and each symbol corresponds to two bits. For example, four bit selections 00, 01, 11, and 10 may be respectively associated with the amplitudes of −3, −1, +1, and +3.

[0020] The DFE 104 is configured to process a symbol decision signal S_D to generate an equalized signal S_DFE. The DFE 104 may be implemented by an n-tap DFE having n multipliers 118, (n−1) single-symbol delay elements 120, and (n−1) adders 122, where n DFE coefficients h1-h n (n≥1) are respectively applied to the n multipliers 118. However, this is only for illustrative purposes and does not mean a limitation to the present invention. In fact, the DFE 104 may adopt any suitable DFE structure. That is, the present invention has no limitation on the DFE design.

[0021] The combinational circuit 108 is configured to combine a data signal (e.g., an equalized signal S_FFE obtained by equalizing the received signal S_IN) and an equalized signal S_DFE to generate a sample signal S_S. For example, the combinational circuit 108 can be implemented by a subtractor (which can be implemented by an adder configured to perform subtraction), and can be used to subtract the equalized signal S_DFE from the equalized signal S_FFE to generate the sample signal S_S. The decision circuit 110 performs a hard decision on the sample signal S_S to generate a symbol decision signal S_D. For example, the decision circuit 110 can be a slicer. In the case where the received signal S_IN is derived from 4-level PAM signaling, each of the equalized signals S_FFE, S_DFE, and the sample signal S_S carries soft data, while the symbol decision signal S_D carries hard data (i.e., the symbols decided by the slicer, and each symbol is decided as one of the four symbols {-3, -1, +1, +3}).

[0022] The sequence detection circuit 106 is configured to perform sequence detection on a data signal (e.g., the equalized signal S_FFE) to generate and output a symbol sequence S_OUT. For 4-level PAM signaling, the symbol sequence S_OUT is a symbol sequence in which each symbol is sequence-detected as one of the four symbols {-3, -1, +1, +3}. In this embodiment, the sequence detection circuit 106 is configured to employ the proposed path selection MLSD. For example, for sequence detection, the sequence detection circuit 106 is configured to select branches for branch metric (BM) calculation based at least on the symbol decision signal S_D. As Figure 1 shown, the sequence detection circuit 106 includes a dynamic path selection and BM calculation circuit 124, an add-compare-select (ACS) circuit 126, and a surviving path and trace-back circuit 128. Regarding the traditional MLSD using M-level pulse amplitude modulation in an n-tap DFE receiver structure, it requires M (n+1)Sub-branch metric calculation, where each branch metric includes the calculation of the Euclidean distance (squared). As M or n increases, its computational complexity and power consumption increase exponentially. To solve this problem, the dynamic path selection and BM calculation circuit 124 adopts the proposed branch reduction technique to provide a power-and-memory-saving structure. Further details of the branch reduction will be described below with reference to the accompanying drawings. The ACS circuit 126 is used to process the path metric (PM) accumulation. The survivor path and traceback circuit 126 is used to identify the symbol sequence using the traceback method based on the survivor path provided by the ACS circuit 126. It should be noted that the input to the dynamic path selection and BM calculation circuit 124 is the equalized signal S_FFE. Therefore, the BM calculation design and PM accumulation design adopted by the sequence detection circuit 106 are the same as those adopted by a typical sequence detector. Similar to a typical sequence detector using traditional MLSD, the sequence detection circuit 106 using the proposed path selection MLSD is configured to directly trace back the survivor path to output the symbol sequence S_OUT. Since the symbol sequence S_OUT output by the sequence detection circuit 106 is directly the symbol sequence, no further processing is required to convert the output of the sequence detection circuit 106 into a symbol sequence.

[0023] Since the present invention focuses on the proposed branch reduction technique adopted by the dynamic path selection and BM calculation circuit 124, those skilled in the art should easily understand the principle of the remaining operations performed by the sequence detection circuit 106. For the sake of brevity, the further description of the remaining operations performed by the sequence detection circuit 106 is omitted here.

[0024] The proposed branch reduction is achieved by relying on the symbol decision signal (e.g., slicer decision) S_D to select the main branches and deselect / ignore the non-important branches. Based on the symbol decision signal (e.g., slicer decision) S_D, some branches with extremely low probabilities can be removed. To better understand the proposed branch reduction scheme, it is assumed below that the received signal S_IN originates from a 4-level PAM signaling in an additive white Gaussian noise (AWGN) channel, the DFE 104 is implemented by a 1-tap DFE with h1 = 0.5 (worst case), and the signal-to-noise ratio (SNR) is 18 dB.

[0025] Figure 2FIG. 0 is a schematic diagram illustrating a trellis 200 generated by a first branch reduction step according to an embodiment of the present invention. According to 4-level PAM signaling, the original trellis should have four previous states 202, 204, 206, 208 at a previous time (k-1) and four subsequent states 212, 214, 216, 218 at a subsequent time k. The previous states 202, 204, 206, 208 correspond to symbols +3, +1, -1, -3 respectively. The subsequent states 212, 214, 216, 218 correspond to symbols +3, +1, -1, -3 respectively. In Figure 2 FIG. Figure 2 illustrates the probability of each branch from one previous state to one subsequent state. For example, for 4-level PAM signaling on an AWGN channel and SNR = 18 dB, the +1→-1 / +3 transition probability is 1.91x10 -4 , and the +1→-3 transition probability is 8.08x10 -27 .

[0026] Assume that the symbol decision signal S_D has consecutive symbols, and the consecutive symbols include a first symbol d corresponding to the previous trellis state 204 at the previous time (k-1) k-1 (d k-1 = +1) and a second symbol d corresponding to the subsequent trellis state 214 at the subsequent time k k (d k = +1). Regarding the BM calculation for the branches between the trellis states at the previous time (k-1) and the subsequent time k, the sequence detection circuit 106 (specifically, the dynamic path selection and BM calculation circuit 124 of the sequence detection circuit 106) can refer to the first symbol d k-1 to unselect specific branches starting from another previous trellis state at the previous time (k-1). As Figure 2 shown, the branches 220, 222, 224, 226 starting from the previous state 208 that is not adjacent to the previous state 204 (corresponding to the first symbol d k-1 ) have extremely low probabilities. Therefore, the first branch reduction step can remove all branches starting from the previous state 208 at the previous time (k-1) to generate a trellis 200 with a reduced number of branches.

[0027] Figure 3 FIG. is a schematic diagram illustrating a trellis 300 generated by a second branch reduction step according to an embodiment of the present invention. Figure 2 The trellis 200 shown in FIG. Figure 2 can be further processed for branch reduction. Regarding the BM calculation for the branches between the trellis states at the previous time (k-1) and the subsequent time k, the sequence detection circuit 106 (specifically, the dynamic path selection and BM calculation circuit 124 of the sequence detection circuit 106) refers to the second symbol d kEnd a particular branch that de-selects another subsequent trellis state at a subsequent time k. As Figure 3 shown. Branches 302, 304, 306 that end at a subsequent state 218 that is not adjacent to the subsequent state 214 (corresponding to the second symbol d k ) have a very low probability. Therefore, the second branch reduction step can remove all branches that end at the subsequent state 218 at the subsequent time k to generate a trellis 300 with a reduced number of branches.

[0028] Figure 4 FIG. is a schematic diagram illustrating a trellis 400 generated by a third branch reduction step according to an embodiment of the present invention. Figure 3 The trellis 300 shown in FIG. can be further processed for branch reduction. Since the DFE generates a specific error pattern, branches corresponding to non-existent error patterns can be further removed. Taking a 4-level PAM signaling and a 1-tap DFE system as an example, only an alternating error pattern of positive and negative should exist. If the hard data {d k-1 , d k} is {+1, +1}, then there should be no {-1, -1} and {+3, +3} branches because the corresponding error patterns {-2, -2} and {+2, +2} are not alternating positive and negative, where the first "-2" in the error pattern {-2, -2} is the difference between the symbol value -1 corresponding to the state 206 at time k-1 and the symbol value +1 corresponding to the state 204 at time k-1, and the second "-2" is the difference between the symbol value -1 corresponding to the state 216 at time k and the symbol value +1 corresponding to the state 214 at time k. The first "+2" in the error pattern {+2, +2} is the difference between the symbol value +3 corresponding to the state 202 at time k-1 and the symbol value +1 corresponding to the state 204 at time k-1, and the second "+2" is the difference between the symbol value +3 corresponding to the state 212 at time k and the symbol value +1 corresponding to the state 214 at time k. On the contrary, {-1, +3}, {-1, +1}, {+3, -1} and {+3, +1} are possible branches. Therefore, for the BM calculation of the branches between the trellis states at the previous time (k-1) and the subsequent time k, the sequence detection circuit 106 (especially the dynamic path selection and BM calculation circuit 124 of the sequence detection circuit 106) is configured to refer to the first symbol d k-1 (d k-1 = +1) and the second symbol d k (d k= +1), both to deselect at least one specific branch corresponding to at least one non - existent error pattern of the DFE 104. The third branch reduction step can remove one branch 402 starting from the previous state 202 and ending at the subsequent state 212, and further remove another branch 404 starting from the previous state 206 and ending at the subsequent state 216, generating a trellis 400 with a reduced number of branches.

[0029] Figure 5 is illustrated in a 4 - level PAM signaling and 1 - tap DFE system for different combinations of consecutive symbols {d k-1 , d k}, showing the trellises obtained by using all the first branch reduction step, the second branch reduction step, and the third branch reduction step. Compared with the traditional MLSD in a 1 - tap DFE receiver structure (which uses 4 - level PAM that requires 4 2 branch metric calculations), the proposed path - selection MLSD requires only a smaller number of branch metric calculations due to branch reduction.

[0030] As described above, the symbol decision signal S_D provides hard data that can be referenced by the sequence detection circuit 106 (specifically, the dynamic path selection and BM calculation circuit 124 of the sequence detection circuit 106) for branch reduction. However, this is for illustrative purposes only and does not imply a limitation of the present invention. In some embodiments of the present invention, the sequence detection circuit 106 (specifically, the dynamic path selection and BM calculation circuit 124 of the sequence detection circuit 106) can also reference additional signals for branch reduction. For example, the sequence detection circuit 106 (specifically, the dynamic path selection and BM calculation circuit 124 of the sequence detection circuit 106) is configured to select branches for branch metric calculation based on the symbol decision signal S_D (which carries the hard data output from the decision circuit 110) and the sampling signal S_S (which carries the soft data to be processed by the decision circuit 110). In addition to the first branch reduction step, the second branch reduction step, and the third branch reduction step that depend on the symbol decision signal S_D as described above, the sequence detection circuit 106 (specifically, the dynamic path selection and BM calculation circuit 124 of the sequence detection circuit 106) can also perform a fourth branch reduction step that depends on both the symbol decision signal S_D and the sampling signal S_S.

[0031] Figure 6 is a schematic diagram illustrating the trellis 602 / 604 generated by the fourth branch reduction step according to an embodiment of the present invention. Figure 4 The trellis 400 shown in can be further processed for branch reduction. The symbol decision signal S_D has consecutive symbols, including a first symbol (hard data) d corresponding to the previous trellis state 204 at the previous moment (k - 1) k-1 (d k-1= +1) and a second symbol (hard data) d corresponding to the subsequent trellis state 214 at a subsequent time k k (d k = +1). The sampled signal S_S has a sample (soft data) s k , from which the decision circuit (e.g., limiter) 110 decides the second symbol d k (d k = +1). Regarding the BM calculation for the branch between the trellis states at the previous time (k - 1) and the subsequent time k, the sequence detection circuit 106 (specifically, the dynamic path selection and BM calculation circuit 124 of the sequence detection circuit 106) is configured to refer to the sample (soft data) s k and the associated second symbol (hard data) d k , and deselect a specific branch from the previous state 204 (which corresponds to the first symbol d k-1 ) to another subsequent trellis state at the subsequent time k. In the case where the sample s k (e.g., s k = 1.1) is greater than the second symbol d k (d k = +1), the branch 608 can be removed, where the branch 608 starts from the previous state 204 and ends at the subsequent state 216, and the subsequent state 216 is adjacent to the subsequent state 214 and corresponds to a symbol {-1} less than the second symbol d k . In another case where the sample s k (e.g., s k = 0.1) is less than the second symbol d k (d k = +1), the branch 606 can be removed, where the branch 606 starts from the previous state 204 and ends at the subsequent state 212, and the subsequent state 212 is adjacent to the subsequent state 214 and corresponds to a symbol {+3} greater than the second symbol d k .

[0032] Figure 7 Illustrates the trellis obtained by using all the first branch reduction steps, second branch reduction steps, third branch reduction steps, and fourth branch reduction steps under different combinations of consecutive symbols {d k-1 , d k} in a 4 - level PAM signaling and 1 - tap DFE system. Figure 7 The dashed line shown in indicates a candidate branch that can be removed by the fourth branch reduction step. Compared with the traditional MLSD in a 1 - tap DFE receiver structure, where 4 - level PAM signaling requires the use of 4 2Compared with the conventional path selection MLSD (Maximum Likelihood Sequence Detection), the proposed path selection MLSD requires only a smaller number of branch metric calculations due to the reduced number of branches. Specifically, in an M-level PAM signaling of a 1-tap DFE (Decision Feedback Equalizer) system, the conventional MLSD requires M 2 branch metric calculations for each time stage associated with the previous time (k - 1) and the subsequent time k. The proposed path selection MLSD of the present invention requires an average of branch metric calculations for each time stage associated with the previous time (k - 1) and the subsequent time k, where the proposed path selection MLSD can achieve the same performance as the conventional MLSD. The power and area requirements of the proposed path selection MLSD can be reduced because the power and area requirements are positively correlated with the number of branches used. As Figure 7 shown, the trellis of the sequence detection circuit 106 can include only two or three previous states and can include only two or three subsequent states. Therefore, the ACS (Add-Compare-Select) circuit 126 can be enabled to employ 3-to-1 comparators and / or 2-to-1 comparators, where the 3-to-1 comparator / 2-to-1 comparator has a smaller comparator size compared to a 4-to-1 comparator. In addition, the trellis of the sequence detection circuit 106 can include N branches, where N is a positive integer not less than 2 and not greater than 6. Due to the smaller number of branches, the computational complexity and power consumption of the BM (Branch Metric) calculation can be reduced.

[0033] It should be noted that the above first branch reduction step, second branch reduction step, third branch reduction step, and fourth branch reduction step do not need to be executed sequentially. In practice, the order of the first branch reduction step, second branch reduction step, third branch reduction step, and fourth branch reduction step can be changed according to actual design considerations. These alternative designs all fall within the scope of the present invention.

[0034] If the proposed path selection MLSD is not always in operation but is only activated during certain periods, its power requirements can be further reduced. The present invention also proposes a path selection MLSD with dynamic switching. Figure 8FIG. 0 is a schematic diagram illustrating a sequence detection apparatus using path selection MLSD with dynamic switching according to an embodiment of the present invention. The sequence detection apparatus 800 may be part of a receiver in a data communication system, and it may be a digital circuit. The main difference between the sequence detection apparatuses 100 and 800 is that the sequence detection circuit 806 of the sequence detection apparatus 800 further includes a dynamic switching evaluation circuit 804. The dynamic switching evaluation circuit 804 is used to control the activation of the sequence detection circuit 806. If the sequence detection circuit 806 is activated by the dynamic switching evaluation circuit 804, the symbol sequence S_OUT is obtained from performing path selection MLSD on the equalized signal S_FFE. If the sequence detection circuit 806 is deactivated by the dynamic switching evaluation circuit 804, the sequence detection circuit 806 may bypass the symbol decision signal S_D (i.e., no MLSD is performed on the symbol decision signal S_D) and directly use it as the symbol sequence S_OUT.

[0035] The proposed path selection MLSD with dynamic switching can achieve the same performance as the always-on traditional MLSD. Specifically, the dynamic switching path selection MLSD greatly reduces power consumption, and the performance loss can be negligible.

[0036] In an exemplary design, the dynamic switching evaluation circuit 804 is configured to control the activation of the sequence detection circuit 806 according to the difference between the sampling signal S_S and the symbol decision signal S_D. The sampling signal S_S may carry a sample (soft data) s at each time instant i i , and the decision circuit 110 may perform a hard decision on the sample s i to generate a symbol (hard data) d at the same time instant i i . For example, the dynamic switching evaluation circuit 804 may compare the absolute difference between the sample s i and the symbol d i with a threshold TH to determine whether to activate or deactivate the sequence detection circuit 806. When the absolute difference |s i - d i | is greater than the threshold TH, this means that the sequence detection apparatus 800 is operating at a high error probability. Therefore, the dynamic switching evaluation circuit 804 may activate the sequence detection circuit 806 to generate the symbol sequence S_OUT through path selection MLSD. When the absolute difference |s i - d i | is not greater than the threshold TH, this means that the sequence detection apparatus 800 is operating at a low error probability. Therefore, the dynamic switching evaluation circuit 804 may deactivate the sequence detection circuit 806 to reduce power consumption and memory usage. Figure 9It is a schematic diagram showing the distribution of samples transmitted via an AWGN channel. For an AWGN channel, there is a one-to-one correspondence between the activation probability of the sequence detection circuit 806 and the threshold TH. For example, assume that the threshold TH is set to 0.8. If there is soft data located in the shaded area because |s i -d i | > 0.8, then the path selection MLSD should be activated. In short, the proposed path selection MLSD with dynamic switching can jointly optimize receiver performance and power efficiency.

[0037] In another exemplary design, the dynamic switching evaluation circuit 804 is configured to control the activation of the sequence detection circuit 806 according to one or more channel properties. For example, when the sequence detection device 800 operates under poor channel characteristics, the dynamic switching evaluation circuit 804 can activate the sequence detection circuit 806; when the sequence detection device 800 operates under good channel characteristics, the dynamic switching evaluation circuit 804 can deactivate the sequence detection circuit 806.

[0038] In yet another exemplary design, the dynamic switching evaluation circuit 804 is configured to control the activation of the sequence detection circuit 806 according to the FFE coefficient settings (e.g., Figure 1 the FFE coefficients f1 - f shown in m ) or the DFE coefficient settings (e.g., Figure 1 the DFE coefficients h1 - h shown in n ). The FFE / DFE coefficient settings can affect the number of branches not selected in the branch reduction operations performed at the dynamic path and BM calculation circuit 124. For example, the activation of the aforementioned fourth branch reduction step for removing an additional branch can depend on the FFE / DFE coefficient settings. Therefore, the dynamic switching evaluation circuit 804 can dynamically activate the sequence detection circuit 806 in response to the adaptively adjustable FFE / DFE coefficient settings.

[0039] Since MLSD is based on the Viterbi algorithm, the proposed path selection MLSD has error correction capabilities. For the sequence detection device 800, the dynamically activated path selection MLSD is a power-efficient function that provides adjustable error correction capabilities and can achieve the performance of the ideal MLSD in the best case.

[0040] It should be noted that the FFE 102 can be optional. For example, in some embodiments, Figure 1The illustrated sequence detection device 100 can be modified to omit the FFE 102 such that the received signal S_IN can serve as the aforementioned data signal fed to the sequence detection circuit 106 and the combining circuit 108. As another example, in some embodiments, Figure 8 The illustrated sequence detection device 800 can be modified to omit the FFE 102 such that the received signal S_IN can serve as the aforementioned data signal fed to the sequence detection circuit 806 and the combining circuit 108. These alternative designs all fall within the scope of the present invention.

[0041] Those skilled in the art will readily understand that many modifications and changes can be made to the devices and methods while retaining the teachings of the present invention. Accordingly, the foregoing disclosure should be construed as being limited only by the scope and bounds of the appended claims.

Claims

1. A sequence detection device, comprising: A decision feedback equalizer (DFE) for processing a symbol decision signal to generate a first equalized signal; A combining circuit for combining a data signal with the first equalized signal to generate a sampling signal; A decision circuit for performing a hard decision on the sampling signal to generate the symbol decision signal; And A sequence detection circuit for performing sequence detection on the data signal, generating and outputting a symbol sequence, wherein, with respect to the sequence detection, the sequence detection circuit is configured to select a branch for branch metric calculation at least according to the symbol decision signal.

2. The sequence detection device according to claim 1, further comprising: A feed-forward equalizer (FFE) for processing a received signal to generate a second equalized signal as the data signal.

3. The sequence detection device according to claim 1, wherein, The symbol decision signal includes consecutive symbols, the consecutive symbols including a first symbol corresponding to a previous trellis state at a previous time and a second symbol corresponding to a subsequent trellis state at a subsequent time. With respect to branch metric calculation for a branch between the trellis states at the previous time and the subsequent time, the sequence detection circuit is configured to refer to the first symbol to cancel the selection of a specific branch starting from another previous trellis state at the previous time.

4. The sequence detection device according to claim 3, wherein, The another previous trellis state at the previous time is not adjacent to the one previous trellis state corresponding to the first symbol at the previous time.

5. The sequence detection device according to claim 1, wherein, The symbol decision signal includes consecutive symbols, the consecutive symbols including a first symbol corresponding to a previous trellis state at a previous time and a second symbol corresponding to a subsequent trellis state at a subsequent time. With respect to branch metric calculation for a branch between the trellis states at the previous time and the subsequent time, the sequence detection circuit is configured to refer to the second symbol to cancel the selection of a specific branch ending at another subsequent trellis state at the subsequent time.

6. The sequence detection device according to claim 5, wherein, The another subsequent trellis state at the subsequent time is not adjacent to the one subsequent trellis state corresponding to the second symbol at the subsequent time.

7. The sequence detection device according to claim 1, wherein, The symbol decision signal includes consecutive symbols, the consecutive symbols including a first symbol corresponding to a previous trellis state at a previous time and a second symbol corresponding to a subsequent trellis state at a subsequent time. With respect to branch metric calculation for a branch between the trellis states at the previous time and the subsequent time, the sequence detection circuit is configured to refer to both the first symbol and the second symbol to cancel the selection of at least one specific branch corresponding to at least one non-existent error pattern of the DFE.

8. The sequence detection device according to claim 7, wherein, The at least one non-existent error pattern is a non-positive-negative alternating error pattern.

9. The sequence detection device according to claim 1, wherein, The sequence detection circuit is configured to select the branch for branch metric calculation according to the symbol decision signal and the sampling signal.

10. The sequence detection device according to claim 9, wherein, The symbol decision signal includes consecutive symbols, the consecutive symbols include a first symbol corresponding to a previous trellis state at a previous time and a second symbol corresponding to a subsequent trellis state at a subsequent time, the sampling signal includes samples at the subsequent time, the decision circuit makes a hard decision on the samples to determine the second symbol, and calculates a branch metric for a branch between the trellis states at the previous time and the subsequent time. The sequence detection circuit is configured to refer to the samples and the second symbol to de-select a specific branch starting from the previous trellis state at the previous time to another subsequent trellis state at the subsequent time.

11. The sequence detection device according to claim 10, wherein, Compare the magnitudes of the samples and the second symbol to determine the other subsequent trellis state at the subsequent time.

12. The sequence detection device according to claim 2, wherein, The received signal is derived from a pulse amplitude modulation (PAM) signal.

13. The sequence detection device according to claim 1, wherein, The sequence detection circuit is used to directly backtrace the surviving path to output the symbol sequence.

14. The sequence detection device according to claim 1, wherein, The trellis of the sequence detection circuit includes only two or three previous states.

15. The sequence detection device according to claim 1, wherein, The trellis of the sequence detection circuit includes only two or three subsequent states.

16. The sequence detection device according to claim 1, wherein, The trellis of the sequence detection circuit includes N branches, where N is a positive integer not less than 2 and not greater than 6.

17. The sequence detection device according to claim 1, further comprising: A dynamic switching evaluation circuit for controlling the activation of the sequence detection circuit.

18. The sequence detection device according to claim 17, wherein, The dynamic switching evaluation circuit is configured to control the activation of the sequence detection circuit according to at least one of the following: the difference between the sampling signal and the symbol decision signal, one or more channel characteristics, FFE coefficient settings, or DFE coefficient settings.

19. The sequence detection device according to claim 17, wherein, The dynamic switching evaluation circuit dynamically activates the sequence detection circuit to provide adjustable error correction capabilities.

20. A sequence detection method, comprising: Performing decision feedback equalization on a symbol decision signal to generate a first equalized signal; Combining a data signal and the first equalized signal to generate a sampling signal; Performing a hard decision on the sampling signal to generate the symbol decision signal; And Performing sequence detection on the data signal to generate and output a symbol sequence, where the sequence detection includes: Selecting at least a branch for branch metric calculation according to the symbol decision signal.

21. The sequence detection method according to claim 20, further comprising: Performing feed-forward equalization on a received signal to generate a second equalized signal as the data signal.

22. The sequence detection method according to claim 20, further comprising: Dynamically activating the sequence detection.

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