An SOT-MRAM and a manufacturing method thereof

Abstract

The application provides a SOT-MRAM and a manufacturing method thereof, the SOT-MRAM comprising a substrate, a plurality of memory cells arranged on the substrate. Each memory cell comprises a SOT layer deposited on the substrate, a magnetic tunnel junction arranged on the SOT layer. Further comprising an antiferromagnetic insulating layer at least wrapping around the side surface of the free layer in each magnetic tunnel junction, and the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current in the SOT layer. By adding the antiferromagnetic insulating layer at least wrapping around the side surface of the free layer in each magnetic tunnel junction, and further making the magnetic moment direction of the antiferromagnetic insulating layer parallel to the direction of the write current, an in-plane magnetic field can be provided for the free layer, for the field-free switching of the SOT-MRAM, solving the problem that the SOT-MRAM cannot be mass integrated due to the need to apply an external magnetic field during the writing process. And the added antiferromagnetic insulating layer is arranged around the magnetic tunnel junction, thereby also having the effect of protecting the magnetic tunnel junction from the surrounding environment.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a SOT-MRAM and its manufacturing method. Background Technology

[0002] Magnetic Random Access Memory (MRAM) is one of the most promising new memory technologies, with the potential to replace Dynamic Random Access Memory (DRAM) and Static Random Access Memory (SRAM). The core structure of MRAM is the Magnetic Tunnel Junction (MTJ), a sandwich structure consisting of two ferromagnetic layers and one tunneling layer. One of the ferromagnetic layers has its magnetization flipped by a current or magnetic field; this is called the free layer. The magnetization of the other layer remains constant; this is called the reference layer (fixed layer). When the magnetization directions of the free and reference layers are parallel, the MTJ is in a low-resistance state; when they are antiparallel, the MTJ is in a high-resistance state. These high and low resistance states can be used to store data "0" and "1". MRAM is classified into two types based on its read / write method: STT and SOT. SOT-MRAM has separate read and write paths, with a write time as low as 0.5 ns, outperforming STT-MRAM in terms of device reliability, stability, and read / write speed. However, a key challenge in SOT-MRAM applications is the need for an external magnetic field to determine its magnetization direction. Since external magnetic fields cannot be integrated into chips on a large scale, SOT-MRAM faces key technical challenges in practical applications.

[0003] To address the issue of SOT-MRAM flipping without an external magnetic field, academia and industry have proposed various alternative external magnetic field solutions. These mainly include inducing an in-plane magnetic anisotropy gradient, inducing an in-plane exchange magnetic field and dipole magnetic field through interfacial coupling of ferromagnetic or antiferromagnetic multilayer films, and growing another ferromagnetic layer on the other side of the free layer to provide an additional external magnetic field. However, creating an in-plane magnetic anisotropy gradient requires inducing structural or material composition non-uniformity in the free layer, making it unsuitable for large-scale integration. Inducing an external magnetic field through interfacial coupling of ferromagnetic or antiferromagnetic multilayer films requires close contact between the multilayer film and the SOT layer. Since the resistance of these multilayer films is much lower than that of the SOT layer, a large portion of the write current is diverted to these multilayer films, reducing the write efficiency of the SOT layer and increasing write power consumption. Furthermore, due to the insufficient in-plane magnetic anisotropy of these ferromagnetic multilayer films, these ferromagnetic layers themselves also face thermal stability issues. Therefore, this solution for SOT flipping without an external field suffers from low data stability and retention capabilities. Summary of the Invention

[0004] This invention provides a SOT-MRAM and its manufacturing method to solve the problem that SOT-MRAM cannot be integrated on a large scale because an external magnetic field needs to be applied during the writing process.

[0005] In a first aspect, the present invention provides a SOT-MRAM comprising a substrate and a plurality of memory cells disposed on the substrate. Each memory cell includes an SOT layer deposited on the substrate for transmitting write current, and a magnetic tunnel junction disposed on the SOT layer, wherein the magnetic tunnel junction includes: a free layer deposited on the SOT layer, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer. The SOT-MRAM further includes at least an antiferromagnetic insulating layer surrounding the sides of the free layer in each magnetic tunnel junction, and the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current in the SOT layer.

[0006] In the above-described scheme, by adding an antiferromagnetic insulating layer that surrounds the free layer side of each magnetic tunnel junction, and ensuring that the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current, an in-plane magnetic field can be provided to the free layer. This facilitates the external magnetic field-free switching of SOT-MRAM, thus solving the problem that SOT-MRAM cannot be mass-produced due to the need for an external magnetic field during the writing process. Furthermore, the added antiferromagnetic insulating layer, because it surrounds the magnetic tunnel junction, also protects the magnetic tunnel junction from the influence of the surrounding environment.

[0007] In one specific implementation, the antiferromagnetic insulating layer covers at least all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction. This increases the height of the antiferromagnetic insulating layer, reduces fabrication difficulty, and better protects the magnetic tunnel junction from environmental influences.

[0008] In one specific implementation, an antiferromagnetic insulating layer fills the space between adjacent magnetic tunnel junctions in multiple memory cells. This reduces fabrication complexity while better protecting the magnetic tunnel junctions from environmental influences.

[0009] In one specific embodiment, the antiferromagnetic insulating layer is made of any one of the following materials: oxide of CoFeB, CoOx, FeOx, NiOx, CrOx, MnOx, CoFe2O4, or a mixture or alloy of any of these materials.

[0010] In one specific implementation, the antiferromagnetic insulating layer surrounds the sides of each magnetic tunnel junction with a thickness of at least 0.5 nanometers to reduce manufacturing difficulty while ensuring that the in-plane magnetic field provided by the antiferromagnetic insulating layer is sufficiently stable and reliable.

[0011] Secondly, the present invention also provides a method for manufacturing SOT-MRAM, the method comprising:

[0012] Provide a substrate;

[0013] Multiple memory cells are disposed on a substrate, including: depositing multiple SOT layers on the substrate for passing write current; forming a magnetic tunnel junction on each SOT layer, wherein the magnetic tunnel junction includes: a free layer deposited on the SOT layer, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer;

[0014] An antiferromagnetic insulating layer is formed that surrounds at least the sides of the free layer in each magnetic tunnel junction;

[0015] Adjust the direction of the magnetic moment of the antiferromagnetic insulating layer so that it is parallel to the direction of the writing current.

[0016] In the above-described scheme, by adding an antiferromagnetic insulating layer that surrounds the free layer side of each magnetic tunnel junction, and ensuring that the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current, an in-plane magnetic field can be provided to the free layer. This facilitates the external magnetic field-free switching of SOT-MRAM, thus solving the problem that SOT-MRAM cannot be mass-produced due to the need for an external magnetic field during the writing process. Furthermore, the added antiferromagnetic insulating layer, because it surrounds the magnetic tunnel junction, also protects the magnetic tunnel junction from the influence of the surrounding environment.

[0017] In one specific embodiment, forming an antiferromagnetic insulating layer that at least surrounds the sides of the free layer in each magnetic tunnel junction includes: using a sputtering process, such that the incident angle between sputtered ions and the substrate surface is greater than 0 degrees and less than 90 degrees, growing antiferromagnetic insulating material on all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction, thereby forming an antiferromagnetic insulating layer that surrounds all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction. This increases the height of the antiferromagnetic insulating layer, facilitating the formation of antiferromagnetic insulating material layers on all sides of the magnetic tunnel junction, reducing processing difficulty, and better protecting the magnetic tunnel junction from the influence of the surrounding environment.

[0018] In one specific embodiment, forming an antiferromagnetic insulating layer that at least surrounds the sides of the free layer in each magnetic tunnel junction further includes: using a vertical sputtering process to continue filling the spaces between adjacent antiferromagnetic insulating layers with antiferromagnetic insulating material or other insulating material to fill the spaces between adjacent magnetic tunnel junctions. This reduces processing difficulty and better protects the magnetic tunnel junctions from the influence of the surrounding environment.

[0019] In one specific implementation, forming a magnetic tunnel junction on each SOT layer and forming an antiferromagnetic insulating layer at least surrounding the sides of the free layer in each magnetic tunnel junction includes:

[0020] A dielectric layer is formed by filling the spaces between adjacent SOT layers on the substrate with dielectric material.

[0021] Deposit free material layers on the SOT layer and dielectric layer;

[0022] Deposit an insulating material layer on a free material layer;

[0023] Deposit a reference material layer on an insulating material layer;

[0024] A layer of photoresist is coated on the reference material layer;

[0025] Photolithography pattern exposure is performed, preserving the photoresist located above each magnetic tunnel junction;

[0026] A plasma oxidation process is employed to oxidize the ferromagnetic material not protected by photoresist in the reference material layer and free material layer into an antiferromagnetic material. This forms a magnetic tunnel junction beneath the retained photoresist and creates an antiferromagnetic insulating layer that fills the space between adjacent magnetic tunnel junctions in multiple memory cells. This allows for the simultaneous fabrication of both the magnetic tunnel junction and the antiferromagnetic insulating layer, eliminating the need for patterned etching during the fabrication of the magnetic tunnel junction. This avoids the need for precise control of the etching depth down to the SOT layer during large-scale integration of SOT-MRAM, thus preventing significant performance changes caused by even a small amount of over-etching of the SOT layer.

[0027] In one specific embodiment, adjusting the magnetic moment direction of the antiferromagnetic insulating layer to make it parallel to the direction of the write current includes: vacuum annealing the antiferromagnetic insulating layer under the application of an external magnetic field; wherein the annealing temperature is higher than the Nieer temperature of the antiferromagnetic insulating layer material, and the direction of the external magnetic field is parallel to the direction of the write current in the SOT layer. This facilitates adjusting the magnetic moment direction of the antiferromagnetic insulating layer so that the magnetic moment direction within it is parallel to the direction of the write current in the SOT layer.

[0028] In one specific embodiment, prior to vacuum annealing the antiferromagnetic insulating layer, the manufacturing method further includes forming an upper electrode above each magnetic tunnel junction to form the upper electrode prior to vacuum annealing, thereby preventing oxidation of the reference layer surface during the annealing process. Attached Figure Description

[0029] Figure 1 This is a schematic diagram of the structure of an SOT-MRAM provided in an embodiment of the present invention;

[0030] Figure 2This is a schematic diagram of the structure of a single memory cell in an SOT-MRAM provided by an embodiment of the present invention;

[0031] Figure 3 A schematic diagram illustrating the formation of an antiferromagnetic insulating layer by sputtering on the side of a magnetic tunnel junction, as provided in an embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of the process of preparing SOT-MRAM by oxidation according to an embodiment of the present invention, after exposure of the photolithographic pattern;

[0033] Figure 5 This is a schematic diagram illustrating the degree of oxidation after plasma oxidation during the preparation of SOT-MRAM by oxidation, as provided in an embodiment of the present invention.

[0034] Figure 6 This is a schematic diagram of a structure for fabricating a Hall bar in an SOT-MRAM test structure provided by an embodiment of the present invention;

[0035] Figure 7 In order to be in Figure 6 A schematic diagram of the magnetic tunnel junction fabricated at the center of the Hall bar is shown.

[0036] Figure 8 This is a sample and test schematic diagram of a single memory cell on SOT-MRAM provided for an embodiment of the present invention.

[0037] Figure label:

[0038] 10-Substrate 11-SOT Layer 111-Transverse Hall Rod 112-Vertical Hall Rod

[0039] 12-Magnetic tunnel junction; 13-Antiferromagnetic insulating layer; 14-Dielectric layer; 15-Photoresist Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] To facilitate understanding of the SOT-MRAM provided in the embodiments of the present invention, the application scenarios of the SOT-MRAM provided in the embodiments of the present invention will be described first. This SOT-MRAM, as a type of memory, is applied in devices such as servers. The SOT-MRAM will then be described in detail below with reference to the accompanying drawings.

[0042] refer to Figure 1 , Figure 2 and Figure 3 The SOT-MRAM provided in this embodiment of the invention includes a substrate 10 and a plurality of memory cells disposed on the substrate 10. Each memory cell includes an SOT layer 11 deposited on the substrate 10 for passing write current, and a magnetic tunnel junction 12 disposed on the SOT layer 11. The magnetic tunnel junction 12 includes a free layer deposited on the SOT layer 11, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer. The SOT-MRAM also includes an antiferromagnetic insulating layer 13 at least surrounding and enclosing the sidewalls of the free layer in each magnetic tunnel junction 12, and the magnetic moment direction of the antiferromagnetic insulating layer 13 is parallel to the direction of the write current in the SOT layer 11.

[0043] In the above-described scheme, by adding an antiferromagnetic insulating layer 13 that surrounds the free layer side of each magnetic tunnel junction 12, and ensuring that the magnetic moment direction of the antiferromagnetic insulating layer 13 is parallel to the direction of the write current, an in-plane magnetic field can be provided to the free layer for external magnetic field-free switching of SOT-MRAM. This solves the problem that SOT-MRAM cannot be mass-produced due to the need for an external magnetic field during the writing process. Furthermore, the added antiferromagnetic insulating layer 13, surrounding the magnetic tunnel junction 12, also protects the magnetic tunnel junction 12 from the influence of the surrounding environment. The following is a detailed description of each of the above structures with reference to the accompanying drawings.

[0044] When setting up the substrate 10, the substrate 10 serves as the carrier structure for all memory cells. Its material can be silicon dioxide or the like, and word line structures, bit line structures, etc. can be integrated on it.

[0045] refer to Figure 1 , Figure 2 and Figure 3Multiple memory cells are disposed on the substrate 10. Each memory cell includes a SOT layer 11 deposited on the substrate 10 and a magnetic tunnel junction 12 disposed on the SOT layer 11. The magnetic tunnel junction 12 is a sandwich-like stacked structure, which sequentially includes a free layer deposited on the SOT layer 11, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer. The material of the SOT layer 11 can be a metal layer with spin Hall effect, a topological material layer, or other materials with spin-orbit coupling effect. It can be one or an alloy of several metals selected from Pt, Ta, W, Mo, Au, Al, BiSe, IrMn, etc. The SOT layer 11 is used to pass write current to cause the magnetization direction of the free layer in the magnetic tunnel junction 12 to reverse. Multiple memory cells can be formed on the substrate 10 in an array to form a memory array. The free layer and reference layer are made of homogeneous ferromagnetic materials. Specifically, they can be metals such as Fe, Co, Ni, CoFeB, or alloys of any combination thereof. The insulating layer can be made of metal oxides, such as AlO₂. x MgO, SiO2, HfO x Metal oxides such as those used as insulating layers in magnetic tunnel junction 12 are employed.

[0046] refer to Figure 1 and Figure 3 The SOT-MRAM also includes an antiferromagnetic insulating layer 13 that surrounds at least the sides of the free layer in each magnetic tunnel junction 12. That is, the antiferromagnetic insulating layer 13 surrounds at least the sides of the free layer in each magnetic tunnel junction 12, allowing the antiferromagnetic insulating layer 13 to protect the magnetic tunnel junction 12 from the influence of the surrounding environment by utilizing its positional characteristics surrounding the magnetic tunnel junction 12. Specifically, the antiferromagnetic insulating layer 13 may surround only the sides of the free layer in each magnetic tunnel junction 12, without surrounding the sides of the insulating layer and reference layer of each magnetic tunnel junction 12. Alternatively, it may surround only the sides of the free layer and insulating layer of each magnetic tunnel junction 12, without surrounding the side of the reference layer of each magnetic tunnel junction 12. (Reference) Figure 1 and Figure 3Furthermore, the antiferromagnetic insulating layer 13 can surround all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction 12 to increase the height of the antiferromagnetic insulating layer 13, reduce manufacturing difficulty, and better protect the magnetic tunnel junction 12 from the influence of the surrounding environment. It is important to note that the thickness of the antiferromagnetic insulating layer 13 surrounding the sides of each magnetic tunnel junction 12 must be at least 0.5 nanometers to reduce manufacturing difficulty and ensure that the in-plane magnetic field provided by the antiferromagnetic insulating layer 13 is sufficiently stable and reliable. Specifically, the thickness of the antiferromagnetic insulating layer 13 surrounding the sides of each magnetic tunnel junction 12 can be any value not thinner than 0.5 nanometers, such as 0.5 nanometers, 1 nanometer, 10 nanometers, 100 nanometers, 1 micrometer, 10 micrometers, 100 micrometers, 300 micrometers, or 500 micrometers. Of course, the antiferromagnetic insulating layer 13 can also further fill the space between adjacent magnetic tunnel junctions 12 in multiple memory cells, that is, fill the spaces between adjacent magnetic tunnel junctions 12 with antiferromagnetic insulating material, forming an antiferromagnetic insulating layer 13 that replaces the dielectric layer between adjacent magnetic tunnel junctions 12. This reduces the difficulty of processing and better protects the magnetic tunnel junction 12 from the influence of the surrounding environment.

[0047] In addition, the magnetic moment direction of the antiferromagnetic insulating layer 13 needs to be adjusted so that it is parallel to the direction of the write current in the SOT layer 11. Specifically, the magnetic moment direction of the antiferromagnetic insulating layer 13 can be the same as the direction of the write current in the SOT layer 11, or it can be opposite to the direction of the write current in the SOT layer 11. This provides an in-plane magnetic field to the free layer for the external magnetic field-free switching of SOT-MRAM, thus solving the problem that SOT-MRAM cannot be integrated on a large scale because an external magnetic field needs to be applied during the writing process.

[0048] When determining the material of the antiferromagnetic insulating layer 13, the material of the antiferromagnetic insulating layer 13 can be any one of the following materials: oxide of CoFeB, CoOx, FeOx, NiOx, CrOx, MnOx, CoFe2O4, or a mixture or alloy made of any of these materials.

[0049] By adding an antiferromagnetic insulating layer 13 that surrounds the free layer side of each magnetic tunnel junction 12, and ensuring that the magnetic moment direction of the antiferromagnetic insulating layer 13 is parallel to the direction of the write current, an in-plane magnetic field can be provided to the free layer for external magnetic field-free switching of SOT-MRAM. This solves the problem that SOT-MRAM cannot be mass-produced due to the need for an external magnetic field during the writing process. Furthermore, the added antiferromagnetic insulating layer 13, surrounding the magnetic tunnel junction 12, also protects the magnetic tunnel junction 12 from the influence of the surrounding environment.

[0050] In addition, embodiments of the present invention also provide a method for manufacturing SOT-MRAM, see reference. Figures 1-5 The manufacturing method includes:

[0051] Provide a substrate 10;

[0052] Multiple memory cells are disposed on the substrate 10, including: depositing multiple SOT layers 11 on the substrate 10 for passing write current; forming a magnetic tunnel junction 12 on each SOT layer 11, wherein the magnetic tunnel junction 12 includes: a free layer deposited on the SOT layer 11, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer.

[0053] An antiferromagnetic insulating layer 13 is formed at least around the sides of the free layer in each magnetic tunnel junction 12;

[0054] Adjust the direction of the magnetic moment of the antiferromagnetic insulating layer 13 so that the direction of the magnetic moment of the antiferromagnetic insulating layer 13 is parallel to the direction of the writing current.

[0055] In the above scheme, by adding an antiferromagnetic insulating layer 13 that surrounds the free layer side of each magnetic tunnel junction 12, and ensuring that the magnetic moment direction of the antiferromagnetic insulating layer 13 is parallel to the direction of the write current, an in-plane magnetic field can be provided to the free layer for external magnetic field-free switching of the SOT-MRAM. This solves the problem that SOT-MRAM cannot be integrated on a large scale because an external magnetic field needs to be applied during the writing process. Furthermore, the added antiferromagnetic insulating layer 13, because it surrounds the magnetic tunnel junction 12, also protects the magnetic tunnel junction 12 from the influence of the surrounding environment. It should be noted that the above steps are not limited in order; that is, the order of the steps can be adjusted to fabricate any of the aforementioned SOT-MRAM types. Each step is described in detail below with reference to the accompanying drawings.

[0056] First, refer to Figure 2 A substrate 10 is provided, which serves as the carrier structure for all memory cells. The substrate 10 can be made of materials such as silicon dioxide, and word line structures, bit line structures, etc. can be integrated on it.

[0057] Next, continue to refer to Figure 2Multiple memory cells are disposed on the substrate 10. When disposing of multiple memory cells, firstly, multiple SOT layers 11 for passing write current are deposited on the substrate 10. Then, a magnetic tunnel junction 12 is formed on each SOT layer 11. The magnetic tunnel junction 12 is a sandwich-like stacked structure, sequentially including a free layer deposited on the SOT layer 11, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer. The material of the SOT layer 11 can be a metal layer with spin Hall effect, a topological material layer, or other materials with spin-orbit coupling effect. It can be one or an alloy of several metals selected from Pt, Ta, W, Mo, Au, Al, BiSe, IrMn, etc., as the material of the SOT layer 11. The SOT layer 11 is used to pass write current to cause the magnetization direction of the free layer in the magnetic tunnel junction 12 to reverse. Multiple memory cells can be formed on the substrate 10 in an array to form a memory array. The free layer and reference layer are made of homogeneous ferromagnetic materials. Specifically, they can be metals such as Fe, Co, Ni, CoFeB, or alloys of any combination thereof. The insulating layer can be made of metal oxides, such as AlO₂. x MgO, SiO2, HfO x Metal oxides such as those used as insulating layers in magnetic tunnel junction 12 are employed.

[0058] Next, refer to Figure 1 and Figure 3An antiferromagnetic insulating layer 13 is formed that at least surrounds the sides of the free layer in each magnetic tunnel junction 12. That is, the antiferromagnetic insulating layer 13 at least surrounds the sides of the free layer in each magnetic tunnel junction 12, allowing the antiferromagnetic insulating layer 13 to protect the magnetic tunnel junction 12 from the influence of the surrounding environment by utilizing its positional characteristics around the magnetic tunnel junction 12. Specifically, when choosing the surrounding wrapping method, the antiferromagnetic insulating layer 13 may only surround the sides of the free layer in each magnetic tunnel junction 12, without surrounding the sides of the insulating layer and reference layer of each magnetic tunnel junction 12. Alternatively, it may only surround the sides of the free layer and insulating layer in each magnetic tunnel junction 12, without surrounding the sides of the reference layer of each magnetic tunnel junction 12. Or it may surround all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction 12 to increase the height of the antiferromagnetic insulating layer 13, reduce the processing difficulty, and better protect the magnetic tunnel junction 12 from the influence of the surrounding environment. It is important to note that the antiferromagnetic insulating layer 13, surrounding the sides of each magnetic tunnel junction 12, has a thickness of at least 0.5 nanometers. This reduces manufacturing difficulty while ensuring a sufficiently stable and reliable in-plane magnetic field provided by the antiferromagnetic insulating layer 13. Specifically, the thickness of the antiferromagnetic insulating layer 13 surrounding the sides of each magnetic tunnel junction 12 can be any value not thinner than 0.5 nanometers, such as 0.5 nanometers, 1 nanometer, 10 nanometers, 100 nanometers, 1 micrometer, 10 micrometers, 100 micrometers, 300 micrometers, or 500 micrometers. Furthermore, the antiferromagnetic insulating layer 13 can further fill the space between adjacent magnetic tunnel junctions 12 in multiple memory cells. This means that antiferromagnetic insulating material is filled between adjacent magnetic tunnel junctions 12, and the resulting antiferromagnetic insulating layer 13 replaces the dielectric layer between adjacent magnetic tunnel junctions 12. This reduces processing difficulty and better protects the magnetic tunnel junctions 12 from environmental influences.

[0059] There are several ways to form the antiferromagnetic insulating layer 13. Two methods for forming the antiferromagnetic insulating layer 13 using sputtering and oxidation are described below.

[0060] First, the antiferromagnetic insulating layer 13 can be formed using a sputtering process, a commonly used process in traditional MRAM fabrication. At this point, before forming the antiferromagnetic insulating layer 13, a substrate such as... Figure 2 The SOT layer 11 and magnetic tunnel junction 12 shown are both formed on the substrate 10 through patterned etching. Specifically, a multilayer film of the magnetic tunnel junction 12 can be sequentially grown on the substrate 10, and then the magnetic tunnel junction 12 is patterned through photolithography and ion etching, with the etching depth reaching the SOT layer 11, forming as shown. Figure 2The SOT layer 11 and magnetic tunnel junction 12 are shown. Next, an antiferromagnetic insulating layer 13 is formed using a sputtering process. That is, after the magnetic tunnel junction 12 is etched, an antiferromagnetic insulating material, rather than ordinary insulating material, is grown on the sides of the magnetic tunnel junction 12, acting as a filler to protect the magnetic tunnel junction 12. In this process, the antiferromagnetic insulating layer 13 needs to completely surround all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction 12.

[0061] When forming an antiferromagnetic insulating layer 13 that at least surrounds the sides of the free layer in each magnetic tunnel junction 12, a sputtering process can be used, such that the incident angle between the sputtered ions and the surface of the substrate 10 is greater than 0 degrees and less than 90 degrees. Antiferromagnetic insulating material is grown on all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction 12 to form an antiferromagnetic insulating layer 13 surrounding all sides of the free layer, insulating layer, and reference layer in each magnetic tunnel junction 12. That is, an antiferromagnetic insulating layer 13 is grown around the patterned magnetic tunnel junction 12 by sputtering, with the incident angle between the sputtered ions and the surface of the substrate 10 between 0 degrees and 90 degrees. This antiferromagnetic insulating material can be any one of the following: oxides of CoFeB, CoOx, FeOx, NiOx, CrOx, MnOx, CoFe2O4, or a mixture or alloy of any of these materials. Furthermore, by using incident angles between sputtered ions and the surface of the substrate 10 within a range greater than 0 degrees and less than 90 degrees (e.g., 1 degree, 10 degrees, 20 degrees, 30 degrees, 40 degrees, 50 degrees, 60 degrees, 70 degrees, 80 degrees, 89 degrees), it is easier to grow antiferromagnetic insulating material on all sides of each magnetic tunnel junction 12, forming an antiferromagnetic insulating material layer surrounding all sides of each magnetic tunnel junction 12. This increases the height of the antiferromagnetic insulating layer 13, facilitating the formation of the antiferromagnetic insulating material layer on all sides of the magnetic tunnel junction 12, reducing processing difficulty, and better protecting the magnetic tunnel junction 12 from the influence of the surrounding environment. Additionally, the thickness of the antiferromagnetic insulating layer 13 grown on the sides of the magnetic tunnel junction 12 using the sputtering process is preferably greater than 1 nm, ensuring that the sides of the magnetic tunnel junction 12 have a sufficiently thick antiferromagnetic insulating layer 13.

[0062] Subsequently, a vertical sputtering process can be further employed to fill the spaces between adjacent antiferromagnetic insulating layers 13 with antiferromagnetic insulating material or other insulating materials, thereby filling the spaces between adjacent magnetic tunnel junctions 12. Specifically, a vertical sputtering process can be used to fill the spaces between adjacent antiferromagnetic insulating layers 13 with antiferromagnetic insulating material, so that the final antiferromagnetic insulating layer 13 fills the spaces between adjacent magnetic tunnel junctions 12, thus replacing the dielectric layer between adjacent magnetic tunnel junctions 12. This reduces the processing difficulty and better protects the magnetic tunnel junctions 12 from the influence of the surrounding environment. Of course, a vertical sputtering process can also be used to fill the spaces between adjacent antiferromagnetic insulating layers 13 with other types of insulating materials besides antiferromagnetic insulating material, thereby filling the spaces between adjacent antiferromagnetic insulating materials with dielectric material to form a dielectric layer.

[0063] Next, we will introduce the method of forming the antiferromagnetic insulating layer 13 using oxidation. In this process, the antiferromagnetic insulating layer 13 needs to fill the space between adjacent magnetic tunnel junctions 12 in multiple memory cells. Furthermore, in this process, the formation of the magnetic tunnel junction 12 and the antiferromagnetic insulating layer 13 on each SOT layer 11 is performed simultaneously, so the order of steps in the aforementioned method needs to be adjusted. Before forming the antiferromagnetic insulating layer 13 using oxidation, the SOT layer 11 has already been formed on the substrate 10; that is, the SOT layer 11 has already been formed on the substrate 10 through image etching.

[0064] Specifically, when forming a magnetic tunnel junction 12 on each SOT layer 11, and forming an antiferromagnetic insulating layer 13 that at least surrounds the sides of the free layer in each magnetic tunnel junction 12, refer to Figure 4 First, dielectric material needs to be filled between adjacent SOT layers 11 on the substrate 10 to form a dielectric layer 14, thereby creating a flat end face above the SOT layers 11. Then, as... Figure 4 As shown, a free material layer is deposited on the SOT layer 11 and the dielectric layer 14, specifically a ferromagnetic material is deposited on the SOT layer 11 and the dielectric layer 14 as the material layer for the subsequent formation of the free layer. Next, an insulating material layer is deposited on the free material layer, specifically an insulating material is deposited on the free material layer as the material layer for the subsequent formation of the insulating layer. Next, a reference material layer is deposited on the insulating material layer, specifically a ferromagnetic material is deposited on the insulating material layer as the material layer for the subsequent formation of the reference layer. Then, a photoresist layer is deposited on the reference material layer so that the pattern of the magnetic tunnel junction 12 can be copied onto the photoresist using photolithography. Afterwards, the reference... Figure 4 Photolithography is performed to expose the pattern, retaining the photoresist 15 above each magnetic tunnel junction 12. The area below the photoresist 15 retained on the reference material layer surface is the region where the magnetic tunnel junction 12 will be formed. Then, the reference... Figure 5A plasma oxidation process is used to oxidize the ferromagnetic material in the reference material layer and free material layer that is not protected by the photoresist 15 into an antiferromagnetic material, thereby forming a magnetic tunnel junction 12 under the retained photoresist 15 and forming an antiferromagnetic insulating layer 13 that fills the space between adjacent magnetic tunnel junctions 12 in multiple memory cells. In other words, plasma oxidation oxidizes the ferromagnetic material layer in the magnetic tunnel junction 12 in areas not protected by the photoresist 15; this ferromagnetic material layer specifically includes the free material layer and the reference material layer. By controlling the oxidation time, all the free material layer and the reference layer above the SOT layer 11 are oxidized, such as... Figure 5 As shown. At this time, the oxide layer of the ferromagnetic material layer in the area not covered by photoresist 15 serves as... Figure 1 The antiferromagnetic insulating layer 13 is shown. Then, the remaining photoresist 15 is removed to facilitate the simultaneous fabrication of the magnetic tunnel junction 12 and the antiferromagnetic insulating layer 13. This eliminates the need for patterning etching during the fabrication of the magnetic tunnel junction 12, thus avoiding the process of precisely controlling the etching depth to the SOT layer 11 during large-scale SOT-MRAM integration. Furthermore, the SOT layer 11 is typically only 3-8 nanometers in size; even a small amount of over-etching can cause significant changes in device performance. By avoiding patterning etching during the fabrication of the magnetic tunnel junction 12, the significant performance changes caused by even a small amount of over-etching of the SOT layer 11 are avoided.

[0065] Next, the magnetic moment direction of the antiferromagnetic insulating layer 13 needs to be adjusted so that it is parallel to the direction of the write current. Specifically, the magnetic moment direction of the antiferromagnetic insulating layer 13 can be the same as the direction of the write current in the SOT layer 11, or it can be opposite to the direction of the write current in the SOT layer 11. This provides an in-plane magnetic field to the free layer for the external magnetic field-free switching of the SOT-MRAM, thus solving the problem that SOT-MRAM cannot be integrated on a large scale because an external magnetic field needs to be applied during the writing process.

[0066] When specifically adjusting the magnetic moment direction of the antiferromagnetic insulating layer 13, it can be vacuum annealed under an applied external magnetic field. The magnetic moment direction of the antiferromagnetic insulating layer 13 can be adjusted by regulating the annealing temperature and the direction of the external magnetic field. Specifically, the annealing temperature needs to be adjusted to be higher than the NieR temperature of the antiferromagnetic insulating layer 13 material to transform the antimagnetic material into a paramagnetic material. Simultaneously, the direction of the external magnetic field should be parallel to the direction of the write current in the SOT layer 11. Specifically, the direction of the external magnetic field can be the same as or opposite to the direction of the write current in the SOT layer 11, thereby guiding the magnetic moment direction within the antiferromagnetic insulating layer 13 to the same direction parallel to the write current in the SOT layer 11. This provides an in-plane magnetic field to the free layer for external magnetic field-free switching of the SOT-MRAM. The external magnetic field is applied throughout the annealing process until the antiferromagnetic insulating layer 13 cools to room temperature, facilitating the adjustment of the magnetic moment direction of the antiferromagnetic insulating layer 13 so that the magnetic moment direction within it is parallel to the direction of the write current in the SOT layer 11.

[0067] In addition, an upper electrode can be formed above each magnetic tunnel junction 12 before vacuum annealing of the antiferromagnetic insulating layer 13, so as to prevent the reference layer surface from being oxidized during the annealing process.

[0068] like Figures 6-8 This illustrates a method for fabricating a test structure for SOT-MRAM. (Reference) Figure 6 First, an 8nm thick Ta layer is sputtered on substrate 1010 (Si wafer), and patterned into a Hall bar structure, serving as the SOT layer 11 in each memory cell. The Hall bar structure includes a lateral Hall bar 111 and a vertical Hall bar 112. The width of the lateral Hall bar 111 can be 2 micrometers, and the width of the vertical Hall bar 112 can also be 2 micrometers. Then, a 0.8nm thick CoFeB material layer is sequentially deposited on substrate 10 and the Hall bar structure as the material layer for processing the free layer; a 1nm thick MgO material layer is deposited as the material layer for processing the insulating layer; and a 1.2nm thick CoFeB material layer is deposited as the material layer for processing the reference layer. Afterwards, the reference... Figure 7 Through photolithography and etching, the etching depth reaches the Ta layer, meaning all layers above the Ta layer are etched. A circular magnetic tunnel junction 12 with a diameter of 100 nanometers is fabricated in the intersection region of the vertical and horizontal Hall bars 111, with an area of ​​2 micrometers × 2 micrometers. An antiferromagnetic insulating layer 13 can then be fabricated using the sputtering process described above. For example, NiO can be sputtered around the etched magnetic tunnel junction 12. x The sputtering angle was 45 degrees, and the sputtering thickness was 20 nm. Subsequently, a 60 nm layer of NiO was sputtered using a vertical sputtering method. xThis forms an antiferromagnetic insulating layer 13 that fills all the spaces between adjacent magnetic tunnel junctions 12. Afterwards, a Ti 15nm / Cu 100nm / Au 50nm layer is deposited again using electron beam exposure as the top electrode. The sample preparation is complete as follows: Figure 8 As shown. Of course, before depositing the top electrode material layer, a 15nm thick Ta material layer can also be deposited on the reference layer as a buffer layer for processing other additional layers, to increase the adhesion strength of the top electrode and prevent it from detaching. Afterwards, the prepared sample is annealed at 350 degrees Celsius for 10 minutes under a magnetic field of 5kOe. During the annealing heating and cooling process, the external magnetic field is maintained at 5kOe until the sample cools to room temperature. The external magnetic field is applied parallel to the extension direction of the transverse Hall bar 111. The prepared sample and test schematic diagram are shown below. Figure 8 As shown, the horizontal Hall bar 111 serves as the write current channel, through which the write current is supplied; the vertical Hall bar 112 serves as the read current channel, through which the read current is supplied.

[0069] By adding an antiferromagnetic insulating layer 13 that surrounds the free layer side of each magnetic tunnel junction 12, and ensuring that the magnetic moment direction of the antiferromagnetic insulating layer 13 is parallel to the direction of the write current, an in-plane magnetic field can be provided to the free layer for external magnetic field-free switching of SOT-MRAM. This solves the problem that SOT-MRAM cannot be mass-produced due to the need for an external magnetic field during the writing process. Furthermore, the added antiferromagnetic insulating layer 13, surrounding the magnetic tunnel junction 12, also protects the magnetic tunnel junction 12 from the influence of the surrounding environment.

[0070] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An SOT-MRAM, characterized in that, include: substrate; Multiple memory cells are disposed on the substrate. Each memory cell includes an SOT layer deposited on the substrate for passing write current and a magnetic tunnel junction disposed on the SOT layer. The magnetic tunnel junction includes a free layer deposited on the SOT layer, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer. At least an antiferromagnetic insulating layer surrounds the side of the free layer in each magnetic tunnel junction, and the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the write current; The magnetic tunnel junction and the antiferromagnetic insulating layer are formed according to the following steps: A dielectric material is filled between adjacent SOT layers on the substrate to form a dielectric layer; A free material layer is deposited on the SOT layer and the dielectric layer; An insulating material layer is deposited on the free material layer; A reference material layer is deposited on the insulating material layer; A layer of photoresist is coated on the reference material layer; Photolithography pattern exposure is performed, preserving the photoresist located above each magnetic tunnel junction; A plasma oxidation process is used to oxidize the ferromagnetic material that is not protected by photoresist in the reference material layer and the free material layer into an antiferromagnetic material, so as to form the magnetic tunnel junction under the retained photoresist and form the antiferromagnetic insulating layer that fills the space between adjacent magnetic tunnel junctions in the plurality of memory cells.

2. The SOT-MRAM of claim 1, wherein, The antiferromagnetic insulating layer at least covers all sides of the free layer, insulating layer and reference layer in each magnetic tunnel junction.

3. The SOT-MRAM of claim 2, wherein, The antiferromagnetic insulating layer fills the space between adjacent magnetic tunnel junctions in the plurality of memory cells.

4. The SOT-MRAM of claim 1, wherein, The antiferromagnetic insulating layer is made of any one of the following materials: oxide of CoFeB, CoOx, FeOx, NiOx, CrOx, MnOx, CoFe2O4, or a mixture or alloy of any of these materials.

5. The SOT-MRAM of claim 1, wherein, The antiferromagnetic insulating layer surrounds the sides of each magnetic tunnel junction with a thickness of at least 0.5 nanometers.

6. A method of manufacturing an SOT-MRAM, characterized by, include: Provide a substrate; Multiple memory cells are disposed on the substrate, including: depositing multiple SOT layers for passing write current on the substrate; forming a magnetic tunnel junction on each SOT layer, wherein the magnetic tunnel junction includes: a free layer deposited on the SOT layer, an insulating layer stacked on the free layer, and a reference layer stacked on the insulating layer; An antiferromagnetic insulating layer is formed that surrounds at least the sides of the free layer in each magnetic tunnel junction; Adjust the magnetic moment direction of the antiferromagnetic insulating layer so that the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the writing current; Wherein, the formation of a magnetic tunnel junction on each SOT layer and the formation of an antiferromagnetic insulating layer at least surrounding and enclosing the free layer sidewalls in each magnetic tunnel junction include: A dielectric material is filled between adjacent SOT layers on the substrate to form a dielectric layer; A free material layer is deposited on the SOT layer and the dielectric layer; An insulating material layer is deposited on the free material layer; A reference material layer is deposited on the insulating material layer; A layer of photoresist is coated on the reference material layer; Photolithography pattern exposure is performed, preserving the photoresist located above each magnetic tunnel junction; A plasma oxidation process is used to oxidize the ferromagnetic material that is not protected by photoresist in the reference material layer and the free material layer into an antiferromagnetic material, so as to form the magnetic tunnel junction under the retained photoresist and form the antiferromagnetic insulating layer that fills the space between adjacent magnetic tunnel junctions in the plurality of memory cells.

7. The production method according to claim 6, wherein The formation of the antiferromagnetic insulating layer, which at least surrounds the sides of the free layer in each magnetic tunnel junction, includes: A sputtering process is used to ensure that the incident angle between the sputtered ions and the substrate surface is greater than 0 degrees and less than 90 degrees. Antiferromagnetic insulating material is grown on all sides of the free layer, insulating layer and reference layer in each magnetic tunnel junction to form an antiferromagnetic insulating layer that surrounds all sides of the free layer, insulating layer and reference layer in each magnetic tunnel junction.

8. The production method according to claim 7, wherein The formation of an antiferromagnetic insulating layer that at least surrounds the sides of the free layer in each magnetic tunnel junction also includes: A vertical sputtering process is used to fill the space between adjacent antiferromagnetic insulating layers with antiferromagnetic insulating material or other insulating material to fill the space between adjacent magnetic tunnel junctions.

9. The manufacturing method as described in claim 6, characterized in that, Adjusting the magnetic moment direction of the antiferromagnetic insulating layer so that the magnetic moment direction of the antiferromagnetic insulating layer is parallel to the direction of the writing current includes: The antiferromagnetic insulating layer is vacuum annealed under the application of an external magnetic field; wherein the annealing temperature is higher than the Nieer temperature of the antiferromagnetic insulating layer material, and the direction of the external magnetic field is parallel to the direction of the write current in the SOT layer.

10. The production method according to claim 9, wherein Before vacuum annealing the antiferromagnetic insulating layer, the manufacturing method further includes: An upper electrode is formed above each magnetic tunnel junction.

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