Method for modeling measurement data on a substrate area and associated apparatus

Abstract

A method and associated apparatus for modeling measurement data on a substrate area are disclosed. The method includes obtaining measurement data related to a first layout, modeling a second model based on the first layout, evaluating the second model on a second layout, the second layout being denser than the first layout, and fitting the first model to the second model according to the second layout.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to EP application 20180323.6, filed on June 16, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to the processing of substrates used in the production of, for example, semiconductor devices. Background Technology

[0004] A lithography apparatus is a machine configured to apply a desired pattern onto a substrate. Lithography apparatuses can be used, for example, in the manufacture of integrated circuits (ICs). For instance, a lithography apparatus can project a pattern (often referred to as a “design layout” or “design”) onto a radiation-sensitive material (resist) layer disposed on a substrate (e.g., a wafer) at a patterning apparatus (e.g., a mask).

[0005] To project patterns onto a substrate, a photolithography apparatus can use radiation. The wavelength of this radiation determines the minimum size of the feature that can be formed on the substrate. Typical wavelengths currently used are approximately 365 nm (i-line), approximately 248 nm, approximately 193 nm, and approximately 13 nm. Compared to photolithography apparatuses using radiation with wavelengths such as approximately 193 nm, photolithography apparatuses using extreme ultraviolet (EUV) radiation in the wavelength range of 4 nm–20 nm (e.g., 6.7 nm or 13.5 nm) can be used to form smaller features on the substrate.

[0006] Low-k1 lithography can be used to process features smaller than the traditional resolution limits of lithography apparatuses. In this process, the resolution formula can be expressed as CD = k1 × λ / NA, where λ is the radiation wavelength used, NA is the numerical aperture of the projection optics in the lithography apparatus, CD is the "critical size" (typically the smallest feature size to be printed, but in this case, half a pitch), and k1 is an empirical resolution factor. Generally, the smaller k1 is, the more difficult it becomes to replicate patterns on the substrate that resemble the shape and size designed by the circuit designer in order to achieve specific electrical functions and performance. To overcome these difficulties, complex fine-tuning steps can be applied to the lithography projection apparatus and / or design layout. These include, for example, but not limited to, optimization of the numerical aperture (NA), customized illumination schemes, the use of one or more phase-shifting patterning devices, optimization of the design layout (such as optical proximity correction (OPC) in the design layout), or other methods generally defined as resolution enhancement techniques (RET). Additionally or alternatively, one or more tight control loops for controlling the stability of the lithography apparatus can be used to improve pattern replication at low k1.

[0007] The effectiveness of control over a lithography apparatus can depend on the characteristics of each substrate. For example, a first substrate (or any other process step of the manufacturing process, collectively referred to herein as a manufacturing process step) processed by a first processing tool prior to being processed by the lithography apparatus may benefit from (slightly) different control parameters than a second substrate processed by a second processing tool prior to being processed by the lithography apparatus.

[0008] Precise placement of patterns on a substrate is a major challenge for reducing the size of circuit components and other products that can be manufactured by photolithography. In particular, the challenge of accurately measuring features already laid on the substrate is a critical step in enabling sufficiently precise alignment of stacked, sequential feature layers to produce functional devices in high yields. Typically, so-called overlay should be achieved within tens of nanometers in today's submicron semiconductor devices, and down to a few nanometers in the most critical layers.

[0009] Therefore, modern lithography apparatuses involve numerous measurement or “mapping” operations prior to the actual exposure or other patterning of the substrate at target locations. So-called advanced alignment models have been developed and continue to be developed to more accurately model and correct the nonlinear distortions of the wafer “grid” caused by processing steps and / or the lithography apparatus itself. However, not all distortions are correctable during exposure, and it remains important to track and eliminate as many of the causes of such distortions as possible.

[0010] These distortions in the wafer grid are represented by measurement data associated with the marker positions. Measurement data is obtained from measurements on the wafer. One example of such measurement is the alignment measurement of alignment marks performed before exposure using an alignment system in the lithography apparatus. Another example is the overlay measurement of overlay targets performed after exposure using a metrology system. Summary of the Invention

[0011] In a first aspect of the invention, a method is provided for modeling measurement data on a substrate region associated with a substrate in a photolithography process, comprising: obtaining measurement data associated with a first layout; modeling a second model based on the first layout; evaluating the second model on a second layout, the second layout being denser than the first layout; and fitting the first model to the second model according to the second layout.

[0012] In a second aspect of the invention, a method is provided for determining a polynomial subspace with minimum bending energy for a given model layout, comprising: performing bending energy orthogonalization on a model matrix describing the model; removing linear portions from the model matrix; calculating and truncating a single-valued decomposition of the model matrix; and calculating a subspace matrix corresponding to the truncated decomposed model matrix obtained by the preceding steps.

[0013] In a third aspect of the invention, a method is provided for regularizing the fitting of a model to measurement data from a substrate; comprising: calculating a bending covariance matrix based on a description of the bending energy within the substrate; and determining a Tikhonov regularization term for fitting from the bending covariance matrix.

[0014] In another aspect of the invention, a computer program is provided, comprising program instructions operable, when run on a suitable device, to perform the method of the first aspect, as well as associated processing means and photolithography means. Attached Figure Description

[0015] Embodiments of the invention will now be described by way of example only with reference to the accompanying schematic diagrams, in which:

[0016] Figure 1 A schematic diagram of the photolithography apparatus is depicted;

[0017] Figure 2 A schematic diagram of the photolithography unit is shown;

[0018] Figure 3 The use is illustrated schematically. Figure 1 and Figure 2 The lithography apparatus and lithography unit, along with one or more other apparatuses, form a manufacturing facility for, for example, semiconductor devices, which implements a control strategy according to an embodiment of the present invention;

[0019] Figure 4 This is a flowchart describing a method according to an embodiment of the present invention; and

[0020] Figure 5 This is a flowchart describing a method for selecting a model subspace according to an embodiment of the present invention. Detailed Implementation

[0021] Figure 1A lithography apparatus LA is schematically depicted. The lithography apparatus LA includes: an irradiation system (also referred to as an irradiator) IL configured to modulate a radiation beam B (e.g., UV radiation, DUV radiation, or EUV radiation); a support (e.g., a mask stage) T configured to support a pattern forming apparatus (e.g., a mask) MA and connected to a first positioner PM configured to precisely position the pattern forming apparatus MA according to certain parameters; one or more substrate supports (e.g., wafer stages) WTa and WTb configured to hold a substrate (e.g., a wafer coated with resist) W and connected to a second positioner PW configured to precisely position the substrate supports according to certain parameters; and a projection system (e.g., a refractive projection lens system) PS configured to project a pattern imparted by the pattern forming apparatus MA to the radiation beam B onto a target portion C (e.g., comprising one or more dies) of the substrate W.

[0022] In operation, the irradiation system IL receives a radiation beam from the radiation source SO, for example, via a beam delivery system BD. The irradiation system IL may include various types of optical components, such as refractive, reflective, magnetic, electromagnetic, electrostatic, and / or other types of optical components, or any combination thereof, for guiding, shaping, and / or controlling the radiation. The irradiator IL can be used to adjust the radiation beam B to have a desired spatial and angular intensity distribution in a cross-section at the plane of the pattern forming apparatus MA.

[0023] The term “projection system” PS as used herein should be interpreted broadly to encompass all types of projection systems, including refractive, reflective, antirefractive, distorting, magnetic, electromagnetic, and / or electrostatic optical systems, or any combination thereof, suitable for the exposure radiation being used, and / or other factors such as the use of immersion liquids or vacuum. Any use of the term “projection lens” in this document may be considered synonymous with the more general term “projection system” PS.

[0024] A lithography apparatus LA can be of the type in which at least a portion of the substrate can be covered by a liquid (e.g., water) having a relatively high refractive index to fill the space between the projection system PS and the substrate W; this is also known as immersion lithography. Further information on immersion techniques is given in U.S. Patent No. 6,952,253, which is incorporated herein by reference in its entirety.

[0025] In this example, the lithography apparatus LA is a so-called dual-stage type, having two substrate stages WTa and WTb and two stations—an exposure station and a measurement station—between which the substrate stage can move. While one substrate on one stage is exposed at the exposure station EXP, the other substrate can be loaded onto the other substrate stage, for example, at the measurement station MEA, or at another location (not shown), or can be processed at the measurement station MEA. The substrate stage with the substrate can be located at the measurement station MEA, allowing various preparation steps to be performed. Preparation steps may include: mapping the surface height of the substrate using a level sensor LS; and / or measuring the position of alignment marks on the substrate using an alignment sensor AS. The alignment marks are nominally arranged in a regular grid pattern. However, due to the inaccuracy in producing the marks and due to substrate deformation that occurs throughout the process, the marks may deviate from the ideal grid. Therefore, in addition to measuring the position and orientation of the substrate, the alignment sensor can actually measure the position of many marks on the substrate area in detail if the apparatus LA is to print product features in the correct positions with high accuracy. Therefore, the measurement of alignment marks can be time-consuming, and providing two substrate stages allows for a significant increase in the throughput of the apparatus. If the position sensor IF cannot measure the position of the substrate stage when it is in both the measurement and exposure stations, a second position sensor can be provided to enable the position of the substrate stage to be tracked at both stations. An embodiment of the invention can be applied to devices having only one substrate stage or more than two substrate stages.

[0026] In addition to having one or more substrate supports, the lithography apparatus LA may also include a measurement stage (not shown). The measurement stage is arranged to hold sensors and / or cleaning devices. The sensors may be arranged to measure characteristics of the projection system PS or the radiation beam B. The measurement stage may accommodate multiple sensors. The cleaning devices may be arranged to clean part of the lithography apparatus, such as part of the projection system PS or part of a system providing immersion liquid. The measurement stage may be movable below the projection system PS when the substrate support WT is moved away from the projection system PS.

[0027] A radiation beam B is incident on a patterning apparatus (e.g., a mask) MA held on a support structure (e.g., a mask stage) MT and patterned by the patterning apparatus. After passing through the patterning apparatus MA, the radiation beam B passes through a projection system PS, which focuses the radiation beam onto a target portion C of the substrate W. The substrate stage WTa / WTb can be precisely moved, for example, to position different target portions C within the path of the radiation beam B, by means of a second positioner PW and a position sensor IF (e.g., an interferometer, a linear encoder, or a capacitive sensor). Similarly, a first positioner PM and another position sensor (… Figure 1(Not explicitly shown) can be used, for example, to precisely position the patterning apparatus MA relative to the path of the radiation beam B after mechanical retrieval from a mask library or during scanning. Typically, movement of the support structure MT can be achieved by means of a long-stroke module (coarse positioning) and a short-stroke module (fine positioning), which form part of a first positioner PM. Similarly, movement of the substrate stage WTa / WTb can be achieved using long-stroke and short-stroke modules, which form part of a second positioner PW. In the case of a stepper (opposite to the scanner), the support structure MT can be connected only to the short-stroke actuator, or it can be fixed. Patterning apparatus alignment marks M1, M2 and substrate alignment marks P1, P2 can be used to align the patterning apparatus MA and the substrate W. Although the substrate alignment marks shown occupy dedicated target portions, they can be located in the space between the target portions (these are called scribing alignment marks). Similarly, when more than one die is provided on the patterning apparatus MA, the patterning apparatus alignment marks can be located between the dies.

[0028] The apparatus also includes a Lithography Apparatus Control Unit (LACU), which controls all movement and measurement of the various actuators and sensors (such as those described) within the lithography apparatus. The LACU also includes signal and data processing capabilities to perform desired calculations related to the operation of the apparatus. In practice, the LACU will be implemented as a system of many sub-units, each handling real-time data acquisition, processing, and control of subsystems or components within the apparatus. For example, one processing subsystem could be dedicated to the servo control of the substrate positioner (PW). Separate units could even handle coarse and fine adjustment actuators or different axes. Another unit could be dedicated to the readout of the position sensor (IF). Overall control of the apparatus can be controlled by a central processing unit that communicates with these subsystem processing units, operators, and other devices involved in the lithography manufacturing process.

[0029] like Figure 2As shown, a lithography apparatus LA can form part of a lithography unit LC, sometimes referred to as a lithography unit or (lithography) cluster, and typically includes equipment for performing pre- and post-exposure processes on a substrate W. Conventionally, this equipment includes one or more spin coaters SC to deposit a resist layer, one or more developers DE to develop the exposed resist, one or more cooling plates CH, and one or more baking plates BK, for example, to regulate the temperature of the substrate W, or, for example, to regulate the solvent in the resist layer. A substrate processor or robot RO picks up the substrate W from input / output ports I / O1, I / O2, moves the substrate W between different processing units, and transfers the substrate W to the loading stage LB of the lithography apparatus LA. Devices within the lithography unit, often collectively referred to as tracks, are typically under the control of a track control unit TCU, which itself can be controlled by a supervisory control system SCS, which can also control the lithography apparatus LA, for example, via a lithography control unit LACU.

[0030] To ensure that the substrate W exposed by the photolithography unit LA is exposed correctly and consistently, it is desirable to inspect the substrate to measure characteristics of the patterned structure, such as overlay error between subsequent layers, line thickness, critical dimension (CD), etc. For this purpose, one or more inspection tools (not shown) may be included in the photolithography unit LC. If an error is detected, adjustments can be made, for example, to the exposure of subsequent substrates or to other processing steps to be performed on the substrate W, especially if the inspection is performed before other substrates W in the same batch or lot are still to be exposed or processed.

[0031] An inspection apparatus (MET), also known as a measurement device or measuring tool, is used to determine one or more characteristics of a substrate W, and in particular how one or more characteristics vary between different substrates W or how one or more characteristics associated with different layers of the same substrate W vary layer by layer. The inspection apparatus can be configured to identify defects on the substrate W and can be, for example, part of a photolithography unit (LC), or integrated into a photolithography apparatus (LA), or even a stand-alone device. The inspection apparatus can measure one or more characteristics in images such as: latent images (images in a resist layer after exposure), or semi-latent images (images in a resist layer after a post-exposure baking step), or developed resist images (where exposed or unexposed portions of the resist have been removed), or even etched images (after a pattern transfer step such as etching).

[0032] Figure 3A lithography apparatus LA and a lithography unit LC are shown in the context of an industrial manufacturing facility for, for example, semiconductor products. Within the lithography apparatus (or simply "lithography tool" 200), a measurement station MEA is shown at 202, and an exposure station EXP is shown at 204. A control unit LACU is shown at 206. As already described, the lithography tool 200 forms part of a "lithography unit" or "lithography cluster," which also includes a coating apparatus SC 208 for applying a photoresist and / or one or more other coatings to a substrate W for patterning by the apparatus 200. On the output side of the apparatus 200, a baking apparatus BK 210 and a developing apparatus DE 212 are provided for developing the exposed pattern into a physical resist pattern. (Details omitted for clarity.) Figure 3 Other components shown.

[0033] Once the pattern has been applied and developed, the patterned substrate 220 is transferred to other processing apparatuses, such as those illustrated at 222, 224, and 226. In typical manufacturing facilities, a wide range of processing steps are performed using various apparatuses. For example, apparatus 222 in this embodiment is an etching station, and apparatus 224 performs a post-etch annealing step. Further physical and / or chemical processing steps are applied in other apparatuses, such as 226. Many types of operations (such as material deposition, modification of surface material properties (oxidation, doping, ion implantation, etc.), chemical mechanical polishing (CMP), etc.) may be required to fabricate actual devices. In practice, apparatus 226 can represent a series of different processing steps performed in one or more apparatuses.

[0034] The semiconductor manufacturing process described herein, which includes a series of patterning steps, is merely one example of an industrial process in which the techniques disclosed herein can be applied. A semiconductor manufacturing process includes a series of patterning steps. Each patterning step includes a patterning operation, such as photolithography, and several other chemical and / or physical operations.

[0035] The fabrication of semiconductor devices involves repeated processing to build device structures with appropriate materials and patterns layer by layer on a substrate. For example, modern device fabrication processes may include 40 or 50 separate patterning steps. Accordingly, the substrate 230 arriving at the photolithographic cluster may be a newly prepared substrate, or it may be a substrate that has previously been processed in cluster 232 or entirely in another device. Similarly, depending on the required processing, the substrate leaving device 226 may be returned for subsequent patterning operations in the same photolithographic cluster (such as substrate 232), which may be designated for patterning operations in a different cluster (such as substrate 234), or it may be a finished product (e.g., substrate 234) to be sent for dicing and packaging.

[0036] Each layer of a product structure typically includes a different set of process steps, and the apparatus used at each layer can be entirely different in type. Furthermore, even in large facilities where the processing steps performed by the apparatus are nominally identical, there may be several supposedly identical machines operating in parallel to perform processing on different substrates. Minor differences in setup or malfunction between these machines can mean they affect different substrates in different ways. Even steps that are relatively common for each layer (such as etching (apparatus 222)) can be achieved using several etching apparatuses that are nominally identical but operate in parallel to maximize throughput. Parallel processing can also be performed in different chambers within a larger facility. Moreover, in practice, different layers often involve different etching processes, such as chemical etching, plasma etching, etc., depending on the details of the material to be etched and specific requirements such as, for example, anisotropic etching.

[0037] As previously mentioned, prior and / or subsequent processes can be performed in other lithography apparatuses, and even in different types of lithography apparatuses. For example, one or more layers in device fabrication processes with very high requirements, such as resolution and / or overlay, can be performed in more advanced lithography tools compared to one or more other layers with lower requirements. Thus, one or more layers can be exposed in immersion lithography tools, while one or more other layers are exposed in "dry" tools. One or more layers can be exposed in tools operating at DUV wavelengths, while one or more other layers are exposed using EUV wavelength radiation.

[0038] Figure 3 The diagram also shows a metrology device (MET) 240, which is provided for measuring parameters of the product at desired stages of the manufacturing process. A common example of a metrology station in modern lithography manufacturing facilities is a scatterometer, such as an angle-resolved scatterometer or a spectral scatterometer, which can be used to measure one or more characteristics of the developed substrate at 220 prior to etching in apparatus 222. Using metrology device 240, performance parameter data PDAT 252 can be determined. Based on this performance parameter data PDAT 252, it can be further determined whether performance parameters such as overlay or critical dimensions (CD) meet the accuracy requirements specified in the developed resist. Prior to the etching step, there is an opportunity to strip the developed resist and reprocess one or more substrates 220 through the lithography cluster. Furthermore, by making small adjustments over time, the measurement results from metrology device 240 can be used to maintain the accurate performance of the patterning operations in the lithography cluster, thereby reducing or minimizing the risk of manufacturing defective products that require rework. Of course, measurement device 240 and / or one or more other measurement devices (not shown) can be used to measure one or more characteristics of the substrates 232, 234 being processed and / or the substrate 230 entering.

[0039] Typically, patterning in a photolithography (LA) apparatus is one of the most critical steps in the process, involving the precise dimensional marking and placement of structures on a substrate W. To help ensure this high precision, techniques such as... Figure 3 The schematic depiction combines three systems within a control environment. One of these systems is a lithography tool 200, which is (virtually) connected to a metrology device 240 (the second system) and a computer system CL 250 (the third system). The aim of this environment is to optimize or improve the collaboration between these three systems to enhance the overall so-called “process window” and provide one or more tight control loops to help ensure that patterning performed by the lithography device LA remains within the process window. The process window defines a range of multiple process parameter values ​​(e.g., two or more process parameters selected from dose, focus, overlay, etc.) within which a particular manufacturing process produces a defined result (e.g., a functional semiconductor device). Typically, within this range, variations in process parameter values ​​in the lithography or patterning process are allowed while producing an appropriate structure (e.g., defined according to an acceptable range of CD (such as ±10% of the nominal CD)).

[0040] The computer system CL can use a portion of the design layout to be patterned to predict which one or more resolution enhancement techniques will be used, and perform computational lithography simulations and calculations to determine which patterning apparatus layout and lithography setup will achieve the maximum total process window (within) the patterning process. Figure 3 (Depicted by double arrows in the first turntable SC1). Typically, resolution enhancement techniques are arranged to match the patterning possibilities of the lithography apparatus LA. The computer system CL can also be used (e.g., using input from the metrology tool MET) to detect where the lithography apparatus LA is currently operating within the process window, to predict whether suboptimal processing (in...) is occurring. Figure 3 The defect is due to the arrow pointing to "0" in the second turntable SC2.

[0041] The measurement tool MET can provide input to the computer system CL for accurate simulation and prediction, and can provide feedback to the lithography apparatus LA to identify possible drifts in, for example, the calibration status of the lithography apparatus LA. Figure 3 (This is depicted by multiple arrows in the third turntable SC3).

[0042] Computer system 250 can control the processing based on a combination of: (i) “preprocessing measurement data” (e.g., including scanner measurement data LADAT 254 and external preprocessing measurement data ExDAT 260) and (ii) performance data or “postprocessing data” PDAT 252, wherein (i) “preprocessing measurement data” is associated with the substrate prior to processing in a given processing step (e.g., photolithography step), and (ii) “postprocessing data” PDAT 252 is associated with the substrate after processing.

[0043] The first set of preprocessed measurement data LADAT 254 (referred to herein as scanner measurement data, as it is data generated by the lithography apparatus LA 200 or a scanner) may include alignment data routinely obtained by the lithography apparatus LA 200 using alignment sensors AS in measurement station 202. Alternatively, or in addition to alignment data, the scanner measurement data LADAT 254 may include height data obtained using a level sensor LS, and / or “wafer quality” signals from alignment sensors AS, etc. Thus, the scanner measurement data LADAT 254 may include alignment grids for the substrate, as well as data related to substrate deformation (flatness). For example, the scanner measurement data LADAT 254 may be generated by the measurement station MEA 202 of the dual-stage lithography apparatus LA 200 before exposure (e.g., because this typically includes alignment and level sensors), enabling simultaneous measurement and exposure operations. Such dual-stage lithography apparatuses are known.

[0044] Increasingly, (e.g., standalone) external pre-exposure metrology tools, such as the ExM 270, are used for measurements prior to exposure on lithography apparatuses. This external pre-exposure metrology tool, the ExM 270, differs from the MEA 202 measurement station on a dual-stage lithography apparatus like the LA 200. Any pre-exposure measurements performed within the track are also considered external measurements. To maintain sufficient exposure throughput, the scanner metrology data LADAT (e.g., alignment grids and substrate deformation grids) measured by the MEA 202 is based on a desired, sparser set of measurements. This typically means that such a measurement station cannot collect enough measurement data for higher-order corrections, particularly beyond the third order. Furthermore, the use of opaque hard masks can make it difficult to accurately measure aligned wafer grids.

[0045] The external pre-exposure metrology tools ExM 270 enable denser measurements on each substrate prior to exposure. Some of these ExM 270 pre-exposure metrology tools measure and / or predict wafer grid deformation at a throughput equal to or faster than that of a scanner, and have a much higher measurement density than that achievable using alignment and level sensors, even when such sensors are included within a separate measurement station MEA202. Pre-exposure metrology tools include, for example, substrate shape inspection tools and / or separate alignment stages.

[0046] Although Figure 3 Separate memories 252, 254, and 260 are shown for each of the performance data PDAT, scanner measurement data LADAT, and external pre-exposure data ExDAT. However, it should be understood that these different types of data may be stored in a common storage unit or may be distributed across more storage units from which specific data items may be retrieved when needed.

[0047] To represent alignment measurements on the wafer and / or in the field, an alignment model is used. The first objective of the alignment model is to provide a mechanism for interpolating and / or extrapolating available measurement data across the entire wafer, allowing the creation of an exposure grid on each die. The measurement data will be sparse because, from a modeling perspective, measuring as many measurement areas as desired is simply impractical: the time and therefore throughput overhead would be prohibitively high. The second objective of the alignment model is to provide noise suppression. This can be achieved by using fewer model parameters than the measurement results.

[0048] While standard models may use fewer than 10 parameters, advanced alignment models typically use more than 15, or even more than 30, parameters. Examples of advanced models are the High-Order Wafer Alignment (HOWA) model, and alignment models based on Region Alignment (ZA) and Radial Basis Functions (RBF). HOWA is an open-source technique based on third-order and higher-order polynomial functions. RBF modeling is described in US2012218533A1, which is incorporated herein by reference. Different versions and extensions of these advanced models can be designed. Advanced models generate complex descriptions of wafer gratings that are corrected during exposure of the target layer. The latest versions of RBF and HOWA provide particularly complex descriptions based on dozens of parameters. This means that a large number of measurements are required to obtain a wafer grating with sufficient detail.

[0049] Currently, polynomial-based models such as HOWA are primarily used to model inter- and intra-field wafer deformation. However, because of the strong non-uniform distribution of polynomials on the wafer, this becomes even worse for higher-order polynomials. Therefore, fitting a polynomial model to a sparse set of alignment measurements can lead to strong modeling artifacts near the wafer edges (or, in the case of intra-field wafer alignment IFWA).

[0050] RBF modeling can address some of these modeling artifact problems. RBF modeling essentially involves interpolation methods based, for example, on radially based thin-plate splines. However, because RBF models consist of interpolation schemes, they lack noise suppression. Furthermore, RBF models are not true models in the sense that the model function depends on the specific wafer alignment mark layout. In addition, there is resistance in industry to fundamental changes, such as moving from more familiar polynomial-based modeling to RBF modeling.

[0051] US2012218533A1 describes an RBF modeling method comprising the steps of: generating radial basis functions using marked measurement locations; and using the generated radial basis functions as basis functions across the substrate to calculate model parameters of the substrate within the device. RBFφ It is a real-valued function whose value depends only on the distance from the origin, or alternatively on the distance x from some other point called the center c, such that:

[0052]

[0053] The functional approximation using RBF can be established in the following form:

[0054]

[0055] Where the approximate function It is represented as the sum of N radial basis functions (RBFs), each of which is associated with a distinct center c and is determined by appropriate coefficients w. i Weighted, and ||·|| is the notation used for the standard Euclidean vector norm. This can satisfy the interpolation condition Y(x) i )=y i The method of calculating weight w using the least squares method. i A linear system with weighted coefficients might look like this:

[0056]

[0057] Where φ ij =φ(r ij ), and r ijThis is the distance between two points (e.g., the distance between two markers). It can be noted that there are as many weighting coefficients (i.e., degrees of freedom) as there are interpolation conditions. The resulting system of equations is nonsingular (invertible) under very mild conditions and therefore has a unique solution. For many radial basis functions (RBFs), the only restriction is that at least three points are not on a straight line.

[0058] Several alternatives to the RBF are possible, such as Gaussian functions, inverse basis functions, multiple quadratic basis functions, inverse quadratic basis functions, spline-degree k-basis functions, and thin-plate spline basis functions. Note that other RBFs are also possible. Two main classes of RBFs are given below: infinite smooth (whose derivative exists at every point); and spline (whose derivative may not exist at some points). Thin-plate spline (TPS) refers to a physical simulation involving the bending of a thin metal sheet. In the physical setting, the deflection is in the z-direction perpendicular to the sheet plane. To apply this idea to the problem of substrate deformation in photolithography, the lifting of the sheet can be interpreted as displacement in the x or y coordinates within the plane. TPS has been widely used as a non-rigid transformation model in image alignment and shape matching.

[0059] Therefore, it is proposed to retain the polynomial-based (first) model, but use a second model to overcome the aforementioned problems near the wafer / field edges of the polynomial model. In this way, the second model should be free from the same edge performance issues. Thus, edge performance can be improved while maintaining the polynomial model as the foundation.

[0060] A suitable model for the second approach would be the RBF model, as it exhibits good interpolation and extrapolation (and therefore wafer edge) characteristics, independent of measurement layout. Therefore, such an approach utilizes the RBF model for what it excels at: interpolation and extrapolation. By using a dense grid, the polynomial problem near the wafer edge disappears.

[0061] Figure 4 This is a flowchart describing the basic steps of this method in a conceptual implementation, which includes:

[0062] 400. Model the second model (e.g., the RBF model) using a first layout (e.g., a standard layout, or a similar fine wafer alignment layout based on a relatively sparse measurement scheme);

[0063] 401. Evaluate the second model on a second layout (e.g., a denser or very denser layout including positions at 10x, 100x, or 1000x the standard layout); this layout can uniformly cover the entire wafer. In this way, the second model performs interpolation / extrapolation;

[0064] 402. Using the desired model order (e.g., 3rd or higher), fit the desired first model (polynomial model) to the second model on a very dense second layout. This model is thus modeled on a dense layout, where the first model reduces the model order.

[0065] 403. Use the fitted first model for alignment; for example, to determine the wafer grid for exposure and control.

[0066] The following are computationally expensive: the conceptual implementation, and particularly the evaluation of the RBF model on a very dense layout, and the fitting of the polynomial model to a very dense layout. Therefore, a more practical implementation could include skewed polynomial fitting based on RBF interpolation. More specifically, such an implementation could include combining this with wafer alignment model mapping (WAMM) on a sparse measurement layout, transforming the process into a skewed subspace model or a generalized least squares fitting model. All these concepts will be described in more detail below. It can be shown that this approach can be entirely equivalent to... Figure 4 A conceptual approach is proposed. In this way, a very dense layout is used solely for the calibration of the modeling technique. This can be done offline because it requires no measurement data; only the (sparse) measurement layout and model type used are needed as inputs to the calibration, and no training is required. To achieve this, tilt fitting techniques, subspace modeling, and WAMM are performed. Another equivalent subspace modeling approach will also be described, which involves determining the subspace with minimum bending energy.

[0067] wafer alignment model mapping and subspace mapping

[0068] In Wafer Alignment Model Mapping (WAMM), model parameters are modified by applying a linear transformation to them. This linear transformation can be considered as matrix multiplication: the model parameters are arranged together as column vectors, which are multiplied by a matrix to obtain a new column vector of model parameters. The matrix involved is called the model mapping matrix. The primary purpose of the model mapping matrix is ​​to act as a linear filter: its aim is to improve the performance of wafer alignment (e.g., overlay) by filtering out components (shapes) that degrade overlay and modifying the remaining shape to further improve overlay. The concept of wafer alignment model mapping is described in WO2017060054 (which is incorporated herein by reference) and will now be briefly described.

[0069] In a known correction strategy known as Advanced Process Correction (APC), the APC control loop calculates / optimizes the APC exposure correction in a feedback loop; that is, based on past alignment and overlay data, it attempts to approximate the “true wafer deformation” as closely as possible to the sum of the following two factors: the measured wafer deformation (i.e., matrix X, which includes wafer alignment model parameters obtained from measurements of alignment sensors on multiple wafers); and the APC exposure correction C. apc :

[0070]

[0071] WAMM includes replacing the approximate method used for this APC correction design with:

[0072]

[0073] Where matrix M wamm This is the model mapping matrix, which defines the mapping from the wafer alignment model parameter space X to the overlay model parameter space Y. By performing model mapping, overlay can be improved compared to earlier APC approximations. The calibration calculations in the control loop can be modified so that not only the calculation process corrects C... apc Furthermore, the model mapping matrix M is calculated. wamm If a nonlinear mapping is desired, a more generalized mapping function can be used instead of a mapping matrix. The computation of model mappings based on historical data can be accomplished using any suitable training method. For example, methods similar to Wiener filters can be applied.

[0074] The dimensionality of the mapped substrate model can also be reduced, for example, by applying known statistical techniques. For instance, by applying singular value decomposition to matrix M, the above equation can be written as:

[0075]

[0076] Where U and V are orthogonal coordinate transformation matrices, and S is the inclusion matrix M. wammThe diagonal matrix of singular values ​​of S. In this case, the expressions XU and YV can be viewed as subspaces of the parameter spaces of X and Y, respectively. Each subspace has a dimension defined by the basis vectors according to the parameters of the parameter space. Each individual basis vector from XU is mapped to a single basis vector YV, where the corresponding singular value from S serves as a scaling factor. By removing selected singular values ​​(setting them to zero), the mapping can be restricted to a linear subspace of the original model parameter space. Removing singular values ​​is equivalent to removing columns from matrices U and V. Note that the values ​​in S, XU, and YV can be used to select which "subspace" parameters to reject and which "subspace" parameters to maintain. For example, S provides the scaling of the parameters. If the scaling factor is very low (close to 0), it means that the subspace basis vectors are irrelevant to overlay and can be discarded. Discarding these terms helps reduce processing and makes important contributions more visible if you want to understand the cause of overlay errors. If S, combined with very weak model parameters in XU, provides (extremely) large singular values ​​(scaling factors), it may be desirable to remove such basis vectors. Such contributions are neither robust nor reliable, and may introduce relatively large errors in the input measurements when random variations are present. Noise suppression (system factor) is improved by reducing the dimensionality of the model space.

[0077] Generalized and oblique projection least squares wafer alignment fitting

[0078] The concept of a tilted projection model will now be described. When moving from a densely aligned grid to a sparsely aligned grid, the orthogonality between the correctable and uncorrectable components changes: in a dense layout, the correctable and uncorrectable components are orthogonal, while in a sparse layout, they are not. This non-orthogonality associated with the sparse layout leads to crosstalk. According to this disclosure, crosstalk can be reduced via tilt fitting techniques or tilted projection least squares fitting, wherein the tilt fitting technique includes modifying the inner product elements associated with the sparse layout such that the orthogonality between the correctable and uncorrectable components is similar to that of the dense layout, and the tilted projection least squares fitting includes basing the inner product on the sparse layout on different (non-orthogonal) foundations.

[0079] According to this disclosure, generalized least squares fitting is discussed below. It can be used...<x,y> =x T The inner product is calculated using y, where x and y are column vectors of measurement data (i.e., alignment measurement data or overlay measurement data) contained at different marked locations on the wafer. The norm associated with this inner product can then be calculated as follows:

[0080] Now, suppose y includes alignment data (or uncorrected overlay data) of dense measurements associated with a dense layout, i.e., the first measurement data. Then, y can be used... correctable =M y cy To calculate the correctable component (y) of dense layout data correctable ), where M y The model function includes sampling at densely labeled locations, and c y This includes the model's fit coefficients to densely laid-out data.

[0081] In the case of ordinary least squares, the aforementioned least squares norm is used to optimize the fitting coefficients. It can be seen that... The result of this optimization is calculated, where the '+' operator represents the pseudo-inverse of the matrix.

[0082] By combining the previous y correctable and c y The two equations,

[0083]

[0084] Where P y It projects the measured data y onto the model matrix M. y The columns span an orthogonal projection matrix over the space, which produces a correctable component y. correctable Therefore, conceptually, conventional wafer alignment using least-squares fitting can be considered as: an orthogonal projection of measurement data onto the space spanned by the model using inner products. The skewed inner product between two column vectors x and y can be calculated as...<x,y> w =x T W r Wy and the slant norm is The matrix W can be considered as a basis transformation matrix (i.e., a tilted inner product matrix). According to this disclosure, the inner product and norm are new inner product and norms defined on a new tilted basis. Consider x containing sparse wafer alignment measurement data (e.g., measurement data) and y describing dense wafer alignment data. It can be seen that the fitting coefficients from the generalized least squares fit using the tilted norm can be written as:

[0085]

[0086] Where M x This is the model matrix used for sparse measurement data. These fitting coefficients c w It can be used to approximate dense layout alignment data and optimize the skewed inner product matrix W.

[0087] An approximation of the wafer alignment model associated with a sparse layout and a model associated with a dense layout are performed together. This wafer alignment model can be calculated by performing the following equation:

[0088]

[0089] In one embodiment, the coefficients in matrix W are optimized such that the wafer alignment model associated with a sparse layout approximates the results for dense layout data (or uncorrected overlay data) in a similar manner. The coefficients of W are determined by performing the following equation:

[0090]

[0091] The following is a brief discussion of tilted projective least squares fitting. In tilted projective least squares fitting, the following equations are performed:

[0092]

[0093] Where P is the tilt projection matrix. Since the uncorrectable component on a dense alignment layout is not orthogonal to the correctable component on a sparse alignment layout, it can be blocked using the tilt projection matrix, provided that the correctable and uncorrectable components are at least linearly independent of the sparse grid.

[0094] In one embodiment, matrix P (i.e., the tilt projection matrix) is optimized such that the sparse wafer alignment model results match the dense alignment data (or dense decorrected overlay data) as closely as possible. For example, the coefficient values ​​in matrix P are determined under the constraint that matrix P is a tilt projection matrix (e.g., a diagonalized matrix where each eigenvalue is equal to 0 or 1). In one embodiment, the optimization is performed iteratively by performing the following model such that the coefficient values ​​of P gradually decrease (e.g., in one embodiment, minimize) the aforementioned discrepancies.

[0095]

[0096] Equivalence of WAMM and tilted projection / generalized LS fitting with steps 401-403

[0097] The process described in steps 401 through 403 involves linear operations because each step is linear. This means that the three steps together can be described by a single matrix F, which maps the measurement results to the polynomial model parameters. Any matrix, and therefore matrix F, can be decomposed into a skewed subspace model (or generalized least squares fitting) in combination with a WAMM. Thus, the conceptual approach implemented by steps 401 through 403 can be transformed into performing the following steps on a sparse layout: skew fitting, subspace modeling, and WAMM.

[0098] This is described through the following steps and equations:

[0099] 1) After RBF interpolation on the sparse layout, perform polynomial modeling:

[0100]

[0101] 2) Using WAMM for skewed subspace modeling:

[0102]

[0103] F = M wamm M subspace (WM 1，s M subspace ) + W

[0104] 3) Use WAMM to transform the modeling into a skewed subspace:

[0105] M subspace =range(F)

[0106] P = M 1，s M subspace (FM 1，s M subspace ) + F

[0107] W = (M 1，s M subspace ) + P = (FM) 1，s M subspace ) + F

[0108] M wamm =FM 1，s

[0109] In these equations, M 1，s M 1，d These are the model matrices of the first (polynomial) model on the sparse and dense layouts, respectively, M. 2，s M 2，d Here, P is the model matrix of the second (RBF) model on sparse and dense layouts, respectively; P is the tilt projection matrix; W is the matrix defining the inner product of the generalized least squares fit; and M is the matrix of the second (RBF) model on sparse and dense layouts, respectively. wamm It is the model mapping matrix, and M subspace It is a subspace matrix. The '+' operator represents the pseudo-inverse of the matrix. M subspace The columns are selected to form the basis of the range of F.

[0110] Using this method, modeling the tilted polynomial model shows a significant improvement at the wafer edges compared to regular polynomials (e.g., HOWA). Additionally, the risk of overfitting is eliminated: 7th-order polynomial models or higher-order polynomials can be used without issue, as the number of measurements in typical measurement schemes is insufficient to fit a 7th-order polynomial using conventional least-squares methods. Thus, the first model can be a 3rd, 4th, 5th, 6th, 7th, or higher-order model.

[0111] Model subspace selection using bending energy and Tikhonov regularization

[0112] The proposed bending energy inner product can be used to improve polynomial fitting, either in the methods described above or generally for any polynomial or other alignment model (although the concept is not limited to polynomial models; however, they can be used for any model where bending energy (or related parameters) can be computed). This approach can include using singular value decomposition and / or performing Tikhonov regularization using bending energy to create a polynomial subspace with minimum bending energy for a given layout. This approach can, for example, be used to determine the aforementioned subspace matrix M. subspace However, note that the subspace embodiment with minimum bending energy only requires subspace modeling; tilt fitting and WAMM are not required.

[0113] Bending energy principle

[0114] Both concepts rely on the bending energy product.<u,v> Usage:

[0115]

[0116] Note that the bending energy is zero for DC and a linear slope, so the inner product is defined only on the orthogonal complement of DC and the slope (3 parameters). As an alternative to bending energy, the technique described here can be based on in-plane deformation energy or similar parameters.

[0117] Note the bending energy E b (u) is:

[0118]

[0119] The bending energy expressed in terms of inner product is:

[0120]

[0121] If the fitted model u(x, y) is:

[0122]

[0123] The bending energy of the fitted model, expressed in terms of model parameter p, is:

[0124]

[0125] And the bending covariance matrix of the model function [M] cov ] ij for

[0126]

[0127] Tikhonov regularization using bending energy

[0128] For the model matrix M, evaluate the fitting function on a sparse layout:

[0129] [M] ij =p j (x i y i )

[0130] Perform ordinary least squares fitting to produce coefficients c. lsq :

[0131]

[0132] Rewrite it as including Tikhonov regularization based on bending energy, thus producing coefficient c tikhonov :

[0133]

[0134] The solution to this is:

[0135] c tikhonov =(M T M+λM cov ) -1 M T dx

[0136] Model subspace selection using SVD truncation

[0137] Figure 5 This includes, according to one embodiment, the selection of a model subspace (e.g., determining the aforementioned subspace matrix M). subspace The steps of the method are as follows. This method is an alternative to any other subspace mapping method described, for example, in WO2017060054 and outlined above.

[0138] In step 500, bending energy orthogonalization of the model matrix is ​​performed on the infinitely dense (continuous) layout (e.g., first / polynomial) because the covariance matrix is ​​based on the integral over the wafer). This may include Cholesky factorization M of the bending covariance matrix. cov (The linear portion is excluded because there is no bending energy):

[0139] M cov =R T R

[0140] The bending energy orthogonalization of the model matrix can then include (based on Tikhonov regularization implementation):

[0141]

[0142]

[0143] In step 501, the linear component (e.g., typically 6 linear parameters) is removed from the model matrix; where the linear model can be:

[0144] [L] i1 =1, [L] i2 =x i [L] i3 =y i ,

[0145] In step 502, the singular value decomposition (SVD) of the model matrix on the sparse layout is calculated and truncated. This includes performing SVD on the standard orthogonal curved model matrix:

[0146]

[0147] Using Tikhonov regularization, the following solution is produced:

[0148]

[0149]

[0150] Other processing is certainly possible; for example, without regularization, this step could produce:

[0151]

[0152] And it has a subspace equal to the SVD truncation:

[0153]

[0154] Another regularization strategy based on Martin Fuhry and Lothar Reichel's publication "A new Tikhonov regularization method" can produce:

[0155]

[0156] In step 503, the corresponding subspace matrix is ​​calculated. Subspace modeling is generated:

[0157]

[0158] The model matrix M has the first model energy with standard orthogonal bending energy and orthogonal SVD sorting. ortho It can be determined as:

[0159]

[0160] The minimum bending energy subspace is equal to the truncated orthogonal model matrix, therefore:

[0161] M subspace =R -l V trunc =R -l V(:,1:N par )

[0162] The calculation of the bending covariance matrix for polynomial models has been described. For the RBF model K; for example:

[0163]

[0164] The RBF problem with finite bending energy constraints becomes:

[0165]

[0166] Pw=0

[0167] And the bending energy is:

[0168]

[0169] Note that for the RBF model, the bending energy extends to infinity across the entire space, while for the polynomial model, the bending energy is considered only within the wafer radius. This is because an expression for the RBF bending energy within the wafer radius has not yet been derived, and such an expression is expected to be very complex.

[0170] While specific references are made to the use of photolithography apparatus in IC manufacturing herein, it should be understood that the photolithography apparatus described herein can have other applications. Possible other applications include: fabrication of integrated optical systems, magnetic domain memory, flat panel displays, liquid crystal displays (LCDs), guiding and detecting patterns for thin-film magnetic heads, etc. In this regard, depending on the type of product being manufactured, the “substrate” processed can be a semiconductor wafer, or it can be any other substrate.

[0171] Although embodiments of the invention may be specifically referred to herein in the context of a lithography apparatus, these embodiments can be used in other apparatuses. Embodiments of the invention can form part of a patterning apparatus, inspection apparatus, measurement apparatus, or any apparatus that measures or processes objects such as wafers (or other substrates) or masks (or other patterning apparatuses). These apparatuses are commonly referred to as lithography tools. Such lithography tools can use vacuum conditions or ambient (non-vacuum) conditions.

[0172] In this document, the terms “radiation” and “beam” are used to cover all types of radiation, including ultraviolet radiation (e.g., with wavelengths of 365 nm, 248 nm, 193 nm, 157 nm, or 126 nm) and EUV (extreme ultraviolet radiation, e.g., with wavelengths in the range of about 5 nm to 100 nm).

[0173] As used herein, the terms "mask," "mask," or "patterning apparatus" can be broadly interpreted to refer to a general patterning apparatus used to impart a patterned cross-section to an incident radiation beam, corresponding to a pattern to be generated in a target portion of a substrate. The term "optical valve" may also be used herein. Examples of such patterning apparatuses, besides classic masks (transmission or reflection, binary, phase-shifting, hybrid, etc.), include programmable mirror arrays and programmable LCD arrays.

[0174] Although specific reference has been made above to the use of embodiments of the invention in the context of optical lithography, it should be understood that, where the context permits, the invention is not limited to optical lithography and can be used in other applications (e.g., imprint lithography).

[0175] As used herein, the terms “optimize” and “optimize” refer to or imply adjusting apparatus (e.g., lithography apparatus), processes, etc., to give the results and / or processes more desirable characteristics, such as higher projection accuracy of the designed pattern onto the substrate, a larger process window, etc. Therefore, as used herein, “optimize” and “optimize” refer to or imply a process that identifies one or more values ​​of one or more parameters that, compared to an initial set of one or more values ​​of these parameters, provides an improvement (e.g., local optimization) in at least one relevant metric. “Optimal” and other relevant terms should be interpreted accordingly. In one embodiment, optimization steps may be applied iteratively to provide further improvements in one or more metrics.

[0176] Various aspects of the invention can be implemented in any convenient form. For example, embodiments can be implemented by one or more suitable computer programs that can be carried on suitable carrier media, which can be tangible carrier media (e.g., disks) or intangible carrier media (e.g., communication signals). Embodiments of the invention can be implemented using suitable means, which can specifically take the form of a programmable computer running computer programs arranged to implement the methods described herein.

[0177] In the block diagram, the illustrated components are depicted as discrete functional blocks; however, the embodiments are not limited to systems where the functions described herein are organized as shown. The functionality provided by each component may be provided by software or hardware modules that are organized differently from those currently described. For example, such software or hardware may be mixed, combined, replicated, decomposed, distributed (e.g., within a data center or geographically), or otherwise organized differently. The functionality described herein may be provided by one or more processors of one or more computers executing code stored on a tangible, non-transitory, machine-readable medium. In some cases, a third-party content delivery network may host some or all of the information transmitted over the network, in which case, to some extent, the information (e.g., content) is considered to be supplied or otherwise provided, and that information can be provided by sending an instruction to retrieve the information from the content delivery network.

[0178] Unless otherwise specifically stated, as is evident from the discussion, it should be understood that throughout the specification, the use of terms such as “processing,” “calculation,” “operation,” and “determining” refers to the actions or processes of a particular device (such as a dedicated computer or similar dedicated electronic processing / computing equipment).

[0179] Readers should understand that this application describes several inventions. These inventions are not intended to be divided into multiple separate patent applications, but rather to be grouped into a single document because their related subject matter makes the filing process economical. However, the obvious advantages and aspects of these inventions should not be combined. In some cases, embodiments resolve all the deficiencies mentioned herein; however, it should be understood that the invention is independently useful, and some embodiments solve only a subset of these problems or provide other unmentioned benefits that will be apparent to those skilled in the art upon reading this disclosure. Due to cost constraints, some inventions disclosed herein may not be claimed at present and may be claimed in later filings, such as continuation applications or by amendment of these claims. Similarly, due to space constraints, neither the abstract nor the abstract portion of this document should be considered a comprehensive list containing all such inventions or all aspects of such inventions.

[0180] It should be understood that the specification and drawings are not intended to limit this disclosure to the specific forms disclosed, but on the contrary, the invention is intended to cover all modifications, equivalents and alternatives that fall within the spirit and scope of the invention as defined by the appended claims.

[0181] Modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in light of this specification. Accordingly, this specification and drawings should be interpreted as illustrative only and intended to teach those skilled in the art the general manner of performing the invention. It should be understood that the forms of the invention shown and described herein are considered examples of embodiments. Elements and materials may be substituted for those shown and described herein, components and processes may be reversed or omitted, certain features may be utilized independently, and embodiments or features of embodiments may be combined, all of which will be apparent to those skilled in the art after benefiting from this specification. Changes may be made to the elements described herein without departing from the spirit and scope of the invention as described in the appended claims. The headings used herein are for organizational purposes only and are not intended to limit the scope of this specification.

[0182] As used throughout this application, the word “may” is used in a permissive sense (i.e., meaning possible) rather than a mandatory sense (i.e., meaning must). The words “comprising,” “including,” and “including,” etc., mean including but not limited to. As used throughout this application, the singular forms “a,” “an,” and “the” include plural indicators unless the content explicitly states otherwise. Thus, for example, a reference to an element “a” or “one” includes a combination of two or more elements, although other terms and phrases such as “one or more” are used for one or more elements. Unless otherwise stated, the term “or” is non-exclusive, i.e., it encompasses both “and” and “or.” Terms describing conditional relationships, such as “in response to X, Y,” “on X, Y,” “if X, Y,” “when X, Y,” etc., encompass causal relationships where the antecedent is a necessary causal condition, a sufficient causal condition, or a contributing causal condition to the result; for example, “state X occurs when condition Y is acquired” is used interchangeably with “X occurs only on Y” and “X occurs on Y and Z.” Such conditional relationships are not limited to results immediately following the acquisition of the prerequisites, as some results may be delayed, and in conditional statements, prerequisites are connected to their results; for example, prerequisites relate to the probability of the result occurring. Statements in which multiple attributes or functions are mapped to multiple objects (e.g., one or more processors performing steps A, B, C, and D) cover all such attributes or functions mapped to all such objects, as well as subsets of attributes or functions mapped to subsets of attributes or functions (e.g., all processors where each processor performs steps A and D, and processor 1 performs step A, processor 2 performs a portion of steps B and C, and processor 3 performs a portion of step C and step D), unless otherwise stated. Furthermore, unless otherwise stated, statements that a value or action is “based on” another condition or value include cases where the condition or value is the only factor and cases where the condition or value is one of multiple factors. Unless otherwise stated, statements that “each” instance of certain sets has certain properties should not be construed as excluding cases where members of a larger set with the same or similar properties do not have that property; that is, each does not necessarily mean every and every. References selected from a scope include the endpoints of the scope.

[0183] In the above description, any process, description, or block in the flowchart should be understood as representing a module, segment, or portion of code including one or more executable instructions for implementing a specific logical function or step in the process, and alternative implementations are included within the scope of exemplary embodiments of this progress, wherein, depending on the function involved, the order of execution of functions may differ from the order shown or discussed, including execution substantially simultaneously or in reverse order, as understood by those skilled in the art.

[0184] While specific embodiments of the invention have been described above, it should be understood that the invention may be practiced in ways other than those described. The above description is intended to be illustrative rather than restrictive. Therefore, it will be apparent to those skilled in the art that modifications can be made to the described invention without departing from the scope of the following claims.

[0185] Other aspects of the invention are set forth in the following numbered clauses:

[0186] 1. A method for modeling measurement data on a substrate-related region during a photolithography process, comprising:

[0187] a) Obtain measurement data related to the first layout;

[0188] b) Based on the first layout, model the second model;

[0189] c) Evaluate the second model on a second layout that is denser than the first layout; and

[0190] d) Fit the first model to the second model according to the implementation of the second layout.

[0191] 2. The method according to Clause 1, wherein the first layout corresponds to a marker position, and the measurement data is obtained from the marker position.

[0192] 3. The method according to Clause 1 or 2, wherein the second layout uniformly covers the entire wafer.

[0193] 4. The method according to any of the preceding clauses, wherein the second layout relates to a position 10 times or more the same as the second layout.

[0194] 5. The method according to any of the preceding clauses, wherein the first model is a polynomial model.

[0195] 6. The method according to any of the preceding clauses, wherein the first model is a higher-order polynomial model.

[0196] 7. The method according to any of the preceding clauses, wherein the second model includes a model having better interpolation and / or extrapolation properties than the first model.

[0197] 8. The method according to any of the preceding clauses, wherein the second model is a radial basis function model.

[0198] 9. The method according to any of the preceding clauses includes performing a process equivalent to steps b), c) and d) instead of these steps to fit the first model to the first layout, said equivalent process being based on subspace modeling or generalized least squares modeling.

[0199] 10. The method described under Clause 9, comprising:

[0200] In the first layout, the skewed subspace model or the generalized least squares model is modeled; and

[0201] Perform model mapping operations on skewed subspace models or generalized least squares models.

[0202] 11. The method according to Clause 10, wherein the skewed subspace model is determined by performing a skew fit on the subspace matrix.

[0203] 12. The method according to any one of clauses 9 to 11, wherein the method further comprises applying a model mapping matrix on the first layout.

[0204] 13. The method according to Clause 12, wherein the model mapping matrix represents the correlation between the first model and the second model.

[0205] 14. The method according to Clause 9, wherein the subspace modeling comprises: determining a subspace with minimum bending energy by determining a subspace with minimum bending energy for the first layout.

[0206] 15. The method according to Clause 14 includes determining the minimum subspace matrix of bending energy by performing the following steps:

[0207] Perform bending energy orthogonalization on the first model matrix;

[0208] Remove the linear component from the first model matrix;

[0209] Calculate and truncate the single-valued decomposition of the first model matrix; and

[0210] Calculate the subspace matrix corresponding to the truncated decomposed model matrix obtained from the previous steps.

[0211] 16. The method according to Clause 15, wherein performing bending energy orthogonalization comprises: determining a bending covariance matrix of a model function of the first model matrix based on a description of the bending energy within the substrate; and

[0212] Factorize the bending covariance matrix.

[0213] 17. The method according to any of the preceding clauses, wherein the fitting step is regularized by using Tikhonov regularization of bending energy.

[0214] 18. The method according to Clause 17, wherein the Tikhonov regularization is based on a bending covariance matrix, the bending covariance matrix being based on a description of the bending energy within the substrate.

[0215] 19. The method according to any of the preceding clauses, wherein the second layout is used only for calibrating the first model to the second model.

[0216] 20. The method according to Clause 19, wherein the calibration is performed offline based solely on the description of the first layout and the first and second models.

[0217] 21. The method according to any of the preceding clauses includes using the first model to determine the wafer grid for exposure and control of the lithography process.

[0218] 22. A method for determining a polynomial subspace with minimum bending energy for a given model layout, comprising:

[0219] Perform bending energy orthogonalization on the model matrix describing the model;

[0220] Remove the linear component from the model matrix;

[0221] Calculate and truncate the single-valued decomposition of the model matrix; and

[0222] Calculate the subspace matrix corresponding to the truncated decomposed model matrix obtained from the previous steps.

[0223] 23. The method according to Clause 22, wherein performing bending energy orthogonalization comprises: determining the bending covariance matrix of the model function of the first model matrix; and

[0224] Factorize the bending covariance matrix.

[0225] 24. A method for regularizing the fitting of a model to measurement data from a substrate; comprising:

[0226] The bending covariance matrix is ​​calculated based on a description of the bending energy within the substrate; and from the bending covariance matrix, a Tikhonov regularization term is determined for the fitting.

[0227] 25. A computer program comprising program instructions operable, when run on a suitable device, to perform the method described in any one of clauses 1 to 24.

[0228] 26. A nontransitory computer program carrier comprising the computer program described in Clause 25.

[0229] 27. A processing apparatus, comprising:

[0230] The non-transitory computer program carrier as described in Clause 26; and

[0231] A processor operable to run the computer program included on the non-transitory computer program carrier.

[0232] 28. A photolithography apparatus, comprising:

[0233] Align with the sensor;

[0234] A support for a pattern forming apparatus, used to support the pattern forming apparatus;

[0235] Substrate support, which is used to support the substrate; and

[0236] The processing apparatus as described in Clause 27.

[0237] 29. The lithography apparatus according to Clause 28, wherein the alignment sensor is operable to measure the substrate to obtain the measurement data.

[0238] 30. The lithography apparatus according to clause 28 or 29, wherein the processing apparatus is also operable to determine, based on the first model, corrections for controlling the patterning apparatus and / or the substrate support.

Claims

1. A method for modeling measurement data on a substrate-related region during a photolithography process, comprising: Obtain measurement data related to the first layout; Fitting a first model to the first layout, wherein the first model includes a skewed subspace model or a generalized least squares model; and Perform a model mapping operation on the first model.

2. The method of claim 1, wherein the first layout corresponds to a marker position, and the measurement data is obtained from the marker position.

3. The method of claim 1, wherein the skewed subspace model is determined by performing a skew fit on the subspace matrix.

4. The method according to claim 1, wherein the subspace modeling comprises: The minimum bending energy subspace is determined by identifying a subspace with minimum bending energy for the first layout.

5. The method of claim 4, further comprising determining the minimum bending energy subspace matrix by performing the following steps: Perform bending energy orthogonalization on the first model matrix; Remove the linear component from the first model matrix; Calculate and truncate the single-valued decomposition of the first model matrix; as well as Calculate the subspace matrix corresponding to the truncated decomposed model matrix obtained from the previous steps.

6. The method of claim 5, wherein performing bending energy standard orthogonalization comprises: Based on the description of the bending energy within the substrate, the bending covariance matrix of the model function of the first model matrix is ​​determined; as well as Factorize the bending covariance matrix.

7. The method according to any one of the preceding claims, wherein the fitting step is regularized by using Tikhonov regularization of bending energy.

8. The method of claim 7, wherein the Tikhonov regularization is based on a bending covariance matrix, the bending covariance matrix being based on a description of the bending energy within the substrate.

9. The method according to any one of the preceding claims, comprising using the first model to determine a wafer grid for exposure and control of the lithography process.

10. A computer program comprising program instructions that, when run on a suitable device, are operable to perform the method according to any one of claims 1 to 9.

11. A non-transitory computer program carrier comprising the computer program according to claim 10.

12. A processing apparatus, comprising: The non-transitory computer program carrier according to claim 11; as well as The processor is operable to run the computer program included on the non-transitory computer program carrier.

13. A photolithography apparatus, comprising: Align with the sensor; A support for a pattern forming apparatus, used to support the pattern forming apparatus; Substrate support, used to support the substrate; as well as The processing apparatus according to claim 12.

14. The lithography apparatus of claim 13, wherein the alignment sensor is operable to measure the substrate to obtain the measurement data.

15. The lithography apparatus of claim 13 or 14, wherein the processing apparatus is further operable to determine, based on the first model, corrections for controlling the patterning apparatus and / or the substrate support.

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