Method for depositing silicon-germanium layers on a substrate

Abstract

A method for heteroepitaxially depositing a silicon-germanium layer (3) on a substrate (1) includes: providing a mask layer (4) on top of the substrate (1); removing an outer portion of the mask layer (4) to provide a pathway to an annular free surface (6) of the substrate, wherein the annular free surface (6) is located in an edge region of the substrate and surrounds the remainder (5) of the mask layer (4); depositing a cylindrical silicon-germanium layer (2) on top of the annular free surface (6) of the substrate; removing the remainder of the mask layer; and depositing the silicon-germanium layer (3) on top of the substrate (1) and on top of the cylindrical silicon-germanium layer (2), the silicon-germanium layer (3) contacting the inner surface of the cylindrical silicon-germanium layer (2).

Description

Technical Field

[0001] This invention relates to a method for depositing a silicon-germanium (SiGe) layer on a substrate. Background Technology

[0002] Semiconductor devices using SiGe channels represent an interesting alternative to their silicon-only counterparts. To provide the SiGe layer for integrating the SiGe channel, the SiGe layer must typically be heteroepitaxially deposited on top of a substrate (e.g., a silicon single-crystal wafer). It is well known that due to the lattice mismatch between the substrate and the heteroepitaxial SiGe layer, dislocation stacks (DP) of misfit dislocations (MD), through-the-wire dislocations (TD), and through-the-wire dislocations (DP) form during the deposition process.

[0003] Many attempts have been made to reduce problems related to the presence of MD, TD, and DP, as well as cross-line issues that roughen the surface of heteroepitaxial SiGe layers.

[0004] US 2010 0 291 761A1 proposes providing a stress-compensating SiGe layer deposited on the back side of a substrate.

[0005] US 2010 0 317 177A1 discloses a method comprising depositing a first SiGe layer on a substrate and depositing a second SiGe layer on top of the first SiGe layer.

[0006] According to US 2004 0 075 105A1, the formation of DP can be reduced by a method comprising forming a generally relaxed capping layer on a first semiconductor layer having a plurality of TDs having a generally uniform distribution on its surface.

[0007] A recent paper (Fabrizio Rovaris, Continuum modeling of heteroepitaxy at the mesoscale: tackling elastic and plastic relaxation, University of Milano-Bicocca Department of Materials Science, Academic Year 2019 / 2020) reported that the presence of a high-defect region at the substrate edge provides a reservoir for the threaded arm, which can relax once the grown film reaches a critical thickness. As a result, a significant reduction in TD density was observed by eliminating the random nucleation of rings in the first relaxation stage. The authors of this paper (who have collaborated with the inventors of this invention) did not disclose obtaining the high-defect region at the substrate edge by depositing a stress-compensated SiGe layer on the back side of the substrate. Summary of the Invention

[0008] The purpose of this invention is to further reduce the TD density of the SiGe layer deposited on the substrate by heteroepitaxial deposition.

[0009] This objective is achieved by a method for heteroepitaxially depositing a silicon-germanium layer on a substrate, the method comprising:

[0010] A mask layer is provided on top of the substrate;

[0011] The outer portion of the mask layer is removed to provide a pathway to an annular free surface of the substrate, wherein the annular free surface is located in the edge region of the substrate and surrounds the remainder of the mask layer;

[0012] A cylindrical silicon-germanium layer is deposited on top of the annular free surface of the substrate;

[0013] Remove the remaining portion of the mask layer; and

[0014] The silicon-germanium layer is deposited on top of the substrate and on top of the cylindrical silicon-germanium layer, and the silicon-germanium layer contacts the inner surface of the cylindrical silicon-germanium layer.

[0015] The SiGe buffer layer on a silicon single-crystal substrate relaxes through heterogeneous nucleation at preferred nucleation sites, since pre-existing dislocations are absent in the substrate. It is well known that the edges of Si wafers exhibit mechanical defects that serve as preferred nucleation sites. Strain energy accumulates in the epitaxial layer during growth, and once the activation energy for the process is reached, dislocations rapidly nucleate at these sites, forming thick dislocation bundles. These mismatched dislocation bundles lead to the formation of threaded dislocation stacks because they effectively block the slip of other dislocations. Because dislocations are blocked, more dislocations need to nucleate to fully relax the layer, resulting in a higher threaded dislocation density (TDD). For a more controlled relaxation process and to prevent mismatched dislocation bundles, a uniformly distributed dislocation source with a low activation energy is required.

[0016] This invention proposes a method for realizing such a source in the edge region of a SiGe layer. The edge reservoir consists of a relaxed or partially relaxed SiGe layer (hereinafter referred to as a cylindrical SiGe layer) deposited prior to the SiGe layer. The SiGe layer and the cylindrical SiGe layer have vertical direct contact, or both vertical direct contact and horizontal contact. By freely sliding towards the center of the wafer after reaching a critical thickness, pre-existing dislocations contained in the edge reservoir are used to relax the SiGe layer during the initial relaxation stage, thereby leaving extremely long mismatched dislocation segments unobstructed. This process prevents the formation of thick dislocation bundles through heterogeneous nucleation at the wafer edge, thereby preventing DP formation and reducing total TDD.

[0017] Although the following description relates to depositing a SiGe layer on a silicon single-crystal substrate, other substrates such as silicon-on-insulator (SOI) wafers may also be used. According to a preferred embodiment of the invention, the substrate is a silicon single-crystal wafer having a diameter of 200 mm or 300 mm.

[0018] To provide a cylindrical SiGe layer at the edge of the substrate, a masking scheme (means) is employed. In principle, any masking mechanism (mechanism) used to temporarily exclude SiGe layer deposition in the surface area of ​​the substrate can be used. According to a preferred embodiment of the invention, an oxide material such as SiO2, for example, a low-temperature oxide (LTO), is used as the masking material. LTO can be deposited on top of the substrate by chemical vapor deposition (CVD) in an atmosphere containing silane (SiH4) and oxygen (O2) at a temperature between 300°C and 500°C. Alternatively, other known methods for depositing oxide layers can be used, or the oxide layer can be grown by dry oxidation in a rapid thermal annealing (RTP) furnace at a temperature between 850°C and 1200°C.

[0019] Next, the mask layer is removed in the edge region of the substrate to provide an annular free surface extending from the edge of the substrate toward the center of the substrate. The mask layer in the edge region can be removed, for example, by wet etching using hydrofluoric acid or wet etching using ammonium fluoride and hydrofluoric acid, or by plasma etching using, for example, CF4. According to one embodiment of the invention, the mask layer in the edge region of the substrate can be removed by placing the substrate face down on a support and introducing HF fumes into the process chamber, the HF fumes diffusing between the support and the mask corroding a mask portion having a width of up to 1.5 mm.

[0020] According to one embodiment of the invention, the annular free surface of the substrate extends radially from the edge of the substrate toward its center at a distance preferably not less than 200 μm and not more than 1.5 mm. The width of the annular free surface of the substrate can even be as small as, or even smaller than, the length of the edge portion of the substrate (where the thickness of the substrate decreases).

[0021] Next, a cylindrical SiGe layer is epitaxially deposited on the annular free surface of the substrate. According to one embodiment of the invention, atmospheric pressure CVD is performed for the deposition of the cylindrical SiGe layer. Details of this deposition process are well known and discussed, for example, in US 2010 0 317 177A1. Alternatively, deposition can be performed at reduced pressure and lower temperature. According to one embodiment of the invention, the composition of the cylindrical SiGe layer is Si. 1-x Ge xWhere 0.01 ≤ x ≤ 1. According to another preferred embodiment of the invention, the cylindrical SiGe layer has a thickness of not less than 10 nm and not more than 10 μm, and the cylindrical SiGe layer is partially or completely relaxed. The above-described characteristics of the cylindrical SiGe layer allow for proper control of the TDD of the cylindrical SiGe layer, which is crucial for achieving the objectives of the invention. The TDD of the cylindrical SiGe layer is preferably at least 1.0 × 10⁻⁶. 3 cm -2 .

[0022] After providing a cylindrical SiGe layer in the edge region of the substrate, the remaining mask layer surrounded by the cylindrical SiGe layer is removed, and the surface of the substrate covered by the mask layer becomes accessible (accessible, reachable, or usable) for depositing a SiGe layer in contact with the surface of the substrate and the inner and upper surfaces of the cylindrical SiGe layer. According to a preferred embodiment of the invention, the SiGe layer is epitaxially deposited via CVD at atmospheric pressure. According to another preferred embodiment of the invention, the SiGe layer is composed of Si. 1-x Ge x Where 0.01 ≤ x ≤ 1. According to one embodiment of the invention, the SiGe layer is a graded (gradation-based) buffer layer or a constant composition layer. The SiGe layer is partially or completely relaxed and is in contact with the substrate and the inner surface of the cylindrical SiGe layer, or both the substrate and the inner and upper surfaces of the cylindrical SiGe layer. The germanium content of the cylindrical SiGe layer can be lower than, equal to, or higher than the germanium content of the SiGe layer. The SiGe layer preferably has a thickness of not less than 0.01 μm and not more than 10 μm.

[0023] Through-dislocations contained in a cylindrical SiGe layer relax the SiGe layer by sliding towards the center after reaching a critical thickness. As a result, compared with prior art solutions, the packing density and through-dislocation density are reduced, as well as the surface roughness and overall uniformity are improved.

[0024] The present invention will be disclosed below with reference to the accompanying drawings. Attached Figure Description

[0025] Figure 1 A cross-sectional view of an embodiment of a wafer in its final production state is presented.

[0026] Figure 2 The display was presented Figure 1 A cross-sectional view of the edge region of the wafer shown.

[0027] Figure 3 and Figure 2 The only difference is that the edge region of the wafer is shown as an intermediate production state of the wafer.

[0028] Figure 4It is based on Figure 3 A top-view view of the wafer.

[0029] Figure 5 Presented in a top-view view, it shows the path starting from the substrate and ending at... Figure 3 and Figure 4 The intermediate production state of the wafer during the process for which protection is required.

[0030] Figure 6 It shows the beginning based on Figure 3 The intermediate production state of the wafer and terminated according to Figure 2 The evolution of TD in the final production state.

[0031] Figure 7 A cross-sectional view of another embodiment of a wafer in its final production state is presented.

[0032] Figure 8 A cross-sectional view of another embodiment of a wafer in its final production state is presented.

[0033] Figure 9 A cross-sectional view of the edge region of the substrate is presented.

[0034] List of reference numerals used

[0035] 1 substrate

[0036] 2 cylindrical silicon-germanium layers

[0037] 3 silicon-germanium layers

[0038] 4 mask layers

[0039] 5. Remaining parts of the mask layer

[0040] 6-substrate annular free surface

[0041] 7 Edges

[0042] Length of the edge portion of I

[0043] w width

[0044] t thickness

[0045] TD threading misalignment Detailed Implementation

[0046] In the final production state, the wafer produced according to the present invention can have Figure 1 The structure shown includes a substrate 1, a cylindrical silicon-germanium layer 2, and a silicon-germanium layer 3 contacting the inner and upper surfaces of the cylindrical silicon-germanium layer 2. Figure 2 The image shows the edge region of the wafer, which extends from the edge of the wafer toward the center in the direction of the arrow.

[0047] Before depositing the silicon-germanium layer 3, the wafer is in Figure 3 The intermediate state is shown. The structure of the intermediate state includes a substrate 1 and a cylindrical silicon-germanium layer 2 having a radial width w and a thickness t. Figure 4 A top view of the wafer in its intermediate state is presented.

[0048] To achieve intermediate states, such as Figure 5 As shown, a mask layer 4 is disposed on top (or above) the upper surface of substrate 1. Then, the outer portion of mask layer 4 is removed to provide a pathway to the annular free surface 6 in the edge region of substrate 1. Next, a cylindrical silicon-germanium layer 2 is deposited on the annular free surface 6, surrounding the remaining portion 5 of mask layer 4. Subsequently, the remaining portion 6 of mask layer 4 is also removed to provide an intermediate state for subsequent deposition of silicon-germanium layer 3 on substrate 1 and cylindrical silicon-germanium layer 2.

[0049] Figure 6 The evolution of the TD from the intermediate production state to the final production state is shown. Once the critical thickness is reached, the wire dislocations contained in the cylindrical silicon-germanium layer 2 promote the relaxation of the silicon-germanium layer 3 by sliding towards the center.

[0050] In the final production state, the wafer produced according to the present invention can also have Figure 7 or Figure 8 The structure shown. According to Figure 7 In the illustrated embodiment, the silicon-germanium layer 3 contacts the surface of the substrate 1 and the inner surface of the cylindrical silicon-germanium layer 2 until a certain height is reached. According to... Figure 8 In the illustrated embodiment, the silicon-germanium layer 3 and the cylindrical silicon-germanium layer 2 have the same thickness.

[0051] like Figure 9 As shown, the width of the annular free surface of the substrate can be as small as, or even smaller than, the length I of the edge portion 7 of the substrate 1 (where the thickness of the substrate decreases).

[0052] The description of the illustrative embodiments above should be understood as exemplary.

Claims

1. A method for heteroepitaxially depositing a silicon-germanium layer (3) on a substrate (1), said silicon-germanium layer (3) having a Si composition. 1- x Ge x Where 0.01 ≤ x < 1, and the substrate (1) is a silicon single crystal wafer or a silicon-on-insulator wafer, the method comprising: A mask layer (4) is disposed on top of the substrate (1), characterized in that, The mask layer (4) is removed from the edge region of the substrate to provide a pathway to an annular free surface (6) of the substrate, wherein the annular free surface (6) is located in the edge region of the substrate and surrounds the remainder (5) of the mask layer (4). An edge reservoir consisting of a relaxed or partially relaxed silicon-germanium layer is deposited on top of the annular free surface (6) of the substrate (1). Remove the remaining portion (5) of the mask layer (4); and The silicon-germanium layer (3) is deposited on top of the substrate (1) and on top of the edge reservoir, and the silicon-germanium layer (3) contacts the inner surface of the edge reservoir.

2. The method according to claim 1, comprising: A low-temperature oxide material formed by chemical vapor deposition at a temperature between 300°C and 500°C is provided as a mask layer (4).

3. The method according to claim 1 or claim 2, comprising: The edge reservoir is deposited on top of the annular free surface (6) of the substrate, such that it has a width of not more than 1.5 mm and a thickness of not less than 10 nm and not more than 10 µm.

4. The method according to any one of claims 1 to 2, comprising: The silicon-germanium layer (3) is deposited on top of the substrate (1) and on top of the edge reservoir, such that it has a thickness of not less than 0.01 µm and not more than 10 µm.

5. The method according to any one of claims 1 to 2, wherein, The silicon-germanium layer (3) is a constant composition layer.

6. The method according to any one of claims 1 to 2, wherein, The silicon-germanium layer (3) is a hierarchical component layer.

7. The method according to any one of claims 1 to 2, wherein, The germanium content of the edge storage is lower than, equal to or higher than the germanium content of the silicon-germanium layer (3).

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