Semiconductor wafers and methods for manufacturing semiconductor wafers

Abstract

This disclosure aims to provide a semiconductor wafer and a method for manufacturing a semiconductor wafer, which can suppress the reduction in the diameter of a convex-shaped portion by providing notches on the outer surface and in the convex-shaped portion of the semiconductor wafer. [Solution] The semiconductor wafer according to the present disclosure is a semiconductor wafer having a first surface and a second surface opposite to the first surface, wherein the first surface has a first main surface and an surrounding surface that surrounds the first main surface via a stepped surface and is recessed toward the second surface than the first main surface, and has a first notch in a circumferential portion of the stepped surface connecting the first main surface and the surrounding surface, and has a second notch in a circumferential portion of the outer surface connecting the second surface and the surrounding surface, wherein the first notch is in the shape of an orientation flat and the second notch is in the shape of a notch.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor wafer and a method for manufacturing the semiconductor wafer.

Background Art

[0002] In Patent Document 1, when forming a device structure on the front side of a semiconductor substrate and thinning it, a method is proposed in which the edge of the semiconductor wafer is trimmed to a convex shape in order to reduce the occurrence of chipping and cracking at the edge.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, the same orientation flat is provided on the outer peripheral surface of the semiconductor wafer and on the convex-shaped portion. When an orientation flat is formed on the outer peripheral surface of the semiconductor wafer, the diameter of the semiconductor wafer becomes smaller, and when an orientation flat is further formed on the inner convex-shaped portion, the diameter of the convex-shaped portion becomes even smaller.

[0005] Therefore, an object of the present disclosure is to provide a semiconductor wafer and a method for manufacturing a semiconductor wafer capable of suppressing a reduction in the diameter of a convex-shaped portion by providing notch portions on the outer peripheral surface and the convex-shaped portion of the semiconductor wafer.

Means for Solving the Problems

[0006] The semiconductor wafer according to the present disclosure is a semiconductor wafer having a first surface and a second surface opposite to the first surface, The first surface has a first main surface and a surrounding surface that surrounds the first main surface via a stepped surface and is recessed toward the second surface side than the first main surface. The stepped surface connecting the first main surface and the surrounding surface has a first notch in a portion of its circumferential direction, The outer circumferential surface connecting the second surface and the surrounding surface has a second notch in a portion of its circumferential direction, the first notch being in an orientation flat shape, and the second notch being in a notch shape.

[0007] The semiconductor wafer manufacturing method relating to this disclosure is: A preparation step of preparing a semiconductor wafer having a first surface and a second surface opposite to the first surface, and having a notch-shaped second cutout in a part of the circumferential direction of the outer peripheral surface connecting the first surface and the second surface, A convex structure forming step is performed by cutting a portion of the first surface corresponding to the surrounding surface so that a first main surface and a surrounding surface that surrounds the first main surface via a stepped surface and is recessed toward the second surface side than the first main surface are formed on the first surface of the semiconductor wafer. A grinding step is performed to cut a first notch with an orientation flat shape in a portion of the circumferential direction of the stepped surface connecting the first main surface and the surrounding surface, It is equipped with. [Effects of the Invention]

[0008] According to the semiconductor wafer and semiconductor wafer manufacturing method described herein, a notch is formed on the outer circumferential surface of the semiconductor wafer. Since the width of the circumferential notch is smaller than the width of the orientation flat, the surrounding surface and the first notch can be ground from above the notch using a grinding wheel larger than the width of the notch, thereby reducing the width of the radial surrounding surface and the depth of the first notch toward the inner diameter. Therefore, it is possible to suppress the reduction in the diameter of the convex-shaped portion. [Brief explanation of the drawing]

[0009] [Figure 1]Top view of the semiconductor wafer according to Embodiment 1 [Figure 2] Schematic cross-sectional view of the semiconductor wafer according to Embodiment 1 [Figure 3] Top view of the semiconductor wafer before processing in Embodiment 1 [Figure 4] Schematic cross-sectional view of the semiconductor wafer before processing in Embodiment 1 [Figure 5] Schematic cross-sectional view of the semiconductor wafer according to a modified example of Embodiment 1 [Figure 6] Top view of the divided semiconductor wafer on the first main surface side according to Embodiment 1 [Figure 7] Top view of the divided semiconductor wafer on the second surface side according to Embodiment 1 [Figure 8] Schematic cross-sectional view of the divided semiconductor wafer on the first main surface side according to Embodiment 1 [Figure 9] Schematic cross-sectional view of the divided semiconductor wafer on the second surface side according to Embodiment 1 [Figure 10] Schematic cross-sectional view of the divided semiconductor wafer on the first main surface side according to the comparative example of Embodiment 1 [Figure 11] Schematic cross-sectional view of the divided semiconductor wafer on the second surface side according to the comparative example of Embodiment 1 [Figure 12] Schematic cross-sectional view of the semiconductor wafer in which two members are joined according to a modified example of Embodiment 1 [Figure 13] Schematic cross-sectional view of the semiconductor wafer in which two members are joined according to a modified example of Embodiment 1 [Figure 14] Schematic cross-sectional view of the semiconductor wafer in which two members are joined according to a modified example of Embodiment 1 [Figure 15] Flowchart of the manufacturing method of the semiconductor wafer according to Embodiment 1

Mode for Carrying Out the Invention

[0010] 1. Embodiment 1 The semiconductor wafer 101 according to Embodiment 1 will be described with reference to the drawings. FIG. 1 is a top view showing the semiconductor wafer 101 according to Embodiment 1. Further, FIG. 2 is a schematic cross-sectional view of the semiconductor wafer 101 according to Embodiment 1. Each cross-sectional view is a cross-sectional view cut at the X-X position in FIG. 1 and the like. Note that each schematic cross-sectional view is a diagram for schematically explaining the features of each part, and the dimensions of each part do not match those of each top view.

[0011] 1-1. Structure of the semiconductor wafer The semiconductor wafer 101 is a semiconductor wafer 101 having a first surface 1 and a second surface 2 opposite to the first surface 1. The first surface 1 has a first main surface 3 and a surrounding surface 108 that surrounds the periphery of the first main surface 3 via a stepped surface 4 and is recessed toward the second surface 2 side from the first main surface 3. The first notch 201 is provided in a circumferential part of the stepped surface 4 between the first main surface 3 and the surrounding surface 108, and the second notch 202 is provided in a circumferential part of the outer peripheral surface 5 between the second surface 2 and the surrounding surface 108. The first notch 201 has an orientation flat shape, and the second notch 202 has a notch shape.

[0012] <Semiconductor wafer> In the present embodiment, the case where the material of the semiconductor wafer 101 is a single crystal of silicon carbide will be described, but it may be formed of other semiconductor materials or ceramic materials. Examples of the semiconductor materials include silicon, gallium nitride-based materials, gallium oxide-based materials, or diamond. Examples of the ceramic materials include Α-AL2O3 (sapphire).

[0013] When silicon carbide is used as the material, it may be 15R-SIC (15R silicon carbide), or a hexagonal polytype of silicon carbide, for example, 2H-SIC (2H type silicon carbide), 4H-SIC (4H type silicon carbide), or 6H-SIC (6H type silicon carbide), and may also be a polycrystal or a sintered body. The dopant atoms may include, for example, nitrogen N, phosphorus P, beryllium BE, boron B, aluminum AL, or gallium GA. Further, it may contain unnecessary impurities, for example, hydrogen, fluorine, or oxygen.

[0014] The semiconductor wafer 101 may have an off-angle on its C-plane. The off-angle is preferably in the A-axis direction ([11-20] direction) of the silicon carbide single crystal. The off-angle may be greater than 0° and less than or equal to 10°, and even better if it is between 2° and 4.5°.

[0015] The diameter of the semiconductor wafer 101 may correspond to production standards and may be 2 inches, 3 inches, 4 inches, 5 inches, 6 inches, 7 inches, 8 inches, or 12 inches. The thickness of the semiconductor wafer 101 is between 0.1 millimeters and 50 millimeters, and is typically 20 millimeters or less. If a wafer for device formation cut from a silicon carbide ingot is used, the thickness is between 0.2 millimeters and 15 millimeters, preferably 10 millimeters or less, and even better if it is 1 millimeter or less.

[0016] An epitaxial film may be deposited on the semiconductor wafer 101, and a semiconductor device structure 121 may be formed on the epitaxial film. The formation of the semiconductor device structure 121 includes ion implantation and the formation of surface electrodes. The semiconductor device structure 121 is, for example, a power device structure such as a MOSFET (METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR), a diode, or an IGBT (INSULATED GATE BIPOLAR TRANSISTOR). When a gallium nitride wafer is used instead of a silicon carbide wafer, the semiconductor device structure 121 may be, for example, a GAN (gallium nitride) high-frequency device structure, and a gallium nitride high-frequency device structure may be formed on the silicon carbide wafer.

[0017] <First main surface and surrounding surface> The semiconductor wafer 101 has a first surface 1 and a second surface 2 opposite to the first surface 1, and the first surface 1 has a first main surface 3 and a surrounding surface 108 that surrounds the first main surface 3 via a stepped surface 4 and is recessed toward the second surface 2 side than the first main surface 3.

[0018] The first main surface 3 has a convex shape with a diameter smaller than the diameter of the second surface 2, and a portion of the outer circumference is characterized by a first notch 201 on the side of the first main surface 3 and a second notch 202 on the side of the second surface 2.

[0019] As shown in the schematic cross-sectional view of Figure 4, the outer periphery of the semiconductor wafer 101 before grinding is ground up to a point in the thickness direction from the first surface 1 to the second surface 2, thereby forming a convex structure on the semiconductor wafer 101 as shown in the schematic cross-sectional view of Figure 2.

[0020] As described above, the semiconductor wafer 101 has a convex shape and has a first main surface 3 and a surrounding surface 108. The first main surface 3 is positioned higher than the surrounding surface 108, and the surrounding surface 108 is positioned to surround the first main surface 3. The first surface 1 has the surrounding surface 108 and the first main surface 3, and there is a thickness on the first main surface 3 side, which is the thickness between the first main surface 3 and the surrounding surface 108, and a thickness on the surrounding surface side, which is the thickness between the surrounding surface 108 and the second surface 2.

[0021] The thickness between the first surface 1 and the second surface 2 differs between the surrounding surface side and the first main surface 3 side. The thickness on the surrounding surface side is preferably 0.05 mm or more and 50 mm or less, and even better if it is 0.15 mm or less. The thickness on the second surface 2 side is 0.05 mm or more and 50 mm, and even better if it is 0.15 mm or less.

[0022] The surrounding surface is preferably thicker than the first main surface 3 side in order to suppress chipping and cracking at the edges, and the first main surface 3 side is preferably 100 to 200 micrometers thick in order to maintain strength after splitting. For example, if the total thickness of the wafer is 350 micrometers, the surrounding surface is 200 to 250 micrometers thick and the first main surface 3 side is 100 to 150 micrometers thick, and if the total thickness of the wafer is 500 micrometers, the surrounding surface is 300 to 400 micrometers thick and the first main surface 3 side is 100 to 200 micrometers thick.

[0023] The difference between the diameter of the first main surface 3 and the diameter of the second surface 2 is preferably less than 2 millimeters, and even better if it is less than 0.5 millimeters. By reducing the diameter to less than 0.5 millimeters, when the semiconductor wafer 101 described later is divided and the semiconductor wafer on the side where the semiconductor device structure 121 is not formed is reprocessed to form the semiconductor device structure 121, no adjustment to the diameter of the apparatus becomes necessary.

[0024] <First notch and second notch> The semiconductor wafer 101 has a first notch 201 in a portion of the circumferential direction of the stepped surface 4 between the first main surface 3 and the surrounding surface 108, and a second notch 202 in a portion of the circumferential direction of the outer peripheral surface 5 between the second surface 2 and the surrounding surface 108.

[0025] As shown in the top view of Figure 1, in this embodiment, when viewed vertically from the first main surface 3, the bottom point 6 of the notch-shaped second notch 202 and the notch surface 8 of the orientation-flat shaped first notch 201 overlap. When viewed vertically from the first main surface 3, the portion of the orientation-flat shaped first notch 201's notch surface 8 closest to the bottom point 6 of the notch-shaped second notch 202 is the center of the notch surface 8 of the first notch 201. With this configuration, the width of the surrounding surface 108 can be made smaller than or equal to the depth of the notch-shaped second notch 202, the depth of the first notch 201 can be made smaller than or equal to the depth of the notch-shaped second notch 202, and the diameter of the first main surface 3 can be made larger. Furthermore, since the width of the circumferential notch is smaller than the width of the orientation flat, the surrounding surface 108 and the first notch 201 can be ground from above the notch using a grinding wheel larger than the width of the notch, thereby reducing the width of the radial surrounding surface 108 and the depth of the inner diameter side of the first notch 201. However, as in Patent Document 1, if the second notch 202 is in the shape of an orientation flat, the width of the orientation flat is wide, so the surrounding surface 108 and the first notch 201 cannot be ground from above the orientation flat, and it is necessary to form the first notch 201 inside the orientation flat, which increases the depth of the first notch 201 and decreases the diameter of the first main surface 3.

[0026] Furthermore, when viewed in the vertical direction of the first main surface 3, the shortest distance between the bottom point 6 of the notch-shaped second cutout 202 and the cutout surface 8 of the orientation-flat shaped first cutout 201 may be less than or equal to the depth of the second cutout 202. With this configuration, even if a certain distance is provided, the width of the surrounding surface 108 and the depth of the first cutout 201 can be reduced, and the diameter of the first main surface 3 can be increased.

[0027] Furthermore, the notch shape does not have to be limited to one on the first main surface 3 side and one on the second surface 2 side; multiple notches may be formed on each side. For example, if another orientation flat is formed at a position 90 degrees circumferentially different from the first notch 201, it becomes easier to determine the specific crystal orientation and conductivity type (P-type or N-type) of the semiconductor wafer 101. The first notch 201 and the second notch 202 may be formed at the same position or at different positions. However, since the notch shape indicates the crystal orientation, it is preferable that the first notch 201 and the second notch 202 coincide.

[0028] As shown in Figure 5, the corners of the semiconductor wafer 101 may be given a rounded edge (R-shaped) 9. By giving the corners a rounded edge (R-shaped), chipping and cracking caused by stress concentration at the edges can be suppressed, thereby increasing the strength of the semiconductor wafer 101. The radius of the chamfer is preferably in the range of 0.5 micrometers to 50 micrometers, or even better, in the range of 5 micrometers to 20 micrometers. This chamfer may be controlled by the shape of the grinding wheel used for trimming, and may also be formed unintentionally as the grinding wheel changes shape due to wear. Alternatively, the chamfer may be formed by etching.

[0029] 1-2. Method for manufacturing semiconductor wafers In the comparative example, when a typical semiconductor wafer 101 on which a semiconductor element structure 121 is formed, as shown in the top view of Figure 3 and the schematic cross-sectional view of Figure 4, is divided into a first surface 1 and a second surface 2, the semiconductor wafer 101 is divided into a semiconductor element-equipped wafer 101 containing the semiconductor element structure 121 as shown in the schematic cross-sectional view of Figure 10, and a semiconductor wafer 101 without the semiconductor element as shown in the schematic cross-sectional view of Figure 11. As shown in Figure 10, in the semiconductor element-equipped wafer 101 of the comparative example, since no convex structure is formed, the edges are sharp. The formation of sharp edges increases the likelihood of stress concentration at the edges, leading to chipping and cracking.

[0030] Figure 15 shows a flowchart of the method for manufacturing a semiconductor wafer 101 according to Embodiment 1.

[0031] <Preparation Step S1> As shown in the top view of Figure 3 and the schematic cross-sectional view of Figure 4, the preparation step prepares a semiconductor wafer 101 having a first surface 1 and a second surface 2 opposite to the first surface 1, and a notch-shaped second cutout portion 202 in a part of the circumferential direction of the outer peripheral surface 5 connecting the first surface 1 and the second surface 2. In Figures 3 and 4, a semiconductor wafer 101 is prepared with a semiconductor element structure 121 formed on the first surface 1. However, the structure of the semiconductor wafer 101 may be formed after the grinding step S3 or the splitting step S4.

[0032] <Convex structure formation process S2> As shown schematically in Figure 2, in the convex structure formation process S2, the portion of the first surface 1 corresponding to the surrounding surface 108 is cut so that a first main surface 3 and a surrounding surface 108 that surrounds the first main surface 3 via a stepped surface 4 and is recessed toward the second surface 2 side than the first main surface 3 are formed on the first surface 1 of the semiconductor wafer 101. The semiconductor wafer 101 having a second notch 202 in a part of the circumferential direction of the outer peripheral surface 5 connecting the first surface 1 and the second surface 2 is ground from the first main surface 3 toward part of the direction of the second surface 2.

[0033] <Grinding process S3> In grinding step S3, cutting is performed to form an orientation-flat shaped first notch 201 in a portion of the circumferential direction of the stepped surface 4 connecting the first main surface 3 and the surrounding surface 108.

[0034] The convex structure formation process S2 and the grinding process S3 are performed using the same cutting device. This configuration can reduce manufacturing costs. For example, in the convex structure formation process S2 and the grinding process S3, a device is used in which a grinding wheel is attached to a rotary edge processing machine. The grinding wheel used is adjusted to grind the outer circumference of the first surface 1 from the upper side. A grinding wheel larger than the width of the notch of the second notch portion 202 is used, and the surrounding surface 108 and the first notch portion 201 can be ground from above the notch.

[0035] Alternatively, the surrounding surface 108 and the first notch 201 may be formed by half-cutting the outer circumference of the first surface 1 using a dicing device. In either method, the grinding wheel used to process the first notch 201 can be the same as the grinding wheel used to trim the surrounding surface 108. By processing in this manner, it becomes possible to form an orientation flat end inside the notch end.

[0036] <Dividing process S4> In the splitting process S4, the semiconductor wafer 101 is cut along the same plane as the surrounding surface 108 to separate it into the semiconductor wafer 101 on the first main surface 3 side and the semiconductor wafer 101 on the second surface 2 side. This separates the semiconductor wafer 101 on the first main surface 3 side, as shown in the top view of Figure 6 and the schematic cross-sectional view of Figure 8, from the semiconductor wafer 101 on the second surface 2 side, as shown in the top view of Figure 7 and the schematic cross-sectional view of Figure 9. As shown in Figure 8, a convex structure is formed, so unlike the comparative example in Figure 10, it is possible to prevent the edges from becoming sharp, and the possibility of chipping and cracking can be reduced. In addition, as described above, the diameter of the semiconductor wafer 101 on the first main surface 3 side can be reduced.

[0037] The semiconductor wafer 101 on the first main surface 3 side can be aligned using an orientation flat when processed in semiconductor manufacturing equipment. This eliminates the need to form a notch on the semiconductor wafer 101 on the first main surface 3 side for additional processing and positioning. Furthermore, the semiconductor wafer 101 on the second surface 2 side has the same diameter as the semiconductor wafer 101 before splitting, eliminating the need to adjust the diameter of the equipment when reprocessing the semiconductor wafer 101 on the second surface 2 side to form semiconductor elements. In addition, because it has a notch, it can be aligned using the notch when processed in semiconductor manufacturing equipment. Therefore, it eliminates the need to form a notch on the semiconductor wafer 101 on the second surface 2 side for additional processing and positioning.

[0038] The splitting of the semiconductor wafer 101 into the semiconductor wafer 101 on the first main surface 3 side and the semiconductor wafer 101 on the second surface 2 side may be done by a method that contacts the semiconductor wafer 101, such as a dicing saw, or by a non-contact method using an optical technique.

[0039] <Variation> As shown in the schematic cross-sectional views in Figures 12 to 14, the semiconductor wafer 101 may be constructed by joining a first surface member and a second surface member 2.

[0040] For example, as shown in the schematic cross-sectional view of Figure 12, in the semiconductor wafer 101, the bonding surface 301 between the first main surface member 10 and the second surface member 11 may be provided on the same plane as the surrounding surface 108.

[0041] Alternatively, as shown in the schematic cross-sectional view of Figure 13, the bonding surface 301 between the member 10 on the first main surface side and the member 11 on the second surface side may be located closer to the second surface 2 than to the surrounding surface 108 in the semiconductor wafer 101.

[0042] Alternatively, as shown in the schematic cross-sectional view of Figure 14, in the semiconductor wafer 101, the member 10 on the first main surface side and the member 11 on the second surface side may be provided closer to the first main surface 3 than to the surrounding surface 108.

[0043] For example, room-temperature bonding is used to join two types of members. With room-temperature bonding, no metal layer or the like is included in the bonding surface 301, and a clean interface is obtained. In addition, when room-temperature bonding is used, an amorphous layer may be formed on the bonding surface 301. The thickness of the amorphous layer is preferably 5 micrometers or less, and even better if it is 0.1 micrometers or less.

[0044] The material of the member on the first main surface 3 side and the member on the second surface 2 side are single crystals. Alternatively, one of the members on the first main surface 3 side and the second surface 2 side may be single crystals, while the other member is polycrystalline. By using a polycrystalline substrate and wafers of different materials, it is possible to form a semiconductor wafer 101 at a lower cost compared to a single-crystal bonded wafer. When two types of members are subjected to high-temperature processing and injection processing, the wafer warps due to stress during processing, so it is preferable to bond materials that have relatively similar physical properties. Physical properties such as the coefficient of thermal expansion and melting point are included as selection factors when selecting the material for the members.

[0045] After joining the two types of components, a convex structure having the same first notch 201 and second notch 202 as the semiconductor wafer 101 is formed using a rotary edge processing machine or dicing device according to the manufacturing method described above. Alternatively, the same structure as the semiconductor wafer 101 may be formed by joining wafers with different diameters and notch shapes from the beginning.

[0046] Although the example shows two types of materials being joined together to form a semiconductor wafer 101, three or more types of materials may also be joined together to form a semiconductor wafer 101. [Explanation of symbols]

[0047] 1 First surface, 2 Second surface, 3 First main surface, 4 Step surface, 5 Outer surface, 6 Bottom point, 8 Notched surface, 9 R-shaped processing, 10 Member on the first main surface side, 11 Member on the second surface side, 101 Semiconductor wafer, 108 Surrounding surface, 121 Semiconductor device structure, 201 First notch, 202 Second notch, 301 Bonding surface

Claims

1. A semiconductor wafer having a first surface and a second surface opposite to the first surface, The first surface has a first main surface and a surrounding surface that surrounds the first main surface via a stepped surface and is recessed toward the second surface side than the first main surface. The stepped surface connecting the first main surface and the surrounding surface has a first notch in a portion of its circumferential direction, A semiconductor wafer having a second notch in a portion of the circumferential direction of the outer peripheral surface connecting the second surface and the surrounding surface, wherein the first notch is in an orientation flat shape and the second notch is in a notch shape.

2. The semiconductor wafer according to claim 1, wherein, when viewed in the direction perpendicular to the first main surface, the shortest distance between the bottom point of the notch-shaped second notch and the notch surface of the orientation-flat-shaped first notch is less than or equal to the depth of the second notch.

3. The semiconductor wafer according to claim 1, wherein, when viewed in the direction perpendicular to the first main surface, the bottom point of the notch-shaped second cutout and the notch surface of the orientation-flat shaped first cutout overlap.

4. The semiconductor wafer according to claim 1, wherein, when viewed in the direction perpendicular to the first main surface, the portion of the orientation flat shape of the notched surface of the first notch that is closest to the bottom point of the notch-shaped second notch is the central part of the notched surface of the first notch.

5. The semiconductor wafer according to any one of claims 1 to 4, wherein the semiconductor wafer is composed of a single component.

6. The semiconductor wafer is configured by joining the first main surface member and the second surface member, as described in any one of claims 1 to 4.

7. The semiconductor wafer according to claim 6, wherein the joining surface between the first main surface member and the second surface member is provided on the same plane as the surrounding surface.

8. The semiconductor wafer according to claim 6, wherein the joining surface between the first main surface member and the second surface member is provided at a location closer to the second surface than the surrounding surface.

9. The semiconductor wafer according to claim 6, wherein the member on the first main surface and the member on the second surface are provided at locations closer to the first main surface than the surrounding surface.

10. The semiconductor wafer according to any one of claims 1 to 4, wherein the material of the first main surface member and the second surface member is a single crystal.

11. A semiconductor wafer according to any one of claims 1 to 4, wherein one of the members on the first main surface side and the member on the second surface side is a single crystal, and the other member is a polycrystalline material.

12. The semiconductor wafer according to any one of claims 1 to 4, wherein the corners of the semiconductor wafer are rounded.

13. A preparation step of preparing a semiconductor wafer having a first surface and a second surface opposite to the first surface, and having a notch-shaped second cutout in a part of the circumferential direction of the outer peripheral surface connecting the first surface and the second surface, A convex structure forming step is performed by cutting a portion of the first surface corresponding to the surrounding surface so that a first main surface and a surrounding surface that surrounds the first main surface via a stepped surface and is recessed toward the second surface side than the first main surface are formed on the first surface of the semiconductor wafer. A grinding step is performed to cut a first notch with an orientation flat shape in a portion of the circumferential direction of the stepped surface connecting the first main surface and the surrounding surface, A method for manufacturing semiconductor wafers equipped with [specific features / equipment].

14. A method for manufacturing a semiconductor wafer according to claim 13, wherein the convex structure formation step and the grinding step are performed using the same cutting device.

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