Hardware implementation of frequency table generation for data compression based on asymmetric digital systems

Abstract

While the symbol occurrence count is rounded to generate the symbol frequency, the lossless data compressor immediately prevents normalization overflow, allowing the code table generator to generate code table entries without waiting for the symbol frequency table to finish filling. As symbols are normalized, rounding errors accumulate, and are compensated for by reducing the symbol frequency when the symbol frequency is at least 2 and the accumulated error exceeds a threshold. The symbol frequency is also reduced when the number of remaining states in the code table is insufficient to accommodate the number of remaining unprocessed symbols and states for the current code table entry. Because error compensation occurs during symbol normalization, it does not force all symbols in the waiting block to be processed before generating the code table, thus reducing latency. Three pipeline stages operate on three input blocks: symbol counting, normalization / error compensation / code table generation, and data encoding.

Description

Technical Field

[0001] This invention relates to data compression systems, and more particularly to the use of parallel hardware to normalize frequency tables. Background Technology

[0002] Data can be compressed using lossy or lossless methods. Image data such as video typically uses lossy compression because the loss of visual data may not be particularly noticeable. Other types of data cannot tolerate loss, so lossless data compression is used.

[0003] Neural networks use weights for the nodes in the network. The network's topology and connectivity can be defined by feature maps. For deep neural networks and convolutional neural networks, these weights and feature maps can be quite large. Neural network weights and feature maps can be compressed before storage or transmission. Since computational results may be altered due to data compression losses, neural networks require lossless data compression.

[0004] Figure 1 shows a neural network whose weights and feature maps are compressed before storage or transmission. The neural network 104 can be a graphics processing unit (GPU) or a dedicated neural network processor. The neural network 104 may have been trained, with its weights and feature maps tuned to optimize for a specific problem or dataset. These weights and feature maps can be backed up or stored in memory 102.

[0005] However, the memory 102 can be located remotely from the neural network 104, for example, when the neural network 104 is on a portable device and the memory 102 is in cloud storage. The connection between the neural network 104 and the memory 102 may be bandwidth-limited. The compressor 100 can use lossless compression to compress the weights and feature maps from the neural network 104 and send the compressed data to the memory 102. This can reduce the amount of memory required for storage in the memory 102 and also reduce the bandwidth consumed by the transmission.

[0006] The compressed weights and feature maps stored in memory 102 can be transmitted via a network link to a local device including compressor 100, which decompresses the weights and feature maps and loads them into neural network 104 to configure neural network 104 for a specific processing task.

[0007] Some data blocks may be so random or unordered that they are poorly compressed. It's best to avoid compressing such data, as the compressed result may be larger than the original. Other data blocks, such as those containing only zeros, may be easily compressed.

[0008] Classic lossless compression algorithms include WinZip, WinRAR, and 7z. These compressors typically employ both run-length coding and entropy coding. The drawback of run-length coding is its large search window, which can become a significant bottleneck. Entropy coding, such as Huffman coding, arithmetic coding, Asymmetric Numerical System (ANS), tabled Asymmetric Numerical System (tANS), and Finite State Entropy (FSE) coding, may require a symbol frequency table. This symbol frequency table can be created or populated during compression and transmitted along with the compressed data. This overloaded symbol frequency table is a bandwidth-intensive overhead and can reduce compression efficiency in some cases.

[0009] For classic two-stage coding systems that use run-length and entropy coding, parallel implementation can be difficult. Latencies can be significant. The frequency table could be sorted to order the symbols, ensuring that high-occurrence symbols appear before low-occurrence symbols. However, frequency table sorting is time-consuming, and coding must wait until the sorting is complete, thus reducing pipeline efficiency.

[0010] Instead of sorting the frequency table, it can be normalized. The total number of occurrences of all symbols is reduced to a target number of states. For example, for a 4K block with N = 4K symbols per block, it can be normalized to 256 states S by dividing the number of symbol occurrences by N / S and rounding. A symbol that occurs 32 times is normalized to 2, while a symbol that occurs 23 times or 8 times is normalized to 1.

[0011] Figure 2 shows a prior art data compressor that generates a frequency table. Input data is stored in input buffer 12 and applied to symbol counter 140, which counts the occurrences of each symbol in the block. These occurrence counts are stored in occurrence memory 10. The occurrence values ​​are normalized by normalizer 150 to generate symbol frequencies stored in frequency table 20. The normalized symbol frequencies from frequency table 20 are used by encoding table generator 154 to generate symbol codes stored in encoding table 30. These codes stored in encoding table 30 are used by encoder 156 to replace the input symbols in input buffer 12 with the encoded symbols stored in output buffer 40 as the compressed encoded data output for that block.

[0012] Faster throughput can be achieved by pipelined symbol counter 140, normalizer 150, code table generator 154, and encoder 156. However, normalizer 150 and code table generator 154 may not be able to operate in parallel. Normalizer 150 reads the appearance memory 10 via symbol counter 140 to generate frequency table 20. This typically only requires reading frequency table 20 once.

[0013] Overflow can occur during normalization. Overflow happens when the total number of states generated by normalization is too large. For example, when a 4KB block is normalized to 256 states, but the sum of the frequencies exceeds 256, an overflow occurs. The sum of the states must be reduced to 256 to correct this overflow.

[0014] Figures 3A-3C highlight the normalization of symbol occurrence counts to generate the frequency table. Figure 3A shows a histogram of symbol occurrence counts, as stored in occurrence memory 10. When the symbol is a byte, there are 256 possible symbols. In this example, symbol 0 occurs 30 times, symbol 1 occurs 60 times, symbols 2, 3, and 4 each occur once, and symbol 255 occurs 40 times. For a 4KB block, the total occurrence count OCCUR[i] will be 4096.

[0015] Figure 3B shows the pseudocode for normalization. The ratio L is the block size divided by the number of normalized states, which is 4K / 256 = 16 in this example. When the occurrence count of symbol i, OCCUR[i], is 0, the frequency of symbol i, FREQ[i], is set to zero.

[0016] When the frequency of occurrence is less than the ratio L but greater than 0, the frequency FREQ[i] of the symbol is set to 1. Otherwise, the frequency FREQ[i] of the symbol i is set to round(OCCUR[i] / L), where round is the rounding operator. For example, 3.4 can be rounded down to 3, but 3.5 is rounded up to 4.

[0017] This pseudocode preserves non-zero values ​​that would otherwise be rounded to zero. Values ​​from 1 to 7 are rounded up to 1 instead of down to 0. This is beneficial because it distinguishes the sign of true zeros from that of small non-zero values. However, this preservation of small non-zero values ​​can introduce overflow errors.

[0018] Figure 3C shows a histogram of symbol frequencies, as stored in frequency table 20. Symbol 0 appears 30 times, which is normalized to 2 for FREQ[0]. Symbol 1 appears 60 times, which is normalized to 4 for FREQ[1]. Symbol 255 appears 40 times, which is normalized to 3 for FREQ

[255] .

[0019] Symbols 2, 3, and 4 each appear once, and are normalized to 1 for FREQ[2], FREQ[3], and FREQ[4]. The total number of occurrences of symbols 0-4 is 93, or 93 / 4096 = 0.022, or 2.2% of the input block, but the total frequency of symbols 0-4 is 9, or 9 / 256 = 0.35, or 3.5% of the normalized block. Symbols 2-4 consume a larger proportion of the available states in the normalized block than their share in the input block. This can lead to overflow, especially when more symbols have small non-zero values.

[0020] Correcting overflow typically requires multiple reads of frequency table 20 to reduce the frequency and correct the overflow. One technique is to generate normalized frequencies for the entire input block and then sum the frequencies. An overflow signal is issued when the sum of the frequencies exceeds the number of states.

[0021] When an overflow signal is issued, frequency table 20 is scanned to find the symbol with the maximum frequency value. If the overflow value is less than one-quarter of that maximum value, the maximum value is subtracted from the overflow value. The overflow is thus compensated.

[0022] However, if the overflow exceeds one-quarter of the maximum value, more complex processing is required to compensate for the overflow. Scan frequency table 20 to find large frequencies equal to or greater than 9. For each large frequency, reduce FLOOR([FREQ[i]-1] / 8), where FLOOR is the round-down operator. Obtain the sum of all corrected frequencies to determine if the overflow has been corrected.

[0023] If the overflow is still not corrected, select a smaller frequency on the next pass through frequency table 20. Scan frequency table 20 to find large frequencies equal to or greater than 5. Decrease FLOOR([FREQ[i]-1] / 4) for each large frequency. Sum all corrected frequencies to determine if the overflow has been corrected.

[0024] If the overflow is still not corrected, a smaller frequency is selected on the fourth pass through frequency table 20. Frequency table 20 is scanned to find any frequency equal to or greater than 3. Each of these selected frequencies is reduced by FLOOR([FREQ[i]-1] / 2). During this correction process, the sum of all frequencies is obtained to determine whether the overflow has been corrected.

[0025] If a large overflow is not corrected after the fourth pass, then in the fifth pass, decrement 1 for each FREQ[i] equal to or greater than 2. This operation can be repeated if necessary until the overflow is eliminated and the sum of states is 256 or less.

[0026] Each read or pass through frequency table 20 may require a number of read clock cycles equal to the number of symbols, or 256 in this example. A worst-case block with many near-zero input symbol values ​​may require 6 passes, or 6 × 256 clock cycles. Encoding table generator 154 also needs to read all frequencies in frequency table 20, again 256 clock cycles, but encoding table generator 154 may have to wait up to 6 × 256 clock cycles to compensate for overflow and complete normalization.

[0027] Therefore, normalizing input blocks with many near-zero symbols can lead to overflow errors. These overflow errors may require multiple adjustments of the frequency table to compensate for the overflow before the encoding table is generated.

[0028] We desire a lossless compression system that does not sort the symbol frequency table. We also desire a data compressor capable of instantly correcting normalization overflow errors. Furthermore, we desire normalizing symbol occurrence counts and correcting potential overflows during frequency table creation or population without waiting for the frequency table to complete before compensating for overflow errors. We further desire the ability to perform normalization, overflow compensation, and code table generation in parallel. Finally, we desire to reduce the latency of normalization overflow correction to reduce the overall latency of the data compression engine. Attached Figure Description

[0029] Figure 1 shows a neural network whose weights and feature maps are compressed before storage or transmission.

[0030] Figure 2 shows a prior art data compressor for generating frequency tables.

[0031] Figures 3A-3C highlight the normalization of the number of occurrences of symbols to generate frequency tables.

[0032] Figure 4 This is a flowchart of normalizing the frequency of a symbol to generate a frequency table.

[0033] Figure 5 This is a flowchart of the overflow check sub-procedure.

[0034] Figure 6 This is a flowchart of the error compensation subprocess.

[0035] Figures 7A-7B It is a histogram of the number and frequency of symbols with overflow error compensation.

[0036] Figure 8 This demonstrates the parallel hardware implementing the normalized data compressor.

[0037] Figure 9 The symbol counter unit is displayed in more detail.

[0038] Figure 10Highlight the encoding table generation process before normalization is completed.

[0039] Figure 11 Display the entries in the encoding table.

[0040] Figure 12 Display usage Figure 4-9 The process of data encoding using hardware is a non-parallel process.

[0041] Figure 13 This shows the compressor process where steps 1 and 4 run in parallel.

[0042] Figure 14 This displays the compressor process where steps 1, 2, and 4 run in parallel.

[0043] Figure 15 This displays the compressor process, with steps 1, 2, 3, and 4 running in parallel. Detailed Implementation

[0044] This invention relates to improvements in data compression. The following description is intended to enable those skilled in the art to make and use the invention in the context of specific applications and their requirements. Various modifications to the preferred embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the invention is not intended to be limited to the specific embodiments shown and described, but is to be given the broadest scope consistent with the principles and novel features disclosed herein.

[0045] Figure 4 This is a flowchart of normalizing the occurrence count of symbols to generate a frequency table. The symbol counter counts the occurrence count of each symbol i as OCCUR[i], which can be stored in the occurrence memory. In step 402, when normalization of a new block begins, various parameters are initialized for the new block. The number of remaining unprocessed symbols in the block, SYM_REM, is set to the total number of non-zero occurrence symbols to be processed, TSYM. The remaining unprocessed states, ST_REM, are set to the maximum possible state number TSTATE in the frequency table, such as 256. The cumulative error EA is initially cleared to zero, and the temporary cumulative error EA_TMP is also cleared to zero. The symbol index selector i is initially set to point to the smallest symbol with non-zero occurrences.

[0046] In step 406, the occurrence memory 10 is read to load the occurrence value of symbol i. In step 407, when the occurrence count of a symbol is zero, or OCCUR[i] = 0, further processing of the zero-occurrence symbol is skipped, and the next symbol is obtained in steps 414 and 406. Otherwise, in step 408, the test value or temporary value FT[i] of the frequency is calculated using the following pseudocode:

[0047] If OCCUR[i] = 0, then FT[i] = 0;

[0048] Otherwise FREQ_RND[i] = round(OCCUR[i] / L).

[0049] If FREQ_RND[i] = 0, then FT[i] = 1;

[0050] Otherwise FT[i] = FREQ_RND[i].

[0051] Where FREQ_RND[i] is the rounded frequency and the normalization ratio L is the input block size BLK_SIZ divided by the total state TSTATE, or in this case 4096 / 256 = 16. This pseudocode sets FT[i] to 0 when OCCUR[i] = 0, sets FT[i] to 1 when OCCUR[i] > 0 and < L, and sets it to round(OCCUR[i] / L) when OCCUR[i] is equal to or greater than L. This preserves occurrence values close to zero that would otherwise be rounded to 0 during normalization.

[0052] Also in step 408, the temporary accumulated error EA_TMP is calculated as:

[0053] EA_TMP = EA + OCCUR[i] – FT[i] * L

[0054] This is the accumulated remainder or error from the rounding operation.

[0055] Then the overflow check step 420 is performed, as Figure 5 shown. When an overflow error is detected, it can be compensated using the error compensation 440 as Figure 6 shown. The overflow check step 420 sets FREQ[i] to FT[i] after adjusting any overflow error.

[0056] Rather than waiting for all symbols to be normalized and the frequency table 20 to be completely filled, the overflow error is checked and compensated immediately as the symbol index selector i advances through the input symbols.

[0057] After any overflow error is compensated by the overflow check step 420, in step 410, the accumulated error EA is set to EA + OCCUR[i] – FREQ[i] * L. The remaining symbols to be processed SYM_REM are decremented, and the remaining available states ST_REM are reduced by the current normalized frequency FREQ[i] of symbol i, or

[0058] ST_REM = ST_REM – FREQ[i].

[0059] In step 412, when the remaining symbol to be processed, SYM_REM, is greater than 0, in step 414, the symbol index selector i is decremented, and then in step 406, the occurrence of the next symbol, OCCUR[i], is loaded from the occurrence memory 10. This process loops and repeats for the next symbol. Once the remaining symbol SYM_REM reaches 0 in step 412, the normalization of this block is completed.

[0060] Figure 5 is a flowchart of the overflow check sub - process. The overflow check step 420 is called during normalization ( Figure 4 ). In step 422, when the temporary frequency FT[i] is equal to or less than 1, error compensation cannot be performed because the frequency is already at its lowest non - zero possible value. In step 424, the frequency is set to the temporary frequency, FREQ[i]=FT[i]. In step 436, FREQ[i] is returned to the normalization program.

[0061] In step 422, when the temporary frequency FT[i] is greater than 1, error compensation can be performed by reducing the frequency. In step 426, when the number of remaining states is less than the sum of the remaining symbols and the temporary frequency, or ST_REM < SYM_REM+FT[i], an overflow occurs. There are not enough remaining states to allocate states to the temporary frequency and the unprocessed symbols. Instead, in step 428, the frequency is set to the available states, or FREQ[i]=ST_REM - SYM_REM+1. In step 436, FREQ[i] is returned to the normalization program.

[0062] In step 426, when there is no overflow signal, the remaining states are sufficient to allocate FT[i] states for symbol i. In step 430, when the cumulative error is positive, then in step 434 the frequency is set to the temporary frequency, FREQ[i]=FT[i]. In step 436, FREQ[i] is returned to the normalization routine.

[0063] In step 426, when there is no overflow signal, and in step 430, the cumulative error is negative, then the error compensation step 440 is called ( Figure 6 ) to compensate for some of the cumulative error. The error compensation step 440 attempts to reduce the cumulative error and returns FREQ[i], which is then returned to the normalization program in step 436.

[0064] Figure 6 is a flowchart of the error compensation sub - process. The error compensation step 440 is called during the overflow check ( Figure 6 ). The adjustment or reduction of the frequency is calculated in two different ways, and then the smallest adjustment is selected and subtracted from the temporary frequency.

[0065] The first frequency adjustment FREQ_ADJ1 is calculated from the normalization ratio L and the temporary cumulative error EA_TMP, that is:

[0066] In step 442, FREQ_ADJ1 = FLOOR[((L-1)-EA_TMP) / L]

[0067] Since the temporary cumulative error is negative (step 430), Figure 5 This tests the adjustment of the entire temporary cumulative error.

[0068] In step 444, the second frequency adjustment FREQ_ADJ2 is calculated as follows:

[0069] FREQ_ADJ2=FT[i]-1

[0070] This test reduced the frequency to 1, its lowest non-zero value.

[0071] In step 466, the minimum frequency adjustment min(FREQ_ADJ1, FREQ_ADJ2) is selected as FREQ_ADJ, and in step 448 it is subtracted from the temporary frequency FT[i], FREQ[i] = FT[i] - FREQ_ADJ. Then in step 450, FREQ[i] returns to the overflow check procedure, and then returns upward to the normalization procedure.

[0072] Therefore, error compensation step 440 adjusts the entire temporary cumulative error if possible. If the entire temporary cumulative error is too large, it lowers the current frequency to its minimum non-zero value of 1.

[0073] Figures 7A-7B A histogram showing the number and frequency of symbol occurrences with overflow error compensation is displayed. Figure 7A The distribution of the number of occurrences of the input symbol OCCUR[i] is shown in Figure 2, which is stored in the occurrence memory 10. Figure 7B The symbol frequency distribution FREQ[i] is shown, which is stored in frequency table 20.

[0074] Normalization will change OCCUR[i]( Figure 7A ) convert to FREQ[i]( Figure 7B For example, by dividing OCCUR[i] by the normalization ratio L and rounding it, we get FREQ[i]. The shapes of the occurrence and frequency distribution curves are similar but not necessarily the same.

[0075] The occurrence count of symbols 0 through 9 is zero, so the first non-zero occurrence of a symbol is symbol 10. OCCUR

[10] is 5, and for L = 16, OCCUR[i] / L is 5 / 16, which is assigned FREQ

[10] = 1 to preserve non-zero occurrences. The error is 5–16, or -11, which becomes the first cumulative error EA. The remaining symbols and remaining states are decremented, and the next symbol 11 is processed.

[0076] OCCUR

[11] is 10, and 10 / 16 is rounded to 1, so FREQ

[11] is 1. The error or remainder of the current sign is 10–16, which is -6, so -6 is added to the previous accumulated error -11, resulting in a new EA of -17. Since FREQ

[10] and FREQ

[11] are the lowest non-zero values ​​of 1, these errors cannot be compensated yet.

[0077] The symbol 12 appears much more frequently, at 140, and 140 / 16 is 8.75, which rounds to 9. Therefore, the temporary frequency FT

[12] is 9. The temporary cumulative error EA_TMP is EA+OCCUR[i]–FT[i]*L, which is -17+140-9*16=-21.

[0078] FREQ_ADJ1 is FLOOR[((L-1)-EA_TMP) / L], which is FLOOR(15–(-21)) / 16 or FLOOR(36 / 16)=2, with a remainder of 4. Therefore, the temporary frequency FT

[12] =9 minus the frequency adjustment 2 to produce the final FREQ

[12] =7. The new cumulative error is -17+140-7*16=+11. Since the cumulative error is now positive, all previous errors have been compensated.

[0079] The number of remaining symbols decreased by 1, but the number of remaining states decreased by FREQ

[12] = 7, because encoding FREQ

[12] = 7 requires 7 states.

[0080] OCCUR

[13] = 90 and 90 / 16 = 5.625 for symbol 13, which is rounded to 6, so FT

[13] = 6. Since the cumulative error is positive, no compensation is needed, FREQ

[13] = FT

[13] = 6. The new cumulative error is EA + OCCUR[i] – FREQ[i] * L = +11 + 90 – 6 * 16 = +5.

[0081] The number of remaining symbols is reduced by 1, but the number of remaining states is reduced by FREQ

[13] = 6, because encoding FREQ

[13] = 6 requires 6 states. Then other non-zero occurrence symbols are processed, and for each processed symbol, the number of remaining symbols and the number of remaining states are reduced.

[0082] When processing the end of symbol 59 and the start of symbol 60, the accumulated error is EA = -2, SYM_REM = 3, and ST_REM = 5.

[0083] Each of symbols 60, 61, and 62 has OCCUR[i] = 40 and 40 / 16 = 2.5, which is rounded up to 3, so FT[i] = 3. However, after symbol 59 is processed and symbol 60 starts, there are only 5 remaining ST_REM states. There are also only 3 remaining symbols. At Figure 5 step 426, an overflow signal is issued because ST_REM < SYM_REM + FT[i] is 5 < 3 + 3. The number of remaining states is less than the sum of the remaining symbols and the temporary frequency. There are not enough remaining states to allocate states for the temporary frequency and the unprocessed symbols. Instead, at step 428, the frequency is set to the available states, or FREQ[i] = ST_REM – SYM_REM + 1 = 5 – 3 + 1 = 3. The new accumulated error is EA + OCCUR[i] – FREQ[i]*L = -2 + 40 – 3*16 = -10.

[0084] For symbol 61, OCCUR

[61] = 40, FT

[61] = 3, and both ST_REM and SYM_REM are 2. At Figure 5 step 426, an overflow signal is issued because ST_REM < SYM_REM + FT[i] is 2 < 2 + 3. The number of remaining states is less than the sum of the remaining symbols and the temporary frequency. There are not enough remaining states to allocate states for the temporary frequency and the unprocessed symbols. Instead, at step 428, the frequency is set to the available states, or FREQ[i] = ST_REM – SYM_REM + 1 = 2 – 2 + 1 = 1. The new accumulated error is EA + OCCUR[i] – FREQ[i]*L = -10 + 40 – 1*16 = +14.

[0085] For symbol 62, OCCUR

[62] = 40, FT

[62] = 3, and both ST_REM and SYM_REM are 1. At Figure 5 step 426, an overflow signal is issued because ST_REM < SYM_REM + FT[i] is 1 < 1 + 3. The number of remaining states is less than the sum of the remaining symbols and the temporary frequency. There are not enough remaining states to allocate states for the temporary frequency and the unprocessed symbols. Instead, at step 428, the frequency is set to the available states, or FREQ[i] = ST_REM – SYM_REM + 1 = 1 – 1 + 1 = 1. The new accumulated error is EA + OCCUR[i] – FREQ[i]*L = 14 + 40 – 1*16 = +38.

[0086] Figure 8The parallel hardware implementing the normalized data compressor is shown. Symbol counters 140 (Figure 2) and occurrence memory 10 are implemented in parallel to reduce latency. For example, assuming the input bus width of the compression / decompression module is 256 bits or 32 bytes, a 4KB symbol block can have 32 parallel instances of symbol counter units 50. Using 32 symbol counter units 50, a total of 32 bytes can be processed per clock cycle. A total of 128 clock cycles are required to input all 4KB bytes. Each symbol counter unit 50 has 256 storage locations or counters for 256 possible symbol values. After the symbol counter units 50 have processed the 4KB block, the 32 counter values ​​from the 32 instances of symbol counter units 50 are added by adder 58 to obtain the final occurrence value OCCUR[i] for each of the 256 symbol values. Adder 58 generates up to 256 OCCUR[i] values ​​over an additional 256 clock cycles, or a total of 128 + 256 = 384 clock cycles.

[0087] During the 256 clock cycles during which adder 58 generates and outputs 256 OCCUR[i] values, normalizer 62 uses Figure 4-6 Each OCCUR[i] value is processed using a method that generates a normalized FREQ[i] value for each OCCUR[i]. The FREQ[i] value is stored in frequency table 60 and processed through... Figure 5-6 The subprocess corrects for any overflows. The encoding table generator 64 reads each FREQ[i] value and generates one or more encoding table entries, which are copied and stored in 32 encoding table instances 70.

[0088] The encoding table generator 64 does not need to wait for all 256 FREQ[i] values ​​to be generated by the normalizer 62. Instead, as each FREQ[i] is generated by the normalizer 62, the encoding table generator 64 immediately generates an encoding table entry for that FREQ[i] value. Therefore, the normalizer 62 and the encoding table generator 64 can run concurrently without waiting for the frequency table 60 to complete. Normalization and encoding entry generation can be performed as a combined step, thus greatly reducing latency.

[0089] Since normalization and code table generation can be performed simultaneously, the code table generator 64 does not need to wait for the frequency table 60 to be filled. Therefore, the normalizer 62, frequency table 60, and code table generator 64 can operate together as a single stage, such as the normalizer-code generator stage 68. Using the normalizer-code generator stage 68 reduces latency, instead of having the code table generator 64 wait for the normalizer 62 to complete the generation of normalized symbol frequencies for all 256 possible symbols.

[0090] The encoding table is not a single table, but rather is copied 32 times as encoding table 70. Each encoding table 70 can encode one input byte from a 4KB input block. Therefore, 32 bytes can be encoded at a time per clock cycle. Encoding the entire 4KB input block to generate a compressed data block requires a total of 128 clock cycles. The encoded data packer 74 combines the 32 codes from each clock cycle over 128 clock cycles to form the compressed data payload. The encoded data packer 74 also appends a header, which may include a copy of the frequency table 60. The header and payload are output as a compressed block.

[0091] Figure 9 The symbol counter unit is shown in more detail. The partial occurrence memory 304 has 256 storage locations for 256 possible symbol values. Each storage location stores a partial counter that counts the number of symbol occurrences for the input byte input to the symbol counter unit.

[0092] The input symbol values ​​are used as storage addresses. Each symbol from the input block is applied to the partial occurrence memory 304 as the memory address A2 to be written to port 2.

[0093] Each time a memory location is written, the stored value in partial occurrence memory 304 increments. Therefore, partial occurrence memory 304 stores a counter value and is addressed by a sign value.

[0094] Partial appearance memory 304 is a two-port memory with one read port and one write port. Partial appearance memory 304 is read and updated when symbol counting occurs, and is read and summed by adder 58 when normalizer 62 reads the OCCUR[i] value.

[0095] A write cycle is a read-modify-write operation. A symbol is applied as a read address to A1, causing the location of that symbol in memory 304 to be read and output on Q1. When this is not the first access, multiplexer 308 passes Q1 to adder 310, which adds 1 to Q1 to increment the counter value. The incremented count from adder 310 is fed back to the write data input of D2 and written to the memory location applied to A2 as the write address for that symbol. Therefore, the old counter value is read from memory, incremented, and then written back to the memory.

[0096] Clearing all counters in the partial appearance memory 304 for each new input block would require special reset hardware or many clock cycles. Instead, each counter is cleared the first time a new block is accessed at that location. Memory 306 is a 256-bit memory with 256 1-bit storage locations. When the next block begins processing, all bits in memory 306 are cleared. A symbol is applied as an address to memory 304, causing the bit at that location to be read and applied to the control input of multiplexer 308. For the first access to a new symbol after a new block, the bit read from memory 306 will be 0, causing multiplexer 308 to drive 0 to adder 310, which can then be incremented and stored back in partial appearance memory 304. For that symbol location, a 1 is written back to memory 304, so future accesses using that symbol will output a 1 to multiplexer 308, causing it to pass the counter value from partial appearance memory 304.

[0097] Sometimes, the same symbol can appear twice in the input stream of the partial appearance memory 304. These back-to-backwrites may not allow enough time to write to the partial appearance memory 304. This continuation can be detected when the write address matches the read address because, in some embodiments, the partial appearance memory 304 is written during symbol counting and read immediately in the next clock cycle. The same symbol appears twice consecutively when the read address of the current symbol matches the write address of the next symbol immediately following the current symbol in the input block. For these two consecutive symbols, the counter should increment by 2. When the read and write symbols (addresses) match, adder 310 increments by 2 instead of 1. The second write can then be canceled.

[0098] Figure 10 The encoding table generation process performed before normalization is complete is highlighted. Instead of waiting for the frequency table to be filled and completed, the encoding table generator 64 generates encoding entries immediately as soon as the symbol frequency FREQ[i] is obtained from the normalizer 62.

[0099] Adder 58 will receive input from sign counter unit 50 ( Figure 8 The partial occurrences of the count are added to produce the OCCUR[i] of the current symbol i. Normalizer 62 executes... Figure 4 The process also includes performing overflow checks as needed when there is accumulated error and the FREQ[i] value is 2 or greater. Figure 5 ) and error compensation ( Figure 6 ).

[0100] Because accumulated errors are compensated during normalization, eventual overflow near the end of the block is prevented. The symbol frequency value FREQ[i] will not need to be adjusted later for overflow compensation as in the prior art, because error compensation is performed instantaneously when the FREQ[i] value is generated. Therefore, once the normalizer 62 generates an FREQ[i] value, that FREQ[i] value will not be adjusted later for overflow.

[0101] The normalized symbol frequency value FREQ[i] can be immediately allocated one or more entries in the encoding table because normalization and overflow processing limit the total number of symbol frequency values ​​to the number of states or slots in the encoding table. The symbol frequency value FREQ[i] does not depend on unprocessed symbols (>i). The encoding table will not prematurely exhaust states or entries. The encoding table will not overflow.

[0102] Therefore, the encoding table generator 64 can handle symbol frequencies FREQ[i], since they are available from the normalizer 62.

[0103] The encoding table generator 64 obtains the FREQ[i] value generated by the normalizer 62, either directly from the encoding table generator 64 or by reading the FREQ[i] entry from the frequency table 60. The value of FREQ[i] represents the number of entries or states corresponding to symbol i retained in the encoding table.

[0104] For example, symbol 1 has FREQ[1] = 5 in an entry of frequency table 60. Encoding table generator 64 creates 5 entries in the encoding table when processing FREQ[1] = 5. States 0 to 4 in encoding table 70 have the encoding for symbol 1.

[0105] The FREQ[3] of symbol 3 is 2, therefore the encoding table generator 64 reserves 2 entries for symbol 3 in the encoding table 70. These 2 entries, in states 5 and 6, have the encoding of symbol 3.

[0106] High-frequency symbols have larger FREQ[i] values, so more states are allocated in encoding table 70. These codes can use fewer bits than low-frequency symbols, resulting in a better compression ratio.

[0107] Figure 11 The entries in the encoding table are displayed. Each entry corresponds to a state. Larger FREQ[i] values ​​require more states than smaller FREQ[i] values. When FREQ[i] is 0, the encoding table generator 64 skips the symbol and does not create an entry for this missing symbol in the encoding table.

[0108] S0 is generated as FREQ[i] x 2 k–256, where k is the number of leading zeros in FREQ[i]. This k is encoded as a 4-bit value and stored in the encoding table entry.

[0109] The offset is generated as offset[i] = CDF[i] = FREQ[0] + FREQ[1] + FREQ[2] + ... + FREQ[i-1]. Then Delta0 is generated as offset[i] – FREQ[i] + 256 / 2. k Delta1 is generated as offset[i] – FREQ[i] + 256 / 2 k-1 S0, Delta0, and Delta1 are 10-bit signed numbers.

[0110] The encoding table generator 64 writes S0, k, Delta0, and Delta1 into entries in the encoding table. These values ​​allow the encoder to replace input symbols with the encoded bits of the output data payload. Compared to low-frequency symbols, high-frequency symbols can use fewer encoded bits, potentially resulting in a better compression ratio.

[0111] Figure 12 Showing the use Figure 4-9 The process involves non-parallel data encoding using both hardware and process logic. The number of clock cycles required to process a 4K block with 32 symbol counter units 50 and encoding table instances 70 is:

[0112] Step 1 – Data Input and Symbol Counting: Symbol counter unit 50 requires 128 clock cycles to count all symbols in the input block. All 4KB bytes of the input block are written to the input buffer, and a partial sum of OCCUR[i] and its value are written to symbol counter unit 50.

[0113] Step 2 – Normalization and Encoding Table Generation: Adder 58, normalizer 62, and encoding table generator 64 require 256 clock cycles to generate OCCUR[i], FREQ[i], and encoding table entries for all 256 possible symbols i. The occurrence count OCCUR[i] is read from symbol counter unit 50, FREQ[i] is written to frequency table 60, and encoding entries are written to encoding table 70.

[0114] Step 3 – Data Encoding: Encoding table 70 and encoded data packer 74 require 128 clock cycles to encode all 4K input symbols. The input buffer is read to obtain the input symbols, and encoding table 70 is read to obtain the encoding to replace the input symbols. The encoding is written to the output buffer.

[0115] Step 4 – Output Data: An additional 128 clock cycles may be needed to output all the encodings in the compressed block. The output table is read to obtain the encodings, forming the compressed data payload, and the frequency table is read and placed in the header.

[0116] Without pipelines, a total of 128 + 256 + 128 + 128 = 640 clock cycles are needed to process each 4K byte block.

[0117] Figure 13 The compressor flow is shown, with steps 1 and 4 running in parallel. It uses... Figure 4-9 The process and hardware. In this embodiment, steps 1 and 4 run in parallel within the same time slot, so they run within the same time period of the same clock cycle, but on different input symbol blocks. During the combined clock period of steps 1 and 4, for step 1, the input buffer is being written to and the symbol counter unit 50 is counting the symbols of the current input block, while for step 4, the output buffer and frequency table are being read to output the data from the previous input block.

[0118] The frequency table is copied. The frequency table (1) is written in step 2 and read in step 4. Since steps 1, 2, and 3 operate on the next block 2, while step 4 operates on the previous block 1, step 4 reads the frequency table (1) of the previous block, while step 2 writes the frequency table (2) of the next block. RD-FREQ TBL (1) stores the data from the previous data block. WR-FREQ TBL (2) stores the data of the current data block.

[0119] The number of clock cycles required to process a 4K block with 32 symbol counter units 50 and encoding table instances 70 is:

[0120] Steps 1 and 4 – Data Input and Symbol Counting & Output: Symbol counter unit 50 requires 128 clock cycles to count all symbols in the input block. The input buffer is written to all 4KB of the input block, and the partial sum OCCUR[i] and value are written to symbol counter unit 50. The output table is read to obtain the encoding, forming the compressed data payload, and the frequency table is read and placed in the header.

[0121] Step 2 – Normalization and Encoding Table Generation: Adder 58, normalizer 62, and encoding table generator 64 require 256 clock cycles to generate OCCUR[i], FREQ[i], and encoding table entries for all 256 possible symbols i. The occurrence count OCCUR[i] is read from symbol counter unit 50, FREQ[i] is written to frequency table 60, and encoding entries are written to encoding table 70.

[0122] Step 3 – Data Encoding: Encoding table 70 and encoded data packer 74 require 128 clock cycles to encode all 4K input symbols. The input buffer is read to obtain the input symbols, and encoding table 70 is read to obtain the codes to replace the input symbols. The codes are written to the output buffer.

[0123] Because steps 1 and 4 are performed in parallel, a total of 128 + 256 + 128 = 512 clock cycles are required. Steps 1, 2, and 3 operate on input block N+2, while step 4 operates on the previous input block N+1.

[0124] Figure 14 The compressor flow is shown, with steps 1, 2, and 4 running in parallel. It uses... Figure 4-9 The process and hardware are described. In this embodiment, steps 1, 2, and 4 are executed in parallel, so they run simultaneously within the same clock cycle. Step 1 operates on input block N+3, steps 2 and 3 operate on input block N+2, and step 4 operates on input block N+1.

[0125] During this pipeline stage clock cycle, for step 1, the input buffer is being written to, and the symbol counter unit 50 is counting symbols. For step 2, OCCUR[i] is read from the symbol counter unit 50 and added by the adder 58, allowing the normalizer 62 to write FREQ[i] into the frequency table 60. The encoding table generator 64 also writes the encoding entries into the encoding table 70.

[0126] The frequency table is copied. The frequency table (2) is written in step 2 and read in step 4. Since steps 2 and 3 operate on the next block N+3, while step 4 operates on the previous block N+1, step 4 reads the frequency table (1) of the previous block, while step 2 writes the frequency table (2) of the next block.

[0127] The output buffer is also copied. Step 3 writes encoded data to input block N+2, while step 4 reads encoded data from input block N+1.

[0128] Due to the parallelization of steps 1+2+4, each input block requires a total of 256+128=384 clock cycles.

[0129] Figure 15 The compressor flow is shown, with steps 1, 2, 3, and 4 running in parallel. It uses... Figure 4-9 The process and hardware. In the embodiment, steps 1, 2, 3, and 4 are run in parallel, so they run in the same time slot within the same clock cycle.

[0130] During the clock cycle of this pipeline phase, for step 1, the input buffer is being written to, and the symbol counter unit 50 is counting symbols. For step 2, OCCUR[i] is read from the symbol counter unit 50 and added by the adder 58, allowing the normalizer 62 to write FREQ[i] into the frequency table 60. The encoding table generator 64 also writes the encoding entries into the encoding table 70.

[0131] The input buffer, output buffer, frequency table, symbol counter unit 50, and encoding table 70 are copied to allow simultaneous operation on two different data blocks. Due to the parallel execution of steps 1+2+4, a total of 256 clock cycles are required for each input block.

[0132] Alternative embodiments

[0133] The inventors have also provided several other embodiments. For example, a 4KB input block with 8-bit symbols has been described as being normalized to a frequency table at a normalization ratio of 16, which is used to generate an encoding table with 256 states. These parameters can also be chosen with other values, such as using 16-bit symbols, 4-bit symbols, or other fixed-length symbols; different block sizes, such as 16KB; different normalization ratios, etc. Zero-occurrence symbols at the beginning and end of the block can be skipped, so processing begins with the first non-zero-occurrence symbol and ends with the last non-zero-occurrence symbol.

[0134] Many data formats are available for OCCUR[i], FREQ[i], or other values ​​such as signed, unsigned, two's complement, binary, etc. Various conversions and encodings can be used or stored in tables in different formats. For example, encoding table 70 may have entries storing actual encoded bits that replace input symbols to form a data payload, or these encoding entries may indicate how other logic, such as encoder 156 or encoded data packetizer 74, encodes the input symbols.

[0135] Although the FLOOR operator has been described, it can be replaced or modified by upper bound operators or other rounding operators, such as FT[i]. Modulo dividers can be used as the FLOOR operator and can be modified in various ways. Various biases or other operations can be added for various conditions, such as preserving small non-zero values ​​by assigning FREQ[i] = 1 to values ​​between, but not including, 0 and 1 (Figure 3B).

[0136] Cumulative error can be the accumulation of remainders from modulo division, where the number of occurrences of the sign is the divisor or modulus, with the normalization ratio L as the divisor or modulus. Cumulative error and remainders from rounding or modulo division can be defined as positive or negative. Incrementing instead of decrementing can be used instead of decrementing, and indices can start from 0 or 1, increasing from the initial maximum value instead of decreasing. Signs with zero occurrences can be skipped as described, or processed, and may be represented by null values ​​or other entries in the table.

[0137] The trigger or threshold for error compensation can be whenever the accumulated error is negative, or there can be some other thresholds, such as the accumulated error being more negative than a threshold like -5.

[0138] The encoding table generator 64 can create a single copy of the encoding table 70, and then copy the encoding table 70 to... Figure 8 Of the 32 instances shown, replicator logic can be added to copy entries from the first encoding table 70 generated by the encoding table generator 64 to the 32 encoding table 70 instances used during parallel encoding.

[0139] Although the 256 entries in frequency table 60 describe 8-bit symbols with 256 possible values, not all possible symbol values ​​will appear in any given data input block. Symbols that do not exist do not need to have entries in frequency table 60 or encoding table 70. Therefore, it can be understood that 256 is the maximum number of entries, and some blocks may have fewer entries than this maximum.

[0140] The number of unprocessed symbols remaining in the block, SYM_REM, can be set to the total number of non-zero occurrence symbols to be processed, TSYM. Alternatively, TSYM can be set to the total number of symbols to be processed from the first non-zero occurrence symbol to the last non-zero occurrence symbol, which may include intermediate zero occurrence symbols. Or, TSYM can be the total number of all symbols, determined by the input block size. For example, an 8-bit symbol (1 byte) input has 256 possible symbols, i.e., TSYM = 256.

[0141] The pipeline can be arranged in various ways, and there are many alternatives. Adder 58 can be placed in the first stage, producing the final occurrence count together with the sign counter, or, when there are many sign counter units, each operating on a different segment of the input block, adder 58 can be placed in the second stage, with occurrence memory 10 partitioned. Encoding table generator 64 can operate on several symbols after normalizer 62, but still within the same pipeline stage. A faster output buffer might allow steps 4 and 3 to be merged into the same pipeline stage. Various additional buffers and logic can be added to achieve a better pipeline. Some memory can be shared, for example, for occurrence memory 10 and encoding table 70, and some tables can be copied to allow different pipeline stages to operate on data from different input blocks.

[0142] Memory 306 can be implemented by registers, such as D-type flip-flops (DFFs) with reset or latches with reset. Both DFFs and latches with reset can be reset within one clock cycle.

[0143] The background section of this invention may include background information about the problem or environment of the invention, rather than a description of prior art. Therefore, the material included in the background section is not an admission of prior art by the applicant.

[0144] Any methods or processes described herein are machine-implemented or computer-implemented and are intended to be performed by machines, computers, or other devices, and not necessarily by humans alone without machine assistance. Tangible results may include reports or other machine-generated displays on display devices such as computer monitors, projection devices, audio generation devices, and related media devices, and may include hard-copy printouts that are also machine-generated. Computer control of other machines is another tangible result.

[0145] Any advantages and benefits described herein may not necessarily apply to all embodiments of the invention. When the word “device” appears in a claim element, the applicant intends that the claim element fall within the provisions of Section 112, Paragraph 6 of 35 USC. Typically, one or more words precede the word “device.” These one or more words preceding “device” are a label intended to facilitate reference to the claim element, not to express a structural limitation. Such device-plus-function claims must cover not only the structure described herein for performing the function and its structural equivalents, but also equivalent structures. For example, although nails and screws have different constructions, they are equivalent structures because they both perform the fastening function. Claims that do not use the word “device” do not fall within the provisions of Section 112, Paragraph 6 of 35 USC. Signals are typically electronic signals, but can also be optical signals, for example, transmitted via fiber optic lines.

[0146] The above description of embodiments of the invention is provided for illustrative and descriptive purposes. It is not intended to be exhaustive, nor is it intended to limit the invention to the precise forms disclosed. Many modifications and variations are possible based on the above teaching. The purpose is that the scope of the invention is not limited by this detailed description, but rather by the appended claims.

Claims

1. A data compression engine, comprising: Input, which is used to receive the input block of symbols; A symbol counter is used to count the number of times a symbol appears in the input block; A normalizer that normalizes the symbol occurrence counts from the symbol counter to generate symbol frequencies; The normalizer generates an error for each symbol frequency generated from the symbol occurrence count; A real-time error tracker that accumulates and tracks the error generated by the normalizer while the normalizer is processing the symbol occurrence count; A real-time overflow corrector is used to reduce the current symbol frequency of the current symbol and reduce the error tracked by the real-time error tracker, wherein the current symbol is not the last symbol in the input block; A frequency table, which stores the symbol frequencies generated by the normalizer; Thus, the normalization error is tracked and corrected in real time before the last symbol in the input block is normalized.

2. The data compression engine according to claim 1 further includes: An encoding table, which is used to store encoding entries; An encoding table generator that allocates states based on the symbol frequencies and generates encoding entries in the encoding table; A data encoder receives an input block of symbols and replaces the symbols in the input block with the codes of the coding entries in the coding table of the symbols to generate a data payload; An encoded data packer attaches a copy of the encoding table to the data payload to form compressed blocks.

3. The data compression engine according to claim 2, wherein, The encoding table generator and the normalizer have overlapping timing, wherein the encoding table generator generates partial encoding entries for the encoding table before the normalizer generates all symbol frequencies for the frequency table. The normalizer and the encoding table generator operate on the same input block at the same time; The encoding table generator is able to generate encoding entries for the encoding table before the normalizer finishes filling the frequency table, because the overflow is corrected instantly by the real-time overflow corrector. The error is the remainder of the rounding or modulo division operation performed by the normalizer.

4. The data compression engine according to claim 3, wherein, The normalizer also includes: A modulo divider, for each symbol, divides the symbol occurrence count by a normalization ratio to produce an integer quotient assigned to the symbol frequency and a remainder assigned to the error. Thus, the real-time error tracker accumulates and tracks the remainder from the modulo divider.

5. The data compression engine according to claim 2, wherein, When the current symbol frequency is at least 2 and the tracking error is reducible, the real-time overflow corrector is activated to reduce the current symbol frequency and the error tracked by the real-time error tracker.

6. The data compression engine according to claim 2, wherein, The symbol counter also includes: Multiple symbol counter units operate in parallel, each of which counts the number of times a symbol appears in a portion of the input block; An adder that sums the number of symbol occurrences from a plurality of the symbol counter units to generate the symbol occurrence count applied to the normalizer; Thus, symbol counting is performed in parallel.

7. The data compression engine according to claim 6, wherein, The encoding table also includes multiple local copies of the encoding table; The data encoder further includes multiple data encoder units operating in parallel. Each data encoder unit encodes a portion of the input block, and each data encoder unit reads the encoding from one of the multiple local copies of the encoding table.

8. The data compression engine according to claim 6, wherein, The symbol counter unit further includes: A memory is provided that has N addressable locations, where N is an integer representing the possible symbol values ​​in the input block of the symbol; An incrementer, whose incrementing counter is stored at a location in the occurrence memory, addressable by the symbol value of the current input symbol being processed from the input block of the symbol; and A reset mechanism is provided to clear the counter when a new input block is processed.

9. The data compression engine according to claim 2, wherein, The encoding table generator assigns multiple states to the symbol being processed, the number of states being equal to the symbol frequency value of the symbol being processed.

10. The data compression engine according to claim 9, wherein, When the number of remaining states in the encoding table is less than the number of unprocessed symbols in the input block plus the symbol frequency, the real-time overflow corrector reduces the symbol frequency to be equal to the number of remaining states in the encoding table minus the number of unprocessed symbols in the input block; Therefore, the real-time overflow corrector can prevent overflow when the number of remaining states is insufficient.

11. The data compression engine according to claim 2, wherein, The frequency table also includes: An odd frequency table, used to store the symbol frequencies of odd-numbered input blocks of symbols; An even-numbered frequency table, used to store the symbol frequencies of even-numbered input blocks of symbols; The input alternately receives the odd-numbered input block and the even-numbered input block; The normalizer alternately writes to the odd frequency table when processing the odd input block and writes to the even frequency table when processing the even input block. The encoded data packer alternately reads the odd frequency table when processing the odd input block and reads the even frequency table when processing the even input block. While the symbol counter is counting the symbols of the odd-numbered input blocks, the encoded data packer is reading the even-numbered frequency table. The encoded data packer and the symbol counter operate on different input blocks of symbols simultaneously.

12. The data compression engine of claim 11, wherein the encoding table further comprises: An odd-numbered encoding table, which stores the encoding entries of the odd-numbered input blocks of the symbol; An even-numbered encoding table, which stores the encoding entries of the even-numbered input blocks of the symbol; The encoding table generator writes the odd encoding table when processing the odd input block and writes the even encoding table when processing the even input block. Specifically, when the data encoder operates on the second input block, and when the encoding table generator and the normalizer operate on the third input block, and when the symbol counter operates on the fourth input block, the encoded data packer operates on the first input block. The input receives the first input block, the second input block, the third input block, and the fourth input block in sequence. Therefore, the four input blocks are processed by four pipeline stages in the same time slot.

13. A symbol frequency normalized data compressor, comprising: The input unit stores the input block of symbols in the input buffer and counts the number of times the symbols appear in the input block; The normalized encoder unit includes: A rounder divides the sign occurrence value from the input unit by a normalization ratio to produce a sign frequency and a remainder. A frequency table, which is used to store the symbol frequencies; An error tracker is used to accumulate the remainder from the rounder to obtain an accumulated error, and to track the accumulated error while processing symbols; An error compensator that reduces the current symbol frequency and decreases the accumulated error when the current symbol frequency is above 2 and the accumulated error exceeds one trigger; An encoding table generator assigns a number of states equal to the frequency of the current symbol to the current symbol and generates encoding entries for the current symbol; The encoding table generator and the rounder operate on the same input block simultaneously. The encoding table generator processes the symbols of the same input block as the rounder, and these symbols are within 10 symbols of the symbol being processed by the rounder. An encoding table, which stores encoding entries generated by the encoding table generator; The encoding unit reads symbols from the input buffer, reads an encoding entry from the encoding table for each symbol, and writes the encoding into the data payload in the output buffer using the encoding entry; and An output unit having an encoded data packer that copies the frequency table to a header and attaches the header to the data payload read from the output buffer as a compressed data block output.

14. The symbol frequency normalized data compressor according to claim 13, wherein, The input unit and the output unit operate simultaneously, wherein the frequency table is copied to store the symbol frequencies of two consecutive input blocks of symbols.

15. The symbol frequency normalized data compressor according to claim 14, wherein, The input unit, the output unit, and the normalized encoder unit operate simultaneously; The output buffer is duplicated to store the data payload of two consecutive input blocks of the symbol.

16. The symbol frequency normalized data compressor according to claim 15, wherein, The input unit, the output unit, the normalized encoder unit, and the encoding unit operate simultaneously; The encoding table is copied to store the encoding entries for two consecutive input blocks of a symbol; The input buffer is copied to store the input blocks of symbols for two consecutive input blocks.

17. A real-time error-compensated data compressor, comprising: Input, which is used to receive the input block of symbols; A symbol counter, used to count the number of times a symbol appears; A normalizer is used to divide the number of symbol occurrences from the symbol counter by a normalization ratio to generate a temporary symbol frequency and a remainder, wherein the normalizer generates a current temporary symbol frequency and a current remainder for the current symbol; An error tracker is used to accumulate the final error generated by the normalizer to generate the accumulated final error; An error corrector, which reduces the current temporary symbol frequency to generate a reduced final symbol frequency when the current remainder plus the accumulated final error exceeds a threshold and the current temporary symbol frequency is at least 2; A frequency table is used to store the current symbol frequency. When the error corrector reduces the current temporary symbol frequency, the frequency table stores the reduced final symbol frequency as the current symbol frequency. When the error corrector does not reduce the current temporary symbol frequency, the frequency table stores the current temporary symbol frequency as the current symbol frequency. An encoding table generator generates a current code for the current symbol immediately after writing the current symbol frequency into the frequency table. The current code has a number of states equal to the current symbol frequency value. The encoding table generator writes the current code into an encoding table. A state tracker having a remaining state counter that is initialized for a new block of symbols and that is decremented by the number of states for each current code generated by the encoding table generator; An overflow adjuster is used to reduce the current temporary symbol frequency to generate the reduced final symbol frequency when the count value of the remaining state counter is less than the number of unprocessed remaining symbols in the input block plus the current remainder and the current temporary symbol frequency is at least 2. An encoder that converts the current symbol in the input block into the current encoded symbol according to the current encoding in the encoding table, the encoder converting all symbols in the input block to generate a data payload; and An encoded data packetizer appends a copy of the frequency table to the data payload to generate a compressed block, which is then transmitted in place of the input block. The encoding table generator operates on the current symbol immediately after generating the current symbol frequency and writing it into the frequency table. Therefore, latency is reduced by running the encoding table generator in parallel with the normalizer and the error corrector to prevent overflow errors.

18. The real-time error-compensated data compressor according to claim 17, wherein, The normalizer uses an operator to divide the number of occurrences of the symbol, the operator being selected from: rounding operator, FLOOR operator, upper limit operator, or modulo operator.

19. The real-time error-compensated data compressor according to claim 17, wherein, The encoding table generator operates on the current symbol before the normalizer operates on a new current symbol that is more than two symbols away from the current symbol; Therefore, the encoding table generator and the normalizer simultaneously operate on the current symbols within two symbols apart in the input block.

20. The real-time error-compensated data compressor according to claim 17, wherein, The error tracker generates the accumulated final error by adding the previously accumulated final error to the number of times the current symbol appears, generated by the symbol counter for the current symbol, and subtracting the product of the current symbol frequency and the normalization ratio.

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