Method of forming top select gate trenches

Abstract

A method for fabricating a semiconductor device (100) having a first stack of alternating insulating layers (111) and sacrificial word line layers (112) arranged over a substrate (101), the first stack comprising a core region (170) and a staircase region (130). The method can comprise forming a first dielectric trench (121) in the core region (170) of the first stack; forming a second dielectric trench (122) adjacent to and connected with the first dielectric trench (121) in the staircase region (130) of the first stack; and forming a dummy channel structure (151) extending through the first stack, wherein the dummy channel structure (151) is spaced apart from the second dielectric trench (122).

Description

Technical Field

[0001] In summary, this application describes embodiments relating to semiconductor memory devices. Background Technology

[0002] Flash memory devices are widely used for electronic data storage in various modern technologies, such as smartphones, computers, etc. To increase storage density and reduce manufacturing costs, three-dimensional (3D) NAND flash memory devices have been developed. As 3D NAND technology advances towards higher densities and capacities (e.g., from 128 layers to 192 layers), high aspect ratio etching and subsequent filling can become increasingly difficult. Specifically, in channel-first manufacturing schemes, top-select gate (TSG) trench patterns are typically printed on a single photomask. The considerable depth of the TSG trenches can make etching and filling a challenging task. Although efforts have been made to mitigate this problem by adding vias to the TSG trenches, the etch profile can be distorted, and crack defects can form during subsequent thermal processes. Summary of the Invention

[0003] This disclosure provides various aspects of a semiconductor device having TSG trenches printed in two photomasks and methods for forming a semiconductor device having TSG trenches.

[0004] According to a first aspect, a semiconductor device is provided. The semiconductor device may include: a first stack of alternating insulating layers and word line layers on a substrate, wherein the first stack may include a core region and a step region, and the word line layers may include a TSG. In some embodiments, the word line layer further includes one or more dummy TSGs below the TSGs. In some embodiments, the word line layer may further include a gate line below the dummy TSGs, one or more bottom select gates (BSGs) below the gate lines, and a BSG below the one or more dummy BSGs.

[0005] The semiconductor device may further include: a first channel structure in the core region of the first stack and a dummy channel structure extending through the first stack. Furthermore, the first channel structure extends through the core region of the first stack. For example, the first channel structure may include a channel layer surrounded by one or more insulating layers. Additionally, the dummy channel structure is formed in at least one of the core region and the stepped region of the first stack.

[0006] The semiconductor device may further include a first TSG cutout structure in the core region and a second TSG cutout structure in the stepped region. The first TSG cutout structure is adjacent to and connected to the second TSG cutout structure. Both the first and second TSG cutout structures extend through the TSG and divide the TSG into sub-TSGs. In some embodiments, both the first and second TSG cutout structures extend through the one or more dummy TSGs and divide the one or more dummy TSGs into dummy sub-TSGs. Furthermore, the first TSG cutout structure may be made of a different dielectric material or the same dielectric material as the second TSG cutout structure. The first TSG cutout structure may have a different depth or the same depth as the second TSG cutout structure.

[0007] In other embodiments, the semiconductor device may include a second stack of alternating insulating and word line layers, sandwiched between the substrate and the first stack. The second stack may include a second channel structure in a core region of the second stack, extending through the core region and aligned with a corresponding first channel structure.

[0008] According to a second aspect of this disclosure, a method for manufacturing a semiconductor device is provided, wherein the semiconductor device has a first stack of alternating insulating layers and sacrificial word line layers disposed on a substrate, the first stack including a core region and a stepped region. The method may include: forming a first dielectric trench in the core region of the first stack; forming a second dielectric trench adjacent to and connected to the first dielectric trench in the stepped region of the first stack; and forming a dummy channel structure extending through the first stack, wherein the dummy channel structure is spaced apart from the second dielectric trench.

[0009] In some embodiments, forming the first dielectric trench in the core region of the first stack can be achieved by etching one or more pairs of alternating insulating layers and sacrificial word line layers in the core region of the first stack based on a first mask to form a first empty trench; and filling the first empty trench with a first dielectric material. Forming the second dielectric trench in the stepped region of the first stack can be achieved by etching one or more pairs of alternating insulating layers and sacrificial word line layers in the stepped region of the first stack based on a second mask to form a second empty trench adjacent to the first empty trench already filled with the first dielectric material; and filling the second empty trench with a second dielectric material. The first dielectric material may be the same as or different from the second dielectric material. Furthermore, forming a dummy channel structure extending through the first stack can be achieved by etching through the first stack based on a third mask to form a dummy channel aperture; and filling the dummy channel aperture with a third dielectric material. The dummy channel structure is formed in at least one of the core region and the stepped region of the first stack. In some embodiments, forming the second dielectric trench may further include: forming a mark on the substrate using a second mask, the second mask including the mark and a pattern of the second dielectric trench. The mark may be used for future alignment.

[0010] The method may further include: forming gate line cut trenches extending through the first stack; and replacing the sacrificial word line layer with a word line layer. The gate line cut trenches may extend in the same direction as the first dielectric trench and the second dielectric trench, and divide the first stack into a first sub-stack. In some embodiments, the word line layer includes a TSG at the top of the first stack, and the first dielectric trench and the second dielectric trench extend through the TSG, dividing the TSG into sub-TSGs. In some embodiments, the word line layer may further include one or more dummy TSGs below the TSG, and the first dielectric trench and the second dielectric trench may further extend through the one or more dummy TSGs, dividing the one or more dummy TSGs into dummy sub-TSGs.

[0011] In some embodiments, prior to forming the second dielectric trench, the method may include: forming a first channel structure in the core region of the first stack, wherein the first channel structure extends through the core region of the first stack; and forming the stepped region of the first stack. For example, the first channel structure may include a channel layer surrounded by one or more insulating layers.

[0012] In some embodiments, prior to forming a first stack of alternating insulating layers and sacrificial word line layers on the substrate, the method may include: forming a second stack of alternating insulating layers and sacrificial word line layers on the substrate, wherein the second stack is sandwiched between the first stack and the substrate; and forming a second channel structure in the core region of the second stack, wherein the second channel structure extends through the core region of the second stack and is aligned with a corresponding first channel structure. Attached Figure Description

[0013] The various aspects of this disclosure can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In practice, the dimensions of the various features may be increased or decreased for clarity of discussion.

[0014] Figure 1A and 1B Cross-sectional and top views of a semiconductor device according to exemplary embodiments of the present disclosure are shown respectively.

[0015] Figure 2-5 This is a cross-sectional view of a semiconductor device at various intermediate steps in the manufacturing process, according to exemplary embodiments of the present disclosure.

[0016] Figure 6 This is a flowchart illustrating an exemplary process for manufacturing an exemplary semiconductor device according to embodiments of the present disclosure. Detailed Implementation

[0017] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are merely examples and are not intended to be limiting. For example, forming a first feature on or over a second feature in the following description may include embodiments in which the first and second features can be in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. Such repetition is for simplicity and clarity and does not, in itself, prescribe relationships between the various embodiments and / or configurations discussed.

[0018] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0019] This disclosure provides a method for forming a top select gate (TSG) trench using two photomasks. The method may include sequentially forming a first dielectric trench, a channel structure, a step, a second dielectric trench, and a dummy channel structure. According to one aspect of this disclosure, the disclosed method can achieve various benefits compared to related examples. For example, related examples typically add vias to the TSG trench to facilitate the trench filling process, but the added vias inevitably make etching more difficult. Furthermore, crack defects may form during subsequent thermal processes. This disclosure avoids etching and filling problems by splitting the TSG trench across two photomasks and forming a portion of the TSG trench at the step. The resulting TSG trench does not need to extend through all word line layers and can withstand thermal processes without crack formation.

[0020] Figure 1A This is a cross-sectional view of a semiconductor device 100 according to an exemplary embodiment of the present disclosure. As shown, the device 100 may include a stack of alternating insulating layers 111 and word line layers 112 (also referred to as gate layers) disposed on a substrate 101 in a vertical direction. The insulating layers 111 may be made of an insulating material (e.g., silicon nitride, silicon dioxide, etc.). The word line layers 112 may be made of a gate stack material (e.g., a high-k gate insulator layer, a metal gate electrode, etc.).

[0021] Device 100 may further include a core region 170 and a stepped region 130. The core region 170 includes a plurality of channel structures (not shown, but to be described later) extending vertically through the stack. Figure 1B (This will be explained in detail below). The alternating stacking of insulating layers 111 and word line layers 112, together with the channel structure, can form a transistor stack, such as a vertical memory cell string array. In some examples, the transistor stack may include memory cells and select transistors, such as one or more bottom select transistors, one or more top select transistors, etc. In some examples, the transistor stack may also include one or more dummy select transistors. Accordingly, word line layer 112 may include one or more top select gates (TSGs), and may also include one or more dummy TSGs below the TSGs.

[0022] As shown in the figure, the stepped area 130 includes multiple stepped steps 110 formed by one or more pairs of alternating insulating layers 111 and word line layers 112. For example, in Figure 1A In this embodiment, the stepped step 110 is shown to have four pairs of alternating insulating layers 111 and word line layers 112. The stepped region 130 may also have an insulating layer 131 above the stepped step 110. Additionally, the top surface of the stepped region 130' may be at the same level as the top surface of the core region 170'. In some embodiments, the top surface of the channel structure (not shown) is at the same level as the top surface of the core region 170'.

[0023] Still in Figure 1A The device may include a TSG trench 120 having a first TSG cutout structure 121 in a core region 170 and a second TSG cutout structure 122 in a stepped region 130. Figure 1A In the example, the first TSG notch structure 121 is made of the same dielectric material (e.g., silicon oxide) as the second TSG notch structure 122. The first TSG notch structure 121 and the second TSG notch structure 122 are formed in separate steps and therefore can have different depths as shown. Of course, the first TSG notch structure 121 and the second TSG notch structure 122 can also have the same depth. Alternatively, the first TSG notch structure 121 can be made of a different dielectric material than the second TSG notch structure 122.

[0024] In addition, device 100 may include a plurality of dummy channel structures (not shown) extending through the stack, which will... Figure 1B A detailed explanation will be provided later.

[0025] Figure 1B This is a top view of device 100, wherein, in an embodiment where the first TSG cutout structure 121 is made of the same material as the second TSG cutout structure 122, Figure 1A The cross-sectional view of device 100 is taken along a line cutting AA' in the z-direction. As shown, device 100 may include a core region 170 and a stepped region 130. In some embodiments, the device may include more than one stepped region 130. Furthermore, device 100 may have various stepped configurations, such as a central stepped implementation, a side stepped implementation, etc.

[0026] Device 100 may also include one or more TSG trenches in TSG trenches 120 extending along the x-direction. Similarly, TSG trenches 120 include a first TSG cutout structure 121 in the core region 170 and a second TSG cutout structure 122 in the stepped region 130. Although in Figure 1BIn the example, device 100 is shown as including five TSG trenches 120, but it should be understood that device 100 may include any number of TSG trenches 120 to meet specific design requirements.

[0027] In embodiments where the stack includes one or more TSGs as mentioned above, the TSG trench 120 extends through the one or more TSGs and divides the one or more TSGs into sub-TSGs. In another embodiment where the stack also includes one or more dummy TSGs below the TSGs, the TSG trench 120 further extends through the one or more dummy TSGs and divides the one or more dummy TSGs into dummy sub-TSGs. For example, the stack may have a TSG and three dummy TSGs, so the TSG trench 120 extends through at least four pairs of alternating insulating layers and word line layers to divide the TSG and the three dummy TSGs into sub-TSGs and dummy sub-TSGs.

[0028] Device 100 may also include a plurality of dummy channel structures 151 in core region 170 and step region 130. In core region 170, the dummy channel structures 151 may extend through the TSG, dummy TSG, word line, dummy bottom select gate BSG, and BSG, and may further extend into the substrate (not shown). In step region 130, the dummy channel structures 151 may extend through the corresponding word line, dummy BSG, and BSG, and may further extend into the substrate (not shown). The dummy channel structures 151 may serve as mechanical components for supporting the stack when the sacrificial word line is removed during manufacturing. For example, the dummy channel structures 151 may be made of the same dielectric material as the TSG trench 120. It should be noted that in some embodiments, the dummy channel structures 151 may be selectively formed only in core region 170 or only in step region 130.

[0029] As previously Figure 1A As mentioned above, device 100 also includes a plurality of channel structures 171 in core region 170. Channel structures 171 may include a channel layer (e.g., polysilicon) surrounded by one or more insulating layers (e.g., a tunneling layer (e.g., silicon oxide), a charge trapping layer (e.g., silicon nitride), and a barrier layer (e.g., silicon oxide)), which together form an oxide-nitride-oxide structure surrounding the channel layer. Channel structures 171 can be used to form transistor stacks, and as described above, these descriptions will be omitted here.

[0030] Despite Figure 1BIn the example, dummy channel structures 151 and 171 are shown as dots aligned on a parallel line array, but dummy channel structures 151 and 171 can have any suitable array shape, such as a matrix array shape along the x and y directions, a zigzag array shape along the x or y direction, a honeycomb (e.g., hexagonal) array shape, etc. Dummy channel structures 151 and 171 can also have any suitable shape, such as a rectangle in the xy plane and a cylinder in the xz and yz planes. Additionally, device 100 can have multiple contact structures (not shown) extending through the insulating layer 131 in the stepped region 130. The multiple contact structures can be electrically connected to corresponding word line layers 112.

[0031] Figure 2-5 This is a cross-sectional view of a semiconductor device 200 at various intermediate steps of manufacturing according to exemplary embodiments of the present disclosure. Device 200 may refer to any suitable device, such as a memory circuit, a semiconductor chip (or die) (having memory circuitry formed on a semiconductor chip), a semiconductor wafer (having a plurality of semiconductor dies formed on a semiconductor wafer), a semiconductor chip stack, a semiconductor package (including one or more semiconductor chips assembled on a package substrate), etc.

[0032] Figure 2 A cross-sectional view of the semiconductor device 200 that will ultimately become device 100 is shown. As shown, device 200 includes a substrate 201, such as a silicon (Si) substrate in this example. Substrate 201 can also be any other suitable substrate, such as a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, and / or a silicon-on-insulator (SOI) substrate. The substrate can include semiconductor materials, such as group IV semiconductors, group III-V compound semiconductors, or group II-VI oxide semiconductors. Group IV semiconductors can include Si, Ge, or SiGe. Substrate 201 can be a bulk wafer or an epitaxial layer.

[0033] Alternating stacks of insulating layers 211 and sacrificial word lines 212 can be formed vertically on substrate 201. The insulating layer 211 corresponds to... Figure 1A The insulating layer 111 in the middle. The sacrificial word line layer 212 will eventually be made by Figure 1A The word line layer 212 is replaced by the word line layer 112. The sacrificial word line layer 212 may be made of a different material (e.g., silicon nitride) than the insulating layer 211 (e.g., silicon oxide).

[0034] Still in Figure 2In this process, a first dielectric trench 221 extending along the x-direction can be formed in the core region 270 of the stack. First, one or more pairs of alternating insulating layers 211 and sacrificial word line layers 212 can be removed by etching based on a mask. Second, a dielectric material such as silicon oxide can be deposited to fill the spaces left by the removed insulating layers 211 and sacrificial word line layers 212. Therefore, the depth of the first dielectric trench 221 can be controlled by etching and can vary depending on the specific application.

[0035] Similar to device 100, multiple channel structures (not shown) can be formed in the core region 270. The multiple channel structures of device 200 correspond to the multiple channel structures 171 of device 100. For simplicity, the descriptions have already been provided above and will be omitted here, except that a vertical memory cell string array can be formed, and after the sacrificial word line layer 212 is replaced by the word line layer, the word line layer 212 may include one or more TSGs and one or more dummy TSGs.

[0036] exist Figure 3 In the stack, a stepped region 230 is formed adjacent to the core region 270. The stepped region 230 may have multiple stepped steps 210, comprising one or more pairs of alternating insulating layers 211 and word line layers 212. For example, in... Figure 3 In this example, the stepped step 210 has four pairs of alternating insulating layers 211 and word line layers 212. Additionally, the top surface of the stepped region 230' may be at the same level as the top surface of the core region 270'. In this example, the top surface of the channel structure (not shown) is at the same level as the top surface of the core region 270'.

[0037] The stepped region 230 can be formed using a trimming etching method. First, a patterned mask can be formed on the stack such that the patterned mask exposes the end portions of the stack (not shown). The mask can include, for example, an amorphous carbon hard mask layer, a dielectric anti-reflective coating, a bottom anti-reflective coating, and a photoresist layer. Then, a first plasma etching process, well controlled by etching time or endpoint traces, can be performed to precisely remove the exposed end portions of the first four pairs of insulating layers 211 and sacrificial word line layers 212. Next, a trimming process can be applied to remove the end portions of the mask to expose more of the stack.

[0038] Subsequently, a second etching process can be performed to precisely remove the exposed end portions of the first four pairs and the next four pairs of insulating layers 211 and sacrificial word line layers 212. The mask can then be trimmed again, and a third etching process can be performed. Thus, the stepped region 230 can be formed through a multi-cycle trimming etching process.

[0039] It should be understood that a trimming etching method may require more than one mask because the original thickness of the mask limits the number of times the mask can be trimmed. Furthermore, device 200 can have various stepped configurations, such as a center stepped implementation or a side stepped implementation.

[0040] Finally, a planarized insulating layer 231 is formed on the stepped step 210. The planarized insulating layer 231 may be made of the same material as the first dielectric trench 221 (e.g., silicon oxide) and may be formed, for example, by a chemical vapor deposition process followed by a chemical mechanical planarization process.

[0041] exist Figure 4 In this process, a second dielectric trench 222 can be formed. As shown, one or more pairs of alternating insulating layers 211 and sacrificial word line layers 212 can be removed by mask-based etching. Similar to the first dielectric trench 221, the depth of the second dielectric trench 222 can be controlled by etching and can vary depending on the specific application. As shown, the first dielectric trench 221 can have a different depth than the second dielectric trench 222. Alternatively, the first dielectric trench 221 and the second dielectric trench 222 can have the same depth. In an example where TSGs and three dummy TSGs are stacked, the dielectric trench 220 extends through at least four pairs of alternating insulating layers 211 and sacrificial word line layers 212 to divide the TSGs and three dummy TSGs into sub-TSGs and dummy sub-TSGs. Additionally, although in Figure 4 In the example, the second dielectric trench 222 is shown as empty at this step, but it can also be filled with the same or different dielectric material as the first dielectric trench 221.

[0042] Still referencing Figure 4 In some embodiments, markings may also be formed on the substrate 201 so that the markings can be used for later alignment (not shown) during manufacturing. Furthermore, the markings and the second dielectric trench 222 may be printed on the same photomask and formed by the same etching and deposition processes.

[0043] exist Figure 5 In this configuration, multiple dummy channel structures (not shown) can be formed in the core region 270 and the stepped region 230. Due to the example embodiment of the dummy channel structure of device 200 and... Figure 1B The example embodiment of the dummy channel structure 151 of device 100 is similar, and therefore the explanation will be given by focusing on the differences. For example, a deposition process can be performed to simultaneously fill the dummy channel structure and the second dielectric trench 222 with the same dielectric material as the first dielectric trench 221. In some embodiments, a dielectric material different from that of the first dielectric trench 221 can be deposited.

[0044] Figure 6 This is a flowchart of an exemplary process 600 for manufacturing an exemplary semiconductor device according to embodiments of the present disclosure. Process 600 begins with a semiconductor device having a first stack of alternating insulating layers and sacrificial word line layers disposed on a substrate, wherein the first stack includes a core region and a stepped region. It should be noted that the sacrificial word line layers will eventually be replaced by word line layers.

[0045] At step S601, a first dielectric trench can be formed in the core region of the first stack. One or more pairs of alternating insulating layers and sacrificial word line layers can be etched based on a mask, and the etching depth can be controlled by the etching time or the endpoint trace. A dielectric material, such as silicon oxide, can then be deposited to fill the spaces left by the removed pair of insulating layers and sacrificial word line layers. A CMP process may be further required to planarize the deposited dielectric material.

[0046] In some embodiments, multiple channel structures can then be formed in the stack. The channel structure may include a channel layer surrounded by one or more insulating layers (such as tunneling layers, charge trapping layers, and barrier layers). The stacking of multiple channel structures and alternating insulating layers and word line layers can form a transistor stack, such as a vertical array of memory cells. In some examples, the transistor stack may include memory cells and select transistors (such as bottom select transistors and top select transistors), and may also include dummy select transistors. Accordingly, the word line layer may include one or more top select gates (TSGs), and may also include one or more dummy TSGs.

[0047] In some embodiments, a stepped region can then be formed in the stack via a multi-cycle trimming etch process. The device can have various stepped configurations, such as a center stepped implementation, a side stepped implementation, etc. Next, a planarized insulating layer can be formed on top of the stepped layer, and multiple contact structures extending through the planarized insulating layer can be formed. The multiple contact structures can be connected to corresponding sacrificial word line layers.

[0048] At step S602, a second dielectric trench adjacent to and connected to the first dielectric trench can be formed in the stepped region of the first stack. Similar to the first dielectric trench, the second dielectric trench can be formed by etching and deposition processes, and the depth of the second dielectric trench can be controlled by the etching process. Therefore, the second dielectric trench can have the same depth as the first dielectric trench or a different depth. Furthermore, in an example where the word line layer includes one or more TSGs and one or more dummy TSGs, both the first and second dielectric trenches extend through the TSGs and dummy TSGs, dividing the TSGs and dummy TSGs into sub-TSGs and dummy sub-TSGs. Additionally, the second dielectric trench can be formed of the same dielectric material as the first dielectric trench.

[0049] At step S603, dummy channels extending through the first stack can be formed in the core region and the step region. The dummy channel structure can serve as a mechanical component for supporting the stack when the sacrificial letter lines are removed during manufacturing. The dummy channel structure can be made of the same dielectric material as the dielectric trench. In some embodiments, the dummy channel structure is formed only in the core region or only in the step region.

[0050] It should be noted that additional steps may be provided before, during, and after process 600, and for additional embodiments of process 600, some of the described steps may be replaced, eliminated, or performed in a different order. For example, prior to step S601, a bottom stack of alternating insulating and sacrificial word line layers may be formed on the substrate, and an oxide layer may be formed on the bottom stack. The bottom stack may include a plurality of bottom channel structures extending through the bottom stack. Accordingly, the channel structure formed at step S601 will be aligned with the corresponding bottom channel structure. In some embodiments, after step S603, gate line cut trenches extending through the stack may be formed. The sacrificial word line layers may then be replaced with word line layers, and the gate line cut trenches may be filled with an insulating material.

[0051] The various embodiments described herein offer several advantages. For example, in related examples, the TSG trench is printed in a single photomask, and the TSG trench typically extends through the stack. The disclosed method splits the TSG trench onto two separate photomasks, forming one dielectric trench of the TSG trench at a time. Therefore, the depth of the two dielectric trenches can be adjusted individually. In another related example, where a second dielectric trench of the TSG trench is printed on the same photomask as the dummy channel structure, vias are typically added to the TSG trench to facilitate the trench filling process, and the TSG trench also extends through the stack. However, the added vias inevitably make etching more difficult. In the disclosed method, printing the second dielectric trench of the TSG trench on a photomask different from the dummy channel structure allows the TSG trench to extend only through a few pairs of alternating insulating layers and (sacrificial) word line layers, reducing the complexity of the associated etching and filling processes. Moreover, the TSG trenches formed by the disclosed method can withstand thermal processes without cracking (a common problem in related examples).

[0052] The foregoing outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. It will be understood by those skilled in the art that they can readily use this disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or advantages of the embodiments described herein. It will also be recognized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. A method for manufacturing a semiconductor device having a first stack of alternating insulating layers and sacrificial word line layers disposed on a substrate, the first stack including a core region and a step region, the method comprising: A first TSG cutout structure is formed in the core region of the first stack; A second TSG cut structure is formed in the stepped area of ​​the first stack, which is adjacent to and connected to the first TSG cut structure; as well as In the stepped area of ​​the first stack, a dummy channel structure extending through the first stack is formed, each of the dummy channel structures being spaced apart from the second TSG cutout structure.

2. The method according to claim 1, wherein, Forming the first TSG cutout structure in the core region of the first stack further includes: Based on the first mask, one or more pairs of alternating insulating layers and sacrificial word line layers are etched in the core region of the first stack to form a first empty trench; and The first empty trench is filled with a first dielectric material.

3. The method according to claim 2, wherein, Forming the second TSG cutout structure in the stepped region of the first stack further includes: Based on the second mask, one or more pairs of alternating insulating layers and sacrificial word line layers are etched in the stepped region of the first stack to form a second empty trench adjacent to the first empty trench already filled with the first dielectric material; and The second empty trench is filled with a second dielectric material.

4. The method according to claim 3, wherein, The dummy channel structure extending through the first stack further includes: Based on the third mask, etching is performed through the first stack to form dummy channel vias; and The dummy channel hole is filled using a third dielectric material.

5. The method according to claim 3, wherein, Forming the second TSG cut structure further includes: A mark is formed on the substrate using the second mask, the second mask containing the mark and a pattern of the second TSG cutout structure, and the mark is used for future alignment.

6. The method according to claim 3, wherein, The first dielectric material may be the same as or different from the second dielectric material.

7. The method according to claim 1, further comprising: A gate line cut-out trench is formed extending through the first stack, the gate line cut-out trench extending in the same direction as the first TSG cut-out structure and the second TSG cut-out structure and dividing the first stack into a first sub-stack; as well as The word line layer is used instead of the sacrificed word line layer.

8. The method according to claim 7, wherein: The word line layer includes a top select gate (TSG) at the top of the first stack; and The first TSG cutout structure and the second TSG cutout structure extend through the TSG and divide the TSG into sub-TSGs.

9. The method according to claim 8, wherein: The word line layer includes one or more dummy TSGs below the TSG; as well as The first TSG cutout structure and the second TSG cutout structure extend through the one or more dummy TSGs and divide the one or more dummy TSGs into dummy sub-TSGs.

10. The method according to claim 1, wherein, Before forming the second TSG cut structure, the method further includes: A first channel structure is formed in the core region of the first stack, the first channel structure extending through the core region of the first stack and including a channel layer surrounded by one or more insulating layers; and The stepped area that forms the first stack.

11. The method according to claim 10, wherein, Before forming the first stack of alternating insulating layers and sacrificial word line layers on the substrate, the method further includes: A second stack of alternating insulating layers and sacrificial word line layers is formed on the substrate, the second stack being sandwiched between the first stack and the substrate; and A second channel structure is formed in the core region of the second stack, the second channel structure extending through the core region of the second stack and aligned with a corresponding first channel structure.

12. The method according to claim 1, wherein, The dummy channel structure is also formed in the core region of the first stack.

13. A semiconductor device, comprising: A first stack of alternating insulating layers and word line layers on a substrate, the first stack including a core region and a step region, and the word line layers including a TSG; A first channel structure in the core region of the first stack, the first channel structure extending through the core region of the first stack and including a channel layer surrounded by one or more insulating layers; The first TSG cut structure in the core area and the second TSG cut structure in the stepped area are adjacent to and connected to each other. Both the first TSG cut structure and the second TSG cut structure extend through the TSG and divide the TSG into sub-TSGs. as well as The dummy channel structures extend through the first stack in the stepped area, each of the dummy channel structures being spaced apart from the second TSG cutout structure.

14. The semiconductor device according to claim 13, wherein: The first TSG cut structure is made of a dielectric material that is different from or the same as the second TSG cut structure.

15. The semiconductor device according to claim 13, wherein: The first TSG cut structure has a different depth or the same depth as the second TSG cut structure.

16. The semiconductor device according to claim 13, wherein: The word line layer also includes one or more dummy TSGs below the TSG; as well as Both the first TSG cutout structure and the second TSG cutout structure extend through the one or more dummy TSGs and divide the one or more dummy TSGs into dummy sub-TSGs.

17. The semiconductor device according to claim 16, wherein, The word line layer also includes a gate line below the dummy TSG, one or more bottom select gates (BSGs) below the gate line, and a BSG below the one or more dummy BSGs.

18. The semiconductor device of claim 13, further comprising: A second stack of alternating insulating and word line layers, the second stack being sandwiched between the substrate and the first stack; as well as A second channel structure in the core region of the second stack, the second channel structure extending through the core region of the second stack and aligned with the corresponding first channel structure.

19. The semiconductor device according to claim 18, wherein: The dummy channel structure extends through the second stack.

20. The semiconductor device according to claim 13, wherein: The dummy channel structure is also formed in the core region of the first stack.

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