Test sorting machine test parameter writing and foolproof method and device, electronic equipment and storage medium
By automating the acquisition and comparison of test parameters, the problem of parameter errors caused by manual adjustment in integrated circuit test sorting machines has been solved, achieving efficient and accurate chip testing and improving production efficiency and chip quality.
Patent Information
- Application Number
- CN202310025134.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-01-04
- Publication Date
- 2026-02-17
- Estimated Expiration
- 2043-01-04
AI Technical Summary
In existing technologies, the test parameters of integrated circuit test sorting machines need to be manually modified, which is prone to omissions or errors, resulting in low production efficiency and batch test anomalies. Furthermore, without system control, it is difficult to guarantee chip quality.
By acquiring the identity information of the chip under test, the system automatically retrieves and writes the corresponding test parameters, performs comparison and testing, and generates a driver file after ensuring parameter consistency. This automates the control of the test program's calls and reduces manual intervention.
It improves the efficiency and quality of chip testing, prevents test anomalies, ensures the accuracy and consistency of test parameters, and enhances production efficiency.
Smart Images

Figure CN116008781B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of integrated circuit product testing technology, and more particularly to a method, device, electronic device, and storage medium for writing test parameters and preventing mistakes in a test sorting machine. Background Technology
[0002] Different chips need to be tested in different testing environments. Therefore, when using an integrated circuit test sorter to test different chips, the test parameters of the test sorter need to be adjusted and reset according to the test requirements. However, each time the parameters are changed, they need to be manually modified and verified, which is prone to omissions or errors, leading to low production efficiency and batch test anomalies. Furthermore, the test sorter program lacks system control, making it difficult to detect and modify parameter errors in a timely manner, thus failing to guarantee the quality of the tested chips. Summary of the Invention
[0003] The purpose of this invention is to provide a test parameter writing and error prevention method, device, electronic device and storage medium for a test sorting machine. It can write the corresponding test parameters to the test sorting machine according to different chips and detect whether the written test parameters are correct, effectively preventing test abnormalities and reducing manual intervention in setting, which is beneficial to improving chip quality and test efficiency.
[0004] To achieve the above objectives, this invention discloses a method for writing test parameters and preventing mistakes in a test sorting machine, which includes the following steps:
[0005] S100: Obtain the identity information of the chip under test and retrieve the corresponding test parameters based on the identity information;
[0006] S101. Write the retrieved test parameters into the shared file of the test sorting machine;
[0007] S102. Read the test parameters from the shared file;
[0008] S103. Compare the read test parameters with the retrieved test parameters. If the read test parameters are consistent with the retrieved test parameters, proceed to step S104. If the read test parameters are inconsistent with the retrieved test parameters, repeat steps S100 to S103.
[0009] S104. Generate a driver file and send the driver file to the test sorting machine so that the test sorting machine can use the driver file to call the test program.
[0010] Further, step S104 includes:
[0011] S105. Read the test parameters in the shared file again after the set time;
[0012] S106. Compare the reread test parameters with the retrieved test parameters. If the reread test parameters are inconsistent with the retrieved test parameters, proceed to step S107. If the reread test parameters are consistent with the retrieved test parameters, proceed to step S108.
[0013] S107. Clear the driver file in the test sorting machine;
[0014] S108. Determine whether a batch of chips under test has been tested. If the test has not been completed, return to steps S105 and S106.
[0015] Further, step S106 includes:
[0016] S1061. Compare the reread test parameters with the retrieved test parameters;
[0017] S1062. Save the comparison results and the test parameters read again to the log file;
[0018] S1063. If the test parameters read again are inconsistent with the test parameters retrieved, then proceed to step S107. If the test parameters read again are consistent with the test parameters retrieved, then proceed to step S108.
[0019] Furthermore, the shared file is a parameter text file, which has multiple content fields. These content fields are used to record different test parameters, including test temperature, preset time, test mode, BIN position, chip disk specifications, card control yield, communication method, and site map.
[0020] To achieve the above objectives, the present invention discloses a test parameter writing and error-proofing device for a test sorting machine, comprising:
[0021] The retrieval module is used to acquire the identity information of the chip under test and retrieve the corresponding test parameters based on the identity information.
[0022] A writing module, which is used to write the retrieved test parameters into a shared file of the test sorting machine;
[0023] A reading module, which is used to read test parameters from the shared file;
[0024] The first comparison module is used to compare the read test parameters with the retrieved test parameters.
[0025] A generation and sending module is used to generate a driver file and send the driver file to the test sorting machine so that the test sorting machine can use the driver file to call the test program.
[0026] Optionally, the test parameter writing and error prevention device for the test sorting machine also includes:
[0027] The reread module is used to read the test parameters in the shared file again after a set time.
[0028] The second comparison module is used to compare the reread test parameters with the retrieved test parameters.
[0029] A clearing module is used to clear the driver files in the test sorting machine;
[0030] The judgment module is used to determine whether a batch of chips under test has been tested.
[0031] Optionally, the test parameter writing and error prevention device for the test sorting machine further includes a storage module, which is used to save the comparison results and the test parameters read again to a record file.
[0032] Optionally, the shared file is a parameter text file, which contains multiple content fields. These content fields are used to record different test parameters, including test temperature, preset time, test mode, BIN position, chip disk specifications, card control yield, communication method, and site map.
[0033] To achieve the above objectives, the present invention discloses an electronic device comprising:
[0034] One or more processors;
[0035] One or more memories are used to store one or more programs, which, when executed by the processor, cause the processor to implement the test parameter writing and error prevention method for the test sorting machine as described in any one of claims 1 to 4.
[0036] To achieve the above objectives, the present invention discloses a computer-readable storage medium having a program stored thereon, characterized in that, when the program is executed by a processor, it implements the test parameter writing and error prevention method for the test sorting machine as described above.
[0037] This invention incorporates a test parameter writing method for a test sorting machine and a foolproof mechanism. Based on the identification information of the chip under test (DUT), the corresponding test parameters are retrieved and written into a shared file of the test sorting machine. The retrieved test parameters are then compared with those in the shared file to verify the correctness of the written parameters. This ensures that the test parameters in the test sorting machine match the test requirements of the DUT. The automatic writing and detection processes effectively prevent test anomalies and reduce manual intervention. Only when the retrieved test parameters match the read parameters are a driver file generated and sent to the test sorting machine. The test sorting machine then uses the driver file to call the test program and begin testing the DUT. Otherwise, the steps of retrieving, writing, and comparing test parameters must be repeated, which improves chip quality and testing efficiency. Attached Figure Description
[0038] Figure 1 This is a flowchart illustrating the method for writing test parameters and preventing errors in a test sorting machine according to an embodiment of the present invention.
[0039] Figure 2 for Figure 1 The detailed flowchart of step 106 in the process.
[0040] Figure 3 This is a block diagram of the test parameter writing and error prevention device for the test sorting machine according to an embodiment of the present invention.
[0041] Figure 4 This is a block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation
[0042] To illustrate the technical content, structural features, objectives, and effects of the present invention in detail, the following description is provided in conjunction with the embodiments and accompanying drawings.
[0043] Please see Figure 1 and Figure 2 This invention discloses a method for writing test parameters and preventing mistakes in a test sorting machine, which includes the following steps:
[0044] S100: Obtain the identity information of the chip under test and retrieve the corresponding test parameters based on the identity information;
[0045] S101. Write the retrieved test parameters into the shared file of the test sorting machine;
[0046] S102, Read the test parameters from the shared file;
[0047] S103. Compare the read test parameters with the retrieved test parameters. If the read test parameters are consistent with the retrieved test parameters, proceed to step S104. If the read test parameters are inconsistent with the retrieved test parameters, repeat steps S100 to S103.
[0048] S104. Generate a driver file and send it to the test sorting machine so that the test sorting machine can use the driver file to call the test program.
[0049] This invention incorporates a test parameter writing method for a test sorting machine and a foolproof mechanism. Based on the identification information of the chip under test (DUT), the corresponding test parameters are retrieved and written into a shared file of the test sorting machine. The retrieved test parameters are then compared with those in the shared file to verify the correctness of the written parameters. This ensures that the test parameters in the test sorting machine match the test requirements of the DUT. The automatic writing and detection processes effectively prevent test anomalies and reduce manual intervention. Only when the retrieved test parameters match the read parameters are a driver file generated and sent to the test sorting machine. The test sorting machine then uses the driver file to call the test program and begin testing the DUT. Otherwise, the steps of retrieving, writing, and comparing test parameters must be repeated, which improves chip quality and testing efficiency.
[0050] Specifically, in this embodiment, the ERP system is responsible for writing test parameters into the test sorting machine and comparing the test parameters. However, it is not limited to this. The ERP system is associated with the test sorting machine through intranet sharing. When the test starts, the tester needs to enter the identity information of the chip under test into the ERP system so that the ERP system can obtain the identity information of the chip under test and retrieve the corresponding test parameters according to the identity information.
[0051] Furthermore, the identification information is the work order number of a batch of chips under test, but it is not limited to this. For example, in some embodiments, the model or batch number of the chip under test can be used as identification information to identify the chip type in order to retrieve the corresponding test parameters.
[0052] Furthermore, the driver file is a TestInof text file, but it is not limited to this. After the test parameters are matched, the ERP system will generate the driver file. If the comparison is inconsistent, the ERP system will pop up an error message, prompting the tester to re-enter the identity information of the chip under test into the ERP system so that the identity information can be retrieved again to re-recall, read and compare the test parameters until the comparison is successful and production can start normally.
[0053] See Figure 1 and Figure 2Furthermore, after step S104 of the test parameter writing and mistaken-proofing method for the test sorting machine, the following steps are included:
[0054] S105. Read the test parameters from the shared file again after the set time;
[0055] S106. Compare the reread test parameters with the retrieved test parameters. If the reread test parameters are inconsistent with the retrieved test parameters, proceed to step S107. If the reread test parameters are consistent with the retrieved test parameters, proceed to step S108.
[0056] S107. Clear the driver files in the test sorting machine;
[0057] S108. Determine whether a batch of chips under test has been tested. If the test has not been completed, return to steps S105 and S106.
[0058] By repeatedly reading and comparing the test parameters in the shared file within a set time period until the testing of a single batch of chips is completed, the reading and comparison are stopped. This ensures that the test parameters in the shared text of the test sorter are consistent with the retrieved test parameters during the testing of a single batch, thereby preventing batch testing anomalies and improving chip quality and testing efficiency.
[0059] Furthermore, the time is set to 10 minutes, which is similar to the chip's testing time, but it is not limited to this. It can be adjusted according to the time it takes for the test sorting machine to perform one test on the chip.
[0060] Specifically, in this embodiment, the test sorting machine includes a test machine and a sorting machine. The test machine uses a driver file to call the test program. If the test machine lacks the driver file to call the test program when it starts testing, the test machine will report a program error and be unable to test. The sorting machine will also alarm and stop and become unable to run because it cannot receive the sorting signal sent by the test machine.
[0061] See Figure 1 and Figure 2 Furthermore, step S106 of the test parameter writing and error prevention method for the test sorting machine includes:
[0062] S1061. Compare the reread test parameters with the retrieved test parameters;
[0063] S1062. Save the comparison results and the test parameters read again to the log file;
[0064] S1063. If the test parameters read again are inconsistent with the test parameters retrieved, then proceed to step S107. If the test parameters read again are consistent with the test parameters retrieved, then proceed to step S108.
[0065] By saving the comparison results and the reread test parameters after each test parameter comparison and detection, the results can be retrieved and recorded in subsequent troubleshooting, and can provide strong evidence that the test parameters of the sorting machine are normal during testing.
[0066] Specifically, in this embodiment, after each comparison of test parameters, the ERP system records and saves the comparison results and the test parameters read again with the work order number as the file name, and saves and uploads them to the server in text format, but is not limited to this.
[0067] See Figure 1 and Figure 2 Furthermore, the shared file is a parameter text file, which has multiple content fields. Each content field is used to record different test parameters, including test temperature, preset time, test mode, BIN position, chip disk specifications, card control yield, communication method, and site map.
[0068] By comparing the test parameters in the parameter text shared by the test sorter, it is ensured that the parameters are consistent with the test requirements of the chip under test, avoiding abnormal or missing test parameter writing, which helps to improve chip quality and improve the efficiency of parameter setting.
[0069] Please see Figure 3 The present invention also discloses a test parameter writing and error prevention device for a test sorting machine, comprising:
[0070] The retrieval module 201 is used to obtain the identity information of the chip under test and retrieve the corresponding test parameters based on the identity information.
[0071] The writing module 202 is used to write the retrieved test parameters into the shared file of the test sorting machine;
[0072] Reading module 203 is used to read test parameters from shared files;
[0073] The first comparison module 204 is used to compare the read test parameters with the retrieved test parameters.
[0074] The generation and sending module 205 is used to generate driver files and send them to the test sorting machine so that the test sorting machine can use the driver files to call the test program.
[0075] See Figure 3 The test parameter writing and error prevention device for the test sorting machine also includes:
[0076] The reread module 206 is used to read the test parameters in the shared file again after a set time.
[0077] The second comparison module 207 is used to compare the reread test parameters with the retrieved test parameters.
[0078] Clearing module 208 is used to clear the driver files in the test sorting machine;
[0079] Judgment module 209 is used to determine whether a batch of chips under test has been tested.
[0080] See Figure 3 The test sorting machine test parameter writing and error prevention device also includes:
[0081] The saving module 210 is used to save the comparison results and the test parameters read again to the record file.
[0082] Furthermore, the shared file is a parameter text file, which contains multiple content fields. These content fields are used to record different test parameters, including test temperature, preset time, test mode, BIN position, chip disk specifications, card control yield, communication method, and site map.
[0083] For a detailed description of the test parameter writing and error prevention device for the test sorting machine, please refer to the above-mentioned test parameter writing and error prevention method for the test sorting machine, which will not be repeated here.
[0084] Please see Figure 4 The present invention also discloses an electronic device comprising:
[0085] One or more processors 301;
[0086] One or more memories 302 are used to store one or more programs. When one or more programs are executed by the processor, the processor 301 implements the test parameter writing and error prevention method of the test sorting machine as described above.
[0087] This invention also discloses a computer-readable storage medium storing a program thereon, which, when executed by a processor, implements the test parameter writing and error-proofing method for the test sorting machine as described in the foregoing embodiments.
[0088] This application discloses a computer program product or computer program, which includes computer instructions stored in a computer-readable storage medium. The processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform the aforementioned test parameter writing and error-proofing method for a test sorting machine.
[0089] It should be understood that, in the embodiments of this application, the processor may be a central processing unit (CPU), but it may also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.
[0090] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by hardware related to computer program instructions. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.
[0091] The above-disclosed embodiments are merely preferred embodiments of the present invention and should not be construed as limiting the scope of the present invention. Therefore, any equivalent variations made in accordance with the claims of the present invention are still within the scope of the present invention.
Claims
1. A test handler test parameter write and fool-proofing method, comprising: The method comprises the following steps: S100, obtaining identity information of a chip to be tested, and calling corresponding test parameters according to the identity information; S101, writing the called test parameters into a shared file of a test handler; S102, reading the test parameters in the shared file; S103, comparing the read test parameters with the called test parameters, if the read test parameters are consistent with the called test parameters, executing step S104, if the read test parameters are inconsistent with the called test parameters, repeating steps S100 to S103; S104, generating a drive file and sending the drive file to the test handler, so that the test handler calls a test program using the drive file; After step S104, the method comprises the following steps: S105, reading the test parameters in the shared file again after a set time; S106, comparing the read test parameters again with the called test parameters, if the read test parameters again are inconsistent with the called test parameters, executing step S107, if the read test parameters again are consistent with the called test parameters, executing step S108; S107, clearing the drive file in the test handler; S108, judging whether a batch of chips to be tested is completed, if not, returning to steps S105 and S106.
2. The test handler test parameter write and fool-proofing method of claim 1, wherein, Step S106 comprises the following steps: S1061, comparing the read test parameters again with the called test parameters; S1062, saving the comparison result and the read test parameters again to a record file; S1063, if the read test parameters again are inconsistent with the called test parameters, executing step S107, if the read test parameters again are consistent with the called test parameters, executing step S108.
3. The test handler test parameter write and fool-proofing method of claim 1, wherein, The shared file is a parameter text, the parameter text is provided with a plurality of content columns, the content columns are respectively used for recording different test parameters, the test parameters comprise test temperature, preset time, test mode, BIN position, chip tray specification, yield control, communication mode and Site map.
4. A test handler test parameter write and fool-proofing device, comprising: The test handler test parameter writing and foolproof method and device of any one of claims 1 to 3 are realized, and the writing and foolproof device comprises: A calling module, the calling module is used for obtaining identity information of a chip to be tested, and calling corresponding test parameters according to the identity information; A writing module, the writing module is used for writing the called test parameters into a shared file of a test handler; A reading module, the reading module is used for reading the test parameters in the shared file; A first comparison module, the first comparison module is used for comparing the read test parameters with the called test parameters; A generating and sending module, the generating and sending module is used for generating a drive file and sending the drive file to the test handler, so that the test handler calls a test program using the drive file.
5. The test handler test parameter write and fool-proofing device of claim 4, wherein, Further comprising: A reading module again, the reading module again is used for reading the test parameters in the shared file again after a set time; A second comparison module, the second comparison module is used for comparing the read test parameters again with the called test parameters; A clearing module is configured to clear the drive file in the test handler; A judging module is configured to judge whether a batch of chips to be tested is completed.
6. The test handler test parameter write and fool-proofing device of claim 5, wherein, Further comprising: A saving module is configured to save the comparison result and the re-read test parameter to a record file.
7. The test handler test parameter write and fool-proofing device of claim 4 wherein, The shared file is a parameter text, and a plurality of content columns are arranged in the parameter text, and the content columns are respectively used to record different test parameters, and the test parameters include test temperature, preset time, test mode, BIN position, chip tray specification, yield control, communication mode, and Site map.
8. An electronic device, comprising: Comprise: One or more processors; One or more memories for storing one or more programs, when the one or more programs are executed by the processor, the processor implements the test handler test parameter writing and foolproof method as claimed in any one of claims 1 to 3.
9. A computer-readable storage medium having stored thereon a program, characterized in that, The program is executed by the processor to implement the test handler test parameter writing and foolproof method as claimed in any one of claims 1 to 3.
Citation Information
Patent Citations
Semiconductor test system
JP2004361219A