An interface multiplexing circuit, method, device, equipment and medium

Abstract

The present application discloses an interface multiplexing circuit, method, device, equipment and medium, relating to the technical field of servers. Both the BMC and the PCIe Switch of this circuit are connected to the same RJ45 network port. At this time, the on or off states of the first input terminal to the third input terminal of the data selector are controlled by the obtained first GPIO signal of the BMC and the second GPIO signal of the PCIe Switch, so as to be used for troubleshooting the PCIe Switch or firmware upgrade. The original solution in which both the BMC and the PCIe Switch are respectively connected to an RJ45 network port is replaced with the solution in which both the BMC and the PCIe Switch are connected to one RJ45 network port, thereby realizing the simplification of the troubleshooting of the PCIe Switch device and firmware upgrade without additionally occupying the panel space.

Description

Technical Field

[0001] This application relates to the technical field of servers, and particularly to an interface multiplexing circuit, method, device, equipment and medium. Background Art

[0002] PCIe bus switching chips (PCIe Switch) are widely used in servers, which are used to expand PCIe (Peripheral Component Interconnect express) signals to enable the system to support more PCIe devices, such as GPU cards, network cards, IB cards, etc. PCIe interfaces are common high-speed interfaces in various servers. However, due to the limitation of the number of ports of the CPU itself, the number of PCIe devices that the server motherboard can support is limited. With the wide application of artificial intelligence (AI) servers and all-flash servers, the PCIe interfaces of the CPU itself can no longer meet the requirements of business operations. Therefore, more and more server system designs support PCIe Switch boards as high-speed IO extensions of the CPU to support more PCIe devices and meet customer needs. With the continuous improvement and update of the functions of PCIe Switch boards, during the entire R & D and testing processes, corresponding troubleshooting and firmware upgrade work of the boards need to be arranged.

[0003] The existing methods for troubleshooting and firmware upgrade are to design additional Universal Asynchronous Receiver / Transmitter (UART) interfaces and RJ45 network ports for the PCIe Switch. Using the UART interface requires corresponding debug tools, software, and drivers to perform operations such as troubleshooting and firmware upgrade of PCIe Switch devices. Moreover, jumper pins need to be placed inside the board, and then special serial devices and tools provided by the manufacturer are used. The operation of achieving troubleshooting and firmware upgrade is relatively complex; using the RJ45 network port to perform operations such as troubleshooting and firmware upgrade of PCIe Switch devices requires the server panel to provide an additional network interface, which occupies panel space. In addition, the above methods all require on-site support, and using the UART interface requires powering off the entire machine and opening the case for operation, which greatly affects the business.

[0004] In view of the above problems, finding a way to simplify the troubleshooting and firmware upgrade of PCIe Switch devices without occupying additional panel space is a problem that those skilled in the art are striving to solve. Summary of the Invention

[0005] The purpose of this application is to provide an interface multiplexing circuit, method, device, equipment and medium, which are used to simplify the troubleshooting and firmware upgrade of PCIe Switch devices without occupying additional panel space.

[0006] To solve the above technical problems, this application provides an interface multiplexing circuit, including: BMC, PCIe Switch, data selector, exclusive-OR gate, RJ45 network interface;

[0007] One end of the BMC is connected to the first input end of the exclusive-OR gate to facilitate obtaining the first GPIO signal of the BMC; one end of the PCIe Switch is connected to the second input end of the exclusive-OR gate to facilitate obtaining the second GPIO signal of the PCIe Switch; the output end of the exclusive-OR gate is connected to the first input end of the data selector, and the other end of the BMC is connected to the second input end of the data selector; the other end of the PCIe Switch is connected to the third input end of the data selector, and the output end of the data selector is connected to the RJ45 network interface to control the on state or off state of the first input end to the third input end of the data selector according to the first GPIO signal and the second GPIO signal to control the troubleshooting or firmware upgrade of the PCIe Switch.

[0008] Preferably, it further includes: at least 2 PHY registers;

[0009] One end of one of the PHY registers is connected to the other end of the BMC; the other end of the PHY register is connected to the second input end of the data selector; one end of the other PHY register is connected to the other end of the PCIe Switch; the other end of the PHY register is connected to the third input end of the data selector.

[0010] Preferably, the data selector is a one-for-two data selector.

[0011] To solve the above technical problems, this application also provides an interface multiplexing method, which is applied to an interface multiplexing circuit including BMC, PCIe Switch, data selector, exclusive-OR gate, RJ45 network interface and at least 2 PHY registers, including:

[0012] Obtain the first GPIO signal of the BMC and the second GPIO signal of the PCIe Switch;

[0013] Control the first input end to the third input end of the data selector to be in an on state or an off state according to the first GPIO signal and the second GPIO signal;

[0014] Control the troubleshooting or firmware upgrade of the PCIe Switch according to the on state or off state of the first input end to the third input end of the data selector.

[0015] Preferably, before obtaining the first GPIO signal of the BMC and the second GPIO signal of the PCIe Switch, it further includes:

[0016] Obtain the LAN signal to facilitate connecting at least two PHY registers and the data selector through the LAN signal.

[0017] Preferably, after obtaining the first GPIO signal of the BMC and the second GPIO signal of the PCIe Switch, before controlling the first input terminal to the third input terminal of the data selector to be in the conducting state or the off state according to the first GPIO signal and the second GPIO signal, it further includes:

[0018] Determine whether the BMC and the PCIe Switch are in the powered-on state;

[0019] If so, set both the first GPIO signal and the second GPIO signal to low-level signals;

[0020] If not, output a power-on signal for controlling the BMC and the PCIe Switch to be in the powered-on state.

[0021] Preferably, after issuing the power-on signal, it further includes:

[0022] Output a prompt message indicating that the BMC and the PCIe Switch are in the powered-on state.

[0023] To solve the above technical problems, the present application also provides an interface multiplexing device, which is applied to an interface multiplexing circuit including a BMC, a PCIe Switch, a data selector, an exclusive OR gate, an RJ45 network interface, and at least two PHY registers, and includes:

[0024] A first acquisition module for acquiring the first GPIO signal of the BMC and the second GPIO signal of the PCIe Switch;

[0025] A first control module for controlling the first input terminal to the third input terminal of the data selector to be in the conducting state or the off state according to the first GPIO signal and the second GPIO signal;

[0026] A second control module for controlling the troubleshooting or firmware upgrade of the PCIe Switch according to the conducting state or the off state of the first input terminal to the third input terminal of the data selector.

[0027] In addition, the device further includes the following modules:

[0028] Preferably, before obtaining the first GPIO signal of the BMC and the second GPIO signal of the PCIe Switch, it further includes:

[0029] A second acquisition module, configured to acquire a LAN signal, so as to connect at least two PHY registers and a data selector through the LAN signal.

[0030] Preferably, after acquiring the first GPIO signal of the BMC and the second GPIO signal of the PCIe Switch, before controlling the first input terminal to the third input terminal of the data selector to be in an on state or an off state according to the first GPIO signal and the second GPIO signal, it further includes:

[0031] A judgment module, configured to judge whether the BMC and the PCIe Switch are in a powered-on state;

[0032] If so, both the first GPIO signal and the second GPIO signal are set to low-level signals;

[0033] If not, a power-on signal is output, configured to control the BMC and the PCIe Switch to be in a powered-on state.

[0034] Preferably, after the power-on signal is issued, it further includes:

[0035] An output module, configured to output a prompt message indicating that the BMC and the PCIe Switch are in a powered-on state.

[0036] To solve the above technical problems, the present application further provides an interface multiplexing device, including:

[0037] A memory, configured to store a computer program;

[0038] A processor, configured to point to the computer program and implement the steps of the interface multiplexing method.

[0039] To solve the above technical problems, the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the above-mentioned entire interface multiplexing method are implemented.

[0040] An interface multiplexing circuit provided by the present application includes: a BMC, a PCIe Switch, a data selector, an exclusive OR gate, and an RJ45 network interface. One end of the BMC is connected to the first input terminal of the exclusive OR gate to facilitate obtaining the first GPIO signal of the BMC; one end of the PCIe Switch is connected to the second input terminal of the exclusive OR gate to facilitate obtaining the second GPIO signal of the PCIe Switch; the output terminal of the exclusive OR gate is connected to the first input terminal of the data selector, and the other end of the BMC is connected to the second input terminal of the data selector; the other end of the PCIe Switch is connected to the third input terminal of the data selector, and the output terminal of the data selector is connected to the RJ45 network interface to control the on or off state of the first to third input terminals of the data selector according to the first GPIO signal and the second GPIO signal, thereby controlling the troubleshooting or firmware upgrade of the PCIe Switch. The solution of respectively connecting a corresponding RJ45 network interface to the original BMC and PCIe Switch is replaced by connecting both the BMC and the PCIe Switch to one RJ45 network interface, thereby simplifying the troubleshooting and firmware upgrade of the PCIe Switch device without additionally occupying the panel space.

[0041] The present application also provides an interface multiplexing method, device, equipment, and medium with the same effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To more clearly illustrate the embodiments of the present application, the following will briefly introduce the drawings required for use in the embodiments. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 It is a circuit diagram of an interface multiplexing provided by an embodiment of the present application;

[0044] Figure 2 It is a flowchart of an interface multiplexing method provided by an embodiment of the present application;

[0045] Figure 3 It is a structural diagram of an interface multiplexing device provided by an embodiment of the present application;

[0046] Figure 4 It is a structural diagram of an interface multiplexing equipment provided by an embodiment of the present application.

[0047] Among them, 10 is the BMC, 11 is the PCIe Switch, 12 is the data selector, 13 is the RJ45 network interface, and 14 is the PHY register. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0048] The following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0049] The core of the present application is to provide an interface multiplexing circuit, method, device, equipment and medium, which can simplify the troubleshooting and firmware upgrade of PCIe Switch devices without additionally occupying panel space.

[0050] In order to enable those skilled in the art to better understand the solution of the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0051] Figure 1 A circuit diagram of an interface multiplexing for an embodiment of the present application is shown as Figure 1 As shown, the interface multiplexing circuit includes: BMC, PCIe Switch, data selector, exclusive-OR gate, and RJ45 network interface.

[0052] One end of the BMC is connected to the first input terminal of the exclusive-OR gate to facilitate obtaining the first GPIO signal of the BMC; one end of the PCIe Switch is connected to the second input terminal of the exclusive-OR gate to facilitate obtaining the second GPIO signal of the PCIe Switch; the output terminal of the exclusive-OR gate is connected to the first input terminal SEL of the data selector, and the other end of the BMC is connected to the second input terminal A0 of the data selector; the other end of the PCIe Switch is connected to the third input terminal A1 of the data selector, and the output terminal B of the data selector is connected to the RJ45 network interface to control the on-state or off-state of the first input terminal to the third input terminal of the data selector according to the first GPIO signal and the second GPIO signal to control the troubleshooting or firmware upgrade of the PCIe Switch. Among them, it further includes: at least two PHY registers; one end of one PHY register is connected to the other end of the BMC; the other end of the PHY register is connected to the second input terminal of the data selector; one end of the other PHY register is connected to the other end of the PCIe Switch; the other end of the PHY register is connected to the third input terminal of the data selector, and the data selector is a two-to-one data selector. The other ends of the BMC and the PCIe Switch are both connected to the PHY register through the RGMII signal, and the other ends of the two PHY registers are respectively input to the second input terminal and the third input terminal of the data selector through the MDI signal, and the output terminal of the data selector is also connected to the RJ45 network interface through the MDI signal.

[0053] Among them, two or more machines can be connected to the same PCIe Switch, and partition configuration is performed on the PCIe Switch to allocate some EP devices to a certain server. In this way, unified management and flexible allocation can be achieved. When the Basic Input Output System (BIOS) or Operating System (OS) of each server enumerates the PCIe bus, it will only find the virtual bridge, virtual bus (virtual BUS), and EP allocated to it. Multiple partitions do not interfere with each other. Multiple independent servers are connected to the same Switch. Since two OSs will respectively enumerate the roles within the same set of PCIe buses and allocate access addresses to them, conflicts will occur at this time. In some special scenarios of NTB, such as multiple controllers in a traditional storage system, they need to synchronize a lot of data and control information and hope to use the PCIe link for direct communication. However, two servers cannot communicate directly because they must be in two different partitions. To meet this requirement, the NTB technology emerged. Its basic principle is address translation because the address spaces of the two different systems overlap. Then, as long as the corresponding data packets are subjected to address mapping translation inside the PCIe Switch, communication between the two parties can be achieved. This bridging technology with address translation is called a Non-Transparent Bridge.

[0054] RJ45 network interfaces are usually used for data transmission, and the most common application is the network card interface. RJ45 network interfaces are a type of various different connectors (for example: RJ11 is also a type of connector, but it is used on telephones). RJ45 network interfaces are divided into two types, T568A and T568B, according to different wire sorting; T568B is orange-white, orange, green-white, blue, blue-white, green, brown-white, brown; T568A is green-white, green, orange-white, blue, blue-white, orange, brown-white, brown; therefore, there are also two types of wires using RJ45 network interfaces, namely: straight-through cables and crossover cables. There are two common types of RJ45 network interfaces: the DTE type used for Ethernet network cards, Ethernet interfaces of routers, etc., and the DCE type used for switches, etc. We can call DTE "data terminal equipment", and we can call DCE "data communication equipment"; in a sense, DTE devices are called "active communication devices", and DCE devices are called "passive communication devices"; when two devices of the same type use RJ45 network interfaces to connect and communicate, a crossover cable must be used for connection. Among them, the straight-through cable interconnection is: both ends of the network cable are connected according to T568B, and it is used to connect the host and the device, that is, DTE and DCE, such as: connecting a computer to an ADSL modem, connecting the ADSL modem to the WAN port of an ADSL router; connecting a computer to the LAN port of an ADSL router; connecting a computer to a hub or a switch. Among them, the crossover cable interconnection is: one end of the network cable is connected according to T568B, and the other end is connected according to T568A, and it is used to connect the host to the host, or the device to the device, such as: connecting a computer to a peer-to-peer network of a computer; connecting a hub to a hub; connecting a switch to a switch.

[0055] An interface multiplexing circuit provided by this application includes: BMC, PCIe Switch, data selector, exclusive-OR gate, and RJ45 network interface. One end of the BMC is connected to the first input terminal of the exclusive-OR gate to facilitate obtaining the first GPIO signal of the BMC; one end of the PCIe Switch is connected to the second input terminal of the exclusive-OR gate to facilitate obtaining the second GPIO signal of the PCIe Switch; the output terminal of the exclusive-OR gate is connected to the first input terminal of the data selector, and the other end of the BMC is connected to the second input terminal of the data selector; the other end of the PCIe Switch is connected to the third input terminal of the data selector, and the output terminal of the data selector is connected to the RJ45 network interface to facilitate controlling the conduction state or the off state of the first input terminal to the third input terminal of the data selector according to the first GPIO signal and the second GPIO signal to control the troubleshooting or firmware upgrade of the PCIe Switch. The original solution of connecting a RJ45 network interface to both the BMC and the PCIeSwitch is replaced by connecting both the BMC and the PCIe Switch to one RJ45 network interface, so as to simplify the troubleshooting and firmware upgrade of the PCIe Switch device without occupying additional panel space.

[0056] Figure 2 The flowchart of an interface multiplexing method provided by an embodiment of the present application is shown as Figure 2 shown. This method is applied to an interface multiplexing circuit including a BMC, a PCIe Switch, a data selector, an exclusive OR gate, an RJ45 network interface, and at least two PHY registers, and includes:

[0057] S20: Obtain a first GPIO signal of the BMC and a second GPIO signal of the PCIe Switch.

[0058] S21: Control the first input terminal to the third input terminal of the data selector to be in a conducting state or a cutoff state according to the first GPIO signal and the second GPIO signal.

[0059] S22: Control the PCIe Switch to troubleshoot or upgrade the firmware according to the conducting state or the cutoff state of the first input terminal to the third input terminal of the data selector.

[0060] It should be noted that both the first GPIO signal and the second GPIO signal are GPIO signals that can switch between high-level and low-level signals. Therefore, after obtaining the first GPIO signal of the BMC and the second GPIO signal of the PCIe Switch, before controlling the first input terminal to the third input terminal of the data selector to be in a conducting state or a cut-off state according to the first GPIO signal and the second GPIO signal, it further includes: determining whether the BMC and the PCIe Switch are in a powered-on state; if so, setting both the first GPIO signal and the second GPIO signal to low-level signals; if not, outputting a power-on signal for controlling the BMC and the PCIe Switch to be in a powered-on state. In addition, before obtaining the first GPIO signal of the BMC and the second GPIO signal of the PCIe Switch, it further includes: obtaining a LAN signal to facilitate connecting at least two PHY registers and the data selector through the LAN signal. The LAN signal is a signal of the entire network, and the PHY register and the data selector are connected through this network signal. Among them, the power-on signal can be expressed in the form of text or a data string. When the power-on signal is expressed in the form of text, the power-on signal can be expressed as "power on" or "yes", etc.; when the power-on signal is expressed in the form of a data string, the data string can be 1 bit, 2 bits, 4 bits, 8 bits, etc., and can be expressed as "0", "00", "1110", "01011111" in the order mentioned above. It should be noted that the above-mentioned representation methods of the power-on signal are only several of many embodiments and do not limit the representation method of the power-on signal. In addition, the power-on signal can also be output by converting the data string into a decimal value and determining whether the value exceeds a preset value; the power-on signal can also be output by counting the number of 0s and 1s in the data string, and when the number of 1s is more than the number of 0s; the power-on signal can also be output by determining whether the number of 0s or 1s in the data string exceeds a preset number. The above-mentioned implementation manners do not limit the power-on signal in this application, and its implementation manner can be determined according to the implementation scenario.

[0061] Regarding the first GPIO signal and the second GPIO signal, the logic for controlling the data selector is shown in the following table. Table 1 is the truth table of the strobe signal of the data selector, and the specific control logic is as follows:

[0062] Table 1 Truth Table of MUX Strobe Signal

[0063] BMC PCIe Switch sel Functional Description 0 0 0 A1 (BMC) Strobe 1 0 1 A0 (PCIe Switch) Strobe 1 1 0 A1 (BMC) Strobe 0 1 1 A0 (PCIe Switch) Strobe

[0064] It should also be noted that after troubleshooting or firmware upgrade of the PCIe Switch, the first GPIO signal and the second GPIO signal need to be set to low-level signals again.

[0065] An interface multiplexing method provided by this application is applied to an interface circuit, which includes: BMC, PCIe Switch, data selector, exclusive OR gate, and RJ45 network interface. One end of the BMC is connected to the first input terminal of the exclusive OR gate to facilitate obtaining the first GPIO signal of the BMC; one end of the PCIe Switch is connected to the second input terminal of the exclusive OR gate to facilitate obtaining the second GPIO signal of the PCIe Switch; the output terminal of the exclusive OR gate is connected to the first input terminal of the data selector, and the other end of the BMC is connected to the second input terminal of the data selector; the other end of the PCIe Switch is connected to the third input terminal of the data selector, and the output terminal of the data selector is connected to the RJ45 network interface to control the on or off state of the first to third input terminals of the data selector according to the first GPIO signal and the second GPIO signal, so as to control the troubleshooting or firmware upgrade of the PCIe Switch. The original solution of connecting an RJ45 network interface to both the BMC and the PCIe Switch is replaced with connecting both the BMC and the PCIe Switch to one RJ45 network interface, thereby simplifying the troubleshooting and firmware upgrade of the PCIe Switch device without occupying additional panel space.

[0066] Based on the above embodiments, as a more optimal implementation manner, after sending the power-on signal, it further includes:

[0067] Outputting a prompt message indicating that the BMC and the PCIe Switch are in the power-on state.

[0068] It should be noted that the prompt message can be expressed in the form of text or data string. When the prompt message is expressed in the form of text, the prompt message can be expressed as "Power on" or "Yes", etc.; when the prompt message is expressed in the form of data string, the data string can be 1-bit, 2-bit, 4-bit, 8-bit, etc., and can be expressed as "1", "10", "1100", "00100111" in the order mentioned above. It should be noted that the above-mentioned representation methods of the prompt message are only several of many embodiments, and do not limit the representation method of the prompt message. In addition, the data string can be converted into a decimal value, and it is judged whether the value exceeds a preset value. When it exceeds the preset value, the prompt message is output; the number of 0s and 1s in the data string can also be counted. When the number of 1s is more than the number of 0s, the prompt message is output; it can also be judged whether the number of 0s or 1s in the data string exceeds a preset number. If it exceeds the preset number, the prompt message is output. The above-mentioned implementation manners do not make any limitation on the prompt message in this application, and its implementation manner can be determined according to the implementation scenario.

[0069] In the above embodiments, the interface multiplexing method has been described in detail. The present application also provides corresponding embodiments of the interface multiplexing device. It should be noted that the embodiments of the device part in the present application are described from two perspectives, one is from the perspective of functional modules, and the other is from the perspective of hardware.

[0070] Figure 3 The following is a structural diagram of an interface multiplexing device provided by an embodiment of the present application. As Figure 3 shown, the present application also provides an interface multiplexing device, which is applied to an interface multiplexing circuit including a BMC, a PCIe Switch, a data selector, an exclusive OR gate, an RJ45 network port, and at least two PHY registers, and includes:

[0071] A first acquisition module 30, configured to acquire a first GPIO signal of the BMC and a second GPIO signal of the PCIe Switch;

[0072] A first control module 31, configured to control the first input terminal to the third input terminal of the data selector to be in a conducting state or a non-conducting state according to the first GPIO signal and the second GPIO signal;

[0073] A second control module 32, configured to control the PCIe Switch to troubleshoot or upgrade the firmware according to the conducting state or the non-conducting state of the first input terminal to the third input terminal of the data selector.

[0074] In addition, the device further includes the following modules:

[0075] Preferably, before acquiring the first GPIO signal of the BMC and the second GPIO signal of the PCIe Switch, it further includes:

[0076] A second acquisition module, configured to acquire a LAN signal, so as to connect at least two PHY registers and the data selector through the LAN signal.

[0077] Preferably, after acquiring the first GPIO signal of the BMC and the second GPIO signal of the PCIe Switch, and before controlling the first input terminal to the third input terminal of the data selector to be in a conducting state or a non-conducting state according to the first GPIO signal and the second GPIO signal, it further includes:

[0078] A judgment module, configured to judge whether the BMC and the PCIe Switch are in a powered-on state;

[0079] If so, both the first GPIO signal and the second GPIO signal are set to low-level signals;

[0080] If not, a power-on signal is output, configured to control the BMC and the PCIe Switch to be in a powered-on state.

[0081] Preferably, after the power-on signal is sent, it further includes:

[0082] An output module for outputting a prompt message indicating that the BMC and the PCIe Switch are in the power-on state.

[0083] Since the embodiments of the device part correspond to the embodiments of the method part, for the embodiments of the device part, please refer to the description of the embodiments of the method part, which will not be elaborated here. An interface multiplexing device provided by this application is applied to an interface circuit, and this circuit includes: BMC, PCIe Switch, data selector, exclusive-OR gate, RJ45 network interface. One end of the BMC is connected to the first input end of the exclusive-OR gate to facilitate obtaining the first GPIO signal of the BMC; one end of the PCIe Switch is connected to the second input end of the exclusive-OR gate to facilitate obtaining the second GPIO signal of the PCIe Switch; the output end of the exclusive-OR gate is connected to the first input end of the data selector, and the other end of the BMC is connected to the second input end of the data selector; the other end of the PCIe Switch is connected to the third input end of the data selector, and the output end of the data selector is connected to the RJ45 network interface to control the on state or off state of the first input end to the third input end of the data selector according to the first GPIO signal and the second GPIO signal to control the troubleshooting or firmware upgrade of the PCIe Switch. The original solution of connecting an RJ45 network interface to both the BMC and the PCIe Switch is replaced with the solution of connecting both the BMC and the PCIe Switch to one RJ45 network interface, so as to simplify the troubleshooting and firmware upgrade of the PCIe Switch device without occupying additional panel space.

[0084] Figure 4 The following is a structural diagram of an interface multiplexing device provided by an embodiment of this application, as Figure 4 shown, an interface multiplexing device includes:

[0085] A memory 40 for storing a computer program;

[0086] A processor 41 for implementing the steps of the interface multiplexing method mentioned in the above embodiments when executing the computer program.

[0087] The interface multiplexing device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a laptop computer, or a desktop computer, etc.

[0088] Among them, the processor 41 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor 41 may be implemented in at least one hardware form of digital signal processing (DSP), field-programmable gate array (FPGA), or programmable logic array (PLA). The processor 41 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the wake state, also known as the central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 41 may be integrated with a graphics processing unit (GPU), and the GPU is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 41 may further include an artificial intelligence (AI) processor, and the AI processor is used to process computational operations related to machine learning.

[0089] The memory 40 may include one or more computer-readable storage media, and the computer-readable storage media may be non-transitory. The memory 40 may further include high-speed random access memory and non-volatile memory, such as one or more disk storage devices and flash storage devices. In this embodiment, the memory 40 is at least used to store the following computer programs. After the computer programs are loaded and executed by the processor 41, the related steps of the interface multiplexing method disclosed in any of the foregoing embodiments can be implemented. In addition, the resources stored in the memory 40 may also include an operating system and data, etc., and the storage method may be transient storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include, but is not limited to, the interface multiplexing method, etc.

[0090] In some embodiments, the interface multiplexing device may further include a display screen, an input / output interface, a communication interface, a power supply, and a communication bus.

[0091] Those skilled in the art can understand that Figure 4 the structure shown in

[0092] does not constitute a limitation on the interface multiplexing device, and may include more or fewer components than shown in the figure.

[0093] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. A computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps recorded in the above method embodiments are implemented.

[0094] It can be understood that if the method in the above embodiments is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage media include: USB flash drives, mobile hard disks, read-only memories (ROMs), random access memories (RAMs), magnetic disks, or optical discs, etc., which can store program codes.

[0095] The above has introduced in detail an interface multiplexing circuit, method, device, equipment, and medium provided by the present application. The various embodiments in the specification are described in a progressive manner, and the key point of each embodiment is to illustrate the differences from other embodiments. The same or similar parts among the various embodiments can be referred to each other. For the device disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part. It should be noted that for those of ordinary skill in the art in the technical field, without departing from the principle of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the protection scope of the claims of the present application.

[0096] It should also be noted that in this specification, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover a non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising a..." does not exclude the existence of additional identical elements in the process, method, article or device comprising the element.

Claims

1. An interface multiplexing circuit, characterized in that, it includes: BMC (10), PCIe Switch (11), data selector (12), exclusive-OR gate, RJ45 network interface (13), at least two PHY registers (14); One end of the BMC (10) is connected to the first input end of the exclusive-OR gate to facilitate obtaining the first GPIO signal of the BMC (10); one end of the PCIe Switch (11) is connected to the second input end of the exclusive-OR gate to facilitate obtaining the second GPIO signal of the PCIe Switch (11); the output end of the exclusive-OR gate is connected to the first input end of the data selector (12), and the other end of the BMC (10) is connected to the second input end of the data selector (12); the other end of the PCIe Switch (11) is connected to the third input end of the data selector (12), and the output end of the data selector (12) is connected to the RJ45 network interface (13) to facilitate controlling the on state or off state of the first input end to the third input end of the data selector (12) according to the first GPIO signal and the second GPIO signal to control the troubleshooting or firmware upgrade of the PCIe Switch (11); One end of one of the PHY registers (14) is connected to the other end of the BMC (10); the other end of the PHY register (14) is connected to the second input end of the data selector (12); one end of the other PHY register (14) is connected to the other end of the PCIe Switch (11); the other end of the PHY register (14) is connected to the third input end of the data selector (12).

2. The interface multiplexing circuit according to claim 1, characterized in that, the data selector (12) is a two-to-one data selector.

3. An interface multiplexing method, characterized in that, applied to an interface multiplexing circuit including a BMC, a PCIe Switch, a data selector, an exclusive-OR gate, an RJ45 network interface, and at least two PHY registers, it includes: Obtaining a LAN signal to facilitate connecting at least two of the PHY registers and the data selector through the LAN signal; Obtaining the first GPIO signal of the BMC and the second GPIO signal of the PCIe Switch; Judging whether the BMC and the PCIe Switch are in the power-on state; if so, setting both the first GPIO signal and the second GPIO signal to low-level signals; if not, outputting a power-on signal for controlling the BMC and the PCIe Switch to be in the power-on state; Controlling the first input end to the third input end of the data selector to be in the on state or off state according to the first GPIO signal and the second GPIO signal; Controlling the troubleshooting or firmware upgrade of the PCIe Switch according to whether the first input terminal to the third input terminal of the data selector are in the conducting state or the off state.

4. The interface multiplexing method according to claim 3, wherein, after outputting the power-on signal, it further includes: outputting a prompt message indicating that the BMC and the PCIe Switch are in the power-on state.

5. An interface multiplexing device, wherein, applied to an interface multiplexing circuit including a BMC, a PCIe Switch, a data selector, an exclusive OR gate, an RJ45 network port, and at least two PHY registers, and includes: a second acquisition module, configured to acquire a LAN signal, so as to connect at least two of the PHY registers and the data selector through the LAN signal; a first acquisition module, configured to acquire a first GPIO signal of the BMC and a second GPIO signal of the PCIe Switch; a judgment module, configured to judge whether the BMC and the PCIe Switch are in the power-on state; if so, set both the first GPIO signal and the second GPIO signal to low-level signals; if not, output a power-on signal for controlling the BMC and the PCIe Switch to be in the power-on state; a first control module, configured to control the first input terminal to the third input terminal of the data selector to be in the conducting state or the off state according to the first GPIO signal and the second GPIO signal; a second control module, configured to control the troubleshooting or firmware upgrade of the PCIe Switch according to whether the first input terminal to the third input terminal of the data selector are in the conducting state or the off state.

6. An interface multiplexing device, wherein, includes: a memory, configured to store a computer program; a processor, configured to implement the steps of the interface multiplexing method according to claim 3 or 4 when executing the computer program.

7. A computer-readable storage medium, wherein, a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the interface multiplexing method according to claim 3 or 4 are implemented.

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